1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2017 MediaTek Inc. |
4 | * Author: Kevin Chen <kevin-cw.chen@mediatek.com> |
5 | */ |
6 | |
7 | #include <linux/clk-provider.h> |
8 | #include <linux/platform_device.h> |
9 | #include <dt-bindings/clock/mt6797-clk.h> |
10 | |
11 | #include "clk-mtk.h" |
12 | #include "clk-gate.h" |
13 | |
14 | static const struct mtk_gate_regs mm0_cg_regs = { |
15 | .set_ofs = 0x0104, |
16 | .clr_ofs = 0x0108, |
17 | .sta_ofs = 0x0100, |
18 | }; |
19 | |
20 | static const struct mtk_gate_regs mm1_cg_regs = { |
21 | .set_ofs = 0x0114, |
22 | .clr_ofs = 0x0118, |
23 | .sta_ofs = 0x0110, |
24 | }; |
25 | |
26 | #define GATE_MM0(_id, _name, _parent, _shift) \ |
27 | GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
28 | |
29 | #define GATE_MM1(_id, _name, _parent, _shift) \ |
30 | GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
31 | |
32 | static const struct mtk_gate mm_clks[] = { |
33 | GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common" , "mm_sel" , 0), |
34 | GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0" , "mm_sel" , 1), |
35 | GATE_MM0(CLK_MM_SMI_LARB5, "mm_smi_larb5" , "mm_sel" , 2), |
36 | GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp" , "mm_sel" , 3), |
37 | GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0" , "mm_sel" , 4), |
38 | GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1" , "mm_sel" , 5), |
39 | GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0" , "mm_sel" , 6), |
40 | GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1" , "mm_sel" , 7), |
41 | GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2" , "mm_sel" , 8), |
42 | GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp" , "mm_sel" , 9), |
43 | GATE_MM0(CLK_MM_MDP_COLOR, "mm_mdp_color" , "mm_sel" , 10), |
44 | GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma" , "mm_sel" , 11), |
45 | GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0" , "mm_sel" , 12), |
46 | GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1" , "mm_sel" , 13), |
47 | GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng" , "mm_sel" , 14), |
48 | GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0" , "mm_sel" , 15), |
49 | GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1" , "mm_sel" , 16), |
50 | GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l" , "mm_sel" , 17), |
51 | GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l" , "mm_sel" , 18), |
52 | GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0" , "mm_sel" , 19), |
53 | GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1" , "mm_sel" , 20), |
54 | GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0" , "mm_sel" , 21), |
55 | GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1" , "mm_sel" , 22), |
56 | GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color" , "mm_sel" , 23), |
57 | GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr" , "mm_sel" , 24), |
58 | GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal" , "mm_sel" , 25), |
59 | GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma" , "mm_sel" , 26), |
60 | GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od" , "mm_sel" , 27), |
61 | GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither" , "mm_sel" , 28), |
62 | GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe" , "mm_sel" , 29), |
63 | GATE_MM0(CLK_MM_DISP_DSC, "mm_disp_dsc" , "mm_sel" , 30), |
64 | GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split" , "mm_sel" , 31), |
65 | GATE_MM1(CLK_MM_DSI0_MM_CLOCK, "mm_dsi0_mm_clock" , "mm_sel" , 0), |
66 | GATE_MM1(CLK_MM_DSI1_MM_CLOCK, "mm_dsi1_mm_clock" , "mm_sel" , 2), |
67 | GATE_MM1(CLK_MM_DPI_MM_CLOCK, "mm_dpi_mm_clock" , "mm_sel" , 4), |
68 | GATE_MM1(CLK_MM_DPI_INTERFACE_CLOCK, "mm_dpi_interface_clock" , |
69 | "dpi0_sel" , 5), |
70 | GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MM_CLOCK, "mm_larb4_axi_asif_mm_clock" , |
71 | "mm_sel" , 6), |
72 | GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK, "mm_larb4_axi_asif_mjc_clock" , |
73 | "mjc_sel" , 7), |
74 | GATE_MM1(CLK_MM_DISP_OVL0_MOUT_CLOCK, "mm_disp_ovl0_mout_clock" , |
75 | "mm_sel" , 8), |
76 | GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2" , "mm_sel" , 9), |
77 | GATE_MM1(CLK_MM_DSI0_INTERFACE_CLOCK, "mm_dsi0_interface_clock" , |
78 | "clk26m" , 1), |
79 | GATE_MM1(CLK_MM_DSI1_INTERFACE_CLOCK, "mm_dsi1_interface_clock" , |
80 | "clk26m" , 3), |
81 | }; |
82 | |
83 | static const struct mtk_clk_desc mm_desc = { |
84 | .clks = mm_clks, |
85 | .num_clks = ARRAY_SIZE(mm_clks), |
86 | }; |
87 | |
88 | static const struct platform_device_id clk_mt6797_mm_id_table[] = { |
89 | { .name = "clk-mt6797-mm" , .driver_data = (kernel_ulong_t)&mm_desc }, |
90 | { /* sentinel */ } |
91 | }; |
92 | MODULE_DEVICE_TABLE(platform, clk_mt6797_mm_id_table); |
93 | |
94 | static struct platform_driver clk_mt6797_mm_drv = { |
95 | .probe = mtk_clk_pdev_probe, |
96 | .remove_new = mtk_clk_pdev_remove, |
97 | .driver = { |
98 | .name = "clk-mt6797-mm" , |
99 | }, |
100 | .id_table = clk_mt6797_mm_id_table, |
101 | }; |
102 | module_platform_driver(clk_mt6797_mm_drv); |
103 | MODULE_LICENSE("GPL" ); |
104 | |