1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2016 Maxime Ripard. All rights reserved. |
4 | */ |
5 | |
6 | #include <linux/clk-provider.h> |
7 | #include <linux/io.h> |
8 | #include <linux/module.h> |
9 | #include <linux/platform_device.h> |
10 | |
11 | #include "ccu_common.h" |
12 | #include "ccu_reset.h" |
13 | |
14 | #include "ccu_div.h" |
15 | #include "ccu_gate.h" |
16 | #include "ccu_mp.h" |
17 | #include "ccu_mult.h" |
18 | #include "ccu_nk.h" |
19 | #include "ccu_nkm.h" |
20 | #include "ccu_nkmp.h" |
21 | #include "ccu_nm.h" |
22 | #include "ccu_phase.h" |
23 | #include "ccu_sdm.h" |
24 | |
25 | #include "ccu-sun8i-a23-a33.h" |
26 | |
27 | |
28 | static struct ccu_nkmp pll_cpux_clk = { |
29 | .enable = BIT(31), |
30 | .lock = BIT(28), |
31 | |
32 | .n = _SUNXI_CCU_MULT(8, 5), |
33 | .k = _SUNXI_CCU_MULT(4, 2), |
34 | .m = _SUNXI_CCU_DIV(0, 2), |
35 | .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), |
36 | |
37 | .common = { |
38 | .reg = 0x000, |
39 | .hw.init = CLK_HW_INIT("pll-cpux" , "osc24M" , |
40 | &ccu_nkmp_ops, |
41 | 0), |
42 | }, |
43 | }; |
44 | |
45 | /* |
46 | * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from |
47 | * the base (2x, 4x and 8x), and one variable divider (the one true |
48 | * pll audio). |
49 | * |
50 | * With sigma-delta modulation for fractional-N on the audio PLL, |
51 | * we have to use specific dividers. This means the variable divider |
52 | * can no longer be used, as the audio codec requests the exact clock |
53 | * rates we support through this mechanism. So we now hard code the |
54 | * variable divider to 1. This means the clock rates will no longer |
55 | * match the clock names. |
56 | */ |
57 | #define SUN8I_A23_PLL_AUDIO_REG 0x008 |
58 | |
59 | static struct ccu_sdm_setting pll_audio_sdm_table[] = { |
60 | { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, |
61 | { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, |
62 | }; |
63 | |
64 | static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base" , |
65 | "osc24M" , 0x008, |
66 | 8, 7, /* N */ |
67 | 0, 5, /* M */ |
68 | pll_audio_sdm_table, BIT(24), |
69 | 0x284, BIT(31), |
70 | BIT(31), /* gate */ |
71 | BIT(28), /* lock */ |
72 | CLK_SET_RATE_UNGATE); |
73 | |
74 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video" , |
75 | "osc24M" , 0x010, |
76 | 8, 7, /* N */ |
77 | 0, 4, /* M */ |
78 | BIT(24), /* frac enable */ |
79 | BIT(25), /* frac select */ |
80 | 270000000, /* frac rate 0 */ |
81 | 297000000, /* frac rate 1 */ |
82 | BIT(31), /* gate */ |
83 | BIT(28), /* lock */ |
84 | CLK_SET_RATE_UNGATE); |
85 | |
86 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve" , |
87 | "osc24M" , 0x018, |
88 | 8, 7, /* N */ |
89 | 0, 4, /* M */ |
90 | BIT(24), /* frac enable */ |
91 | BIT(25), /* frac select */ |
92 | 270000000, /* frac rate 0 */ |
93 | 297000000, /* frac rate 1 */ |
94 | BIT(31), /* gate */ |
95 | BIT(28), /* lock */ |
96 | CLK_SET_RATE_UNGATE); |
97 | |
98 | static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr" , |
99 | "osc24M" , 0x020, |
100 | 8, 5, /* N */ |
101 | 4, 2, /* K */ |
102 | 0, 2, /* M */ |
103 | BIT(31), /* gate */ |
104 | BIT(28), /* lock */ |
105 | 0); |
106 | |
107 | static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph" , |
108 | "osc24M" , 0x028, |
109 | 8, 5, /* N */ |
110 | 4, 2, /* K */ |
111 | BIT(31), /* gate */ |
112 | BIT(28), /* lock */ |
113 | 2, /* post-div */ |
114 | CLK_SET_RATE_UNGATE); |
115 | |
116 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu" , |
117 | "osc24M" , 0x038, |
118 | 8, 7, /* N */ |
119 | 0, 4, /* M */ |
120 | BIT(24), /* frac enable */ |
121 | BIT(25), /* frac select */ |
122 | 270000000, /* frac rate 0 */ |
123 | 297000000, /* frac rate 1 */ |
124 | BIT(31), /* gate */ |
125 | BIT(28), /* lock */ |
126 | CLK_SET_RATE_UNGATE); |
127 | |
128 | /* |
129 | * The MIPI PLL has 2 modes: "MIPI" and "HDMI". |
130 | * |
131 | * The MIPI mode is a standard NKM-style clock. The HDMI mode is an |
132 | * integer / fractional clock with switchable multipliers and dividers. |
133 | * This is not supported here. We hardcode the PLL to MIPI mode. |
134 | */ |
135 | #define SUN8I_A23_PLL_MIPI_REG 0x040 |
136 | static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi" , |
137 | "pll-video" , 0x040, |
138 | 8, 4, /* N */ |
139 | 4, 2, /* K */ |
140 | 0, 4, /* M */ |
141 | BIT(31) | BIT(23) | BIT(22), /* gate */ |
142 | BIT(28), /* lock */ |
143 | CLK_SET_RATE_UNGATE); |
144 | |
145 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic" , |
146 | "osc24M" , 0x044, |
147 | 8, 7, /* N */ |
148 | 0, 4, /* M */ |
149 | BIT(24), /* frac enable */ |
150 | BIT(25), /* frac select */ |
151 | 270000000, /* frac rate 0 */ |
152 | 297000000, /* frac rate 1 */ |
153 | BIT(31), /* gate */ |
154 | BIT(28), /* lock */ |
155 | CLK_SET_RATE_UNGATE); |
156 | |
157 | static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de" , |
158 | "osc24M" , 0x048, |
159 | 8, 7, /* N */ |
160 | 0, 4, /* M */ |
161 | BIT(24), /* frac enable */ |
162 | BIT(25), /* frac select */ |
163 | 270000000, /* frac rate 0 */ |
164 | 297000000, /* frac rate 1 */ |
165 | BIT(31), /* gate */ |
166 | BIT(28), /* lock */ |
167 | CLK_SET_RATE_UNGATE); |
168 | |
169 | static const char * const cpux_parents[] = { "osc32k" , "osc24M" , |
170 | "pll-cpux" , "pll-cpux" }; |
171 | static SUNXI_CCU_MUX(cpux_clk, "cpux" , cpux_parents, |
172 | 0x050, 16, 2, CLK_IS_CRITICAL); |
173 | |
174 | static SUNXI_CCU_M(axi_clk, "axi" , "cpux" , 0x050, 0, 2, 0); |
175 | |
176 | static const char * const ahb1_parents[] = { "osc32k" , "osc24M" , |
177 | "axi" , "pll-periph" }; |
178 | static const struct ccu_mux_var_prediv ahb1_predivs[] = { |
179 | { .index = 3, .shift = 6, .width = 2 }, |
180 | }; |
181 | static struct ccu_div ahb1_clk = { |
182 | .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), |
183 | |
184 | .mux = { |
185 | .shift = 12, |
186 | .width = 2, |
187 | |
188 | .var_predivs = ahb1_predivs, |
189 | .n_var_predivs = ARRAY_SIZE(ahb1_predivs), |
190 | }, |
191 | |
192 | .common = { |
193 | .reg = 0x054, |
194 | .features = CCU_FEATURE_VARIABLE_PREDIV, |
195 | .hw.init = CLK_HW_INIT_PARENTS("ahb1" , |
196 | ahb1_parents, |
197 | &ccu_div_ops, |
198 | 0), |
199 | }, |
200 | }; |
201 | |
202 | static struct clk_div_table apb1_div_table[] = { |
203 | { .val = 0, .div = 2 }, |
204 | { .val = 1, .div = 2 }, |
205 | { .val = 2, .div = 4 }, |
206 | { .val = 3, .div = 8 }, |
207 | { /* Sentinel */ }, |
208 | }; |
209 | static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1" , "ahb1" , |
210 | 0x054, 8, 2, apb1_div_table, 0); |
211 | |
212 | static const char * const apb2_parents[] = { "osc32k" , "osc24M" , |
213 | "pll-periph" , "pll-periph" }; |
214 | static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2" , apb2_parents, 0x058, |
215 | 0, 5, /* M */ |
216 | 16, 2, /* P */ |
217 | 24, 2, /* mux */ |
218 | 0); |
219 | |
220 | static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi" , "ahb1" , |
221 | 0x060, BIT(1), 0); |
222 | static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma" , "ahb1" , |
223 | 0x060, BIT(6), 0); |
224 | static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0" , "ahb1" , |
225 | 0x060, BIT(8), 0); |
226 | static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1" , "ahb1" , |
227 | 0x060, BIT(9), 0); |
228 | static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2" , "ahb1" , |
229 | 0x060, BIT(10), 0); |
230 | static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand" , "ahb1" , |
231 | 0x060, BIT(13), 0); |
232 | static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram" , "ahb1" , |
233 | 0x060, BIT(14), 0); |
234 | static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer" , "ahb1" , |
235 | 0x060, BIT(19), 0); |
236 | static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0" , "ahb1" , |
237 | 0x060, BIT(20), 0); |
238 | static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1" , "ahb1" , |
239 | 0x060, BIT(21), 0); |
240 | static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg" , "ahb1" , |
241 | 0x060, BIT(24), 0); |
242 | static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci" , "ahb1" , |
243 | 0x060, BIT(26), 0); |
244 | static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci" , "ahb1" , |
245 | 0x060, BIT(29), 0); |
246 | |
247 | static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve" , "ahb1" , |
248 | 0x064, BIT(0), 0); |
249 | static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd" , "ahb1" , |
250 | 0x064, BIT(4), 0); |
251 | static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi" , "ahb1" , |
252 | 0x064, BIT(8), 0); |
253 | static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be" , "ahb1" , |
254 | 0x064, BIT(12), 0); |
255 | static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe" , "ahb1" , |
256 | 0x064, BIT(14), 0); |
257 | static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu" , "ahb1" , |
258 | 0x064, BIT(20), 0); |
259 | static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox" , "ahb1" , |
260 | 0x064, BIT(21), 0); |
261 | static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock" , "ahb1" , |
262 | 0x064, BIT(22), 0); |
263 | static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc" , "ahb1" , |
264 | 0x064, BIT(25), 0); |
265 | |
266 | static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec" , "apb1" , |
267 | 0x068, BIT(0), 0); |
268 | static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio" , "apb1" , |
269 | 0x068, BIT(5), 0); |
270 | static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0" , "apb1" , |
271 | 0x068, BIT(12), 0); |
272 | static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1" , "apb1" , |
273 | 0x068, BIT(13), 0); |
274 | |
275 | static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0" , "apb2" , |
276 | 0x06c, BIT(0), 0); |
277 | static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1" , "apb2" , |
278 | 0x06c, BIT(1), 0); |
279 | static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2" , "apb2" , |
280 | 0x06c, BIT(2), 0); |
281 | static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0" , "apb2" , |
282 | 0x06c, BIT(16), 0); |
283 | static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1" , "apb2" , |
284 | 0x06c, BIT(17), 0); |
285 | static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2" , "apb2" , |
286 | 0x06c, BIT(18), 0); |
287 | static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3" , "apb2" , |
288 | 0x06c, BIT(19), 0); |
289 | static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4" , "apb2" , |
290 | 0x06c, BIT(20), 0); |
291 | |
292 | static const char * const mod0_default_parents[] = { "osc24M" , "pll-periph" }; |
293 | static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand" , mod0_default_parents, 0x080, |
294 | 0, 4, /* M */ |
295 | 16, 2, /* P */ |
296 | 24, 2, /* mux */ |
297 | BIT(31), /* gate */ |
298 | 0); |
299 | |
300 | static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0" , mod0_default_parents, 0x088, |
301 | 0, 4, /* M */ |
302 | 16, 2, /* P */ |
303 | 24, 2, /* mux */ |
304 | BIT(31), /* gate */ |
305 | 0); |
306 | |
307 | static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample" , "mmc0" , |
308 | 0x088, 20, 3, 0); |
309 | static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output" , "mmc0" , |
310 | 0x088, 8, 3, 0); |
311 | |
312 | static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1" , mod0_default_parents, 0x08c, |
313 | 0, 4, /* M */ |
314 | 16, 2, /* P */ |
315 | 24, 2, /* mux */ |
316 | BIT(31), /* gate */ |
317 | 0); |
318 | |
319 | static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample" , "mmc1" , |
320 | 0x08c, 20, 3, 0); |
321 | static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output" , "mmc1" , |
322 | 0x08c, 8, 3, 0); |
323 | |
324 | static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2" , mod0_default_parents, 0x090, |
325 | 0, 4, /* M */ |
326 | 16, 2, /* P */ |
327 | 24, 2, /* mux */ |
328 | BIT(31), /* gate */ |
329 | 0); |
330 | |
331 | static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample" , "mmc2" , |
332 | 0x090, 20, 3, 0); |
333 | static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output" , "mmc2" , |
334 | 0x090, 8, 3, 0); |
335 | |
336 | static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0" , mod0_default_parents, 0x0a0, |
337 | 0, 4, /* M */ |
338 | 16, 2, /* P */ |
339 | 24, 2, /* mux */ |
340 | BIT(31), /* gate */ |
341 | 0); |
342 | |
343 | static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1" , mod0_default_parents, 0x0a4, |
344 | 0, 4, /* M */ |
345 | 16, 2, /* P */ |
346 | 24, 2, /* mux */ |
347 | BIT(31), /* gate */ |
348 | 0); |
349 | |
350 | static const char * const i2s_parents[] = { "pll-audio-8x" , "pll-audio-4x" , |
351 | "pll-audio-2x" , "pll-audio" }; |
352 | static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0" , i2s_parents, |
353 | 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); |
354 | |
355 | static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1" , i2s_parents, |
356 | 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); |
357 | |
358 | /* TODO: the parent for most of the USB clocks is not known */ |
359 | static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0" , "osc24M" , |
360 | 0x0cc, BIT(8), 0); |
361 | static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1" , "osc24M" , |
362 | 0x0cc, BIT(9), 0); |
363 | static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic" , "pll-hsic" , |
364 | 0x0cc, BIT(10), 0); |
365 | static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M" , "osc24M" , |
366 | 0x0cc, BIT(11), 0); |
367 | static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci" , "osc24M" , |
368 | 0x0cc, BIT(16), 0); |
369 | |
370 | static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve" , "pll-ddr" , |
371 | 0x100, BIT(0), 0); |
372 | static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi" , "pll-ddr" , |
373 | 0x100, BIT(1), 0); |
374 | static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc" , "pll-ddr" , |
375 | 0x100, BIT(16), 0); |
376 | static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe" , "pll-ddr" , |
377 | 0x100, BIT(24), 0); |
378 | static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be" , "pll-ddr" , |
379 | 0x100, BIT(26), 0); |
380 | |
381 | static const char * const de_parents[] = { "pll-video" , "pll-periph-2x" , |
382 | "pll-gpu" , "pll-de" }; |
383 | static const u8 de_table[] = { 0, 2, 3, 5 }; |
384 | static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be" , |
385 | de_parents, de_table, |
386 | 0x104, 0, 4, 24, 3, BIT(31), 0); |
387 | |
388 | static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe" , |
389 | de_parents, de_table, |
390 | 0x10c, 0, 4, 24, 3, BIT(31), 0); |
391 | |
392 | static const char * const lcd_ch0_parents[] = { "pll-video" , "pll-video-2x" , |
393 | "pll-mipi" }; |
394 | static const u8 lcd_ch0_table[] = { 0, 2, 4 }; |
395 | static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0" , |
396 | lcd_ch0_parents, lcd_ch0_table, |
397 | 0x118, 24, 3, BIT(31), |
398 | CLK_SET_RATE_PARENT); |
399 | |
400 | static const char * const lcd_ch1_parents[] = { "pll-video" , "pll-video-2x" }; |
401 | static const u8 lcd_ch1_table[] = { 0, 2 }; |
402 | static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1" , |
403 | lcd_ch1_parents, lcd_ch1_table, |
404 | 0x12c, 0, 4, 24, 2, BIT(31), 0); |
405 | |
406 | static const char * const csi_sclk_parents[] = { "pll-video" , "pll-de" , |
407 | "pll-mipi" , "pll-ve" }; |
408 | static const u8 csi_sclk_table[] = { 0, 3, 4, 5 }; |
409 | static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk" , |
410 | csi_sclk_parents, csi_sclk_table, |
411 | 0x134, 16, 4, 24, 3, BIT(31), 0); |
412 | |
413 | static const char * const csi_mclk_parents[] = { "pll-video" , "pll-de" , |
414 | "osc24M" }; |
415 | static const u8 csi_mclk_table[] = { 0, 3, 5 }; |
416 | static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk" , |
417 | csi_mclk_parents, csi_mclk_table, |
418 | 0x134, 0, 5, 8, 3, BIT(15), 0); |
419 | |
420 | static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve" , "pll-ve" , |
421 | 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); |
422 | |
423 | static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig" , "pll-audio" , |
424 | 0x140, BIT(31), CLK_SET_RATE_PARENT); |
425 | static SUNXI_CCU_GATE(avs_clk, "avs" , "osc24M" , |
426 | 0x144, BIT(31), 0); |
427 | |
428 | static const char * const mbus_parents[] = { "osc24M" , "pll-periph-2x" , |
429 | "pll-ddr" }; |
430 | static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus" , mbus_parents, |
431 | 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); |
432 | |
433 | static const char * const dsi_sclk_parents[] = { "pll-video" , "pll-video-2x" }; |
434 | static const u8 dsi_sclk_table[] = { 0, 2 }; |
435 | static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk" , |
436 | dsi_sclk_parents, dsi_sclk_table, |
437 | 0x168, 16, 4, 24, 2, BIT(31), 0); |
438 | |
439 | static const char * const dsi_dphy_parents[] = { "pll-video" , "pll-periph" }; |
440 | static const u8 dsi_dphy_table[] = { 0, 2 }; |
441 | static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy" , |
442 | dsi_dphy_parents, dsi_dphy_table, |
443 | 0x168, 0, 4, 8, 2, BIT(15), 0); |
444 | |
445 | static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc" , |
446 | de_parents, de_table, |
447 | 0x180, 0, 4, 24, 3, BIT(31), 0); |
448 | |
449 | static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu" , "pll-gpu" , |
450 | 0x1a0, 0, 3, BIT(31), 0); |
451 | |
452 | static const char * const ats_parents[] = { "osc24M" , "pll-periph" }; |
453 | static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats" , ats_parents, |
454 | 0x1b0, 0, 3, 24, 2, BIT(31), 0); |
455 | |
456 | static struct ccu_common *sun8i_a23_ccu_clks[] = { |
457 | &pll_cpux_clk.common, |
458 | &pll_audio_base_clk.common, |
459 | &pll_video_clk.common, |
460 | &pll_ve_clk.common, |
461 | &pll_ddr_clk.common, |
462 | &pll_periph_clk.common, |
463 | &pll_gpu_clk.common, |
464 | &pll_mipi_clk.common, |
465 | &pll_hsic_clk.common, |
466 | &pll_de_clk.common, |
467 | &cpux_clk.common, |
468 | &axi_clk.common, |
469 | &ahb1_clk.common, |
470 | &apb1_clk.common, |
471 | &apb2_clk.common, |
472 | &bus_mipi_dsi_clk.common, |
473 | &bus_dma_clk.common, |
474 | &bus_mmc0_clk.common, |
475 | &bus_mmc1_clk.common, |
476 | &bus_mmc2_clk.common, |
477 | &bus_nand_clk.common, |
478 | &bus_dram_clk.common, |
479 | &bus_hstimer_clk.common, |
480 | &bus_spi0_clk.common, |
481 | &bus_spi1_clk.common, |
482 | &bus_otg_clk.common, |
483 | &bus_ehci_clk.common, |
484 | &bus_ohci_clk.common, |
485 | &bus_ve_clk.common, |
486 | &bus_lcd_clk.common, |
487 | &bus_csi_clk.common, |
488 | &bus_de_fe_clk.common, |
489 | &bus_de_be_clk.common, |
490 | &bus_gpu_clk.common, |
491 | &bus_msgbox_clk.common, |
492 | &bus_spinlock_clk.common, |
493 | &bus_drc_clk.common, |
494 | &bus_codec_clk.common, |
495 | &bus_pio_clk.common, |
496 | &bus_i2s0_clk.common, |
497 | &bus_i2s1_clk.common, |
498 | &bus_i2c0_clk.common, |
499 | &bus_i2c1_clk.common, |
500 | &bus_i2c2_clk.common, |
501 | &bus_uart0_clk.common, |
502 | &bus_uart1_clk.common, |
503 | &bus_uart2_clk.common, |
504 | &bus_uart3_clk.common, |
505 | &bus_uart4_clk.common, |
506 | &nand_clk.common, |
507 | &mmc0_clk.common, |
508 | &mmc0_sample_clk.common, |
509 | &mmc0_output_clk.common, |
510 | &mmc1_clk.common, |
511 | &mmc1_sample_clk.common, |
512 | &mmc1_output_clk.common, |
513 | &mmc2_clk.common, |
514 | &mmc2_sample_clk.common, |
515 | &mmc2_output_clk.common, |
516 | &spi0_clk.common, |
517 | &spi1_clk.common, |
518 | &i2s0_clk.common, |
519 | &i2s1_clk.common, |
520 | &usb_phy0_clk.common, |
521 | &usb_phy1_clk.common, |
522 | &usb_hsic_clk.common, |
523 | &usb_hsic_12M_clk.common, |
524 | &usb_ohci_clk.common, |
525 | &dram_ve_clk.common, |
526 | &dram_csi_clk.common, |
527 | &dram_drc_clk.common, |
528 | &dram_de_fe_clk.common, |
529 | &dram_de_be_clk.common, |
530 | &de_be_clk.common, |
531 | &de_fe_clk.common, |
532 | &lcd_ch0_clk.common, |
533 | &lcd_ch1_clk.common, |
534 | &csi_sclk_clk.common, |
535 | &csi_mclk_clk.common, |
536 | &ve_clk.common, |
537 | &ac_dig_clk.common, |
538 | &avs_clk.common, |
539 | &mbus_clk.common, |
540 | &dsi_sclk_clk.common, |
541 | &dsi_dphy_clk.common, |
542 | &drc_clk.common, |
543 | &gpu_clk.common, |
544 | &ats_clk.common, |
545 | }; |
546 | |
547 | static const struct clk_hw *clk_parent_pll_audio[] = { |
548 | &pll_audio_base_clk.common.hw |
549 | }; |
550 | |
551 | /* We hardcode the divider to 1 for now */ |
552 | static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio" , |
553 | clk_parent_pll_audio, |
554 | 1, 1, CLK_SET_RATE_PARENT); |
555 | static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x" , |
556 | clk_parent_pll_audio, |
557 | 2, 1, CLK_SET_RATE_PARENT); |
558 | static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x" , |
559 | clk_parent_pll_audio, |
560 | 1, 1, CLK_SET_RATE_PARENT); |
561 | static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x" , |
562 | clk_parent_pll_audio, |
563 | 1, 2, CLK_SET_RATE_PARENT); |
564 | static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x" , |
565 | &pll_periph_clk.common.hw, |
566 | 1, 2, 0); |
567 | static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x" , |
568 | &pll_video_clk.common.hw, |
569 | 1, 2, 0); |
570 | |
571 | static struct clk_hw_onecell_data sun8i_a23_hw_clks = { |
572 | .hws = { |
573 | [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, |
574 | [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, |
575 | [CLK_PLL_AUDIO] = &pll_audio_clk.hw, |
576 | [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, |
577 | [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, |
578 | [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, |
579 | [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, |
580 | [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw, |
581 | [CLK_PLL_VE] = &pll_ve_clk.common.hw, |
582 | [CLK_PLL_DDR0] = &pll_ddr_clk.common.hw, |
583 | [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw, |
584 | [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw, |
585 | [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, |
586 | [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, |
587 | [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, |
588 | [CLK_PLL_DE] = &pll_de_clk.common.hw, |
589 | [CLK_CPUX] = &cpux_clk.common.hw, |
590 | [CLK_AXI] = &axi_clk.common.hw, |
591 | [CLK_AHB1] = &ahb1_clk.common.hw, |
592 | [CLK_APB1] = &apb1_clk.common.hw, |
593 | [CLK_APB2] = &apb2_clk.common.hw, |
594 | [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, |
595 | [CLK_BUS_DMA] = &bus_dma_clk.common.hw, |
596 | [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, |
597 | [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, |
598 | [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, |
599 | [CLK_BUS_NAND] = &bus_nand_clk.common.hw, |
600 | [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, |
601 | [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, |
602 | [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, |
603 | [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, |
604 | [CLK_BUS_OTG] = &bus_otg_clk.common.hw, |
605 | [CLK_BUS_EHCI] = &bus_ehci_clk.common.hw, |
606 | [CLK_BUS_OHCI] = &bus_ohci_clk.common.hw, |
607 | [CLK_BUS_VE] = &bus_ve_clk.common.hw, |
608 | [CLK_BUS_LCD] = &bus_lcd_clk.common.hw, |
609 | [CLK_BUS_CSI] = &bus_csi_clk.common.hw, |
610 | [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw, |
611 | [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw, |
612 | [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, |
613 | [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, |
614 | [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, |
615 | [CLK_BUS_DRC] = &bus_drc_clk.common.hw, |
616 | [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, |
617 | [CLK_BUS_PIO] = &bus_pio_clk.common.hw, |
618 | [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, |
619 | [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, |
620 | [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, |
621 | [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, |
622 | [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, |
623 | [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, |
624 | [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, |
625 | [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, |
626 | [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, |
627 | [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, |
628 | [CLK_NAND] = &nand_clk.common.hw, |
629 | [CLK_MMC0] = &mmc0_clk.common.hw, |
630 | [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, |
631 | [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, |
632 | [CLK_MMC1] = &mmc1_clk.common.hw, |
633 | [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, |
634 | [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, |
635 | [CLK_MMC2] = &mmc2_clk.common.hw, |
636 | [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, |
637 | [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, |
638 | [CLK_SPI0] = &spi0_clk.common.hw, |
639 | [CLK_SPI1] = &spi1_clk.common.hw, |
640 | [CLK_I2S0] = &i2s0_clk.common.hw, |
641 | [CLK_I2S1] = &i2s1_clk.common.hw, |
642 | [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, |
643 | [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, |
644 | [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, |
645 | [CLK_USB_HSIC_12M] = &usb_hsic_12M_clk.common.hw, |
646 | [CLK_USB_OHCI] = &usb_ohci_clk.common.hw, |
647 | [CLK_DRAM_VE] = &dram_ve_clk.common.hw, |
648 | [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, |
649 | [CLK_DRAM_DRC] = &dram_drc_clk.common.hw, |
650 | [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw, |
651 | [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw, |
652 | [CLK_DE_BE] = &de_be_clk.common.hw, |
653 | [CLK_DE_FE] = &de_fe_clk.common.hw, |
654 | [CLK_LCD_CH0] = &lcd_ch0_clk.common.hw, |
655 | [CLK_LCD_CH1] = &lcd_ch1_clk.common.hw, |
656 | [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, |
657 | [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, |
658 | [CLK_VE] = &ve_clk.common.hw, |
659 | [CLK_AC_DIG] = &ac_dig_clk.common.hw, |
660 | [CLK_AVS] = &avs_clk.common.hw, |
661 | [CLK_MBUS] = &mbus_clk.common.hw, |
662 | [CLK_DSI_SCLK] = &dsi_sclk_clk.common.hw, |
663 | [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, |
664 | [CLK_DRC] = &drc_clk.common.hw, |
665 | [CLK_GPU] = &gpu_clk.common.hw, |
666 | [CLK_ATS] = &ats_clk.common.hw, |
667 | }, |
668 | .num = CLK_NUMBER, |
669 | }; |
670 | |
671 | static struct ccu_reset_map sun8i_a23_ccu_resets[] = { |
672 | [RST_USB_PHY0] = { 0x0cc, BIT(0) }, |
673 | [RST_USB_PHY1] = { 0x0cc, BIT(1) }, |
674 | [RST_USB_HSIC] = { 0x0cc, BIT(2) }, |
675 | |
676 | [RST_MBUS] = { 0x0fc, BIT(31) }, |
677 | |
678 | [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, |
679 | [RST_BUS_DMA] = { 0x2c0, BIT(6) }, |
680 | [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, |
681 | [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, |
682 | [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, |
683 | [RST_BUS_NAND] = { 0x2c0, BIT(13) }, |
684 | [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, |
685 | [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, |
686 | [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, |
687 | [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, |
688 | [RST_BUS_OTG] = { 0x2c0, BIT(24) }, |
689 | [RST_BUS_EHCI] = { 0x2c0, BIT(26) }, |
690 | [RST_BUS_OHCI] = { 0x2c0, BIT(29) }, |
691 | |
692 | [RST_BUS_VE] = { 0x2c4, BIT(0) }, |
693 | [RST_BUS_LCD] = { 0x2c4, BIT(4) }, |
694 | [RST_BUS_CSI] = { 0x2c4, BIT(8) }, |
695 | [RST_BUS_DE_BE] = { 0x2c4, BIT(12) }, |
696 | [RST_BUS_DE_FE] = { 0x2c4, BIT(14) }, |
697 | [RST_BUS_GPU] = { 0x2c4, BIT(20) }, |
698 | [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, |
699 | [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, |
700 | [RST_BUS_DRC] = { 0x2c4, BIT(25) }, |
701 | |
702 | [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, |
703 | |
704 | [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, |
705 | [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, |
706 | [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, |
707 | |
708 | [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, |
709 | [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, |
710 | [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, |
711 | [RST_BUS_UART0] = { 0x2d8, BIT(16) }, |
712 | [RST_BUS_UART1] = { 0x2d8, BIT(17) }, |
713 | [RST_BUS_UART2] = { 0x2d8, BIT(18) }, |
714 | [RST_BUS_UART3] = { 0x2d8, BIT(19) }, |
715 | [RST_BUS_UART4] = { 0x2d8, BIT(20) }, |
716 | }; |
717 | |
718 | static const struct sunxi_ccu_desc sun8i_a23_ccu_desc = { |
719 | .ccu_clks = sun8i_a23_ccu_clks, |
720 | .num_ccu_clks = ARRAY_SIZE(sun8i_a23_ccu_clks), |
721 | |
722 | .hw_clks = &sun8i_a23_hw_clks, |
723 | |
724 | .resets = sun8i_a23_ccu_resets, |
725 | .num_resets = ARRAY_SIZE(sun8i_a23_ccu_resets), |
726 | }; |
727 | |
728 | static int sun8i_a23_ccu_probe(struct platform_device *pdev) |
729 | { |
730 | void __iomem *reg; |
731 | u32 val; |
732 | |
733 | reg = devm_platform_ioremap_resource(pdev, index: 0); |
734 | if (IS_ERR(ptr: reg)) |
735 | return PTR_ERR(ptr: reg); |
736 | |
737 | /* Force the PLL-Audio-1x divider to 1 */ |
738 | val = readl(addr: reg + SUN8I_A23_PLL_AUDIO_REG); |
739 | val &= ~GENMASK(19, 16); |
740 | writel(val: val | (0 << 16), addr: reg + SUN8I_A23_PLL_AUDIO_REG); |
741 | |
742 | /* Force PLL-MIPI to MIPI mode */ |
743 | val = readl(addr: reg + SUN8I_A23_PLL_MIPI_REG); |
744 | val &= ~BIT(16); |
745 | writel(val, addr: reg + SUN8I_A23_PLL_MIPI_REG); |
746 | |
747 | return devm_sunxi_ccu_probe(dev: &pdev->dev, reg, desc: &sun8i_a23_ccu_desc); |
748 | } |
749 | |
750 | static const struct of_device_id sun8i_a23_ccu_ids[] = { |
751 | { .compatible = "allwinner,sun8i-a23-ccu" }, |
752 | { } |
753 | }; |
754 | |
755 | static struct platform_driver sun8i_a23_ccu_driver = { |
756 | .probe = sun8i_a23_ccu_probe, |
757 | .driver = { |
758 | .name = "sun8i-a23-ccu" , |
759 | .suppress_bind_attrs = true, |
760 | .of_match_table = sun8i_a23_ccu_ids, |
761 | }, |
762 | }; |
763 | module_platform_driver(sun8i_a23_ccu_driver); |
764 | |
765 | MODULE_IMPORT_NS(SUNXI_CCU); |
766 | MODULE_LICENSE("GPL" ); |
767 | |