1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #include "reg_helper.h" |
27 | #include "core_types.h" |
28 | #include "dccg.h" |
29 | #include "clk_mgr_internal.h" |
30 | #include "dcn201_clk_mgr.h" |
31 | #include "dcn20/dcn20_clk_mgr.h" |
32 | #include "dce100/dce_clk_mgr.h" |
33 | #include "dm_helpers.h" |
34 | #include "dm_services.h" |
35 | |
36 | #include "cyan_skillfish_ip_offset.h" |
37 | #include "dcn/dcn_2_0_3_offset.h" |
38 | #include "dcn/dcn_2_0_3_sh_mask.h" |
39 | #include "clk/clk_11_0_1_offset.h" |
40 | #include "clk/clk_11_0_1_sh_mask.h" |
41 | |
42 | #define REG(reg) \ |
43 | (clk_mgr->regs->reg) |
44 | |
45 | #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg |
46 | |
47 | #define BASE(seg) BASE_INNER(seg) |
48 | |
49 | #define SR(reg_name)\ |
50 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ |
51 | mm ## reg_name |
52 | |
53 | #define CLK_BASE_INNER(seg) \ |
54 | CLK_BASE__INST0_SEG ## seg |
55 | |
56 | #undef FN |
57 | #define FN(reg_name, field_name) \ |
58 | clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name |
59 | |
60 | #define CTX \ |
61 | clk_mgr->base.ctx |
62 | |
63 | static const struct clk_mgr_registers clk_mgr_regs = { |
64 | CLK_COMMON_REG_LIST_DCN_201() |
65 | }; |
66 | |
67 | static const struct clk_mgr_shift clk_mgr_shift = { |
68 | CLK_COMMON_MASK_SH_LIST_DCN201_BASE(__SHIFT) |
69 | }; |
70 | |
71 | static const struct clk_mgr_mask clk_mgr_mask = { |
72 | CLK_COMMON_MASK_SH_LIST_DCN201_BASE(_MASK) |
73 | }; |
74 | |
75 | static void dcn201_init_clocks(struct clk_mgr *clk_mgr) |
76 | { |
77 | memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); |
78 | clk_mgr->clks.p_state_change_support = true; |
79 | clk_mgr->clks.prev_p_state_change_support = true; |
80 | clk_mgr->clks.max_supported_dppclk_khz = 1200000; |
81 | clk_mgr->clks.max_supported_dispclk_khz = 1200000; |
82 | } |
83 | |
84 | static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base, |
85 | struct dc_state *context, |
86 | bool safe_to_lower) |
87 | { |
88 | struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); |
89 | struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; |
90 | struct dc *dc = clk_mgr_base->ctx->dc; |
91 | bool update_dppclk = false; |
92 | bool update_dispclk = false; |
93 | bool dpp_clock_lowered = false; |
94 | bool force_reset = false; |
95 | bool p_state_change_support; |
96 | int total_plane_count; |
97 | |
98 | if (dc->work_arounds.skip_clock_update) |
99 | return; |
100 | |
101 | if (clk_mgr_base->clks.dispclk_khz == 0 || |
102 | dc->debug.force_clock_mode & 0x1) { |
103 | force_reset = true; |
104 | |
105 | dcn2_read_clocks_from_hw_dentist(clk_mgr_base); |
106 | } |
107 | |
108 | clk_mgr_helper_get_active_display_cnt(dc, context); |
109 | |
110 | if (should_set_clock(safe_to_lower, calc_clk: new_clocks->phyclk_khz, cur_clk: clk_mgr_base->clks.phyclk_khz)) |
111 | clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; |
112 | |
113 | if (dc->debug.force_min_dcfclk_mhz > 0) |
114 | new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? |
115 | new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); |
116 | |
117 | if (should_set_clock(safe_to_lower, calc_clk: new_clocks->dcfclk_khz, cur_clk: clk_mgr_base->clks.dcfclk_khz)) |
118 | clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; |
119 | |
120 | if (should_set_clock(safe_to_lower, |
121 | calc_clk: new_clocks->dcfclk_deep_sleep_khz, cur_clk: clk_mgr_base->clks.dcfclk_deep_sleep_khz)) |
122 | clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; |
123 | |
124 | if (should_set_clock(safe_to_lower, calc_clk: new_clocks->socclk_khz, cur_clk: clk_mgr_base->clks.socclk_khz)) |
125 | clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; |
126 | |
127 | total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context); |
128 | p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0); |
129 | if (should_update_pstate_support(safe_to_lower, calc_support: p_state_change_support, cur_support: clk_mgr_base->clks.p_state_change_support)) { |
130 | clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; |
131 | clk_mgr_base->clks.p_state_change_support = p_state_change_support; |
132 | } |
133 | |
134 | if (should_set_clock(safe_to_lower, calc_clk: new_clocks->dramclk_khz, cur_clk: clk_mgr_base->clks.dramclk_khz)) |
135 | clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; |
136 | |
137 | if (should_set_clock(safe_to_lower, calc_clk: new_clocks->dppclk_khz, cur_clk: clk_mgr->base.clks.dppclk_khz)) { |
138 | if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) |
139 | dpp_clock_lowered = true; |
140 | clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; |
141 | |
142 | update_dppclk = true; |
143 | } |
144 | |
145 | if (should_set_clock(safe_to_lower, calc_clk: new_clocks->dispclk_khz, cur_clk: clk_mgr_base->clks.dispclk_khz)) { |
146 | clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; |
147 | |
148 | update_dispclk = true; |
149 | } |
150 | |
151 | if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { |
152 | if (dpp_clock_lowered) { |
153 | dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); |
154 | dcn20_update_clocks_update_dentist(clk_mgr, context); |
155 | } else { |
156 | if (update_dppclk || update_dispclk) |
157 | dcn20_update_clocks_update_dentist(clk_mgr, context); |
158 | dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); |
159 | } |
160 | } |
161 | } |
162 | |
163 | static struct clk_mgr_funcs dcn201_funcs = { |
164 | .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, |
165 | .update_clocks = dcn201_update_clocks, |
166 | .init_clocks = dcn201_init_clocks, |
167 | .get_clock = dcn2_get_clock, |
168 | }; |
169 | |
170 | void dcn201_clk_mgr_construct(struct dc_context *ctx, |
171 | struct clk_mgr_internal *clk_mgr, |
172 | struct pp_smu_funcs *pp_smu, |
173 | struct dccg *dccg) |
174 | { |
175 | struct dc_debug_options *debug = &ctx->dc->debug; |
176 | struct dc_bios *bp = ctx->dc_bios; |
177 | clk_mgr->base.ctx = ctx; |
178 | clk_mgr->base.funcs = &dcn201_funcs; |
179 | clk_mgr->regs = &clk_mgr_regs; |
180 | clk_mgr->clk_mgr_shift = &clk_mgr_shift; |
181 | clk_mgr->clk_mgr_mask = &clk_mgr_mask; |
182 | |
183 | clk_mgr->dccg = dccg; |
184 | |
185 | clk_mgr->dfs_bypass_disp_clk = 0; |
186 | |
187 | clk_mgr->dprefclk_ss_percentage = 0; |
188 | clk_mgr->dprefclk_ss_divider = 1000; |
189 | clk_mgr->ss_on_dprefclk = false; |
190 | |
191 | clk_mgr->base.dprefclk_khz = REG_READ(CLK4_CLK2_CURRENT_CNT); |
192 | clk_mgr->base.dprefclk_khz *= 100; |
193 | |
194 | if (clk_mgr->base.dprefclk_khz == 0) |
195 | clk_mgr->base.dprefclk_khz = 600000; |
196 | |
197 | REG_GET(CLK4_CLK_PLL_REQ, FbMult_int, &clk_mgr->base.dentist_vco_freq_khz); |
198 | clk_mgr->base.dentist_vco_freq_khz *= 100000; |
199 | |
200 | if (clk_mgr->base.dentist_vco_freq_khz == 0) |
201 | clk_mgr->base.dentist_vco_freq_khz = 3000000; |
202 | |
203 | if (!debug->disable_dfs_bypass && bp->integrated_info) |
204 | if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) |
205 | clk_mgr->dfs_bypass_enabled = true; |
206 | |
207 | dce_clock_read_ss_info(dccg_dce: clk_mgr); |
208 | } |
209 | |