1 | /* |
2 | * Copyright 2015 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #include "dm_services.h" |
27 | #include "core_types.h" |
28 | #include "timing_generator.h" |
29 | #include "hw_sequencer.h" |
30 | #include "hw_sequencer_private.h" |
31 | #include "basics/dc_common.h" |
32 | #include "resource.h" |
33 | #include "dc_dmub_srv.h" |
34 | #include "dc_state_priv.h" |
35 | |
36 | #define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0])) |
37 | |
38 | /* used as index in array of black_color_format */ |
39 | enum black_color_format { |
40 | BLACK_COLOR_FORMAT_RGB_FULLRANGE = 0, |
41 | BLACK_COLOR_FORMAT_RGB_LIMITED, |
42 | BLACK_COLOR_FORMAT_YUV_TV, |
43 | BLACK_COLOR_FORMAT_YUV_CV, |
44 | BLACK_COLOR_FORMAT_YUV_SUPER_AA, |
45 | BLACK_COLOR_FORMAT_DEBUG, |
46 | }; |
47 | |
48 | enum dc_color_space_type { |
49 | COLOR_SPACE_RGB_TYPE, |
50 | COLOR_SPACE_RGB_LIMITED_TYPE, |
51 | COLOR_SPACE_YCBCR601_TYPE, |
52 | COLOR_SPACE_YCBCR709_TYPE, |
53 | COLOR_SPACE_YCBCR2020_TYPE, |
54 | COLOR_SPACE_YCBCR601_LIMITED_TYPE, |
55 | COLOR_SPACE_YCBCR709_LIMITED_TYPE, |
56 | COLOR_SPACE_YCBCR709_BLACK_TYPE, |
57 | }; |
58 | |
59 | static const struct tg_color black_color_format[] = { |
60 | /* BlackColorFormat_RGB_FullRange */ |
61 | {0, 0, 0}, |
62 | /* BlackColorFormat_RGB_Limited */ |
63 | {0x40, 0x40, 0x40}, |
64 | /* BlackColorFormat_YUV_TV */ |
65 | {0x200, 0x40, 0x200}, |
66 | /* BlackColorFormat_YUV_CV */ |
67 | {0x1f4, 0x40, 0x1f4}, |
68 | /* BlackColorFormat_YUV_SuperAA */ |
69 | {0x1a2, 0x20, 0x1a2}, |
70 | /* visual confirm debug */ |
71 | {0xff, 0xff, 0}, |
72 | }; |
73 | |
74 | struct out_csc_color_matrix_type { |
75 | enum dc_color_space_type color_space_type; |
76 | uint16_t regval[12]; |
77 | }; |
78 | |
79 | static const struct out_csc_color_matrix_type output_csc_matrix[] = { |
80 | { COLOR_SPACE_RGB_TYPE, |
81 | { 0x2000, 0, 0, 0, |
82 | 0, 0x2000, 0, 0, |
83 | 0, 0, 0x2000, 0} }, |
84 | { COLOR_SPACE_RGB_LIMITED_TYPE, |
85 | { 0x1B67, 0, 0, 0x201, |
86 | 0, 0x1B67, 0, 0x201, |
87 | 0, 0, 0x1B67, 0x201} }, |
88 | { COLOR_SPACE_YCBCR601_TYPE, |
89 | { 0xE04, 0xF444, 0xFDB9, 0x1004, |
90 | 0x831, 0x1016, 0x320, 0x201, |
91 | 0xFB45, 0xF6B7, 0xE04, 0x1004} }, |
92 | { COLOR_SPACE_YCBCR709_TYPE, |
93 | { 0xE04, 0xF345, 0xFEB7, 0x1004, |
94 | 0x5D3, 0x1399, 0x1FA, 0x201, |
95 | 0xFCCA, 0xF533, 0xE04, 0x1004} }, |
96 | /* TODO: correct values below */ |
97 | { COLOR_SPACE_YCBCR601_LIMITED_TYPE, |
98 | { 0xE00, 0xF447, 0xFDB9, 0x1000, |
99 | 0x991, 0x12C9, 0x3A6, 0x200, |
100 | 0xFB47, 0xF6B9, 0xE00, 0x1000} }, |
101 | { COLOR_SPACE_YCBCR709_LIMITED_TYPE, |
102 | { 0xE00, 0xF349, 0xFEB7, 0x1000, |
103 | 0x6CE, 0x16E3, 0x24F, 0x200, |
104 | 0xFCCB, 0xF535, 0xE00, 0x1000} }, |
105 | { COLOR_SPACE_YCBCR2020_TYPE, |
106 | { 0x1000, 0xF149, 0xFEB7, 0x1004, |
107 | 0x0868, 0x15B2, 0x01E6, 0x201, |
108 | 0xFB88, 0xF478, 0x1000, 0x1004} }, |
109 | { COLOR_SPACE_YCBCR709_BLACK_TYPE, |
110 | { 0x0000, 0x0000, 0x0000, 0x1000, |
111 | 0x0000, 0x0000, 0x0000, 0x0200, |
112 | 0x0000, 0x0000, 0x0000, 0x1000} }, |
113 | }; |
114 | |
115 | static bool is_rgb_type( |
116 | enum dc_color_space color_space) |
117 | { |
118 | bool ret = false; |
119 | |
120 | if (color_space == COLOR_SPACE_SRGB || |
121 | color_space == COLOR_SPACE_XR_RGB || |
122 | color_space == COLOR_SPACE_MSREF_SCRGB || |
123 | color_space == COLOR_SPACE_2020_RGB_FULLRANGE || |
124 | color_space == COLOR_SPACE_ADOBERGB || |
125 | color_space == COLOR_SPACE_DCIP3 || |
126 | color_space == COLOR_SPACE_DOLBYVISION) |
127 | ret = true; |
128 | return ret; |
129 | } |
130 | |
131 | static bool is_rgb_limited_type( |
132 | enum dc_color_space color_space) |
133 | { |
134 | bool ret = false; |
135 | |
136 | if (color_space == COLOR_SPACE_SRGB_LIMITED || |
137 | color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) |
138 | ret = true; |
139 | return ret; |
140 | } |
141 | |
142 | static bool is_ycbcr601_type( |
143 | enum dc_color_space color_space) |
144 | { |
145 | bool ret = false; |
146 | |
147 | if (color_space == COLOR_SPACE_YCBCR601 || |
148 | color_space == COLOR_SPACE_XV_YCC_601) |
149 | ret = true; |
150 | return ret; |
151 | } |
152 | |
153 | static bool is_ycbcr601_limited_type( |
154 | enum dc_color_space color_space) |
155 | { |
156 | bool ret = false; |
157 | |
158 | if (color_space == COLOR_SPACE_YCBCR601_LIMITED) |
159 | ret = true; |
160 | return ret; |
161 | } |
162 | |
163 | static bool is_ycbcr709_type( |
164 | enum dc_color_space color_space) |
165 | { |
166 | bool ret = false; |
167 | |
168 | if (color_space == COLOR_SPACE_YCBCR709 || |
169 | color_space == COLOR_SPACE_XV_YCC_709) |
170 | ret = true; |
171 | return ret; |
172 | } |
173 | |
174 | static bool is_ycbcr2020_type( |
175 | enum dc_color_space color_space) |
176 | { |
177 | bool ret = false; |
178 | |
179 | if (color_space == COLOR_SPACE_2020_YCBCR) |
180 | ret = true; |
181 | return ret; |
182 | } |
183 | |
184 | static bool is_ycbcr709_limited_type( |
185 | enum dc_color_space color_space) |
186 | { |
187 | bool ret = false; |
188 | |
189 | if (color_space == COLOR_SPACE_YCBCR709_LIMITED) |
190 | ret = true; |
191 | return ret; |
192 | } |
193 | |
194 | static enum dc_color_space_type get_color_space_type(enum dc_color_space color_space) |
195 | { |
196 | enum dc_color_space_type type = COLOR_SPACE_RGB_TYPE; |
197 | |
198 | if (is_rgb_type(color_space)) |
199 | type = COLOR_SPACE_RGB_TYPE; |
200 | else if (is_rgb_limited_type(color_space)) |
201 | type = COLOR_SPACE_RGB_LIMITED_TYPE; |
202 | else if (is_ycbcr601_type(color_space)) |
203 | type = COLOR_SPACE_YCBCR601_TYPE; |
204 | else if (is_ycbcr709_type(color_space)) |
205 | type = COLOR_SPACE_YCBCR709_TYPE; |
206 | else if (is_ycbcr601_limited_type(color_space)) |
207 | type = COLOR_SPACE_YCBCR601_LIMITED_TYPE; |
208 | else if (is_ycbcr709_limited_type(color_space)) |
209 | type = COLOR_SPACE_YCBCR709_LIMITED_TYPE; |
210 | else if (is_ycbcr2020_type(color_space)) |
211 | type = COLOR_SPACE_YCBCR2020_TYPE; |
212 | else if (color_space == COLOR_SPACE_YCBCR709) |
213 | type = COLOR_SPACE_YCBCR709_BLACK_TYPE; |
214 | else if (color_space == COLOR_SPACE_YCBCR709_BLACK) |
215 | type = COLOR_SPACE_YCBCR709_BLACK_TYPE; |
216 | return type; |
217 | } |
218 | |
219 | const uint16_t *find_color_matrix(enum dc_color_space color_space, |
220 | uint32_t *array_size) |
221 | { |
222 | int i; |
223 | enum dc_color_space_type type; |
224 | const uint16_t *val = NULL; |
225 | int arr_size = NUM_ELEMENTS(output_csc_matrix); |
226 | |
227 | type = get_color_space_type(color_space); |
228 | for (i = 0; i < arr_size; i++) |
229 | if (output_csc_matrix[i].color_space_type == type) { |
230 | val = output_csc_matrix[i].regval; |
231 | *array_size = 12; |
232 | break; |
233 | } |
234 | |
235 | return val; |
236 | } |
237 | |
238 | |
239 | void color_space_to_black_color( |
240 | const struct dc *dc, |
241 | enum dc_color_space colorspace, |
242 | struct tg_color *black_color) |
243 | { |
244 | switch (colorspace) { |
245 | case COLOR_SPACE_YCBCR601: |
246 | case COLOR_SPACE_YCBCR709: |
247 | case COLOR_SPACE_YCBCR709_BLACK: |
248 | case COLOR_SPACE_YCBCR601_LIMITED: |
249 | case COLOR_SPACE_YCBCR709_LIMITED: |
250 | case COLOR_SPACE_2020_YCBCR: |
251 | *black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV]; |
252 | break; |
253 | |
254 | case COLOR_SPACE_SRGB_LIMITED: |
255 | *black_color = |
256 | black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED]; |
257 | break; |
258 | |
259 | /** |
260 | * Remove default and add case for all color space |
261 | * so when we forget to add new color space |
262 | * compiler will give a warning |
263 | */ |
264 | case COLOR_SPACE_UNKNOWN: |
265 | case COLOR_SPACE_SRGB: |
266 | case COLOR_SPACE_XR_RGB: |
267 | case COLOR_SPACE_MSREF_SCRGB: |
268 | case COLOR_SPACE_XV_YCC_709: |
269 | case COLOR_SPACE_XV_YCC_601: |
270 | case COLOR_SPACE_2020_RGB_FULLRANGE: |
271 | case COLOR_SPACE_2020_RGB_LIMITEDRANGE: |
272 | case COLOR_SPACE_ADOBERGB: |
273 | case COLOR_SPACE_DCIP3: |
274 | case COLOR_SPACE_DISPLAYNATIVE: |
275 | case COLOR_SPACE_DOLBYVISION: |
276 | case COLOR_SPACE_APPCTRL: |
277 | case COLOR_SPACE_CUSTOMPOINTS: |
278 | /* fefault is sRGB black (full range). */ |
279 | *black_color = |
280 | black_color_format[BLACK_COLOR_FORMAT_RGB_FULLRANGE]; |
281 | /* default is sRGB black 0. */ |
282 | break; |
283 | } |
284 | } |
285 | |
286 | bool hwss_wait_for_blank_complete( |
287 | struct timing_generator *tg) |
288 | { |
289 | int counter; |
290 | |
291 | /* Not applicable if the pipe is not primary, save 300ms of boot time */ |
292 | if (!tg->funcs->is_blanked) |
293 | return true; |
294 | for (counter = 0; counter < 100; counter++) { |
295 | if (tg->funcs->is_blanked(tg)) |
296 | break; |
297 | |
298 | msleep(msecs: 1); |
299 | } |
300 | |
301 | if (counter == 100) { |
302 | dm_error("DC: failed to blank crtc!\n" ); |
303 | return false; |
304 | } |
305 | |
306 | return true; |
307 | } |
308 | |
309 | void get_mpctree_visual_confirm_color( |
310 | struct pipe_ctx *pipe_ctx, |
311 | struct tg_color *color) |
312 | { |
313 | const struct tg_color pipe_colors[6] = { |
314 | {MAX_TG_COLOR_VALUE, 0, 0}, /* red */ |
315 | {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE / 4, 0}, /* orange */ |
316 | {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */ |
317 | {0, MAX_TG_COLOR_VALUE, 0}, /* green */ |
318 | {0, 0, MAX_TG_COLOR_VALUE}, /* blue */ |
319 | {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, /* purple */ |
320 | }; |
321 | |
322 | struct pipe_ctx *top_pipe = pipe_ctx; |
323 | |
324 | while (top_pipe->top_pipe) |
325 | top_pipe = top_pipe->top_pipe; |
326 | |
327 | *color = pipe_colors[top_pipe->pipe_idx]; |
328 | } |
329 | |
330 | void get_surface_visual_confirm_color( |
331 | const struct pipe_ctx *pipe_ctx, |
332 | struct tg_color *color) |
333 | { |
334 | uint32_t color_value = MAX_TG_COLOR_VALUE; |
335 | |
336 | switch (pipe_ctx->plane_res.scl_data.format) { |
337 | case PIXEL_FORMAT_ARGB8888: |
338 | /* set border color to red */ |
339 | color->color_r_cr = color_value; |
340 | if (pipe_ctx->plane_state->layer_index > 0) { |
341 | /* set border color to pink */ |
342 | color->color_b_cb = color_value; |
343 | color->color_g_y = color_value * 0.5; |
344 | } |
345 | break; |
346 | |
347 | case PIXEL_FORMAT_ARGB2101010: |
348 | /* set border color to blue */ |
349 | color->color_b_cb = color_value; |
350 | if (pipe_ctx->plane_state->layer_index > 0) { |
351 | /* set border color to cyan */ |
352 | color->color_g_y = color_value; |
353 | } |
354 | break; |
355 | case PIXEL_FORMAT_420BPP8: |
356 | /* set border color to green */ |
357 | color->color_g_y = color_value; |
358 | break; |
359 | case PIXEL_FORMAT_420BPP10: |
360 | /* set border color to yellow */ |
361 | color->color_g_y = color_value; |
362 | color->color_r_cr = color_value; |
363 | break; |
364 | case PIXEL_FORMAT_FP16: |
365 | /* set border color to white */ |
366 | color->color_r_cr = color_value; |
367 | color->color_b_cb = color_value; |
368 | color->color_g_y = color_value; |
369 | if (pipe_ctx->plane_state->layer_index > 0) { |
370 | /* set border color to orange */ |
371 | color->color_g_y = 0.22 * color_value; |
372 | color->color_b_cb = 0; |
373 | } |
374 | break; |
375 | default: |
376 | break; |
377 | } |
378 | } |
379 | |
380 | void get_hdr_visual_confirm_color( |
381 | struct pipe_ctx *pipe_ctx, |
382 | struct tg_color *color) |
383 | { |
384 | uint32_t color_value = MAX_TG_COLOR_VALUE; |
385 | bool is_sdr = false; |
386 | |
387 | /* Determine the overscan color based on the top-most (desktop) plane's context */ |
388 | struct pipe_ctx *top_pipe_ctx = pipe_ctx; |
389 | |
390 | while (top_pipe_ctx->top_pipe != NULL) |
391 | top_pipe_ctx = top_pipe_ctx->top_pipe; |
392 | |
393 | switch (top_pipe_ctx->plane_res.scl_data.format) { |
394 | case PIXEL_FORMAT_ARGB2101010: |
395 | if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) { |
396 | /* HDR10, ARGB2101010 - set border color to red */ |
397 | color->color_r_cr = color_value; |
398 | } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) { |
399 | /* FreeSync 2 ARGB2101010 - set border color to pink */ |
400 | color->color_r_cr = color_value; |
401 | color->color_b_cb = color_value; |
402 | } else |
403 | is_sdr = true; |
404 | break; |
405 | case PIXEL_FORMAT_FP16: |
406 | if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) { |
407 | /* HDR10, FP16 - set border color to blue */ |
408 | color->color_b_cb = color_value; |
409 | } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) { |
410 | /* FreeSync 2 HDR - set border color to green */ |
411 | color->color_g_y = color_value; |
412 | } else |
413 | is_sdr = true; |
414 | break; |
415 | default: |
416 | is_sdr = true; |
417 | break; |
418 | } |
419 | |
420 | if (is_sdr) { |
421 | /* SDR - set border color to Gray */ |
422 | color->color_r_cr = color_value/2; |
423 | color->color_b_cb = color_value/2; |
424 | color->color_g_y = color_value/2; |
425 | } |
426 | } |
427 | |
428 | void get_subvp_visual_confirm_color( |
429 | struct pipe_ctx *pipe_ctx, |
430 | struct tg_color *color) |
431 | { |
432 | uint32_t color_value = MAX_TG_COLOR_VALUE; |
433 | if (pipe_ctx) { |
434 | switch (pipe_ctx->p_state_type) { |
435 | case P_STATE_SUB_VP: |
436 | color->color_r_cr = color_value; |
437 | color->color_g_y = 0; |
438 | color->color_b_cb = 0; |
439 | break; |
440 | case P_STATE_DRR_SUB_VP: |
441 | color->color_r_cr = 0; |
442 | color->color_g_y = color_value; |
443 | color->color_b_cb = 0; |
444 | break; |
445 | case P_STATE_V_BLANK_SUB_VP: |
446 | color->color_r_cr = 0; |
447 | color->color_g_y = 0; |
448 | color->color_b_cb = color_value; |
449 | break; |
450 | default: |
451 | break; |
452 | } |
453 | } |
454 | } |
455 | |
456 | void get_mclk_switch_visual_confirm_color( |
457 | struct pipe_ctx *pipe_ctx, |
458 | struct tg_color *color) |
459 | { |
460 | uint32_t color_value = MAX_TG_COLOR_VALUE; |
461 | |
462 | if (pipe_ctx) { |
463 | switch (pipe_ctx->p_state_type) { |
464 | case P_STATE_V_BLANK: |
465 | color->color_r_cr = color_value; |
466 | color->color_g_y = color_value; |
467 | color->color_b_cb = 0; |
468 | break; |
469 | case P_STATE_FPO: |
470 | color->color_r_cr = 0; |
471 | color->color_g_y = color_value; |
472 | color->color_b_cb = color_value; |
473 | break; |
474 | case P_STATE_V_ACTIVE: |
475 | color->color_r_cr = color_value; |
476 | color->color_g_y = 0; |
477 | color->color_b_cb = color_value; |
478 | break; |
479 | case P_STATE_SUB_VP: |
480 | color->color_r_cr = color_value; |
481 | color->color_g_y = 0; |
482 | color->color_b_cb = 0; |
483 | break; |
484 | case P_STATE_DRR_SUB_VP: |
485 | color->color_r_cr = 0; |
486 | color->color_g_y = color_value; |
487 | color->color_b_cb = 0; |
488 | break; |
489 | case P_STATE_V_BLANK_SUB_VP: |
490 | color->color_r_cr = 0; |
491 | color->color_g_y = 0; |
492 | color->color_b_cb = color_value; |
493 | break; |
494 | default: |
495 | break; |
496 | } |
497 | } |
498 | } |
499 | |
500 | void set_p_state_switch_method( |
501 | struct dc *dc, |
502 | struct dc_state *context, |
503 | struct pipe_ctx *pipe_ctx) |
504 | { |
505 | struct vba_vars_st *vba = &context->bw_ctx.dml.vba; |
506 | bool enable_subvp; |
507 | |
508 | if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba || !context) |
509 | return; |
510 | |
511 | if (vba->DRAMClockChangeSupport[vba->VoltageLevel][vba->maxMpcComb] != |
512 | dm_dram_clock_change_unsupported) { |
513 | /* MCLK switching is supported */ |
514 | if (!pipe_ctx->has_vactive_margin) { |
515 | /* In Vblank - yellow */ |
516 | pipe_ctx->p_state_type = P_STATE_V_BLANK; |
517 | |
518 | if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { |
519 | /* FPO + Vblank - cyan */ |
520 | pipe_ctx->p_state_type = P_STATE_FPO; |
521 | } |
522 | } else { |
523 | /* In Vactive - pink */ |
524 | pipe_ctx->p_state_type = P_STATE_V_ACTIVE; |
525 | } |
526 | |
527 | /* SubVP */ |
528 | enable_subvp = false; |
529 | |
530 | for (int i = 0; i < dc->res_pool->pipe_count; i++) { |
531 | struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; |
532 | |
533 | if (pipe->stream && dc_state_get_paired_subvp_stream(state: context, stream: pipe->stream) && |
534 | dc_state_get_pipe_subvp_type(state: context, pipe_ctx: pipe) == SUBVP_MAIN) { |
535 | /* SubVP enable - red */ |
536 | pipe_ctx->p_state_type = P_STATE_SUB_VP; |
537 | enable_subvp = true; |
538 | |
539 | if (pipe_ctx->stream == pipe->stream) |
540 | return; |
541 | break; |
542 | } |
543 | } |
544 | |
545 | if (enable_subvp && dc_state_get_pipe_subvp_type(state: context, pipe_ctx) == SUBVP_NONE) { |
546 | if (pipe_ctx->stream->allow_freesync == 1) { |
547 | /* SubVP enable and DRR on - green */ |
548 | pipe_ctx->p_state_type = P_STATE_DRR_SUB_VP; |
549 | } else { |
550 | /* SubVP enable and No DRR - blue */ |
551 | pipe_ctx->p_state_type = P_STATE_V_BLANK_SUB_VP; |
552 | } |
553 | } |
554 | } |
555 | } |
556 | |
557 | void hwss_build_fast_sequence(struct dc *dc, |
558 | struct dc_dmub_cmd *dc_dmub_cmd, |
559 | unsigned int dmub_cmd_count, |
560 | struct block_sequence block_sequence[], |
561 | int *num_steps, |
562 | struct pipe_ctx *pipe_ctx, |
563 | struct dc_stream_status *stream_status) |
564 | { |
565 | struct dc_plane_state *plane = pipe_ctx->plane_state; |
566 | struct dc_stream_state *stream = pipe_ctx->stream; |
567 | struct dce_hwseq *hws = dc->hwseq; |
568 | struct pipe_ctx *current_pipe = NULL; |
569 | struct pipe_ctx *current_mpc_pipe = NULL; |
570 | unsigned int i = 0; |
571 | |
572 | *num_steps = 0; // Initialize to 0 |
573 | |
574 | if (!plane || !stream) |
575 | return; |
576 | |
577 | if (dc->hwss.subvp_pipe_control_lock_fast) { |
578 | block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc; |
579 | block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true; |
580 | block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip = |
581 | plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN; |
582 | block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST; |
583 | (*num_steps)++; |
584 | } |
585 | if (dc->hwss.pipe_control_lock) { |
586 | block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc; |
587 | block_sequence[*num_steps].params.pipe_control_lock_params.lock = true; |
588 | block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx; |
589 | block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK; |
590 | (*num_steps)++; |
591 | } |
592 | |
593 | for (i = 0; i < dmub_cmd_count; i++) { |
594 | block_sequence[*num_steps].params.send_dmcub_cmd_params.ctx = dc->ctx; |
595 | block_sequence[*num_steps].params.send_dmcub_cmd_params.cmd = &(dc_dmub_cmd[i].dmub_cmd); |
596 | block_sequence[*num_steps].params.send_dmcub_cmd_params.wait_type = dc_dmub_cmd[i].wait_type; |
597 | block_sequence[*num_steps].func = DMUB_SEND_DMCUB_CMD; |
598 | (*num_steps)++; |
599 | } |
600 | |
601 | current_pipe = pipe_ctx; |
602 | while (current_pipe) { |
603 | current_mpc_pipe = current_pipe; |
604 | while (current_mpc_pipe) { |
605 | if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state && current_mpc_pipe->plane_state->update_flags.raw) { |
606 | block_sequence[*num_steps].params.set_flip_control_gsl_params.pipe_ctx = current_mpc_pipe; |
607 | block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate; |
608 | block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL; |
609 | (*num_steps)++; |
610 | } |
611 | if (dc->hwss.program_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->update_flags.raw) { |
612 | block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc; |
613 | block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe; |
614 | block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe->plane_state->triplebuffer_flips; |
615 | block_sequence[*num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER; |
616 | (*num_steps)++; |
617 | } |
618 | if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) { |
619 | if (resource_is_pipe_type(pipe_ctx: current_mpc_pipe, type: OTG_MASTER) && |
620 | stream_status->mall_stream_config.type == SUBVP_MAIN) { |
621 | block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv; |
622 | block_sequence[*num_steps].params.subvp_save_surf_addr.addr = ¤t_mpc_pipe->plane_state->address; |
623 | block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe->subvp_index; |
624 | block_sequence[*num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR; |
625 | (*num_steps)++; |
626 | } |
627 | |
628 | block_sequence[*num_steps].params.update_plane_addr_params.dc = dc; |
629 | block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe; |
630 | block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR; |
631 | (*num_steps)++; |
632 | } |
633 | |
634 | if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) { |
635 | block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc; |
636 | block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe; |
637 | block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state; |
638 | block_sequence[*num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC; |
639 | (*num_steps)++; |
640 | } |
641 | |
642 | if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change) { |
643 | block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe; |
644 | block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP; |
645 | (*num_steps)++; |
646 | } |
647 | if (current_mpc_pipe->plane_state->update_flags.bits.input_csc_change) { |
648 | block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe; |
649 | block_sequence[*num_steps].func = DPP_SETUP_DPP; |
650 | (*num_steps)++; |
651 | } |
652 | if (current_mpc_pipe->plane_state->update_flags.bits.coeff_reduction_change) { |
653 | block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe; |
654 | block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE; |
655 | (*num_steps)++; |
656 | } |
657 | if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) { |
658 | block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc; |
659 | block_sequence[*num_steps].params.set_output_transfer_func_params.pipe_ctx = current_mpc_pipe; |
660 | block_sequence[*num_steps].params.set_output_transfer_func_params.stream = current_mpc_pipe->stream; |
661 | block_sequence[*num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC; |
662 | (*num_steps)++; |
663 | } |
664 | |
665 | if (current_mpc_pipe->stream->update_flags.bits.out_csc) { |
666 | block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpc = dc->res_pool->mpc; |
667 | block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.mpcc_id = current_mpc_pipe->plane_res.hubp->inst; |
668 | block_sequence[*num_steps].params.power_on_mpc_mem_pwr_params.power_on = true; |
669 | block_sequence[*num_steps].func = MPC_POWER_ON_MPC_MEM_PWR; |
670 | (*num_steps)++; |
671 | |
672 | if (current_mpc_pipe->stream->csc_color_matrix.enable_adjustment == true) { |
673 | block_sequence[*num_steps].params.set_output_csc_params.mpc = dc->res_pool->mpc; |
674 | block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst; |
675 | block_sequence[*num_steps].params.set_output_csc_params.regval = current_mpc_pipe->stream->csc_color_matrix.matrix; |
676 | block_sequence[*num_steps].params.set_output_csc_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A; |
677 | block_sequence[*num_steps].func = MPC_SET_OUTPUT_CSC; |
678 | (*num_steps)++; |
679 | } else { |
680 | block_sequence[*num_steps].params.set_ocsc_default_params.mpc = dc->res_pool->mpc; |
681 | block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst; |
682 | block_sequence[*num_steps].params.set_ocsc_default_params.color_space = current_mpc_pipe->stream->output_color_space; |
683 | block_sequence[*num_steps].params.set_ocsc_default_params.ocsc_mode = MPC_OUTPUT_CSC_COEF_A; |
684 | block_sequence[*num_steps].func = MPC_SET_OCSC_DEFAULT; |
685 | (*num_steps)++; |
686 | } |
687 | } |
688 | current_mpc_pipe = current_mpc_pipe->bottom_pipe; |
689 | } |
690 | current_pipe = current_pipe->next_odm_pipe; |
691 | } |
692 | |
693 | if (dc->hwss.pipe_control_lock) { |
694 | block_sequence[*num_steps].params.pipe_control_lock_params.dc = dc; |
695 | block_sequence[*num_steps].params.pipe_control_lock_params.lock = false; |
696 | block_sequence[*num_steps].params.pipe_control_lock_params.pipe_ctx = pipe_ctx; |
697 | block_sequence[*num_steps].func = OPTC_PIPE_CONTROL_LOCK; |
698 | (*num_steps)++; |
699 | } |
700 | if (dc->hwss.subvp_pipe_control_lock_fast) { |
701 | block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc; |
702 | block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = false; |
703 | block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip = |
704 | plane->flip_immediate && stream_status->mall_stream_config.type == SUBVP_MAIN; |
705 | block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST; |
706 | (*num_steps)++; |
707 | } |
708 | |
709 | current_pipe = pipe_ctx; |
710 | while (current_pipe) { |
711 | current_mpc_pipe = current_pipe; |
712 | |
713 | while (current_mpc_pipe) { |
714 | if (!current_mpc_pipe->bottom_pipe && !current_mpc_pipe->next_odm_pipe && |
715 | current_mpc_pipe->stream && current_mpc_pipe->plane_state && |
716 | current_mpc_pipe->plane_state->update_flags.bits.addr_update && |
717 | !current_mpc_pipe->plane_state->skip_manual_trigger) { |
718 | block_sequence[*num_steps].params.program_manual_trigger_params.pipe_ctx = current_mpc_pipe; |
719 | block_sequence[*num_steps].func = OPTC_PROGRAM_MANUAL_TRIGGER; |
720 | (*num_steps)++; |
721 | } |
722 | current_mpc_pipe = current_mpc_pipe->bottom_pipe; |
723 | } |
724 | current_pipe = current_pipe->next_odm_pipe; |
725 | } |
726 | } |
727 | |
728 | void hwss_execute_sequence(struct dc *dc, |
729 | struct block_sequence block_sequence[], |
730 | int num_steps) |
731 | { |
732 | unsigned int i; |
733 | union block_sequence_params *params; |
734 | struct dce_hwseq *hws = dc->hwseq; |
735 | |
736 | for (i = 0; i < num_steps; i++) { |
737 | params = &(block_sequence[i].params); |
738 | switch (block_sequence[i].func) { |
739 | |
740 | case DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST: |
741 | dc->hwss.subvp_pipe_control_lock_fast(params); |
742 | break; |
743 | case OPTC_PIPE_CONTROL_LOCK: |
744 | dc->hwss.pipe_control_lock(params->pipe_control_lock_params.dc, |
745 | params->pipe_control_lock_params.pipe_ctx, |
746 | params->pipe_control_lock_params.lock); |
747 | break; |
748 | case HUBP_SET_FLIP_CONTROL_GSL: |
749 | dc->hwss.set_flip_control_gsl(params->set_flip_control_gsl_params.pipe_ctx, |
750 | params->set_flip_control_gsl_params.flip_immediate); |
751 | break; |
752 | case HUBP_PROGRAM_TRIPLEBUFFER: |
753 | dc->hwss.program_triplebuffer(params->program_triplebuffer_params.dc, |
754 | params->program_triplebuffer_params.pipe_ctx, |
755 | params->program_triplebuffer_params.enableTripleBuffer); |
756 | break; |
757 | case HUBP_UPDATE_PLANE_ADDR: |
758 | dc->hwss.update_plane_addr(params->update_plane_addr_params.dc, |
759 | params->update_plane_addr_params.pipe_ctx); |
760 | break; |
761 | case DPP_SET_INPUT_TRANSFER_FUNC: |
762 | hws->funcs.set_input_transfer_func(params->set_input_transfer_func_params.dc, |
763 | params->set_input_transfer_func_params.pipe_ctx, |
764 | params->set_input_transfer_func_params.plane_state); |
765 | break; |
766 | case DPP_PROGRAM_GAMUT_REMAP: |
767 | dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx); |
768 | break; |
769 | case DPP_SETUP_DPP: |
770 | hwss_setup_dpp(params); |
771 | break; |
772 | case DPP_PROGRAM_BIAS_AND_SCALE: |
773 | hwss_program_bias_and_scale(params); |
774 | break; |
775 | case OPTC_PROGRAM_MANUAL_TRIGGER: |
776 | hwss_program_manual_trigger(params); |
777 | break; |
778 | case DPP_SET_OUTPUT_TRANSFER_FUNC: |
779 | hws->funcs.set_output_transfer_func(params->set_output_transfer_func_params.dc, |
780 | params->set_output_transfer_func_params.pipe_ctx, |
781 | params->set_output_transfer_func_params.stream); |
782 | break; |
783 | case MPC_UPDATE_VISUAL_CONFIRM: |
784 | dc->hwss.update_visual_confirm_color(params->update_visual_confirm_params.dc, |
785 | params->update_visual_confirm_params.pipe_ctx, |
786 | params->update_visual_confirm_params.mpcc_id); |
787 | break; |
788 | case MPC_POWER_ON_MPC_MEM_PWR: |
789 | hwss_power_on_mpc_mem_pwr(params); |
790 | break; |
791 | case MPC_SET_OUTPUT_CSC: |
792 | hwss_set_output_csc(params); |
793 | break; |
794 | case MPC_SET_OCSC_DEFAULT: |
795 | hwss_set_ocsc_default(params); |
796 | break; |
797 | case DMUB_SEND_DMCUB_CMD: |
798 | hwss_send_dmcub_cmd(params); |
799 | break; |
800 | case DMUB_SUBVP_SAVE_SURF_ADDR: |
801 | hwss_subvp_save_surf_addr(params); |
802 | break; |
803 | default: |
804 | ASSERT(false); |
805 | break; |
806 | } |
807 | } |
808 | } |
809 | |
810 | void hwss_send_dmcub_cmd(union block_sequence_params *params) |
811 | { |
812 | struct dc_context *ctx = params->send_dmcub_cmd_params.ctx; |
813 | union dmub_rb_cmd *cmd = params->send_dmcub_cmd_params.cmd; |
814 | enum dm_dmub_wait_type wait_type = params->send_dmcub_cmd_params.wait_type; |
815 | |
816 | dc_wake_and_execute_dmub_cmd(ctx, cmd, wait_type); |
817 | } |
818 | |
819 | void hwss_program_manual_trigger(union block_sequence_params *params) |
820 | { |
821 | struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx; |
822 | |
823 | if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger) |
824 | pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); |
825 | } |
826 | |
827 | void hwss_setup_dpp(union block_sequence_params *params) |
828 | { |
829 | struct pipe_ctx *pipe_ctx = params->setup_dpp_params.pipe_ctx; |
830 | struct dpp *dpp = pipe_ctx->plane_res.dpp; |
831 | struct dc_plane_state *plane_state = pipe_ctx->plane_state; |
832 | |
833 | if (dpp && dpp->funcs->dpp_setup) { |
834 | // program the input csc |
835 | dpp->funcs->dpp_setup(dpp, |
836 | plane_state->format, |
837 | EXPANSION_MODE_ZERO, |
838 | plane_state->input_csc_color_matrix, |
839 | plane_state->color_space, |
840 | NULL); |
841 | } |
842 | } |
843 | |
844 | void hwss_program_bias_and_scale(union block_sequence_params *params) |
845 | { |
846 | struct pipe_ctx *pipe_ctx = params->program_bias_and_scale_params.pipe_ctx; |
847 | struct dpp *dpp = pipe_ctx->plane_res.dpp; |
848 | struct dc_plane_state *plane_state = pipe_ctx->plane_state; |
849 | struct dc_bias_and_scale bns_params = {0}; |
850 | |
851 | //TODO :for CNVC set scale and bias registers if necessary |
852 | build_prescale_params(bias_and_scale: &bns_params, plane_state); |
853 | if (dpp->funcs->dpp_program_bias_and_scale) |
854 | dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); |
855 | } |
856 | |
857 | void hwss_power_on_mpc_mem_pwr(union block_sequence_params *params) |
858 | { |
859 | struct mpc *mpc = params->power_on_mpc_mem_pwr_params.mpc; |
860 | int mpcc_id = params->power_on_mpc_mem_pwr_params.mpcc_id; |
861 | bool power_on = params->power_on_mpc_mem_pwr_params.power_on; |
862 | |
863 | if (mpc->funcs->power_on_mpc_mem_pwr) |
864 | mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, power_on); |
865 | } |
866 | |
867 | void hwss_set_output_csc(union block_sequence_params *params) |
868 | { |
869 | struct mpc *mpc = params->set_output_csc_params.mpc; |
870 | int opp_id = params->set_output_csc_params.opp_id; |
871 | const uint16_t *matrix = params->set_output_csc_params.regval; |
872 | enum mpc_output_csc_mode ocsc_mode = params->set_output_csc_params.ocsc_mode; |
873 | |
874 | if (mpc->funcs->set_output_csc != NULL) |
875 | mpc->funcs->set_output_csc(mpc, |
876 | opp_id, |
877 | matrix, |
878 | ocsc_mode); |
879 | } |
880 | |
881 | void hwss_set_ocsc_default(union block_sequence_params *params) |
882 | { |
883 | struct mpc *mpc = params->set_ocsc_default_params.mpc; |
884 | int opp_id = params->set_ocsc_default_params.opp_id; |
885 | enum dc_color_space colorspace = params->set_ocsc_default_params.color_space; |
886 | enum mpc_output_csc_mode ocsc_mode = params->set_ocsc_default_params.ocsc_mode; |
887 | |
888 | if (mpc->funcs->set_ocsc_default != NULL) |
889 | mpc->funcs->set_ocsc_default(mpc, |
890 | opp_id, |
891 | colorspace, |
892 | ocsc_mode); |
893 | } |
894 | |
895 | void hwss_subvp_save_surf_addr(union block_sequence_params *params) |
896 | { |
897 | struct dc_dmub_srv *dc_dmub_srv = params->subvp_save_surf_addr.dc_dmub_srv; |
898 | const struct dc_plane_address *addr = params->subvp_save_surf_addr.addr; |
899 | uint8_t subvp_index = params->subvp_save_surf_addr.subvp_index; |
900 | |
901 | dc_dmub_srv_subvp_save_surf_addr(dc_dmub_srv, addr, subvp_index); |
902 | } |
903 | |
904 | void get_surface_tile_visual_confirm_color( |
905 | struct pipe_ctx *pipe_ctx, |
906 | struct tg_color *color) |
907 | { |
908 | uint32_t color_value = MAX_TG_COLOR_VALUE; |
909 | /* Determine the overscan color based on the bottom-most plane's context */ |
910 | struct pipe_ctx *bottom_pipe_ctx = pipe_ctx; |
911 | |
912 | while (bottom_pipe_ctx->bottom_pipe != NULL) |
913 | bottom_pipe_ctx = bottom_pipe_ctx->bottom_pipe; |
914 | |
915 | switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) { |
916 | case DC_SW_LINEAR: |
917 | /* LINEAR Surface - set border color to red */ |
918 | color->color_r_cr = color_value; |
919 | break; |
920 | default: |
921 | break; |
922 | } |
923 | } |
924 | |