1 | /* |
2 | * Copyright 2020 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | #include "dm_services.h" |
26 | #include "include/gpio_types.h" |
27 | #include "../hw_factory.h" |
28 | |
29 | |
30 | #include "../hw_gpio.h" |
31 | #include "../hw_ddc.h" |
32 | #include "../hw_hpd.h" |
33 | #include "../hw_generic.h" |
34 | |
35 | #include "hw_factory_dcn30.h" |
36 | |
37 | |
38 | #include "sienna_cichlid_ip_offset.h" |
39 | #include "dcn/dcn_3_0_0_offset.h" |
40 | #include "dcn/dcn_3_0_0_sh_mask.h" |
41 | |
42 | #include "nbio/nbio_7_4_offset.h" |
43 | |
44 | #include "dpcs/dpcs_3_0_0_offset.h" |
45 | #include "dpcs/dpcs_3_0_0_sh_mask.h" |
46 | |
47 | #include "mmhub/mmhub_2_0_0_offset.h" |
48 | #include "mmhub/mmhub_2_0_0_sh_mask.h" |
49 | |
50 | #include "reg_helper.h" |
51 | #include "../hpd_regs.h" |
52 | /* begin ********************* |
53 | * macros to expend register list macro defined in HW object header file */ |
54 | |
55 | /* DCN */ |
56 | #define block HPD |
57 | #define reg_num 0 |
58 | |
59 | #undef BASE_INNER |
60 | #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg |
61 | |
62 | #define BASE(seg) BASE_INNER(seg) |
63 | |
64 | |
65 | |
66 | #define REG(reg_name)\ |
67 | BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name |
68 | |
69 | #define SF_HPD(reg_name, field_name, post_fix)\ |
70 | .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix |
71 | |
72 | #define REGI(reg_name, block, id)\ |
73 | BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ |
74 | mm ## block ## id ## _ ## reg_name |
75 | |
76 | #define SF(reg_name, field_name, post_fix)\ |
77 | .field_name = reg_name ## __ ## field_name ## post_fix |
78 | |
79 | /* macros to expend register list macro defined in HW object header file |
80 | * end *********************/ |
81 | |
82 | |
83 | |
84 | #define hpd_regs(id) \ |
85 | {\ |
86 | HPD_REG_LIST(id)\ |
87 | } |
88 | |
89 | static const struct hpd_registers hpd_regs[] = { |
90 | hpd_regs(0), |
91 | hpd_regs(1), |
92 | hpd_regs(2), |
93 | hpd_regs(3), |
94 | hpd_regs(4), |
95 | hpd_regs(5), |
96 | }; |
97 | |
98 | static const struct hpd_sh_mask hpd_shift = { |
99 | HPD_MASK_SH_LIST(__SHIFT) |
100 | }; |
101 | |
102 | static const struct hpd_sh_mask hpd_mask = { |
103 | HPD_MASK_SH_LIST(_MASK) |
104 | }; |
105 | |
106 | #include "../ddc_regs.h" |
107 | |
108 | /* set field name */ |
109 | #define SF_DDC(reg_name, field_name, post_fix)\ |
110 | .field_name = reg_name ## __ ## field_name ## post_fix |
111 | |
112 | static const struct ddc_registers ddc_data_regs_dcn[] = { |
113 | ddc_data_regs_dcn2(1), |
114 | ddc_data_regs_dcn2(2), |
115 | ddc_data_regs_dcn2(3), |
116 | ddc_data_regs_dcn2(4), |
117 | ddc_data_regs_dcn2(5), |
118 | ddc_data_regs_dcn2(6), |
119 | { |
120 | DDC_GPIO_VGA_REG_LIST(DATA), |
121 | .ddc_setup = 0, |
122 | .phy_aux_cntl = 0, |
123 | .dc_gpio_aux_ctrl_5 = 0 |
124 | } |
125 | }; |
126 | |
127 | static const struct ddc_registers ddc_clk_regs_dcn[] = { |
128 | ddc_clk_regs_dcn2(1), |
129 | ddc_clk_regs_dcn2(2), |
130 | ddc_clk_regs_dcn2(3), |
131 | ddc_clk_regs_dcn2(4), |
132 | ddc_clk_regs_dcn2(5), |
133 | ddc_clk_regs_dcn2(6), |
134 | { |
135 | DDC_GPIO_VGA_REG_LIST(CLK), |
136 | .ddc_setup = 0, |
137 | .phy_aux_cntl = 0, |
138 | .dc_gpio_aux_ctrl_5 = 0 |
139 | } |
140 | }; |
141 | |
142 | static const struct ddc_sh_mask ddc_shift[] = { |
143 | DDC_MASK_SH_LIST_DCN2(__SHIFT, 1), |
144 | DDC_MASK_SH_LIST_DCN2(__SHIFT, 2), |
145 | DDC_MASK_SH_LIST_DCN2(__SHIFT, 3), |
146 | DDC_MASK_SH_LIST_DCN2(__SHIFT, 4), |
147 | DDC_MASK_SH_LIST_DCN2(__SHIFT, 5), |
148 | DDC_MASK_SH_LIST_DCN2(__SHIFT, 6), |
149 | DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT) |
150 | }; |
151 | |
152 | static const struct ddc_sh_mask ddc_mask[] = { |
153 | DDC_MASK_SH_LIST_DCN2(_MASK, 1), |
154 | DDC_MASK_SH_LIST_DCN2(_MASK, 2), |
155 | DDC_MASK_SH_LIST_DCN2(_MASK, 3), |
156 | DDC_MASK_SH_LIST_DCN2(_MASK, 4), |
157 | DDC_MASK_SH_LIST_DCN2(_MASK, 5), |
158 | DDC_MASK_SH_LIST_DCN2(_MASK, 6), |
159 | DDC_MASK_SH_LIST_DCN2_VGA(_MASK) |
160 | }; |
161 | |
162 | #include "../generic_regs.h" |
163 | |
164 | /* set field name */ |
165 | #define SF_GENERIC(reg_name, field_name, post_fix)\ |
166 | .field_name = reg_name ## __ ## field_name ## post_fix |
167 | |
168 | #define generic_regs(id) \ |
169 | {\ |
170 | GENERIC_REG_LIST(id)\ |
171 | } |
172 | |
173 | static const struct generic_registers generic_regs[] = { |
174 | generic_regs(A), |
175 | generic_regs(B), |
176 | }; |
177 | |
178 | static const struct generic_sh_mask generic_shift[] = { |
179 | GENERIC_MASK_SH_LIST(__SHIFT, A), |
180 | GENERIC_MASK_SH_LIST(__SHIFT, B), |
181 | }; |
182 | |
183 | static const struct generic_sh_mask generic_mask[] = { |
184 | GENERIC_MASK_SH_LIST(_MASK, A), |
185 | GENERIC_MASK_SH_LIST(_MASK, B), |
186 | }; |
187 | |
188 | static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en) |
189 | { |
190 | struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin); |
191 | |
192 | generic->regs = &generic_regs[en]; |
193 | generic->shifts = &generic_shift[en]; |
194 | generic->masks = &generic_mask[en]; |
195 | generic->base.regs = &generic_regs[en].gpio; |
196 | } |
197 | |
198 | static void define_ddc_registers( |
199 | struct hw_gpio_pin *pin, |
200 | uint32_t en) |
201 | { |
202 | struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); |
203 | |
204 | switch (pin->id) { |
205 | case GPIO_ID_DDC_DATA: |
206 | ddc->regs = &ddc_data_regs_dcn[en]; |
207 | ddc->base.regs = &ddc_data_regs_dcn[en].gpio; |
208 | break; |
209 | case GPIO_ID_DDC_CLOCK: |
210 | ddc->regs = &ddc_clk_regs_dcn[en]; |
211 | ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; |
212 | break; |
213 | default: |
214 | ASSERT_CRITICAL(false); |
215 | return; |
216 | } |
217 | |
218 | ddc->shifts = &ddc_shift[en]; |
219 | ddc->masks = &ddc_mask[en]; |
220 | |
221 | } |
222 | |
223 | static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en) |
224 | { |
225 | struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin); |
226 | |
227 | hpd->regs = &hpd_regs[en]; |
228 | hpd->shifts = &hpd_shift; |
229 | hpd->masks = &hpd_mask; |
230 | hpd->base.regs = &hpd_regs[en].gpio; |
231 | } |
232 | |
233 | |
234 | /* function table */ |
235 | static const struct hw_factory_funcs funcs = { |
236 | .init_ddc_data = dal_hw_ddc_init, |
237 | .init_generic = dal_hw_generic_init, |
238 | .init_hpd = dal_hw_hpd_init, |
239 | .get_ddc_pin = dal_hw_ddc_get_pin, |
240 | .get_hpd_pin = dal_hw_hpd_get_pin, |
241 | .get_generic_pin = dal_hw_generic_get_pin, |
242 | .define_hpd_registers = define_hpd_registers, |
243 | .define_ddc_registers = define_ddc_registers, |
244 | .define_generic_registers = define_generic_registers |
245 | }; |
246 | /* |
247 | * dal_hw_factory_dcn10_init |
248 | * |
249 | * @brief |
250 | * Initialize HW factory function pointers and pin info |
251 | * |
252 | * @param |
253 | * struct hw_factory *factory - [out] struct of function pointers |
254 | */ |
255 | void dal_hw_factory_dcn30_init(struct hw_factory *factory) |
256 | { |
257 | /*TODO check ASIC CAPs*/ |
258 | factory->number_of_pins[GPIO_ID_DDC_DATA] = 8; |
259 | factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8; |
260 | factory->number_of_pins[GPIO_ID_GENERIC] = 4; |
261 | factory->number_of_pins[GPIO_ID_HPD] = 6; |
262 | factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28; |
263 | factory->number_of_pins[GPIO_ID_VIP_PAD] = 0; |
264 | factory->number_of_pins[GPIO_ID_SYNC] = 0; |
265 | factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/ |
266 | |
267 | factory->funcs = &funcs; |
268 | } |
269 | |
270 | |