1 | /* |
2 | * Copyright 2008 Red Hat Inc. |
3 | * Copyright 2009 Jerome Glisse. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Authors: |
24 | * Dave Airlie |
25 | * Jerome Glisse <glisse@freedesktop.org> |
26 | */ |
27 | |
28 | #include <linux/pci.h> |
29 | |
30 | #include <drm/drm_device.h> |
31 | #include <drm/radeon_drm.h> |
32 | |
33 | #include "radeon.h" |
34 | |
35 | #if IS_ENABLED(CONFIG_AGP) |
36 | |
37 | struct radeon_agpmode_quirk { |
38 | u32 hostbridge_vendor; |
39 | u32 hostbridge_device; |
40 | u32 chip_vendor; |
41 | u32 chip_device; |
42 | u32 subsys_vendor; |
43 | u32 subsys_device; |
44 | u32 default_mode; |
45 | }; |
46 | |
47 | static struct radeon_agpmode_quirk radeon_agpmode_quirk_list[] = { |
48 | /* Intel E7505 Memory Controller Hub / RV350 AR [Radeon 9600XT] Needs AGPMode 4 (deb #515326) */ |
49 | { PCI_VENDOR_ID_INTEL, 0x2550, PCI_VENDOR_ID_ATI, 0x4152, 0x1458, 0x4038, 4}, |
50 | /* Intel 82865G/PE/P DRAM Controller/Host-Hub / Mobility 9800 Needs AGPMode 4 (deb #462590) */ |
51 | { PCI_VENDOR_ID_INTEL, 0x2570, PCI_VENDOR_ID_ATI, 0x4a4e, PCI_VENDOR_ID_DELL, 0x5106, 4}, |
52 | /* Intel 82865G/PE/P DRAM Controller/Host-Hub / RV280 [Radeon 9200 SE] Needs AGPMode 4 (lp #300304) */ |
53 | { PCI_VENDOR_ID_INTEL, 0x2570, PCI_VENDOR_ID_ATI, 0x5964, |
54 | 0x148c, 0x2073, 4}, |
55 | /* Intel 82855PM Processor to I/O Controller / Mobility M6 LY Needs AGPMode 1 (deb #467235) */ |
56 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c59, |
57 | PCI_VENDOR_ID_IBM, 0x052f, 1}, |
58 | /* Intel 82855PM host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #195051) */ |
59 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e50, |
60 | PCI_VENDOR_ID_IBM, 0x0550, 1}, |
61 | /* Intel 82855PM host bridge / RV250/M9 GL [Mobility FireGL 9000/Radeon 9000] needs AGPMode 1 (Thinkpad T40p) */ |
62 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c66, |
63 | PCI_VENDOR_ID_IBM, 0x054d, 1}, |
64 | /* Intel 82855PM host bridge / Mobility M7 needs AGPMode 1 */ |
65 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c57, |
66 | PCI_VENDOR_ID_IBM, 0x0530, 1}, |
67 | /* Intel 82855PM host bridge / FireGL Mobility T2 RV350 Needs AGPMode 2 (fdo #20647) */ |
68 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e54, |
69 | PCI_VENDOR_ID_IBM, 0x054f, 2}, |
70 | /* Intel 82855PM host bridge / Mobility M9+ / VaioPCG-V505DX Needs AGPMode 2 (fdo #17928) */ |
71 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x5c61, |
72 | PCI_VENDOR_ID_SONY, 0x816b, 2}, |
73 | /* Intel 82855PM Processor to I/O Controller / Mobility M9+ Needs AGPMode 8 (phoronix forum) */ |
74 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x5c61, |
75 | PCI_VENDOR_ID_SONY, 0x8195, 8}, |
76 | /* Intel 82830 830 Chipset Host Bridge / Mobility M6 LY Needs AGPMode 2 (fdo #17360)*/ |
77 | { PCI_VENDOR_ID_INTEL, 0x3575, PCI_VENDOR_ID_ATI, 0x4c59, |
78 | PCI_VENDOR_ID_DELL, 0x00e3, 2}, |
79 | /* Intel 82852/82855 host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 (lp #296617) */ |
80 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4c66, |
81 | PCI_VENDOR_ID_DELL, 0x0149, 1}, |
82 | /* Intel 82855PM host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 for suspend/resume */ |
83 | { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c66, |
84 | PCI_VENDOR_ID_IBM, 0x0531, 1}, |
85 | /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (deb #467460) */ |
86 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50, |
87 | 0x1025, 0x0061, 1}, |
88 | /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #203007) */ |
89 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50, |
90 | 0x1025, 0x0064, 1}, |
91 | /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #141551) */ |
92 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50, |
93 | PCI_VENDOR_ID_ASUSTEK, 0x1942, 1}, |
94 | /* Intel 82852/82855 host bridge / Mobility 9600/9700 Needs AGPMode 1 (deb #510208) */ |
95 | { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50, |
96 | 0x10cf, 0x127f, 1}, |
97 | /* ASRock K7VT4A+ AGP 8x / ATI Radeon 9250 AGP Needs AGPMode 4 (lp #133192) */ |
98 | { 0x1849, 0x3189, PCI_VENDOR_ID_ATI, 0x5960, |
99 | 0x1787, 0x5960, 4}, |
100 | /* VIA K8M800 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (fdo #12544) */ |
101 | { PCI_VENDOR_ID_VIA, 0x0204, PCI_VENDOR_ID_ATI, 0x5960, |
102 | 0x17af, 0x2020, 4}, |
103 | /* VIA KT880 Host Bridge / RV350 [Radeon 9550] Needs AGPMode 4 (fdo #19981) */ |
104 | { PCI_VENDOR_ID_VIA, 0x0269, PCI_VENDOR_ID_ATI, 0x4153, |
105 | PCI_VENDOR_ID_ASUSTEK, 0x003c, 4}, |
106 | /* VIA VT8363 Host Bridge / R200 QL [Radeon 8500] Needs AGPMode 2 (lp #141551) */ |
107 | { PCI_VENDOR_ID_VIA, 0x0305, PCI_VENDOR_ID_ATI, 0x514c, |
108 | PCI_VENDOR_ID_ATI, 0x013a, 2}, |
109 | /* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 (deb #515512) */ |
110 | { PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_ATI, 0x5960, |
111 | PCI_VENDOR_ID_ASUSTEK, 0x004c, 2}, |
112 | /* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 */ |
113 | { PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_ATI, 0x5960, |
114 | PCI_VENDOR_ID_ASUSTEK, 0x0054, 2}, |
115 | /* VIA VT8377 Host Bridge / R200 QM [Radeon 9100] Needs AGPMode 4 (deb #461144) */ |
116 | { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x514d, |
117 | 0x174b, 0x7149, 4}, |
118 | /* VIA VT8377 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (lp #312693) */ |
119 | { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x5960, |
120 | 0x1462, 0x0380, 4}, |
121 | /* VIA VT8377 Host Bridge / RV280 Needs AGPMode 4 (ati ML) */ |
122 | { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x5964, |
123 | 0x148c, 0x2073, 4}, |
124 | /* ATI Host Bridge / RV280 [M9+] Needs AGPMode 1 (phoronix forum) */ |
125 | { PCI_VENDOR_ID_ATI, 0xcbb2, PCI_VENDOR_ID_ATI, 0x5c61, |
126 | PCI_VENDOR_ID_SONY, 0x8175, 1}, |
127 | { 0, 0, 0, 0, 0, 0, 0 }, |
128 | }; |
129 | |
130 | struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev) |
131 | { |
132 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
133 | struct radeon_agp_head *head; |
134 | |
135 | head = kzalloc(size: sizeof(*head), GFP_KERNEL); |
136 | if (!head) |
137 | return NULL; |
138 | head->bridge = agp_find_bridge(pdev); |
139 | if (!head->bridge) { |
140 | head->bridge = agp_backend_acquire(pdev); |
141 | if (!head->bridge) { |
142 | kfree(objp: head); |
143 | return NULL; |
144 | } |
145 | agp_copy_info(head->bridge, &head->agp_info); |
146 | agp_backend_release(head->bridge); |
147 | } else { |
148 | agp_copy_info(head->bridge, &head->agp_info); |
149 | } |
150 | if (head->agp_info.chipset == NOT_SUPPORTED) { |
151 | kfree(objp: head); |
152 | return NULL; |
153 | } |
154 | INIT_LIST_HEAD(list: &head->memory); |
155 | head->cant_use_aperture = head->agp_info.cant_use_aperture; |
156 | head->page_mask = head->agp_info.page_mask; |
157 | head->base = head->agp_info.aper_base; |
158 | |
159 | return head; |
160 | } |
161 | |
162 | static int radeon_agp_head_acquire(struct radeon_device *rdev) |
163 | { |
164 | struct drm_device *dev = rdev->ddev; |
165 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
166 | |
167 | if (!rdev->agp) |
168 | return -ENODEV; |
169 | if (rdev->agp->acquired) |
170 | return -EBUSY; |
171 | rdev->agp->bridge = agp_backend_acquire(pdev); |
172 | if (!rdev->agp->bridge) |
173 | return -ENODEV; |
174 | rdev->agp->acquired = 1; |
175 | return 0; |
176 | } |
177 | |
178 | static int radeon_agp_head_release(struct radeon_device *rdev) |
179 | { |
180 | if (!rdev->agp || !rdev->agp->acquired) |
181 | return -EINVAL; |
182 | agp_backend_release(rdev->agp->bridge); |
183 | rdev->agp->acquired = 0; |
184 | return 0; |
185 | } |
186 | |
187 | static int radeon_agp_head_enable(struct radeon_device *rdev, struct radeon_agp_mode mode) |
188 | { |
189 | if (!rdev->agp || !rdev->agp->acquired) |
190 | return -EINVAL; |
191 | |
192 | rdev->agp->mode = mode.mode; |
193 | agp_enable(rdev->agp->bridge, mode.mode); |
194 | rdev->agp->enabled = 1; |
195 | return 0; |
196 | } |
197 | |
198 | static int radeon_agp_head_info(struct radeon_device *rdev, struct radeon_agp_info *info) |
199 | { |
200 | struct agp_kern_info *kern; |
201 | |
202 | if (!rdev->agp || !rdev->agp->acquired) |
203 | return -EINVAL; |
204 | |
205 | kern = &rdev->agp->agp_info; |
206 | info->agp_version_major = kern->version.major; |
207 | info->agp_version_minor = kern->version.minor; |
208 | info->mode = kern->mode; |
209 | info->aperture_base = kern->aper_base; |
210 | info->aperture_size = kern->aper_size * 1024 * 1024; |
211 | info->memory_allowed = kern->max_memory << PAGE_SHIFT; |
212 | info->memory_used = kern->current_memory << PAGE_SHIFT; |
213 | info->id_vendor = kern->device->vendor; |
214 | info->id_device = kern->device->device; |
215 | |
216 | return 0; |
217 | } |
218 | #endif |
219 | |
220 | int radeon_agp_init(struct radeon_device *rdev) |
221 | { |
222 | #if IS_ENABLED(CONFIG_AGP) |
223 | struct radeon_agpmode_quirk *p = radeon_agpmode_quirk_list; |
224 | struct radeon_agp_mode mode; |
225 | struct radeon_agp_info info; |
226 | uint32_t agp_status; |
227 | int default_mode; |
228 | bool is_v3; |
229 | int ret; |
230 | |
231 | /* Acquire AGP. */ |
232 | ret = radeon_agp_head_acquire(rdev); |
233 | if (ret) { |
234 | DRM_ERROR("Unable to acquire AGP: %d\n" , ret); |
235 | return ret; |
236 | } |
237 | |
238 | ret = radeon_agp_head_info(rdev, info: &info); |
239 | if (ret) { |
240 | radeon_agp_head_release(rdev); |
241 | DRM_ERROR("Unable to get AGP info: %d\n" , ret); |
242 | return ret; |
243 | } |
244 | |
245 | if (rdev->agp->agp_info.aper_size < 32) { |
246 | radeon_agp_head_release(rdev); |
247 | dev_warn(rdev->dev, "AGP aperture too small (%zuM) " |
248 | "need at least 32M, disabling AGP\n" , |
249 | rdev->agp->agp_info.aper_size); |
250 | return -EINVAL; |
251 | } |
252 | |
253 | mode.mode = info.mode; |
254 | /* chips with the agp to pcie bridge don't have the AGP_STATUS register |
255 | * Just use the whatever mode the host sets up. |
256 | */ |
257 | if (rdev->family <= CHIP_RV350) |
258 | agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode; |
259 | else |
260 | agp_status = mode.mode; |
261 | is_v3 = !!(agp_status & RADEON_AGPv3_MODE); |
262 | |
263 | if (is_v3) { |
264 | default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4; |
265 | } else { |
266 | if (agp_status & RADEON_AGP_4X_MODE) { |
267 | default_mode = 4; |
268 | } else if (agp_status & RADEON_AGP_2X_MODE) { |
269 | default_mode = 2; |
270 | } else { |
271 | default_mode = 1; |
272 | } |
273 | } |
274 | |
275 | /* Apply AGPMode Quirks */ |
276 | while (p && p->chip_device != 0) { |
277 | if (info.id_vendor == p->hostbridge_vendor && |
278 | info.id_device == p->hostbridge_device && |
279 | rdev->pdev->vendor == p->chip_vendor && |
280 | rdev->pdev->device == p->chip_device && |
281 | rdev->pdev->subsystem_vendor == p->subsys_vendor && |
282 | rdev->pdev->subsystem_device == p->subsys_device) { |
283 | default_mode = p->default_mode; |
284 | } |
285 | ++p; |
286 | } |
287 | |
288 | if (radeon_agpmode > 0) { |
289 | if ((radeon_agpmode < (is_v3 ? 4 : 1)) || |
290 | (radeon_agpmode > (is_v3 ? 8 : 4)) || |
291 | (radeon_agpmode & (radeon_agpmode - 1))) { |
292 | DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n" , |
293 | radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4" , |
294 | default_mode); |
295 | radeon_agpmode = default_mode; |
296 | } else { |
297 | DRM_INFO("AGP mode requested: %d\n" , radeon_agpmode); |
298 | } |
299 | } else { |
300 | radeon_agpmode = default_mode; |
301 | } |
302 | |
303 | mode.mode &= ~RADEON_AGP_MODE_MASK; |
304 | if (is_v3) { |
305 | switch (radeon_agpmode) { |
306 | case 8: |
307 | mode.mode |= RADEON_AGPv3_8X_MODE; |
308 | break; |
309 | case 4: |
310 | default: |
311 | mode.mode |= RADEON_AGPv3_4X_MODE; |
312 | break; |
313 | } |
314 | } else { |
315 | switch (radeon_agpmode) { |
316 | case 4: |
317 | mode.mode |= RADEON_AGP_4X_MODE; |
318 | break; |
319 | case 2: |
320 | mode.mode |= RADEON_AGP_2X_MODE; |
321 | break; |
322 | case 1: |
323 | default: |
324 | mode.mode |= RADEON_AGP_1X_MODE; |
325 | break; |
326 | } |
327 | } |
328 | |
329 | mode.mode &= ~RADEON_AGP_FW_MODE; /* disable fw */ |
330 | ret = radeon_agp_head_enable(rdev, mode); |
331 | if (ret) { |
332 | DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n" , mode.mode); |
333 | radeon_agp_head_release(rdev); |
334 | return ret; |
335 | } |
336 | |
337 | rdev->mc.agp_base = rdev->agp->agp_info.aper_base; |
338 | rdev->mc.gtt_size = rdev->agp->agp_info.aper_size << 20; |
339 | rdev->mc.gtt_start = rdev->mc.agp_base; |
340 | rdev->mc.gtt_end = rdev->mc.gtt_start + rdev->mc.gtt_size - 1; |
341 | dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n" , |
342 | rdev->mc.gtt_size >> 20, rdev->mc.gtt_start, rdev->mc.gtt_end); |
343 | |
344 | /* workaround some hw issues */ |
345 | if (rdev->family < CHIP_R200) { |
346 | WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000); |
347 | } |
348 | return 0; |
349 | #else |
350 | return 0; |
351 | #endif |
352 | } |
353 | |
354 | void radeon_agp_resume(struct radeon_device *rdev) |
355 | { |
356 | #if IS_ENABLED(CONFIG_AGP) |
357 | int r; |
358 | if (rdev->flags & RADEON_IS_AGP) { |
359 | r = radeon_agp_init(rdev); |
360 | if (r) |
361 | dev_warn(rdev->dev, "radeon AGP reinit failed\n" ); |
362 | } |
363 | #endif |
364 | } |
365 | |
366 | void radeon_agp_fini(struct radeon_device *rdev) |
367 | { |
368 | #if IS_ENABLED(CONFIG_AGP) |
369 | if (rdev->agp && rdev->agp->acquired) { |
370 | radeon_agp_head_release(rdev); |
371 | } |
372 | #endif |
373 | } |
374 | |
375 | void radeon_agp_suspend(struct radeon_device *rdev) |
376 | { |
377 | radeon_agp_fini(rdev); |
378 | } |
379 | |