1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* Driver for Realtek PCI-Express card reader |
3 | * |
4 | * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved. |
5 | * |
6 | * Author: |
7 | * Ricky WU <ricky_wu@realtek.com> |
8 | * Rui FENG <rui_feng@realsil.com.cn> |
9 | * Wei WANG <wei_wang@realsil.com.cn> |
10 | */ |
11 | #ifndef RTS5228_H |
12 | #define RTS5228_H |
13 | |
14 | |
15 | #define RTS5228_AUTOLOAD_CFG0 0xFF7B |
16 | #define RTS5228_AUTOLOAD_CFG1 0xFF7C |
17 | #define RTS5228_AUTOLOAD_CFG2 0xFF7D |
18 | #define RTS5228_AUTOLOAD_CFG3 0xFF7E |
19 | #define RTS5228_AUTOLOAD_CFG4 0xFF7F |
20 | |
21 | #define RTS5228_REG_VREF 0xFE97 |
22 | #define RTS5228_PWD_SUSPND_EN (1 << 4) |
23 | |
24 | #define RTS5228_PAD_H3L1 0xFF79 |
25 | #define PAD_GPIO_H3L1 (1 << 3) |
26 | |
27 | /* SSC_CTL2 0xFC12 */ |
28 | #define RTS5228_SSC_DEPTH_MASK 0x07 |
29 | #define RTS5228_SSC_DEPTH_DISALBE 0x00 |
30 | #define RTS5228_SSC_DEPTH_8M 0x01 |
31 | #define RTS5228_SSC_DEPTH_4M 0x02 |
32 | #define RTS5228_SSC_DEPTH_2M 0x03 |
33 | #define RTS5228_SSC_DEPTH_1M 0x04 |
34 | #define RTS5228_SSC_DEPTH_512K 0x05 |
35 | #define RTS5228_SSC_DEPTH_256K 0x06 |
36 | #define RTS5228_SSC_DEPTH_128K 0x07 |
37 | |
38 | /* DMACTL 0xFE2C */ |
39 | #define RTS5228_DMA_PACK_SIZE_MASK 0xF0 |
40 | |
41 | #define RTS5228_REG_LDO12_CFG 0xFF6E |
42 | #define RTS5228_LDO12_VO_TUNE_MASK (0x07<<1) |
43 | #define RTS5228_LDO12_100 (0x00<<1) |
44 | #define RTS5228_LDO12_105 (0x01<<1) |
45 | #define RTS5228_LDO12_110 (0x02<<1) |
46 | #define RTS5228_LDO12_115 (0x03<<1) |
47 | #define RTS5228_LDO12_120 (0x04<<1) |
48 | #define RTS5228_LDO12_125 (0x05<<1) |
49 | #define RTS5228_LDO12_130 (0x06<<1) |
50 | #define RTS5228_LDO12_135 (0x07<<1) |
51 | #define RTS5228_REG_PWD_LDO12 (0x01<<0) |
52 | |
53 | #define RTS5228_REG_LDO12_L12 0xFF6F |
54 | #define RTS5228_LDO12_L12_MASK (0x07<<4) |
55 | #define RTS5228_LDO12_L12_120 (0x04<<4) |
56 | |
57 | /* LDO control register */ |
58 | #define RTS5228_CARD_PWR_CTL 0xFD50 |
59 | #define RTS5228_PUPDC (0x01<<5) |
60 | |
61 | #define RTS5228_LDO1233318_POW_CTL 0xFF70 |
62 | #define RTS5228_LDO3318_POWERON (0x01<<3) |
63 | #define RTS5228_LDO1_POWEROFF (0x00<<0) |
64 | #define RTS5228_LDO1_SOFTSTART (0x01<<0) |
65 | #define RTS5228_LDO1_FULLON (0x03<<0) |
66 | #define RTS5228_LDO1_POWERON_MASK (0x03<<0) |
67 | #define RTS5228_LDO_POWERON_MASK (0x0F<<0) |
68 | |
69 | #define RTS5228_DV3318_CFG 0xFF71 |
70 | #define RTS5228_DV3318_TUNE_MASK (0x07<<4) |
71 | #define RTS5228_DV3318_17 (0x00<<4) |
72 | #define RTS5228_DV3318_1V75 (0x01<<4) |
73 | #define RTS5228_DV3318_18 (0x02<<4) |
74 | #define RTS5228_DV3318_1V85 (0x03<<4) |
75 | #define RTS5228_DV3318_19 (0x04<<4) |
76 | #define RTS5228_DV3318_33 (0x07<<4) |
77 | #define RTS5228_DV3318_SR_MASK (0x03<<2) |
78 | #define RTS5228_DV3318_SR_0 (0x00<<2) |
79 | #define RTS5228_DV3318_SR_250 (0x01<<2) |
80 | #define RTS5228_DV3318_SR_500 (0x02<<2) |
81 | #define RTS5228_DV3318_SR_1000 (0x03<<2) |
82 | |
83 | #define RTS5228_LDO1_CFG0 0xFF72 |
84 | #define RTS5228_LDO1_OCP_THD_MASK (0x07<<5) |
85 | #define RTS5228_LDO1_OCP_EN (0x01<<4) |
86 | #define RTS5228_LDO1_OCP_LMT_THD_MASK (0x03<<2) |
87 | #define RTS5228_LDO1_OCP_LMT_EN (0x01<<1) |
88 | |
89 | #define RTS5228_LDO1_OCP_THD_730 (0x00<<5) |
90 | #define RTS5228_LDO1_OCP_THD_780 (0x01<<5) |
91 | #define RTS5228_LDO1_OCP_THD_860 (0x02<<5) |
92 | #define RTS5228_LDO1_OCP_THD_930 (0x03<<5) |
93 | #define RTS5228_LDO1_OCP_THD_1000 (0x04<<5) |
94 | #define RTS5228_LDO1_OCP_THD_1070 (0x05<<5) |
95 | #define RTS5228_LDO1_OCP_THD_1140 (0x06<<5) |
96 | #define RTS5228_LDO1_OCP_THD_1220 (0x07<<5) |
97 | |
98 | #define RTS5228_LDO1_LMT_THD_450 (0x00<<2) |
99 | #define RTS5228_LDO1_LMT_THD_1000 (0x01<<2) |
100 | #define RTS5228_LDO1_LMT_THD_1500 (0x02<<2) |
101 | #define RTS5228_LDO1_LMT_THD_2000 (0x03<<2) |
102 | |
103 | #define RTS5228_LDO1_CFG1 0xFF73 |
104 | #define RTS5228_LDO1_SR_TIME_MASK (0x03<<6) |
105 | #define RTS5228_LDO1_SR_0_0 (0x00<<6) |
106 | #define RTS5228_LDO1_SR_0_25 (0x01<<6) |
107 | #define RTS5228_LDO1_SR_0_5 (0x02<<6) |
108 | #define RTS5228_LDO1_SR_1_0 (0x03<<6) |
109 | #define RTS5228_LDO1_TUNE_MASK (0x07<<1) |
110 | #define RTS5228_LDO1_18 (0x05<<1) |
111 | #define RTS5228_LDO1_33 (0x07<<1) |
112 | #define RTS5228_LDO1_PWD_MASK (0x01<<0) |
113 | |
114 | #define RTS5228_AUXCLK_GAT_CTL 0xFF74 |
115 | |
116 | #define RTS5228_REG_RREF_CTL_0 0xFF75 |
117 | #define RTS5228_FORCE_RREF_EXTL (0x01<<7) |
118 | #define RTS5228_REG_BG33_MASK (0x07<<0) |
119 | #define RTS5228_RREF_12_1V (0x04<<0) |
120 | #define RTS5228_RREF_12_3V (0x05<<0) |
121 | |
122 | #define RTS5228_REG_RREF_CTL_1 0xFF76 |
123 | |
124 | #define RTS5228_REG_RREF_CTL_2 0xFF77 |
125 | #define RTS5228_TEST_INTL_RREF (0x01<<7) |
126 | #define RTS5228_DGLCH_TIME_MASK (0x03<<5) |
127 | #define RTS5228_DGLCH_TIME_50 (0x00<<5) |
128 | #define RTS5228_DGLCH_TIME_75 (0x01<<5) |
129 | #define RTS5228_DGLCH_TIME_100 (0x02<<5) |
130 | #define RTS5228_DGLCH_TIME_125 (0x03<<5) |
131 | #define RTS5228_REG_REXT_TUNE_MASK (0x1F<<0) |
132 | |
133 | #define RTS5228_REG_PME_FORCE_CTL 0xFF78 |
134 | #define FORCE_PM_CONTROL 0x20 |
135 | #define FORCE_PM_VALUE 0x10 |
136 | |
137 | |
138 | /* Single LUN, support SD */ |
139 | #define DEFAULT_SINGLE 0 |
140 | #define SD_LUN 1 |
141 | |
142 | |
143 | /* For Change_FPGA_SSCClock Function */ |
144 | #define MULTIPLY_BY_1 0x00 |
145 | #define MULTIPLY_BY_2 0x01 |
146 | #define MULTIPLY_BY_3 0x02 |
147 | #define MULTIPLY_BY_4 0x03 |
148 | #define MULTIPLY_BY_5 0x04 |
149 | #define MULTIPLY_BY_6 0x05 |
150 | #define MULTIPLY_BY_7 0x06 |
151 | #define MULTIPLY_BY_8 0x07 |
152 | #define MULTIPLY_BY_9 0x08 |
153 | #define MULTIPLY_BY_10 0x09 |
154 | |
155 | #define DIVIDE_BY_2 0x01 |
156 | #define DIVIDE_BY_3 0x02 |
157 | #define DIVIDE_BY_4 0x03 |
158 | #define DIVIDE_BY_5 0x04 |
159 | #define DIVIDE_BY_6 0x05 |
160 | #define DIVIDE_BY_7 0x06 |
161 | #define DIVIDE_BY_8 0x07 |
162 | #define DIVIDE_BY_9 0x08 |
163 | #define DIVIDE_BY_10 0x09 |
164 | |
165 | int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, |
166 | u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk); |
167 | |
168 | #endif /* RTS5228_H */ |
169 | |