1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* Driver for Realtek PCI-Express card reader |
3 | * |
4 | * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved. |
5 | * |
6 | * Author: |
7 | * Ricky WU <ricky_wu@realtek.com> |
8 | * Rui FENG <rui_feng@realsil.com.cn> |
9 | * Wei WANG <wei_wang@realsil.com.cn> |
10 | */ |
11 | |
12 | #include <linux/module.h> |
13 | #include <linux/delay.h> |
14 | #include <linux/rtsx_pci.h> |
15 | |
16 | #include "rts5228.h" |
17 | #include "rtsx_pcr.h" |
18 | |
19 | static u8 rts5228_get_ic_version(struct rtsx_pcr *pcr) |
20 | { |
21 | u8 val; |
22 | |
23 | rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, data: &val); |
24 | return val & IC_VERSION_MASK; |
25 | } |
26 | |
27 | static void rts5228_fill_driving(struct rtsx_pcr *pcr, u8 voltage) |
28 | { |
29 | u8 driving_3v3[4][3] = { |
30 | {0x13, 0x13, 0x13}, |
31 | {0x96, 0x96, 0x96}, |
32 | {0x7F, 0x7F, 0x7F}, |
33 | {0x96, 0x96, 0x96}, |
34 | }; |
35 | u8 driving_1v8[4][3] = { |
36 | {0x99, 0x99, 0x99}, |
37 | {0xB5, 0xB5, 0xB5}, |
38 | {0xE6, 0x7E, 0xFE}, |
39 | {0x6B, 0x6B, 0x6B}, |
40 | }; |
41 | u8 (*driving)[3], drive_sel; |
42 | |
43 | if (voltage == OUTPUT_3V3) { |
44 | driving = driving_3v3; |
45 | drive_sel = pcr->sd30_drive_sel_3v3; |
46 | } else { |
47 | driving = driving_1v8; |
48 | drive_sel = pcr->sd30_drive_sel_1v8; |
49 | } |
50 | |
51 | rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL, |
52 | mask: 0xFF, data: driving[drive_sel][0]); |
53 | |
54 | rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL, |
55 | mask: 0xFF, data: driving[drive_sel][1]); |
56 | |
57 | rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL, |
58 | mask: 0xFF, data: driving[drive_sel][2]); |
59 | } |
60 | |
61 | static void rtsx5228_fetch_vendor_settings(struct rtsx_pcr *pcr) |
62 | { |
63 | struct pci_dev *pdev = pcr->pci; |
64 | u32 reg; |
65 | |
66 | /* 0x724~0x727 */ |
67 | pci_read_config_dword(dev: pdev, PCR_SETTING_REG1, val: ®); |
68 | pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n" , PCR_SETTING_REG1, reg); |
69 | |
70 | if (!rtsx_vendor_setting_valid(reg)) { |
71 | pcr_dbg(pcr, "skip fetch vendor setting\n" ); |
72 | return; |
73 | } |
74 | pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); |
75 | pcr->aspm_en = rtsx_reg_to_aspm(reg); |
76 | |
77 | /* 0x814~0x817 */ |
78 | pci_read_config_dword(dev: pdev, PCR_SETTING_REG2, val: ®); |
79 | pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n" , PCR_SETTING_REG2, reg); |
80 | |
81 | pcr->rtd3_en = rtsx_reg_to_rtd3(reg); |
82 | if (rtsx_check_mmc_support(reg)) |
83 | pcr->extra_caps |= EXTRA_CAPS_NO_MMC; |
84 | pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); |
85 | if (rtsx_reg_check_reverse_socket(reg)) |
86 | pcr->flags |= PCR_REVERSE_SOCKET; |
87 | } |
88 | |
89 | static int rts5228_optimize_phy(struct rtsx_pcr *pcr) |
90 | { |
91 | return rtsx_pci_write_phy_register(pcr, addr: 0x07, val: 0x8F40); |
92 | } |
93 | |
94 | static void rts5228_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime) |
95 | { |
96 | /* Set relink_time to 0 */ |
97 | rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, data: 0); |
98 | rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, data: 0); |
99 | rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, |
100 | RELINK_TIME_MASK, data: 0); |
101 | |
102 | rtsx_pci_write_register(pcr, addr: pcr->reg_pm_ctrl3, |
103 | D3_DELINK_MODE_EN, D3_DELINK_MODE_EN); |
104 | |
105 | if (!runtime) { |
106 | rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1, |
107 | CD_RESUME_EN_MASK, data: 0); |
108 | rtsx_pci_write_register(pcr, addr: pcr->reg_pm_ctrl3, mask: 0x01, data: 0x00); |
109 | rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL, |
110 | FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL); |
111 | } |
112 | |
113 | rtsx_pci_write_register(pcr, FPDCTL, |
114 | SSC_POWER_DOWN, SSC_POWER_DOWN); |
115 | } |
116 | |
117 | static int rts5228_enable_auto_blink(struct rtsx_pcr *pcr) |
118 | { |
119 | return rtsx_pci_write_register(pcr, OLT_LED_CTL, |
120 | LED_SHINE_MASK, LED_SHINE_EN); |
121 | } |
122 | |
123 | static int rts5228_disable_auto_blink(struct rtsx_pcr *pcr) |
124 | { |
125 | return rtsx_pci_write_register(pcr, OLT_LED_CTL, |
126 | LED_SHINE_MASK, LED_SHINE_DISABLE); |
127 | } |
128 | |
129 | static int rts5228_turn_on_led(struct rtsx_pcr *pcr) |
130 | { |
131 | return rtsx_pci_write_register(pcr, GPIO_CTL, |
132 | mask: 0x02, data: 0x02); |
133 | } |
134 | |
135 | static int rts5228_turn_off_led(struct rtsx_pcr *pcr) |
136 | { |
137 | return rtsx_pci_write_register(pcr, GPIO_CTL, |
138 | mask: 0x02, data: 0x00); |
139 | } |
140 | |
141 | /* SD Pull Control Enable: |
142 | * SD_DAT[3:0] ==> pull up |
143 | * SD_CD ==> pull up |
144 | * SD_WP ==> pull up |
145 | * SD_CMD ==> pull up |
146 | * SD_CLK ==> pull down |
147 | */ |
148 | static const u32 rts5228_sd_pull_ctl_enable_tbl[] = { |
149 | RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), |
150 | RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9), |
151 | 0, |
152 | }; |
153 | |
154 | /* SD Pull Control Disable: |
155 | * SD_DAT[3:0] ==> pull down |
156 | * SD_CD ==> pull up |
157 | * SD_WP ==> pull down |
158 | * SD_CMD ==> pull down |
159 | * SD_CLK ==> pull down |
160 | */ |
161 | static const u32 rts5228_sd_pull_ctl_disable_tbl[] = { |
162 | RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), |
163 | RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5), |
164 | 0, |
165 | }; |
166 | |
167 | static int rts5228_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr) |
168 | { |
169 | rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK |
170 | | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); |
171 | rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); |
172 | rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, mask: 0xFF, |
173 | CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); |
174 | rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, data: 0); |
175 | |
176 | return 0; |
177 | } |
178 | |
179 | static int rts5228_card_power_on(struct rtsx_pcr *pcr, int card) |
180 | { |
181 | struct rtsx_cr_option *option = &pcr->option; |
182 | |
183 | if (option->ocp_en) |
184 | rtsx_pci_enable_ocp(pcr); |
185 | |
186 | rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, |
187 | CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD); |
188 | |
189 | rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1, |
190 | RTS5228_LDO1_TUNE_MASK, RTS5228_LDO1_33); |
191 | |
192 | rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL, |
193 | RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_SOFTSTART); |
194 | mdelay(2); |
195 | rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL, |
196 | RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_FULLON); |
197 | |
198 | |
199 | rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL, |
200 | RTS5228_LDO3318_POWERON, RTS5228_LDO3318_POWERON); |
201 | |
202 | msleep(msecs: 20); |
203 | |
204 | rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); |
205 | |
206 | /* Initialize SD_CFG1 register */ |
207 | rtsx_pci_write_register(pcr, SD_CFG1, mask: 0xFF, |
208 | SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT); |
209 | |
210 | rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL, |
211 | mask: 0xFF, SD20_RX_POS_EDGE); |
212 | rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, mask: 0xFF, data: 0); |
213 | rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR, |
214 | SD_STOP | SD_CLR_ERR); |
215 | |
216 | /* Reset SD_CFG3 register */ |
217 | rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, data: 0); |
218 | rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG, |
219 | SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 | |
220 | SD30_CLK_STOP_CFG0, data: 0); |
221 | |
222 | if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 || |
223 | pcr->extra_caps & EXTRA_CAPS_SD_SDR104) |
224 | rts5228_sd_set_sample_push_timing_sd30(pcr); |
225 | |
226 | return 0; |
227 | } |
228 | |
229 | static int rts5228_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) |
230 | { |
231 | int err; |
232 | u16 val = 0; |
233 | |
234 | rtsx_pci_write_register(pcr, RTS5228_CARD_PWR_CTL, |
235 | RTS5228_PUPDC, RTS5228_PUPDC); |
236 | |
237 | switch (voltage) { |
238 | case OUTPUT_3V3: |
239 | rtsx_pci_read_phy_register(pcr, PHY_TUNE, val: &val); |
240 | val |= PHY_TUNE_SDBUS_33; |
241 | err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val); |
242 | if (err < 0) |
243 | return err; |
244 | |
245 | rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG, |
246 | RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_33); |
247 | rtsx_pci_write_register(pcr, SD_PAD_CTL, |
248 | SD_IO_USING_1V8, data: 0); |
249 | break; |
250 | case OUTPUT_1V8: |
251 | rtsx_pci_read_phy_register(pcr, PHY_TUNE, val: &val); |
252 | val &= ~PHY_TUNE_SDBUS_33; |
253 | err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val); |
254 | if (err < 0) |
255 | return err; |
256 | |
257 | rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG, |
258 | RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_18); |
259 | rtsx_pci_write_register(pcr, SD_PAD_CTL, |
260 | SD_IO_USING_1V8, SD_IO_USING_1V8); |
261 | break; |
262 | default: |
263 | return -EINVAL; |
264 | } |
265 | |
266 | /* set pad drive */ |
267 | rts5228_fill_driving(pcr, voltage); |
268 | |
269 | return 0; |
270 | } |
271 | |
272 | static void rts5228_stop_cmd(struct rtsx_pcr *pcr) |
273 | { |
274 | rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD); |
275 | rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA); |
276 | rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0, |
277 | RTS5260_DMA_RST | RTS5260_ADMA3_RST, |
278 | RTS5260_DMA_RST | RTS5260_ADMA3_RST); |
279 | rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH); |
280 | } |
281 | |
282 | static void rts5228_card_before_power_off(struct rtsx_pcr *pcr) |
283 | { |
284 | rts5228_stop_cmd(pcr); |
285 | rts5228_switch_output_voltage(pcr, OUTPUT_3V3); |
286 | } |
287 | |
288 | static void rts5228_enable_ocp(struct rtsx_pcr *pcr) |
289 | { |
290 | u8 val = 0; |
291 | |
292 | val = SD_OCP_INT_EN | SD_DETECT_EN; |
293 | rtsx_pci_write_register(pcr, REG_OCPCTL, mask: 0xFF, data: val); |
294 | rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, |
295 | RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, |
296 | RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN); |
297 | } |
298 | |
299 | static void rts5228_disable_ocp(struct rtsx_pcr *pcr) |
300 | { |
301 | u8 mask = 0; |
302 | |
303 | mask = SD_OCP_INT_EN | SD_DETECT_EN; |
304 | rtsx_pci_write_register(pcr, REG_OCPCTL, mask, data: 0); |
305 | rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, |
306 | RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, data: 0); |
307 | } |
308 | |
309 | static int rts5228_card_power_off(struct rtsx_pcr *pcr, int card) |
310 | { |
311 | int err = 0; |
312 | |
313 | rts5228_card_before_power_off(pcr); |
314 | err = rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL, |
315 | RTS5228_LDO_POWERON_MASK, data: 0); |
316 | rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, CFG_SD_POW_AUTO_PD, data: 0); |
317 | |
318 | if (pcr->option.ocp_en) |
319 | rtsx_pci_disable_ocp(pcr); |
320 | |
321 | return err; |
322 | } |
323 | |
324 | static void rts5228_init_ocp(struct rtsx_pcr *pcr) |
325 | { |
326 | struct rtsx_cr_option *option = &pcr->option; |
327 | |
328 | if (option->ocp_en) { |
329 | u8 mask, val; |
330 | |
331 | rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, |
332 | RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, |
333 | RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN); |
334 | |
335 | rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, |
336 | RTS5228_LDO1_OCP_THD_MASK, data: option->sd_800mA_ocp_thd); |
337 | |
338 | rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, |
339 | RTS5228_LDO1_OCP_LMT_THD_MASK, |
340 | RTS5228_LDO1_LMT_THD_1500); |
341 | |
342 | rtsx_pci_read_register(pcr, RTS5228_LDO1_CFG0, data: &val); |
343 | |
344 | mask = SD_OCP_GLITCH_MASK; |
345 | val = pcr->hw_param.ocp_glitch; |
346 | rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, data: val); |
347 | |
348 | rts5228_enable_ocp(pcr); |
349 | |
350 | } else { |
351 | rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, |
352 | RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, data: 0); |
353 | } |
354 | } |
355 | |
356 | static void rts5228_clear_ocpstat(struct rtsx_pcr *pcr) |
357 | { |
358 | u8 mask = 0; |
359 | u8 val = 0; |
360 | |
361 | mask = SD_OCP_INT_CLR | SD_OC_CLR; |
362 | val = SD_OCP_INT_CLR | SD_OC_CLR; |
363 | |
364 | rtsx_pci_write_register(pcr, REG_OCPCTL, mask, data: val); |
365 | |
366 | udelay(1000); |
367 | rtsx_pci_write_register(pcr, REG_OCPCTL, mask, data: 0); |
368 | |
369 | } |
370 | |
371 | static void rts5228_process_ocp(struct rtsx_pcr *pcr) |
372 | { |
373 | if (!pcr->option.ocp_en) |
374 | return; |
375 | |
376 | rtsx_pci_get_ocpstat(pcr, val: &pcr->ocp_stat); |
377 | |
378 | if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { |
379 | rts5228_clear_ocpstat(pcr); |
380 | rts5228_card_power_off(pcr, RTSX_SD_CARD); |
381 | rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, data: 0); |
382 | pcr->ocp_stat = 0; |
383 | } |
384 | |
385 | } |
386 | |
387 | static void rts5228_init_from_cfg(struct rtsx_pcr *pcr) |
388 | { |
389 | struct rtsx_cr_option *option = &pcr->option; |
390 | |
391 | if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN |
392 | | PM_L1_1_EN | PM_L1_2_EN)) |
393 | rtsx_pci_disable_oobs_polling(pcr); |
394 | else |
395 | rtsx_pci_enable_oobs_polling(pcr); |
396 | |
397 | rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask: 0xFF, data: 0); |
398 | |
399 | if (option->ltr_en) { |
400 | if (option->ltr_enabled) |
401 | rtsx_set_ltr_latency(pcr, latency: option->ltr_active_latency); |
402 | } |
403 | } |
404 | |
405 | static int (struct rtsx_pcr *pcr) |
406 | { |
407 | struct rtsx_cr_option *option = &pcr->option; |
408 | |
409 | rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1, |
410 | CD_RESUME_EN_MASK, CD_RESUME_EN_MASK); |
411 | |
412 | rts5228_init_from_cfg(pcr); |
413 | |
414 | rtsx_pci_write_register(pcr, L1SUB_CONFIG1, |
415 | AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE); |
416 | rtsx_pci_write_register(pcr, L1SUB_CONFIG3, mask: 0xFF, data: 0); |
417 | |
418 | rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, |
419 | FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG); |
420 | |
421 | rtsx_pci_write_register(pcr, PCLK_CTL, |
422 | PCLK_MODE_SEL, PCLK_MODE_SEL); |
423 | |
424 | rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); |
425 | rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN); |
426 | |
427 | /* LED shine disabled, set initial shine cycle period */ |
428 | rtsx_pci_write_register(pcr, OLT_LED_CTL, mask: 0x0F, data: 0x02); |
429 | |
430 | /* Configure driving */ |
431 | rts5228_fill_driving(pcr, OUTPUT_3V3); |
432 | |
433 | if (pcr->flags & PCR_REVERSE_SOCKET) |
434 | rtsx_pci_write_register(pcr, PETXCFG, mask: 0x30, data: 0x30); |
435 | else |
436 | rtsx_pci_write_register(pcr, PETXCFG, mask: 0x30, data: 0x00); |
437 | |
438 | /* |
439 | * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced |
440 | * to drive low, and we forcibly request clock. |
441 | */ |
442 | if (option->force_clkreq_0) |
443 | rtsx_pci_write_register(pcr, PETXCFG, |
444 | FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); |
445 | else |
446 | rtsx_pci_write_register(pcr, PETXCFG, |
447 | FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); |
448 | |
449 | rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, mask: 0xFF, data: 0xFB); |
450 | |
451 | if (pcr->rtd3_en) { |
452 | rtsx_pci_write_register(pcr, addr: pcr->reg_pm_ctrl3, mask: 0x01, data: 0x01); |
453 | rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL, |
454 | FORCE_PM_CONTROL | FORCE_PM_VALUE, |
455 | FORCE_PM_CONTROL | FORCE_PM_VALUE); |
456 | } else { |
457 | rtsx_pci_write_register(pcr, addr: pcr->reg_pm_ctrl3, mask: 0x01, data: 0x00); |
458 | rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL, |
459 | FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL); |
460 | } |
461 | rtsx_pci_write_register(pcr, addr: pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, data: 0x00); |
462 | |
463 | return 0; |
464 | } |
465 | |
466 | static void rts5228_enable_aspm(struct rtsx_pcr *pcr, bool enable) |
467 | { |
468 | u8 mask, val; |
469 | |
470 | if (pcr->aspm_enabled == enable) |
471 | return; |
472 | |
473 | mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; |
474 | val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; |
475 | val |= (pcr->aspm_en & 0x02); |
476 | rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, data: val); |
477 | pcie_capability_clear_and_set_word(dev: pcr->pci, PCI_EXP_LNKCTL, |
478 | PCI_EXP_LNKCTL_ASPMC, set: pcr->aspm_en); |
479 | pcr->aspm_enabled = enable; |
480 | } |
481 | |
482 | static void rts5228_disable_aspm(struct rtsx_pcr *pcr, bool enable) |
483 | { |
484 | u8 mask, val; |
485 | |
486 | if (pcr->aspm_enabled == enable) |
487 | return; |
488 | |
489 | pcie_capability_clear_and_set_word(dev: pcr->pci, PCI_EXP_LNKCTL, |
490 | PCI_EXP_LNKCTL_ASPMC, set: 0); |
491 | mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; |
492 | val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; |
493 | rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, data: val); |
494 | rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, data: 0); |
495 | mdelay(10); |
496 | pcr->aspm_enabled = enable; |
497 | } |
498 | |
499 | static void rts5228_set_aspm(struct rtsx_pcr *pcr, bool enable) |
500 | { |
501 | if (enable) |
502 | rts5228_enable_aspm(pcr, enable: true); |
503 | else |
504 | rts5228_disable_aspm(pcr, enable: false); |
505 | } |
506 | |
507 | static void rts5228_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) |
508 | { |
509 | struct rtsx_cr_option *option = &pcr->option; |
510 | int aspm_L1_1, aspm_L1_2; |
511 | u8 val = 0; |
512 | |
513 | aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); |
514 | aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); |
515 | |
516 | if (active) { |
517 | /* run, latency: 60us */ |
518 | if (aspm_L1_1) |
519 | val = option->ltr_l1off_snooze_sspwrgate; |
520 | } else { |
521 | /* l1off, latency: 300us */ |
522 | if (aspm_L1_2) |
523 | val = option->ltr_l1off_sspwrgate; |
524 | } |
525 | |
526 | rtsx_set_l1off_sub(pcr, val); |
527 | } |
528 | |
529 | static const struct pcr_ops rts5228_pcr_ops = { |
530 | .fetch_vendor_settings = rtsx5228_fetch_vendor_settings, |
531 | .turn_on_led = rts5228_turn_on_led, |
532 | .turn_off_led = rts5228_turn_off_led, |
533 | .extra_init_hw = rts5228_extra_init_hw, |
534 | .enable_auto_blink = rts5228_enable_auto_blink, |
535 | .disable_auto_blink = rts5228_disable_auto_blink, |
536 | .card_power_on = rts5228_card_power_on, |
537 | .card_power_off = rts5228_card_power_off, |
538 | .switch_output_voltage = rts5228_switch_output_voltage, |
539 | .force_power_down = rts5228_force_power_down, |
540 | .stop_cmd = rts5228_stop_cmd, |
541 | .set_aspm = rts5228_set_aspm, |
542 | .set_l1off_cfg_sub_d0 = rts5228_set_l1off_cfg_sub_d0, |
543 | .enable_ocp = rts5228_enable_ocp, |
544 | .disable_ocp = rts5228_disable_ocp, |
545 | .init_ocp = rts5228_init_ocp, |
546 | .process_ocp = rts5228_process_ocp, |
547 | .clear_ocpstat = rts5228_clear_ocpstat, |
548 | .optimize_phy = rts5228_optimize_phy, |
549 | }; |
550 | |
551 | |
552 | static inline u8 double_ssc_depth(u8 depth) |
553 | { |
554 | return ((depth > 1) ? (depth - 1) : depth); |
555 | } |
556 | |
557 | int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, |
558 | u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk) |
559 | { |
560 | int err, clk; |
561 | u16 n; |
562 | u8 clk_divider, mcu_cnt, div; |
563 | static const u8 depth[] = { |
564 | [RTSX_SSC_DEPTH_4M] = RTS5228_SSC_DEPTH_4M, |
565 | [RTSX_SSC_DEPTH_2M] = RTS5228_SSC_DEPTH_2M, |
566 | [RTSX_SSC_DEPTH_1M] = RTS5228_SSC_DEPTH_1M, |
567 | [RTSX_SSC_DEPTH_500K] = RTS5228_SSC_DEPTH_512K, |
568 | }; |
569 | |
570 | if (initial_mode) { |
571 | /* We use 250k(around) here, in initial stage */ |
572 | clk_divider = SD_CLK_DIVIDE_128; |
573 | card_clock = 30000000; |
574 | } else { |
575 | clk_divider = SD_CLK_DIVIDE_0; |
576 | } |
577 | err = rtsx_pci_write_register(pcr, SD_CFG1, |
578 | SD_CLK_DIVIDE_MASK, data: clk_divider); |
579 | if (err < 0) |
580 | return err; |
581 | |
582 | card_clock /= 1000000; |
583 | pcr_dbg(pcr, "Switch card clock to %dMHz\n" , card_clock); |
584 | |
585 | clk = card_clock; |
586 | if (!initial_mode && double_clk) |
587 | clk = card_clock * 2; |
588 | pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n" , |
589 | clk, pcr->cur_clock); |
590 | |
591 | if (clk == pcr->cur_clock) |
592 | return 0; |
593 | |
594 | if (pcr->ops->conv_clk_and_div_n) |
595 | n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); |
596 | else |
597 | n = clk - 4; |
598 | if ((clk <= 4) || (n > 396)) |
599 | return -EINVAL; |
600 | |
601 | mcu_cnt = 125/clk + 3; |
602 | if (mcu_cnt > 15) |
603 | mcu_cnt = 15; |
604 | |
605 | div = CLK_DIV_1; |
606 | while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) { |
607 | if (pcr->ops->conv_clk_and_div_n) { |
608 | int dbl_clk = pcr->ops->conv_clk_and_div_n(n, |
609 | DIV_N_TO_CLK) * 2; |
610 | n = pcr->ops->conv_clk_and_div_n(dbl_clk, |
611 | CLK_TO_DIV_N); |
612 | } else { |
613 | n = (n + 4) * 2 - 4; |
614 | } |
615 | div++; |
616 | } |
617 | |
618 | n = (n / 2) - 1; |
619 | pcr_dbg(pcr, "n = %d, div = %d\n" , n, div); |
620 | |
621 | ssc_depth = depth[ssc_depth]; |
622 | if (double_clk) |
623 | ssc_depth = double_ssc_depth(depth: ssc_depth); |
624 | |
625 | if (ssc_depth) { |
626 | if (div == CLK_DIV_2) { |
627 | if (ssc_depth > 1) |
628 | ssc_depth -= 1; |
629 | else |
630 | ssc_depth = RTS5228_SSC_DEPTH_8M; |
631 | } else if (div == CLK_DIV_4) { |
632 | if (ssc_depth > 2) |
633 | ssc_depth -= 2; |
634 | else |
635 | ssc_depth = RTS5228_SSC_DEPTH_8M; |
636 | } else if (div == CLK_DIV_8) { |
637 | if (ssc_depth > 3) |
638 | ssc_depth -= 3; |
639 | else |
640 | ssc_depth = RTS5228_SSC_DEPTH_8M; |
641 | } |
642 | } else { |
643 | ssc_depth = 0; |
644 | } |
645 | pcr_dbg(pcr, "ssc_depth = %d\n" , ssc_depth); |
646 | |
647 | rtsx_pci_init_cmd(pcr); |
648 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, |
649 | CLK_LOW_FREQ, CLK_LOW_FREQ); |
650 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, |
651 | mask: 0xFF, data: (div << 4) | mcu_cnt); |
652 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, data: 0); |
653 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, |
654 | SSC_DEPTH_MASK, data: ssc_depth); |
655 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, mask: 0xFF, data: n); |
656 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); |
657 | if (vpclk) { |
658 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, |
659 | PHASE_NOT_RESET, data: 0); |
660 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, |
661 | PHASE_NOT_RESET, data: 0); |
662 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, |
663 | PHASE_NOT_RESET, PHASE_NOT_RESET); |
664 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, |
665 | PHASE_NOT_RESET, PHASE_NOT_RESET); |
666 | } |
667 | |
668 | err = rtsx_pci_send_cmd(pcr, timeout: 2000); |
669 | if (err < 0) |
670 | return err; |
671 | |
672 | /* Wait SSC clock stable */ |
673 | udelay(SSC_CLOCK_STABLE_WAIT); |
674 | err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, data: 0); |
675 | if (err < 0) |
676 | return err; |
677 | |
678 | pcr->cur_clock = clk; |
679 | return 0; |
680 | |
681 | } |
682 | |
683 | void rts5228_init_params(struct rtsx_pcr *pcr) |
684 | { |
685 | struct rtsx_cr_option *option = &pcr->option; |
686 | struct rtsx_hw_param *hw_param = &pcr->hw_param; |
687 | |
688 | pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; |
689 | pcr->num_slots = 1; |
690 | pcr->ops = &rts5228_pcr_ops; |
691 | |
692 | pcr->flags = 0; |
693 | pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; |
694 | pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; |
695 | pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; |
696 | pcr->aspm_en = ASPM_L1_EN; |
697 | pcr->aspm_mode = ASPM_MODE_REG; |
698 | pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11); |
699 | pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); |
700 | |
701 | pcr->ic_version = rts5228_get_ic_version(pcr); |
702 | pcr->sd_pull_ctl_enable_tbl = rts5228_sd_pull_ctl_enable_tbl; |
703 | pcr->sd_pull_ctl_disable_tbl = rts5228_sd_pull_ctl_disable_tbl; |
704 | |
705 | pcr->reg_pm_ctrl3 = RTS5228_AUTOLOAD_CFG3; |
706 | |
707 | option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN |
708 | | LTR_L1SS_PWR_GATE_EN); |
709 | option->ltr_en = true; |
710 | |
711 | /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */ |
712 | option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF; |
713 | option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF; |
714 | option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF; |
715 | option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; |
716 | option->ltr_l1off_sspwrgate = 0x7F; |
717 | option->ltr_l1off_snooze_sspwrgate = 0x78; |
718 | |
719 | option->ocp_en = 1; |
720 | hw_param->interrupt_en |= SD_OC_INT_EN; |
721 | hw_param->ocp_glitch = SD_OCP_GLITCH_800U; |
722 | option->sd_800mA_ocp_thd = RTS5228_LDO1_OCP_THD_930; |
723 | } |
724 | |