1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Overview:
4	* This is the generic MTD driver for NAND flash devices. It should be
5	* capable of working with almost all NAND chips currently available.
6	*
7	* Additional technical information is available on
8	* http://www.linux-mtd.infradead.org/doc/nand.html
9	*
10	* Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
11	* 2002-2006 Thomas Gleixner (tglx@linutronix.de)
12	*
13	* Credits:
14	* David Woodhouse for adding multichip support
15	*
16	* Aleph One Ltd. and Toby Churchill Ltd. for supporting the
17	* rework for 2K page size chips
18	*
19	* TODO:
20	* Enable cached programming for 2k page size chips
21	* Check, if mtd->ecctype should be set to MTD_ECC_HW
22	* if we have HW ECC support.
23	* BBT table is not serialized, has to be fixed
24	*/
25
26	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
28	#include <linux/module.h>
29	#include <linux/delay.h>
30	#include <linux/errno.h>
31	#include <linux/err.h>
32	#include <linux/sched.h>
33	#include <linux/slab.h>
34	#include <linux/mm.h>
35	#include <linux/types.h>
36	#include <linux/mtd/mtd.h>
37	#include <linux/mtd/nand.h>
38	#include <linux/mtd/nand-ecc-sw-hamming.h>
39	#include <linux/mtd/nand-ecc-sw-bch.h>
40	#include <linux/interrupt.h>
41	#include <linux/bitops.h>
42	#include <linux/io.h>
43	#include <linux/mtd/partitions.h>
44	#include <linux/of.h>
45	#include <linux/gpio/consumer.h>
46
47	#include "internals.h"
48
49	static int nand_pairing_dist3_get_info(struct mtd_info *mtd, int page,
50	struct mtd_pairing_info *info)
51	{
52	int lastpage = (mtd->erasesize / mtd->writesize) - 1;
53	int dist = 3;
54
55	if (page == lastpage)
56	dist = 2;
57
58	if (!page || (page & 1)) {
59	info->group = 0;
60	info->pair = (page + 1) / 2;
61	} else {
62	info->group = 1;
63	info->pair = (page + 1 - dist) / 2;
64	}
65
66	return 0;
67	}
68
69	static int nand_pairing_dist3_get_wunit(struct mtd_info *mtd,
70	const struct mtd_pairing_info *info)
71	{
72	int lastpair = ((mtd->erasesize / mtd->writesize) - 1) / 2;
73	int page = info->pair * 2;
74	int dist = 3;
75
76	if (!info->group && !info->pair)
77	return 0;
78
79	if (info->pair == lastpair && info->group)
80	dist = 2;
81
82	if (!info->group)
83	page--;
84	else if (info->pair)
85	page += dist - 1;
86
87	if (page >= mtd->erasesize / mtd->writesize)
88	return -EINVAL;
89
90	return page;
91	}
92
93	const struct mtd_pairing_scheme dist3_pairing_scheme = {
94	.ngroups = 2,
95	.get_info = nand_pairing_dist3_get_info,
96	.get_wunit = nand_pairing_dist3_get_wunit,
97	};
98
99	static int check_offs_len(struct nand_chip *chip, loff_t ofs, uint64_t len)
100	{
101	int ret = 0;
102
103	/* Start address must align on block boundary */
104	if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
105	pr_debug("%s: unaligned address\n", __func__);
106	ret = -EINVAL;
107	}
108
109	/* Length must align on block boundary */
110	if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
111	pr_debug("%s: length not block aligned\n", __func__);
112	ret = -EINVAL;
113	}
114
115	return ret;
116	}
117
118	/**
119	* nand_extract_bits - Copy unaligned bits from one buffer to another one
120	* @dst: destination buffer
121	* @dst_off: bit offset at which the writing starts
122	* @src: source buffer
123	* @src_off: bit offset at which the reading starts
124	* @nbits: number of bits to copy from @src to @dst
125	*
126	* Copy bits from one memory region to another (overlap authorized).
127	*/
128	void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src,
129	unsigned int src_off, unsigned int nbits)
130	{
131	unsigned int tmp, n;
132
133	dst += dst_off / 8;
134	dst_off %= 8;
135	src += src_off / 8;
136	src_off %= 8;
137
138	while (nbits) {
139	n = min3(8 - dst_off, 8 - src_off, nbits);
140
141	tmp = (*src >> src_off) & GENMASK(n - 1, 0);
142	*dst &= ~GENMASK(n - 1 + dst_off, dst_off);
143	*dst |= tmp << dst_off;
144
145	dst_off += n;
146	if (dst_off >= 8) {
147	dst++;
148	dst_off -= 8;
149	}
150
151	src_off += n;
152	if (src_off >= 8) {
153	src++;
154	src_off -= 8;
155	}
156
157	nbits -= n;
158	}
159	}
160	EXPORT_SYMBOL_GPL(nand_extract_bits);
161
162	/**
163	* nand_select_target() - Select a NAND target (A.K.A. die)
164	* @chip: NAND chip object
165	* @cs: the CS line to select. Note that this CS id is always from the chip
166	* PoV, not the controller one
167	*
168	* Select a NAND target so that further operations executed on @chip go to the
169	* selected NAND target.
170	*/
171	void nand_select_target(struct nand_chip *chip, unsigned int cs)
172	{
173	/*
174	* cs should always lie between 0 and nanddev_ntargets(), when that's
175	* not the case it's a bug and the caller should be fixed.
176	*/
177	if (WARN_ON(cs > nanddev_ntargets(&chip->base)))
178	return;
179
180	chip->cur_cs = cs;
181
182	if (chip->legacy.select_chip)
183	chip->legacy.select_chip(chip, cs);
184	}
185	EXPORT_SYMBOL_GPL(nand_select_target);
186
187	/**
188	* nand_deselect_target() - Deselect the currently selected target
189	* @chip: NAND chip object
190	*
191	* Deselect the currently selected NAND target. The result of operations
192	* executed on @chip after the target has been deselected is undefined.
193	*/
194	void nand_deselect_target(struct nand_chip *chip)
195	{
196	if (chip->legacy.select_chip)
197	chip->legacy.select_chip(chip, -1);
198
199	chip->cur_cs = -1;
200	}
201	EXPORT_SYMBOL_GPL(nand_deselect_target);
202
203	/**
204	* nand_release_device - [GENERIC] release chip
205	* @chip: NAND chip object
206	*
207	* Release chip lock and wake up anyone waiting on the device.
208	*/
209	static void nand_release_device(struct nand_chip *chip)
210	{
211	/* Release the controller and the chip */
212	mutex_unlock(lock: &chip->controller->lock);
213	mutex_unlock(lock: &chip->lock);
214	}
215
216	/**
217	* nand_bbm_get_next_page - Get the next page for bad block markers
218	* @chip: NAND chip object
219	* @page: First page to start checking for bad block marker usage
220	*
221	* Returns an integer that corresponds to the page offset within a block, for
222	* a page that is used to store bad block markers. If no more pages are
223	* available, -EINVAL is returned.
224	*/
225	int nand_bbm_get_next_page(struct nand_chip *chip, int page)
226	{
227	struct mtd_info *mtd = nand_to_mtd(chip);
228	int last_page = ((mtd->erasesize - mtd->writesize) >>
229	chip->page_shift) & chip->pagemask;
230	unsigned int bbm_flags = NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE
231	| NAND_BBM_LASTPAGE;
232
233	if (page == 0 && !(chip->options & bbm_flags))
234	return 0;
235	if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE)
236	return 0;
237	if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE)
238	return 1;
239	if (page <= last_page && chip->options & NAND_BBM_LASTPAGE)
240	return last_page;
241
242	return -EINVAL;
243	}
244
245	/**
246	* nand_block_bad - [DEFAULT] Read bad block marker from the chip
247	* @chip: NAND chip object
248	* @ofs: offset from device start
249	*
250	* Check, if the block is bad.
251	*/
252	static int nand_block_bad(struct nand_chip *chip, loff_t ofs)
253	{
254	int first_page, page_offset;
255	int res;
256	u8 bad;
257
258	first_page = (int)(ofs >> chip->page_shift) & chip->pagemask;
259	page_offset = nand_bbm_get_next_page(chip, page: 0);
260
261	while (page_offset >= 0) {
262	res = chip->ecc.read_oob(chip, first_page + page_offset);
263	if (res < 0)
264	return res;
265
266	bad = chip->oob_poi[chip->badblockpos];
267
268	if (likely(chip->badblockbits == 8))
269	res = bad != 0xFF;
270	else
271	res = hweight8(bad) < chip->badblockbits;
272	if (res)
273	return res;
274
275	page_offset = nand_bbm_get_next_page(chip, page: page_offset + 1);
276	}
277
278	return 0;
279	}
280
281	/**
282	* nand_region_is_secured() - Check if the region is secured
283	* @chip: NAND chip object
284	* @offset: Offset of the region to check
285	* @size: Size of the region to check
286	*
287	* Checks if the region is secured by comparing the offset and size with the
288	* list of secure regions obtained from DT. Returns true if the region is
289	* secured else false.
290	*/
291	static bool nand_region_is_secured(struct nand_chip *chip, loff_t offset, u64 size)
292	{
293	int i;
294
295	/* Skip touching the secure regions if present */
296	for (i = 0; i < chip->nr_secure_regions; i++) {
297	const struct nand_secure_region *region = &chip->secure_regions[i];
298
299	if (offset + size <= region->offset ||
300	offset >= region->offset + region->size)
301	continue;
302
303	pr_debug("%s: Region 0x%llx - 0x%llx is secured!",
304	__func__, offset, offset + size);
305
306	return true;
307	}
308
309	return false;
310	}
311
312	static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs)
313	{
314	struct mtd_info *mtd = nand_to_mtd(chip);
315
316	if (chip->options & NAND_NO_BBM_QUIRK)
317	return 0;
318
319	/* Check if the region is secured */
320	if (nand_region_is_secured(chip, offset: ofs, size: mtd->erasesize))
321	return -EIO;
322
323	if (mtd_check_expert_analysis_mode())
324	return 0;
325
326	if (chip->legacy.block_bad)
327	return chip->legacy.block_bad(chip, ofs);
328
329	return nand_block_bad(chip, ofs);
330	}
331
332	/**
333	* nand_get_device - [GENERIC] Get chip for selected access
334	* @chip: NAND chip structure
335	*
336	* Lock the device and its controller for exclusive access
337	*/
338	static void nand_get_device(struct nand_chip *chip)
339	{
340	/* Wait until the device is resumed. */
341	while (1) {
342	mutex_lock(&chip->lock);
343	if (!chip->suspended) {
344	mutex_lock(&chip->controller->lock);
345	return;
346	}
347	mutex_unlock(lock: &chip->lock);
348
349	wait_event(chip->resume_wq, !chip->suspended);
350	}
351	}
352
353	/**
354	* nand_check_wp - [GENERIC] check if the chip is write protected
355	* @chip: NAND chip object
356	*
357	* Check, if the device is write protected. The function expects, that the
358	* device is already selected.
359	*/
360	static int nand_check_wp(struct nand_chip *chip)
361	{
362	u8 status;
363	int ret;
364
365	/* Broken xD cards report WP despite being writable */
366	if (chip->options & NAND_BROKEN_XD)
367	return 0;
368
369	/* controller responsible for NAND write protect */
370	if (chip->controller->controller_wp)
371	return 0;
372
373	/* Check the WP bit */
374	ret = nand_status_op(chip, status: &status);
375	if (ret)
376	return ret;
377
378	return status & NAND_STATUS_WP ? 0 : 1;
379	}
380
381	/**
382	* nand_fill_oob - [INTERN] Transfer client buffer to oob
383	* @chip: NAND chip object
384	* @oob: oob data buffer
385	* @len: oob data write length
386	* @ops: oob ops structure
387	*/
388	static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
389	struct mtd_oob_ops *ops)
390	{
391	struct mtd_info *mtd = nand_to_mtd(chip);
392	int ret;
393
394	/*
395	* Initialise to all 0xFF, to avoid the possibility of left over OOB
396	* data from a previous OOB read.
397	*/
398	memset(chip->oob_poi, 0xff, mtd->oobsize);
399
400	switch (ops->mode) {
401
402	case MTD_OPS_PLACE_OOB:
403	case MTD_OPS_RAW:
404	memcpy(chip->oob_poi + ops->ooboffs, oob, len);
405	return oob + len;
406
407	case MTD_OPS_AUTO_OOB:
408	ret = mtd_ooblayout_set_databytes(mtd, databuf: oob, oobbuf: chip->oob_poi,
409	start: ops->ooboffs, nbytes: len);
410	BUG_ON(ret);
411	return oob + len;
412
413	default:
414	BUG();
415	}
416	return NULL;
417	}
418
419	/**
420	* nand_do_write_oob - [MTD Interface] NAND write out-of-band
421	* @chip: NAND chip object
422	* @to: offset to write to
423	* @ops: oob operation description structure
424	*
425	* NAND write out-of-band.
426	*/
427	static int nand_do_write_oob(struct nand_chip *chip, loff_t to,
428	struct mtd_oob_ops *ops)
429	{
430	struct mtd_info *mtd = nand_to_mtd(chip);
431	int chipnr, page, status, len, ret;
432
433	pr_debug("%s: to = 0x%08x, len = %i\n",
434	__func__, (unsigned int)to, (int)ops->ooblen);
435
436	len = mtd_oobavail(mtd, ops);
437
438	/* Do not allow write past end of page */
439	if ((ops->ooboffs + ops->ooblen) > len) {
440	pr_debug("%s: attempt to write past end of page\n",
441	__func__);
442	return -EINVAL;
443	}
444
445	/* Check if the region is secured */
446	if (nand_region_is_secured(chip, offset: to, size: ops->ooblen))
447	return -EIO;
448
449	chipnr = (int)(to >> chip->chip_shift);
450
451	/*
452	* Reset the chip. Some chips (like the Toshiba TC5832DC found in one
453	* of my DiskOnChip 2000 test units) will clear the whole data page too
454	* if we don't do this. I have no clue why, but I seem to have 'fixed'
455	* it in the doc2000 driver in August 1999. dwmw2.
456	*/
457	ret = nand_reset(chip, chipnr);
458	if (ret)
459	return ret;
460
461	nand_select_target(chip, chipnr);
462
463	/* Shift to get page */
464	page = (int)(to >> chip->page_shift);
465
466	/* Check, if it is write protected */
467	if (nand_check_wp(chip)) {
468	nand_deselect_target(chip);
469	return -EROFS;
470	}
471
472	/* Invalidate the page cache, if we write to the cached page */
473	if (page == chip->pagecache.page)
474	chip->pagecache.page = -1;
475
476	nand_fill_oob(chip, oob: ops->oobbuf, len: ops->ooblen, ops);
477
478	if (ops->mode == MTD_OPS_RAW)
479	status = chip->ecc.write_oob_raw(chip, page & chip->pagemask);
480	else
481	status = chip->ecc.write_oob(chip, page & chip->pagemask);
482
483	nand_deselect_target(chip);
484
485	if (status)
486	return status;
487
488	ops->oobretlen = ops->ooblen;
489
490	return 0;
491	}
492
493	/**
494	* nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
495	* @chip: NAND chip object
496	* @ofs: offset from device start
497	*
498	* This is the default implementation, which can be overridden by a hardware
499	* specific driver. It provides the details for writing a bad block marker to a
500	* block.
501	*/
502	static int nand_default_block_markbad(struct nand_chip *chip, loff_t ofs)
503	{
504	struct mtd_info *mtd = nand_to_mtd(chip);
505	struct mtd_oob_ops ops;
506	uint8_t buf[2] = { 0, 0 };
507	int ret = 0, res, page_offset;
508
509	memset(&ops, 0, sizeof(ops));
510	ops.oobbuf = buf;
511	ops.ooboffs = chip->badblockpos;
512	if (chip->options & NAND_BUSWIDTH_16) {
513	ops.ooboffs &= ~0x01;
514	ops.len = ops.ooblen = 2;
515	} else {
516	ops.len = ops.ooblen = 1;
517	}
518	ops.mode = MTD_OPS_PLACE_OOB;
519
520	page_offset = nand_bbm_get_next_page(chip, page: 0);
521
522	while (page_offset >= 0) {
523	res = nand_do_write_oob(chip,
524	to: ofs + (page_offset * mtd->writesize),
525	ops: &ops);
526
527	if (!ret)
528	ret = res;
529
530	page_offset = nand_bbm_get_next_page(chip, page: page_offset + 1);
531	}
532
533	return ret;
534	}
535
536	/**
537	* nand_markbad_bbm - mark a block by updating the BBM
538	* @chip: NAND chip object
539	* @ofs: offset of the block to mark bad
540	*/
541	int nand_markbad_bbm(struct nand_chip *chip, loff_t ofs)
542	{
543	if (chip->legacy.block_markbad)
544	return chip->legacy.block_markbad(chip, ofs);
545
546	return nand_default_block_markbad(chip, ofs);
547	}
548
549	/**
550	* nand_block_markbad_lowlevel - mark a block bad
551	* @chip: NAND chip object
552	* @ofs: offset from device start
553	*
554	* This function performs the generic NAND bad block marking steps (i.e., bad
555	* block table(s) and/or marker(s)). We only allow the hardware driver to
556	* specify how to write bad block markers to OOB (chip->legacy.block_markbad).
557	*
558	* We try operations in the following order:
559	*
560	* (1) erase the affected block, to allow OOB marker to be written cleanly
561	* (2) write bad block marker to OOB area of affected block (unless flag
562	* NAND_BBT_NO_OOB_BBM is present)
563	* (3) update the BBT
564	*
565	* Note that we retain the first error encountered in (2) or (3), finish the
566	* procedures, and dump the error in the end.
567	*/
568	static int nand_block_markbad_lowlevel(struct nand_chip *chip, loff_t ofs)
569	{
570	struct mtd_info *mtd = nand_to_mtd(chip);
571	int res, ret = 0;
572
573	if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
574	struct erase_info einfo;
575
576	/* Attempt erase before marking OOB */
577	memset(&einfo, 0, sizeof(einfo));
578	einfo.addr = ofs;
579	einfo.len = 1ULL << chip->phys_erase_shift;
580	nand_erase_nand(chip, instr: &einfo, allowbbt: 0);
581
582	/* Write bad block marker to OOB */
583	nand_get_device(chip);
584
585	ret = nand_markbad_bbm(chip, ofs);
586	nand_release_device(chip);
587	}
588
589	/* Mark block bad in BBT */
590	if (chip->bbt) {
591	res = nand_markbad_bbt(chip, offs: ofs);
592	if (!ret)
593	ret = res;
594	}
595
596	if (!ret)
597	mtd->ecc_stats.badblocks++;
598
599	return ret;
600	}
601
602	/**
603	* nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
604	* @mtd: MTD device structure
605	* @ofs: offset from device start
606	*
607	* Check if the block is marked as reserved.
608	*/
609	static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
610	{
611	struct nand_chip *chip = mtd_to_nand(mtd);
612
613	if (!chip->bbt)
614	return 0;
615	/* Return info from the table */
616	return nand_isreserved_bbt(chip, offs: ofs);
617	}
618
619	/**
620	* nand_block_checkbad - [GENERIC] Check if a block is marked bad
621	* @chip: NAND chip object
622	* @ofs: offset from device start
623	* @allowbbt: 1, if its allowed to access the bbt area
624	*
625	* Check, if the block is bad. Either by reading the bad block table or
626	* calling of the scan function.
627	*/
628	static int nand_block_checkbad(struct nand_chip *chip, loff_t ofs, int allowbbt)
629	{
630	/* Return info from the table */
631	if (chip->bbt)
632	return nand_isbad_bbt(chip, offs: ofs, allowbbt);
633
634	return nand_isbad_bbm(chip, ofs);
635	}
636
637	/**
638	* nand_soft_waitrdy - Poll STATUS reg until RDY bit is set to 1
639	* @chip: NAND chip structure
640	* @timeout_ms: Timeout in ms
641	*
642	* Poll the STATUS register using ->exec_op() until the RDY bit becomes 1.
643	* If that does not happen whitin the specified timeout, -ETIMEDOUT is
644	* returned.
645	*
646	* This helper is intended to be used when the controller does not have access
647	* to the NAND R/B pin.
648	*
649	* Be aware that calling this helper from an ->exec_op() implementation means
650	* ->exec_op() must be re-entrant.
651	*
652	* Return 0 if the NAND chip is ready, a negative error otherwise.
653	*/
654	int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms)
655	{
656	const struct nand_interface_config *conf;
657	u8 status = 0;
658	int ret;
659
660	if (!nand_has_exec_op(chip))
661	return -ENOTSUPP;
662
663	/* Wait tWB before polling the STATUS reg. */
664	conf = nand_get_interface_config(chip);
665	ndelay(NAND_COMMON_TIMING_NS(conf, tWB_max));
666
667	ret = nand_status_op(chip, NULL);
668	if (ret)
669	return ret;
670
671	/*
672	* +1 below is necessary because if we are now in the last fraction
673	* of jiffy and msecs_to_jiffies is 1 then we will wait only that
674	* small jiffy fraction - possibly leading to false timeout
675	*/
676	timeout_ms = jiffies + msecs_to_jiffies(m: timeout_ms) + 1;
677	do {
678	ret = nand_read_data_op(chip, buf: &status, len: sizeof(status), force_8bit: true,
679	check_only: false);
680	if (ret)
681	break;
682
683	if (status & NAND_STATUS_READY)
684	break;
685
686	/*
687	* Typical lowest execution time for a tR on most NANDs is 10us,
688	* use this as polling delay before doing something smarter (ie.
689	* deriving a delay from the timeout value, timeout_ms/ratio).
690	*/
691	udelay(10);
692	} while (time_before(jiffies, timeout_ms));
693
694	/*
695	* We have to exit READ_STATUS mode in order to read real data on the
696	* bus in case the WAITRDY instruction is preceding a DATA_IN
697	* instruction.
698	*/
699	nand_exit_status_op(chip);
700
701	if (ret)
702	return ret;
703
704	return status & NAND_STATUS_READY ? 0 : -ETIMEDOUT;
705	};
706	EXPORT_SYMBOL_GPL(nand_soft_waitrdy);
707
708	/**
709	* nand_gpio_waitrdy - Poll R/B GPIO pin until ready
710	* @chip: NAND chip structure
711	* @gpiod: GPIO descriptor of R/B pin
712	* @timeout_ms: Timeout in ms
713	*
714	* Poll the R/B GPIO pin until it becomes ready. If that does not happen
715	* whitin the specified timeout, -ETIMEDOUT is returned.
716	*
717	* This helper is intended to be used when the controller has access to the
718	* NAND R/B pin over GPIO.
719	*
720	* Return 0 if the R/B pin indicates chip is ready, a negative error otherwise.
721	*/
722	int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
723	unsigned long timeout_ms)
724	{
725
726	/*
727	* Wait until R/B pin indicates chip is ready or timeout occurs.
728	* +1 below is necessary because if we are now in the last fraction
729	* of jiffy and msecs_to_jiffies is 1 then we will wait only that
730	* small jiffy fraction - possibly leading to false timeout.
731	*/
732	timeout_ms = jiffies + msecs_to_jiffies(m: timeout_ms) + 1;
733	do {
734	if (gpiod_get_value_cansleep(desc: gpiod))
735	return 0;
736
737	cond_resched();
738	} while (time_before(jiffies, timeout_ms));
739
740	return gpiod_get_value_cansleep(desc: gpiod) ? 0 : -ETIMEDOUT;
741	};
742	EXPORT_SYMBOL_GPL(nand_gpio_waitrdy);
743
744	/**
745	* panic_nand_wait - [GENERIC] wait until the command is done
746	* @chip: NAND chip structure
747	* @timeo: timeout
748	*
749	* Wait for command done. This is a helper function for nand_wait used when
750	* we are in interrupt context. May happen when in panic and trying to write
751	* an oops through mtdoops.
752	*/
753	void panic_nand_wait(struct nand_chip *chip, unsigned long timeo)
754	{
755	int i;
756	for (i = 0; i < timeo; i++) {
757	if (chip->legacy.dev_ready) {
758	if (chip->legacy.dev_ready(chip))
759	break;
760	} else {
761	int ret;
762	u8 status;
763
764	ret = nand_read_data_op(chip, buf: &status, len: sizeof(status),
765	force_8bit: true, check_only: false);
766	if (ret)
767	return;
768
769	if (status & NAND_STATUS_READY)
770	break;
771	}
772	mdelay(1);
773	}
774	}
775
776	static bool nand_supports_get_features(struct nand_chip *chip, int addr)
777	{
778	return (chip->parameters.supports_set_get_features &&
779	test_bit(addr, chip->parameters.get_feature_list));
780	}
781
782	static bool nand_supports_set_features(struct nand_chip *chip, int addr)
783	{
784	return (chip->parameters.supports_set_get_features &&
785	test_bit(addr, chip->parameters.set_feature_list));
786	}
787
788	/**
789	* nand_reset_interface - Reset data interface and timings
790	* @chip: The NAND chip
791	* @chipnr: Internal die id
792	*
793	* Reset the Data interface and timings to ONFI mode 0.
794	*
795	* Returns 0 for success or negative error code otherwise.
796	*/
797	static int nand_reset_interface(struct nand_chip *chip, int chipnr)
798	{
799	const struct nand_controller_ops *ops = chip->controller->ops;
800	int ret;
801
802	if (!nand_controller_can_setup_interface(chip))
803	return 0;
804
805	/*
806	* The ONFI specification says:
807	* "
808	* To transition from NV-DDR or NV-DDR2 to the SDR data
809	* interface, the host shall use the Reset (FFh) command
810	* using SDR timing mode 0. A device in any timing mode is
811	* required to recognize Reset (FFh) command issued in SDR
812	* timing mode 0.
813	* "
814	*
815	* Configure the data interface in SDR mode and set the
816	* timings to timing mode 0.
817	*/
818
819	chip->current_interface_config = nand_get_reset_interface_config();
820	ret = ops->setup_interface(chip, chipnr,
821	chip->current_interface_config);
822	if (ret)
823	pr_err("Failed to configure data interface to SDR timing mode 0\n");
824
825	return ret;
826	}
827
828	/**
829	* nand_setup_interface - Setup the best data interface and timings
830	* @chip: The NAND chip
831	* @chipnr: Internal die id
832	*
833	* Configure what has been reported to be the best data interface and NAND
834	* timings supported by the chip and the driver.
835	*
836	* Returns 0 for success or negative error code otherwise.
837	*/
838	static int nand_setup_interface(struct nand_chip *chip, int chipnr)
839	{
840	const struct nand_controller_ops *ops = chip->controller->ops;
841	u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { }, request;
842	int ret;
843
844	if (!nand_controller_can_setup_interface(chip))
845	return 0;
846
847	/*
848	* A nand_reset_interface() put both the NAND chip and the NAND
849	* controller in timings mode 0. If the default mode for this chip is
850	* also 0, no need to proceed to the change again. Plus, at probe time,
851	* nand_setup_interface() uses ->set/get_features() which would
852	* fail anyway as the parameter page is not available yet.
853	*/
854	if (!chip->best_interface_config)
855	return 0;
856
857	request = chip->best_interface_config->timings.mode;
858	if (nand_interface_is_sdr(conf: chip->best_interface_config))
859	request |= ONFI_DATA_INTERFACE_SDR;
860	else
861	request |= ONFI_DATA_INTERFACE_NVDDR;
862	tmode_param[0] = request;
863
864	/* Change the mode on the chip side (if supported by the NAND chip) */
865	if (nand_supports_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) {
866	nand_select_target(chip, chipnr);
867	ret = nand_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,
868	subfeature_param: tmode_param);
869	nand_deselect_target(chip);
870	if (ret)
871	return ret;
872	}
873
874	/* Change the mode on the controller side */
875	ret = ops->setup_interface(chip, chipnr, chip->best_interface_config);
876	if (ret)
877	return ret;
878
879	/* Check the mode has been accepted by the chip, if supported */
880	if (!nand_supports_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE))
881	goto update_interface_config;
882
883	memset(tmode_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
884	nand_select_target(chip, chipnr);
885	ret = nand_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,
886	subfeature_param: tmode_param);
887	nand_deselect_target(chip);
888	if (ret)
889	goto err_reset_chip;
890
891	if (request != tmode_param[0]) {
892	pr_warn("%s timing mode %d not acknowledged by the NAND chip\n",
893	nand_interface_is_nvddr(chip->best_interface_config) ? "NV-DDR" : "SDR",
894	chip->best_interface_config->timings.mode);
895	pr_debug("NAND chip would work in %s timing mode %d\n",
896	tmode_param[0] & ONFI_DATA_INTERFACE_NVDDR ? "NV-DDR" : "SDR",
897	(unsigned int)ONFI_TIMING_MODE_PARAM(tmode_param[0]));
898	goto err_reset_chip;
899	}
900
901	update_interface_config:
902	chip->current_interface_config = chip->best_interface_config;
903
904	return 0;
905
906	err_reset_chip:
907	/*
908	* Fallback to mode 0 if the chip explicitly did not ack the chosen
909	* timing mode.
910	*/
911	nand_reset_interface(chip, chipnr);
912	nand_select_target(chip, chipnr);
913	nand_reset_op(chip);
914	nand_deselect_target(chip);
915
916	return ret;
917	}
918
919	/**
920	* nand_choose_best_sdr_timings - Pick up the best SDR timings that both the
921	* NAND controller and the NAND chip support
922	* @chip: the NAND chip
923	* @iface: the interface configuration (can eventually be updated)
924	* @spec_timings: specific timings, when not fitting the ONFI specification
925	*
926	* If specific timings are provided, use them. Otherwise, retrieve supported
927	* timing modes from ONFI information.
928	*/
929	int nand_choose_best_sdr_timings(struct nand_chip *chip,
930	struct nand_interface_config *iface,
931	struct nand_sdr_timings *spec_timings)
932	{
933	const struct nand_controller_ops *ops = chip->controller->ops;
934	int best_mode = 0, mode, ret = -EOPNOTSUPP;
935
936	iface->type = NAND_SDR_IFACE;
937
938	if (spec_timings) {
939	iface->timings.sdr = *spec_timings;
940	iface->timings.mode = onfi_find_closest_sdr_mode(spec_timings);
941
942	/* Verify the controller supports the requested interface */
943	ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
944	iface);
945	if (!ret) {
946	chip->best_interface_config = iface;
947	return ret;
948	}
949
950	/* Fallback to slower modes */
951	best_mode = iface->timings.mode;
952	} else if (chip->parameters.onfi) {
953	best_mode = fls(x: chip->parameters.onfi->sdr_timing_modes) - 1;
954	}
955
956	for (mode = best_mode; mode >= 0; mode--) {
957	onfi_fill_interface_config(chip, iface, type: NAND_SDR_IFACE, timing_mode: mode);
958
959	ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
960	iface);
961	if (!ret) {
962	chip->best_interface_config = iface;
963	break;
964	}
965	}
966
967	return ret;
968	}
969
970	/**
971	* nand_choose_best_nvddr_timings - Pick up the best NVDDR timings that both the
972	* NAND controller and the NAND chip support
973	* @chip: the NAND chip
974	* @iface: the interface configuration (can eventually be updated)
975	* @spec_timings: specific timings, when not fitting the ONFI specification
976	*
977	* If specific timings are provided, use them. Otherwise, retrieve supported
978	* timing modes from ONFI information.
979	*/
980	int nand_choose_best_nvddr_timings(struct nand_chip *chip,
981	struct nand_interface_config *iface,
982	struct nand_nvddr_timings *spec_timings)
983	{
984	const struct nand_controller_ops *ops = chip->controller->ops;
985	int best_mode = 0, mode, ret = -EOPNOTSUPP;
986
987	iface->type = NAND_NVDDR_IFACE;
988
989	if (spec_timings) {
990	iface->timings.nvddr = *spec_timings;
991	iface->timings.mode = onfi_find_closest_nvddr_mode(spec_timings);
992
993	/* Verify the controller supports the requested interface */
994	ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
995	iface);
996	if (!ret) {
997	chip->best_interface_config = iface;
998	return ret;
999	}
1000
1001	/* Fallback to slower modes */
1002	best_mode = iface->timings.mode;
1003	} else if (chip->parameters.onfi) {
1004	best_mode = fls(x: chip->parameters.onfi->nvddr_timing_modes) - 1;
1005	}
1006
1007	for (mode = best_mode; mode >= 0; mode--) {
1008	onfi_fill_interface_config(chip, iface, type: NAND_NVDDR_IFACE, timing_mode: mode);
1009
1010	ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,
1011	iface);
1012	if (!ret) {
1013	chip->best_interface_config = iface;
1014	break;
1015	}
1016	}
1017
1018	return ret;
1019	}
1020
1021	/**
1022	* nand_choose_best_timings - Pick up the best NVDDR or SDR timings that both
1023	* NAND controller and the NAND chip support
1024	* @chip: the NAND chip
1025	* @iface: the interface configuration (can eventually be updated)
1026	*
1027	* If specific timings are provided, use them. Otherwise, retrieve supported
1028	* timing modes from ONFI information.
1029	*/
1030	static int nand_choose_best_timings(struct nand_chip *chip,
1031	struct nand_interface_config *iface)
1032	{
1033	int ret;
1034
1035	/* Try the fastest timings: NV-DDR */
1036	ret = nand_choose_best_nvddr_timings(chip, iface, NULL);
1037	if (!ret)
1038	return 0;
1039
1040	/* Fallback to SDR timings otherwise */
1041	return nand_choose_best_sdr_timings(chip, iface, NULL);
1042	}
1043
1044	/**
1045	* nand_choose_interface_config - find the best data interface and timings
1046	* @chip: The NAND chip
1047	*
1048	* Find the best data interface and NAND timings supported by the chip
1049	* and the driver. Eventually let the NAND manufacturer driver propose his own
1050	* set of timings.
1051	*
1052	* After this function nand_chip->interface_config is initialized with the best
1053	* timing mode available.
1054	*
1055	* Returns 0 for success or negative error code otherwise.
1056	*/
1057	static int nand_choose_interface_config(struct nand_chip *chip)
1058	{
1059	struct nand_interface_config *iface;
1060	int ret;
1061
1062	if (!nand_controller_can_setup_interface(chip))
1063	return 0;
1064
1065	iface = kzalloc(size: sizeof(*iface), GFP_KERNEL);
1066	if (!iface)
1067	return -ENOMEM;
1068
1069	if (chip->ops.choose_interface_config)
1070	ret = chip->ops.choose_interface_config(chip, iface);
1071	else
1072	ret = nand_choose_best_timings(chip, iface);
1073
1074	if (ret)
1075	kfree(objp: iface);
1076
1077	return ret;
1078	}
1079
1080	/**
1081	* nand_fill_column_cycles - fill the column cycles of an address
1082	* @chip: The NAND chip
1083	* @addrs: Array of address cycles to fill
1084	* @offset_in_page: The offset in the page
1085	*
1086	* Fills the first or the first two bytes of the @addrs field depending
1087	* on the NAND bus width and the page size.
1088	*
1089	* Returns the number of cycles needed to encode the column, or a negative
1090	* error code in case one of the arguments is invalid.
1091	*/
1092	static int nand_fill_column_cycles(struct nand_chip *chip, u8 *addrs,
1093	unsigned int offset_in_page)
1094	{
1095	struct mtd_info *mtd = nand_to_mtd(chip);
1096
1097	/* Make sure the offset is less than the actual page size. */
1098	if (offset_in_page > mtd->writesize + mtd->oobsize)
1099	return -EINVAL;
1100
1101	/*
1102	* On small page NANDs, there's a dedicated command to access the OOB
1103	* area, and the column address is relative to the start of the OOB
1104	* area, not the start of the page. Asjust the address accordingly.
1105	*/
1106	if (mtd->writesize <= 512 && offset_in_page >= mtd->writesize)
1107	offset_in_page -= mtd->writesize;
1108
1109	/*
1110	* The offset in page is expressed in bytes, if the NAND bus is 16-bit
1111	* wide, then it must be divided by 2.
1112	*/
1113	if (chip->options & NAND_BUSWIDTH_16) {
1114	if (WARN_ON(offset_in_page % 2))
1115	return -EINVAL;
1116
1117	offset_in_page /= 2;
1118	}
1119
1120	addrs[0] = offset_in_page;
1121
1122	/*
1123	* Small page NANDs use 1 cycle for the columns, while large page NANDs
1124	* need 2
1125	*/
1126	if (mtd->writesize <= 512)
1127	return 1;
1128
1129	addrs[1] = offset_in_page >> 8;
1130
1131	return 2;
1132	}
1133
1134	static int nand_sp_exec_read_page_op(struct nand_chip *chip, unsigned int page,
1135	unsigned int offset_in_page, void *buf,
1136	unsigned int len)
1137	{
1138	const struct nand_interface_config *conf =
1139	nand_get_interface_config(chip);
1140	struct mtd_info *mtd = nand_to_mtd(chip);
1141	u8 addrs[4];
1142	struct nand_op_instr instrs[] = {
1143	NAND_OP_CMD(NAND_CMD_READ0, 0),
1144	NAND_OP_ADDR(3, addrs, NAND_COMMON_TIMING_NS(conf, tWB_max)),
1145	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),
1146	NAND_COMMON_TIMING_NS(conf, tRR_min)),
1147	NAND_OP_DATA_IN(len, buf, 0),
1148	};
1149	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1150	int ret;
1151
1152	/* Drop the DATA_IN instruction if len is set to 0. */
1153	if (!len)
1154	op.ninstrs--;
1155
1156	if (offset_in_page >= mtd->writesize)
1157	instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB;
1158	else if (offset_in_page >= 256 &&
1159	!(chip->options & NAND_BUSWIDTH_16))
1160	instrs[0].ctx.cmd.opcode = NAND_CMD_READ1;
1161
1162	ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1163	if (ret < 0)
1164	return ret;
1165
1166	addrs[1] = page;
1167	addrs[2] = page >> 8;
1168
1169	if (chip->options & NAND_ROW_ADDR_3) {
1170	addrs[3] = page >> 16;
1171	instrs[1].ctx.addr.naddrs++;
1172	}
1173
1174	return nand_exec_op(chip, op: &op);
1175	}
1176
1177	static int nand_lp_exec_read_page_op(struct nand_chip *chip, unsigned int page,
1178	unsigned int offset_in_page, void *buf,
1179	unsigned int len)
1180	{
1181	const struct nand_interface_config *conf =
1182	nand_get_interface_config(chip);
1183	u8 addrs[5];
1184	struct nand_op_instr instrs[] = {
1185	NAND_OP_CMD(NAND_CMD_READ0, 0),
1186	NAND_OP_ADDR(4, addrs, 0),
1187	NAND_OP_CMD(NAND_CMD_READSTART, NAND_COMMON_TIMING_NS(conf, tWB_max)),
1188	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),
1189	NAND_COMMON_TIMING_NS(conf, tRR_min)),
1190	NAND_OP_DATA_IN(len, buf, 0),
1191	};
1192	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1193	int ret;
1194
1195	/* Drop the DATA_IN instruction if len is set to 0. */
1196	if (!len)
1197	op.ninstrs--;
1198
1199	ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1200	if (ret < 0)
1201	return ret;
1202
1203	addrs[2] = page;
1204	addrs[3] = page >> 8;
1205
1206	if (chip->options & NAND_ROW_ADDR_3) {
1207	addrs[4] = page >> 16;
1208	instrs[1].ctx.addr.naddrs++;
1209	}
1210
1211	return nand_exec_op(chip, op: &op);
1212	}
1213
1214	static unsigned int rawnand_last_page_of_lun(unsigned int pages_per_lun, unsigned int lun)
1215	{
1216	/* lun is expected to be very small */
1217	return (lun * pages_per_lun) + pages_per_lun - 1;
1218	}
1219
1220	static void rawnand_cap_cont_reads(struct nand_chip *chip)
1221	{
1222	struct nand_memory_organization *memorg;
1223	unsigned int ppl, first_lun, last_lun;
1224
1225	memorg = nanddev_get_memorg(nand: &chip->base);
1226	ppl = memorg->pages_per_eraseblock * memorg->eraseblocks_per_lun;
1227	first_lun = chip->cont_read.first_page / ppl;
1228	last_lun = chip->cont_read.last_page / ppl;
1229
1230	/* Prevent sequential cache reads across LUN boundaries */
1231	if (first_lun != last_lun)
1232	chip->cont_read.pause_page = rawnand_last_page_of_lun(pages_per_lun: ppl, lun: first_lun);
1233	else
1234	chip->cont_read.pause_page = chip->cont_read.last_page;
1235
1236	if (chip->cont_read.first_page == chip->cont_read.pause_page) {
1237	chip->cont_read.first_page++;
1238	chip->cont_read.pause_page = min(chip->cont_read.last_page,
1239	rawnand_last_page_of_lun(ppl, first_lun + 1));
1240	}
1241
1242	if (chip->cont_read.first_page >= chip->cont_read.last_page)
1243	chip->cont_read.ongoing = false;
1244	}
1245
1246	static int nand_lp_exec_cont_read_page_op(struct nand_chip *chip, unsigned int page,
1247	unsigned int offset_in_page, void *buf,
1248	unsigned int len, bool check_only)
1249	{
1250	const struct nand_interface_config *conf =
1251	nand_get_interface_config(chip);
1252	u8 addrs[5];
1253	struct nand_op_instr start_instrs[] = {
1254	NAND_OP_CMD(NAND_CMD_READ0, 0),
1255	NAND_OP_ADDR(4, addrs, 0),
1256	NAND_OP_CMD(NAND_CMD_READSTART, NAND_COMMON_TIMING_NS(conf, tWB_max)),
1257	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max), 0),
1258	NAND_OP_CMD(NAND_CMD_READCACHESEQ, NAND_COMMON_TIMING_NS(conf, tWB_max)),
1259	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),
1260	NAND_COMMON_TIMING_NS(conf, tRR_min)),
1261	NAND_OP_DATA_IN(len, buf, 0),
1262	};
1263	struct nand_op_instr cont_instrs[] = {
1264	NAND_OP_CMD(page == chip->cont_read.pause_page ?
1265	NAND_CMD_READCACHEEND : NAND_CMD_READCACHESEQ,
1266	NAND_COMMON_TIMING_NS(conf, tWB_max)),
1267	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),
1268	NAND_COMMON_TIMING_NS(conf, tRR_min)),
1269	NAND_OP_DATA_IN(len, buf, 0),
1270	};
1271	struct nand_operation start_op = NAND_OPERATION(chip->cur_cs, start_instrs);
1272	struct nand_operation cont_op = NAND_OPERATION(chip->cur_cs, cont_instrs);
1273	int ret;
1274
1275	if (!len) {
1276	start_op.ninstrs--;
1277	cont_op.ninstrs--;
1278	}
1279
1280	ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1281	if (ret < 0)
1282	return ret;
1283
1284	addrs[2] = page;
1285	addrs[3] = page >> 8;
1286
1287	if (chip->options & NAND_ROW_ADDR_3) {
1288	addrs[4] = page >> 16;
1289	start_instrs[1].ctx.addr.naddrs++;
1290	}
1291
1292	/* Check if cache reads are supported */
1293	if (check_only) {
1294	if (nand_check_op(chip, op: &start_op) || nand_check_op(chip, op: &cont_op))
1295	return -EOPNOTSUPP;
1296
1297	return 0;
1298	}
1299
1300	if (page == chip->cont_read.first_page)
1301	ret = nand_exec_op(chip, op: &start_op);
1302	else
1303	ret = nand_exec_op(chip, op: &cont_op);
1304	if (ret)
1305	return ret;
1306
1307	if (!chip->cont_read.ongoing)
1308	return 0;
1309
1310	if (page == chip->cont_read.last_page) {
1311	chip->cont_read.ongoing = false;
1312	} else if (page == chip->cont_read.pause_page) {
1313	chip->cont_read.first_page++;
1314	rawnand_cap_cont_reads(chip);
1315	}
1316
1317	return 0;
1318	}
1319
1320	static bool rawnand_cont_read_ongoing(struct nand_chip *chip, unsigned int page)
1321	{
1322	return chip->cont_read.ongoing && page >= chip->cont_read.first_page;
1323	}
1324
1325	/**
1326	* nand_read_page_op - Do a READ PAGE operation
1327	* @chip: The NAND chip
1328	* @page: page to read
1329	* @offset_in_page: offset within the page
1330	* @buf: buffer used to store the data
1331	* @len: length of the buffer
1332	*
1333	* This function issues a READ PAGE operation.
1334	* This function does not select/unselect the CS line.
1335	*
1336	* Returns 0 on success, a negative error code otherwise.
1337	*/
1338	int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1339	unsigned int offset_in_page, void *buf, unsigned int len)
1340	{
1341	struct mtd_info *mtd = nand_to_mtd(chip);
1342
1343	if (len && !buf)
1344	return -EINVAL;
1345
1346	if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1347	return -EINVAL;
1348
1349	if (nand_has_exec_op(chip)) {
1350	if (mtd->writesize > 512) {
1351	if (rawnand_cont_read_ongoing(chip, page))
1352	return nand_lp_exec_cont_read_page_op(chip, page,
1353	offset_in_page,
1354	buf, len, check_only: false);
1355	else
1356	return nand_lp_exec_read_page_op(chip, page,
1357	offset_in_page, buf,
1358	len);
1359	}
1360
1361	return nand_sp_exec_read_page_op(chip, page, offset_in_page,
1362	buf, len);
1363	}
1364
1365	chip->legacy.cmdfunc(chip, NAND_CMD_READ0, offset_in_page, page);
1366	if (len)
1367	chip->legacy.read_buf(chip, buf, len);
1368
1369	return 0;
1370	}
1371	EXPORT_SYMBOL_GPL(nand_read_page_op);
1372
1373	/**
1374	* nand_read_param_page_op - Do a READ PARAMETER PAGE operation
1375	* @chip: The NAND chip
1376	* @page: parameter page to read
1377	* @buf: buffer used to store the data
1378	* @len: length of the buffer
1379	*
1380	* This function issues a READ PARAMETER PAGE operation.
1381	* This function does not select/unselect the CS line.
1382	*
1383	* Returns 0 on success, a negative error code otherwise.
1384	*/
1385	int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,
1386	unsigned int len)
1387	{
1388	unsigned int i;
1389	u8 *p = buf;
1390
1391	if (len && !buf)
1392	return -EINVAL;
1393
1394	if (nand_has_exec_op(chip)) {
1395	const struct nand_interface_config *conf =
1396	nand_get_interface_config(chip);
1397	struct nand_op_instr instrs[] = {
1398	NAND_OP_CMD(NAND_CMD_PARAM, 0),
1399	NAND_OP_ADDR(1, &page,
1400	NAND_COMMON_TIMING_NS(conf, tWB_max)),
1401	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),
1402	NAND_COMMON_TIMING_NS(conf, tRR_min)),
1403	NAND_OP_8BIT_DATA_IN(len, buf, 0),
1404	};
1405	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1406
1407	/* Drop the DATA_IN instruction if len is set to 0. */
1408	if (!len)
1409	op.ninstrs--;
1410
1411	return nand_exec_op(chip, op: &op);
1412	}
1413
1414	chip->legacy.cmdfunc(chip, NAND_CMD_PARAM, page, -1);
1415	for (i = 0; i < len; i++)
1416	p[i] = chip->legacy.read_byte(chip);
1417
1418	return 0;
1419	}
1420
1421	/**
1422	* nand_change_read_column_op - Do a CHANGE READ COLUMN operation
1423	* @chip: The NAND chip
1424	* @offset_in_page: offset within the page
1425	* @buf: buffer used to store the data
1426	* @len: length of the buffer
1427	* @force_8bit: force 8-bit bus access
1428	*
1429	* This function issues a CHANGE READ COLUMN operation.
1430	* This function does not select/unselect the CS line.
1431	*
1432	* Returns 0 on success, a negative error code otherwise.
1433	*/
1434	int nand_change_read_column_op(struct nand_chip *chip,
1435	unsigned int offset_in_page, void *buf,
1436	unsigned int len, bool force_8bit)
1437	{
1438	struct mtd_info *mtd = nand_to_mtd(chip);
1439
1440	if (len && !buf)
1441	return -EINVAL;
1442
1443	if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1444	return -EINVAL;
1445
1446	/* Small page NANDs do not support column change. */
1447	if (mtd->writesize <= 512)
1448	return -ENOTSUPP;
1449
1450	if (nand_has_exec_op(chip)) {
1451	const struct nand_interface_config *conf =
1452	nand_get_interface_config(chip);
1453	u8 addrs[2] = {};
1454	struct nand_op_instr instrs[] = {
1455	NAND_OP_CMD(NAND_CMD_RNDOUT, 0),
1456	NAND_OP_ADDR(2, addrs, 0),
1457	NAND_OP_CMD(NAND_CMD_RNDOUTSTART,
1458	NAND_COMMON_TIMING_NS(conf, tCCS_min)),
1459	NAND_OP_DATA_IN(len, buf, 0),
1460	};
1461	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1462	int ret;
1463
1464	ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1465	if (ret < 0)
1466	return ret;
1467
1468	/* Drop the DATA_IN instruction if len is set to 0. */
1469	if (!len)
1470	op.ninstrs--;
1471
1472	instrs[3].ctx.data.force_8bit = force_8bit;
1473
1474	return nand_exec_op(chip, op: &op);
1475	}
1476
1477	chip->legacy.cmdfunc(chip, NAND_CMD_RNDOUT, offset_in_page, -1);
1478	if (len)
1479	chip->legacy.read_buf(chip, buf, len);
1480
1481	return 0;
1482	}
1483	EXPORT_SYMBOL_GPL(nand_change_read_column_op);
1484
1485	/**
1486	* nand_read_oob_op - Do a READ OOB operation
1487	* @chip: The NAND chip
1488	* @page: page to read
1489	* @offset_in_oob: offset within the OOB area
1490	* @buf: buffer used to store the data
1491	* @len: length of the buffer
1492	*
1493	* This function issues a READ OOB operation.
1494	* This function does not select/unselect the CS line.
1495	*
1496	* Returns 0 on success, a negative error code otherwise.
1497	*/
1498	int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1499	unsigned int offset_in_oob, void *buf, unsigned int len)
1500	{
1501	struct mtd_info *mtd = nand_to_mtd(chip);
1502
1503	if (len && !buf)
1504	return -EINVAL;
1505
1506	if (offset_in_oob + len > mtd->oobsize)
1507	return -EINVAL;
1508
1509	if (nand_has_exec_op(chip))
1510	return nand_read_page_op(chip, page,
1511	mtd->writesize + offset_in_oob,
1512	buf, len);
1513
1514	chip->legacy.cmdfunc(chip, NAND_CMD_READOOB, offset_in_oob, page);
1515	if (len)
1516	chip->legacy.read_buf(chip, buf, len);
1517
1518	return 0;
1519	}
1520	EXPORT_SYMBOL_GPL(nand_read_oob_op);
1521
1522	static int nand_exec_prog_page_op(struct nand_chip *chip, unsigned int page,
1523	unsigned int offset_in_page, const void *buf,
1524	unsigned int len, bool prog)
1525	{
1526	const struct nand_interface_config *conf =
1527	nand_get_interface_config(chip);
1528	struct mtd_info *mtd = nand_to_mtd(chip);
1529	u8 addrs[5] = {};
1530	struct nand_op_instr instrs[] = {
1531	/*
1532	* The first instruction will be dropped if we're dealing
1533	* with a large page NAND and adjusted if we're dealing
1534	* with a small page NAND and the page offset is > 255.
1535	*/
1536	NAND_OP_CMD(NAND_CMD_READ0, 0),
1537	NAND_OP_CMD(NAND_CMD_SEQIN, 0),
1538	NAND_OP_ADDR(0, addrs, NAND_COMMON_TIMING_NS(conf, tADL_min)),
1539	NAND_OP_DATA_OUT(len, buf, 0),
1540	NAND_OP_CMD(NAND_CMD_PAGEPROG,
1541	NAND_COMMON_TIMING_NS(conf, tWB_max)),
1542	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tPROG_max), 0),
1543	};
1544	struct nand_operation op = NAND_DESTRUCTIVE_OPERATION(chip->cur_cs,
1545	instrs);
1546	int naddrs = nand_fill_column_cycles(chip, addrs, offset_in_page);
1547
1548	if (naddrs < 0)
1549	return naddrs;
1550
1551	addrs[naddrs++] = page;
1552	addrs[naddrs++] = page >> 8;
1553	if (chip->options & NAND_ROW_ADDR_3)
1554	addrs[naddrs++] = page >> 16;
1555
1556	instrs[2].ctx.addr.naddrs = naddrs;
1557
1558	/* Drop the last two instructions if we're not programming the page. */
1559	if (!prog) {
1560	op.ninstrs -= 2;
1561	/* Also drop the DATA_OUT instruction if empty. */
1562	if (!len)
1563	op.ninstrs--;
1564	}
1565
1566	if (mtd->writesize <= 512) {
1567	/*
1568	* Small pages need some more tweaking: we have to adjust the
1569	* first instruction depending on the page offset we're trying
1570	* to access.
1571	*/
1572	if (offset_in_page >= mtd->writesize)
1573	instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB;
1574	else if (offset_in_page >= 256 &&
1575	!(chip->options & NAND_BUSWIDTH_16))
1576	instrs[0].ctx.cmd.opcode = NAND_CMD_READ1;
1577	} else {
1578	/*
1579	* Drop the first command if we're dealing with a large page
1580	* NAND.
1581	*/
1582	op.instrs++;
1583	op.ninstrs--;
1584	}
1585
1586	return nand_exec_op(chip, op: &op);
1587	}
1588
1589	/**
1590	* nand_prog_page_begin_op - starts a PROG PAGE operation
1591	* @chip: The NAND chip
1592	* @page: page to write
1593	* @offset_in_page: offset within the page
1594	* @buf: buffer containing the data to write to the page
1595	* @len: length of the buffer
1596	*
1597	* This function issues the first half of a PROG PAGE operation.
1598	* This function does not select/unselect the CS line.
1599	*
1600	* Returns 0 on success, a negative error code otherwise.
1601	*/
1602	int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1603	unsigned int offset_in_page, const void *buf,
1604	unsigned int len)
1605	{
1606	struct mtd_info *mtd = nand_to_mtd(chip);
1607
1608	if (len && !buf)
1609	return -EINVAL;
1610
1611	if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1612	return -EINVAL;
1613
1614	if (nand_has_exec_op(chip))
1615	return nand_exec_prog_page_op(chip, page, offset_in_page, buf,
1616	len, prog: false);
1617
1618	chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, page);
1619
1620	if (buf)
1621	chip->legacy.write_buf(chip, buf, len);
1622
1623	return 0;
1624	}
1625	EXPORT_SYMBOL_GPL(nand_prog_page_begin_op);
1626
1627	/**
1628	* nand_prog_page_end_op - ends a PROG PAGE operation
1629	* @chip: The NAND chip
1630	*
1631	* This function issues the second half of a PROG PAGE operation.
1632	* This function does not select/unselect the CS line.
1633	*
1634	* Returns 0 on success, a negative error code otherwise.
1635	*/
1636	int nand_prog_page_end_op(struct nand_chip *chip)
1637	{
1638	int ret;
1639	u8 status;
1640
1641	if (nand_has_exec_op(chip)) {
1642	const struct nand_interface_config *conf =
1643	nand_get_interface_config(chip);
1644	struct nand_op_instr instrs[] = {
1645	NAND_OP_CMD(NAND_CMD_PAGEPROG,
1646	NAND_COMMON_TIMING_NS(conf, tWB_max)),
1647	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tPROG_max),
1648	0),
1649	};
1650	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1651
1652	ret = nand_exec_op(chip, op: &op);
1653	if (ret)
1654	return ret;
1655
1656	ret = nand_status_op(chip, status: &status);
1657	if (ret)
1658	return ret;
1659	} else {
1660	chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
1661	ret = chip->legacy.waitfunc(chip);
1662	if (ret < 0)
1663	return ret;
1664
1665	status = ret;
1666	}
1667
1668	if (status & NAND_STATUS_FAIL)
1669	return -EIO;
1670
1671	return 0;
1672	}
1673	EXPORT_SYMBOL_GPL(nand_prog_page_end_op);
1674
1675	/**
1676	* nand_prog_page_op - Do a full PROG PAGE operation
1677	* @chip: The NAND chip
1678	* @page: page to write
1679	* @offset_in_page: offset within the page
1680	* @buf: buffer containing the data to write to the page
1681	* @len: length of the buffer
1682	*
1683	* This function issues a full PROG PAGE operation.
1684	* This function does not select/unselect the CS line.
1685	*
1686	* Returns 0 on success, a negative error code otherwise.
1687	*/
1688	int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1689	unsigned int offset_in_page, const void *buf,
1690	unsigned int len)
1691	{
1692	struct mtd_info *mtd = nand_to_mtd(chip);
1693	u8 status;
1694	int ret;
1695
1696	if (!len || !buf)
1697	return -EINVAL;
1698
1699	if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1700	return -EINVAL;
1701
1702	if (nand_has_exec_op(chip)) {
1703	ret = nand_exec_prog_page_op(chip, page, offset_in_page, buf,
1704	len, prog: true);
1705	if (ret)
1706	return ret;
1707
1708	ret = nand_status_op(chip, status: &status);
1709	if (ret)
1710	return ret;
1711	} else {
1712	chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page,
1713	page);
1714	chip->legacy.write_buf(chip, buf, len);
1715	chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);
1716	ret = chip->legacy.waitfunc(chip);
1717	if (ret < 0)
1718	return ret;
1719
1720	status = ret;
1721	}
1722
1723	if (status & NAND_STATUS_FAIL)
1724	return -EIO;
1725
1726	return 0;
1727	}
1728	EXPORT_SYMBOL_GPL(nand_prog_page_op);
1729
1730	/**
1731	* nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation
1732	* @chip: The NAND chip
1733	* @offset_in_page: offset within the page
1734	* @buf: buffer containing the data to send to the NAND
1735	* @len: length of the buffer
1736	* @force_8bit: force 8-bit bus access
1737	*
1738	* This function issues a CHANGE WRITE COLUMN operation.
1739	* This function does not select/unselect the CS line.
1740	*
1741	* Returns 0 on success, a negative error code otherwise.
1742	*/
1743	int nand_change_write_column_op(struct nand_chip *chip,
1744	unsigned int offset_in_page,
1745	const void *buf, unsigned int len,
1746	bool force_8bit)
1747	{
1748	struct mtd_info *mtd = nand_to_mtd(chip);
1749
1750	if (len && !buf)
1751	return -EINVAL;
1752
1753	if (offset_in_page + len > mtd->writesize + mtd->oobsize)
1754	return -EINVAL;
1755
1756	/* Small page NANDs do not support column change. */
1757	if (mtd->writesize <= 512)
1758	return -ENOTSUPP;
1759
1760	if (nand_has_exec_op(chip)) {
1761	const struct nand_interface_config *conf =
1762	nand_get_interface_config(chip);
1763	u8 addrs[2];
1764	struct nand_op_instr instrs[] = {
1765	NAND_OP_CMD(NAND_CMD_RNDIN, 0),
1766	NAND_OP_ADDR(2, addrs, NAND_COMMON_TIMING_NS(conf, tCCS_min)),
1767	NAND_OP_DATA_OUT(len, buf, 0),
1768	};
1769	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1770	int ret;
1771
1772	ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
1773	if (ret < 0)
1774	return ret;
1775
1776	instrs[2].ctx.data.force_8bit = force_8bit;
1777
1778	/* Drop the DATA_OUT instruction if len is set to 0. */
1779	if (!len)
1780	op.ninstrs--;
1781
1782	return nand_exec_op(chip, op: &op);
1783	}
1784
1785	chip->legacy.cmdfunc(chip, NAND_CMD_RNDIN, offset_in_page, -1);
1786	if (len)
1787	chip->legacy.write_buf(chip, buf, len);
1788
1789	return 0;
1790	}
1791	EXPORT_SYMBOL_GPL(nand_change_write_column_op);
1792
1793	/**
1794	* nand_readid_op - Do a READID operation
1795	* @chip: The NAND chip
1796	* @addr: address cycle to pass after the READID command
1797	* @buf: buffer used to store the ID
1798	* @len: length of the buffer
1799	*
1800	* This function sends a READID command and reads back the ID returned by the
1801	* NAND.
1802	* This function does not select/unselect the CS line.
1803	*
1804	* Returns 0 on success, a negative error code otherwise.
1805	*/
1806	int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1807	unsigned int len)
1808	{
1809	unsigned int i;
1810	u8 *id = buf, *ddrbuf = NULL;
1811
1812	if (len && !buf)
1813	return -EINVAL;
1814
1815	if (nand_has_exec_op(chip)) {
1816	const struct nand_interface_config *conf =
1817	nand_get_interface_config(chip);
1818	struct nand_op_instr instrs[] = {
1819	NAND_OP_CMD(NAND_CMD_READID, 0),
1820	NAND_OP_ADDR(1, &addr,
1821	NAND_COMMON_TIMING_NS(conf, tADL_min)),
1822	NAND_OP_8BIT_DATA_IN(len, buf, 0),
1823	};
1824	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1825	int ret;
1826
1827	/* READ_ID data bytes are received twice in NV-DDR mode */
1828	if (len && nand_interface_is_nvddr(conf)) {
1829	ddrbuf = kzalloc(size: len * 2, GFP_KERNEL);
1830	if (!ddrbuf)
1831	return -ENOMEM;
1832
1833	instrs[2].ctx.data.len *= 2;
1834	instrs[2].ctx.data.buf.in = ddrbuf;
1835	}
1836
1837	/* Drop the DATA_IN instruction if len is set to 0. */
1838	if (!len)
1839	op.ninstrs--;
1840
1841	ret = nand_exec_op(chip, op: &op);
1842	if (!ret && len && nand_interface_is_nvddr(conf)) {
1843	for (i = 0; i < len; i++)
1844	id[i] = ddrbuf[i * 2];
1845	}
1846
1847	kfree(objp: ddrbuf);
1848
1849	return ret;
1850	}
1851
1852	chip->legacy.cmdfunc(chip, NAND_CMD_READID, addr, -1);
1853
1854	for (i = 0; i < len; i++)
1855	id[i] = chip->legacy.read_byte(chip);
1856
1857	return 0;
1858	}
1859	EXPORT_SYMBOL_GPL(nand_readid_op);
1860
1861	/**
1862	* nand_status_op - Do a STATUS operation
1863	* @chip: The NAND chip
1864	* @status: out variable to store the NAND status
1865	*
1866	* This function sends a STATUS command and reads back the status returned by
1867	* the NAND.
1868	* This function does not select/unselect the CS line.
1869	*
1870	* Returns 0 on success, a negative error code otherwise.
1871	*/
1872	int nand_status_op(struct nand_chip *chip, u8 *status)
1873	{
1874	if (nand_has_exec_op(chip)) {
1875	const struct nand_interface_config *conf =
1876	nand_get_interface_config(chip);
1877	u8 ddrstatus[2];
1878	struct nand_op_instr instrs[] = {
1879	NAND_OP_CMD(NAND_CMD_STATUS,
1880	NAND_COMMON_TIMING_NS(conf, tADL_min)),
1881	NAND_OP_8BIT_DATA_IN(1, status, 0),
1882	};
1883	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1884	int ret;
1885
1886	/* The status data byte will be received twice in NV-DDR mode */
1887	if (status && nand_interface_is_nvddr(conf)) {
1888	instrs[1].ctx.data.len *= 2;
1889	instrs[1].ctx.data.buf.in = ddrstatus;
1890	}
1891
1892	if (!status)
1893	op.ninstrs--;
1894
1895	ret = nand_exec_op(chip, op: &op);
1896	if (!ret && status && nand_interface_is_nvddr(conf))
1897	*status = ddrstatus[0];
1898
1899	return ret;
1900	}
1901
1902	chip->legacy.cmdfunc(chip, NAND_CMD_STATUS, -1, -1);
1903	if (status)
1904	*status = chip->legacy.read_byte(chip);
1905
1906	return 0;
1907	}
1908	EXPORT_SYMBOL_GPL(nand_status_op);
1909
1910	/**
1911	* nand_exit_status_op - Exit a STATUS operation
1912	* @chip: The NAND chip
1913	*
1914	* This function sends a READ0 command to cancel the effect of the STATUS
1915	* command to avoid reading only the status until a new read command is sent.
1916	*
1917	* This function does not select/unselect the CS line.
1918	*
1919	* Returns 0 on success, a negative error code otherwise.
1920	*/
1921	int nand_exit_status_op(struct nand_chip *chip)
1922	{
1923	if (nand_has_exec_op(chip)) {
1924	struct nand_op_instr instrs[] = {
1925	NAND_OP_CMD(NAND_CMD_READ0, 0),
1926	};
1927	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
1928
1929	return nand_exec_op(chip, op: &op);
1930	}
1931
1932	chip->legacy.cmdfunc(chip, NAND_CMD_READ0, -1, -1);
1933
1934	return 0;
1935	}
1936	EXPORT_SYMBOL_GPL(nand_exit_status_op);
1937
1938	/**
1939	* nand_erase_op - Do an erase operation
1940	* @chip: The NAND chip
1941	* @eraseblock: block to erase
1942	*
1943	* This function sends an ERASE command and waits for the NAND to be ready
1944	* before returning.
1945	* This function does not select/unselect the CS line.
1946	*
1947	* Returns 0 on success, a negative error code otherwise.
1948	*/
1949	int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)
1950	{
1951	unsigned int page = eraseblock <<
1952	(chip->phys_erase_shift - chip->page_shift);
1953	int ret;
1954	u8 status;
1955
1956	if (nand_has_exec_op(chip)) {
1957	const struct nand_interface_config *conf =
1958	nand_get_interface_config(chip);
1959	u8 addrs[3] = { page, page >> 8, page >> 16 };
1960	struct nand_op_instr instrs[] = {
1961	NAND_OP_CMD(NAND_CMD_ERASE1, 0),
1962	NAND_OP_ADDR(2, addrs, 0),
1963	NAND_OP_CMD(NAND_CMD_ERASE2,
1964	NAND_COMMON_TIMING_NS(conf, tWB_max)),
1965	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tBERS_max),
1966	0),
1967	};
1968	struct nand_operation op = NAND_DESTRUCTIVE_OPERATION(chip->cur_cs,
1969	instrs);
1970
1971	if (chip->options & NAND_ROW_ADDR_3)
1972	instrs[1].ctx.addr.naddrs++;
1973
1974	ret = nand_exec_op(chip, op: &op);
1975	if (ret)
1976	return ret;
1977
1978	ret = nand_status_op(chip, &status);
1979	if (ret)
1980	return ret;
1981	} else {
1982	chip->legacy.cmdfunc(chip, NAND_CMD_ERASE1, -1, page);
1983	chip->legacy.cmdfunc(chip, NAND_CMD_ERASE2, -1, -1);
1984
1985	ret = chip->legacy.waitfunc(chip);
1986	if (ret < 0)
1987	return ret;
1988
1989	status = ret;
1990	}
1991
1992	if (status & NAND_STATUS_FAIL)
1993	return -EIO;
1994
1995	return 0;
1996	}
1997	EXPORT_SYMBOL_GPL(nand_erase_op);
1998
1999	/**
2000	* nand_set_features_op - Do a SET FEATURES operation
2001	* @chip: The NAND chip
2002	* @feature: feature id
2003	* @data: 4 bytes of data
2004	*
2005	* This function sends a SET FEATURES command and waits for the NAND to be
2006	* ready before returning.
2007	* This function does not select/unselect the CS line.
2008	*
2009	* Returns 0 on success, a negative error code otherwise.
2010	*/
2011	static int nand_set_features_op(struct nand_chip *chip, u8 feature,
2012	const void *data)
2013	{
2014	const u8 *params = data;
2015	int i, ret;
2016
2017	if (nand_has_exec_op(chip)) {
2018	const struct nand_interface_config *conf =
2019	nand_get_interface_config(chip);
2020	struct nand_op_instr instrs[] = {
2021	NAND_OP_CMD(NAND_CMD_SET_FEATURES, 0),
2022	NAND_OP_ADDR(1, &feature, NAND_COMMON_TIMING_NS(conf,
2023	tADL_min)),
2024	NAND_OP_8BIT_DATA_OUT(ONFI_SUBFEATURE_PARAM_LEN, data,
2025	NAND_COMMON_TIMING_NS(conf,
2026	tWB_max)),
2027	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tFEAT_max),
2028	0),
2029	};
2030	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2031
2032	return nand_exec_op(chip, op: &op);
2033	}
2034
2035	chip->legacy.cmdfunc(chip, NAND_CMD_SET_FEATURES, feature, -1);
2036	for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2037	chip->legacy.write_byte(chip, params[i]);
2038
2039	ret = chip->legacy.waitfunc(chip);
2040	if (ret < 0)
2041	return ret;
2042
2043	if (ret & NAND_STATUS_FAIL)
2044	return -EIO;
2045
2046	return 0;
2047	}
2048
2049	/**
2050	* nand_get_features_op - Do a GET FEATURES operation
2051	* @chip: The NAND chip
2052	* @feature: feature id
2053	* @data: 4 bytes of data
2054	*
2055	* This function sends a GET FEATURES command and waits for the NAND to be
2056	* ready before returning.
2057	* This function does not select/unselect the CS line.
2058	*
2059	* Returns 0 on success, a negative error code otherwise.
2060	*/
2061	static int nand_get_features_op(struct nand_chip *chip, u8 feature,
2062	void *data)
2063	{
2064	u8 *params = data, ddrbuf[ONFI_SUBFEATURE_PARAM_LEN * 2];
2065	int i;
2066
2067	if (nand_has_exec_op(chip)) {
2068	const struct nand_interface_config *conf =
2069	nand_get_interface_config(chip);
2070	struct nand_op_instr instrs[] = {
2071	NAND_OP_CMD(NAND_CMD_GET_FEATURES, 0),
2072	NAND_OP_ADDR(1, &feature,
2073	NAND_COMMON_TIMING_NS(conf, tWB_max)),
2074	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tFEAT_max),
2075	NAND_COMMON_TIMING_NS(conf, tRR_min)),
2076	NAND_OP_8BIT_DATA_IN(ONFI_SUBFEATURE_PARAM_LEN,
2077	data, 0),
2078	};
2079	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2080	int ret;
2081
2082	/* GET_FEATURE data bytes are received twice in NV-DDR mode */
2083	if (nand_interface_is_nvddr(conf)) {
2084	instrs[3].ctx.data.len *= 2;
2085	instrs[3].ctx.data.buf.in = ddrbuf;
2086	}
2087
2088	ret = nand_exec_op(chip, op: &op);
2089	if (nand_interface_is_nvddr(conf)) {
2090	for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; i++)
2091	params[i] = ddrbuf[i * 2];
2092	}
2093
2094	return ret;
2095	}
2096
2097	chip->legacy.cmdfunc(chip, NAND_CMD_GET_FEATURES, feature, -1);
2098	for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2099	params[i] = chip->legacy.read_byte(chip);
2100
2101	return 0;
2102	}
2103
2104	static int nand_wait_rdy_op(struct nand_chip *chip, unsigned int timeout_ms,
2105	unsigned int delay_ns)
2106	{
2107	if (nand_has_exec_op(chip)) {
2108	struct nand_op_instr instrs[] = {
2109	NAND_OP_WAIT_RDY(PSEC_TO_MSEC(timeout_ms),
2110	PSEC_TO_NSEC(delay_ns)),
2111	};
2112	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2113
2114	return nand_exec_op(chip, op: &op);
2115	}
2116
2117	/* Apply delay or wait for ready/busy pin */
2118	if (!chip->legacy.dev_ready)
2119	udelay(chip->legacy.chip_delay);
2120	else
2121	nand_wait_ready(chip);
2122
2123	return 0;
2124	}
2125
2126	/**
2127	* nand_reset_op - Do a reset operation
2128	* @chip: The NAND chip
2129	*
2130	* This function sends a RESET command and waits for the NAND to be ready
2131	* before returning.
2132	* This function does not select/unselect the CS line.
2133	*
2134	* Returns 0 on success, a negative error code otherwise.
2135	*/
2136	int nand_reset_op(struct nand_chip *chip)
2137	{
2138	if (nand_has_exec_op(chip)) {
2139	const struct nand_interface_config *conf =
2140	nand_get_interface_config(chip);
2141	struct nand_op_instr instrs[] = {
2142	NAND_OP_CMD(NAND_CMD_RESET,
2143	NAND_COMMON_TIMING_NS(conf, tWB_max)),
2144	NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tRST_max),
2145	0),
2146	};
2147	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2148
2149	return nand_exec_op(chip, op: &op);
2150	}
2151
2152	chip->legacy.cmdfunc(chip, NAND_CMD_RESET, -1, -1);
2153
2154	return 0;
2155	}
2156	EXPORT_SYMBOL_GPL(nand_reset_op);
2157
2158	/**
2159	* nand_read_data_op - Read data from the NAND
2160	* @chip: The NAND chip
2161	* @buf: buffer used to store the data
2162	* @len: length of the buffer
2163	* @force_8bit: force 8-bit bus access
2164	* @check_only: do not actually run the command, only checks if the
2165	* controller driver supports it
2166	*
2167	* This function does a raw data read on the bus. Usually used after launching
2168	* another NAND operation like nand_read_page_op().
2169	* This function does not select/unselect the CS line.
2170	*
2171	* Returns 0 on success, a negative error code otherwise.
2172	*/
2173	int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
2174	bool force_8bit, bool check_only)
2175	{
2176	if (!len || !buf)
2177	return -EINVAL;
2178
2179	if (nand_has_exec_op(chip)) {
2180	const struct nand_interface_config *conf =
2181	nand_get_interface_config(chip);
2182	struct nand_op_instr instrs[] = {
2183	NAND_OP_DATA_IN(len, buf, 0),
2184	};
2185	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2186	u8 *ddrbuf = NULL;
2187	int ret, i;
2188
2189	instrs[0].ctx.data.force_8bit = force_8bit;
2190
2191	/*
2192	* Parameter payloads (ID, status, features, etc) do not go
2193	* through the same pipeline as regular data, hence the
2194	* force_8bit flag must be set and this also indicates that in
2195	* case NV-DDR timings are being used the data will be received
2196	* twice.
2197	*/
2198	if (force_8bit && nand_interface_is_nvddr(conf)) {
2199	ddrbuf = kzalloc(size: len * 2, GFP_KERNEL);
2200	if (!ddrbuf)
2201	return -ENOMEM;
2202
2203	instrs[0].ctx.data.len *= 2;
2204	instrs[0].ctx.data.buf.in = ddrbuf;
2205	}
2206
2207	if (check_only) {
2208	ret = nand_check_op(chip, op: &op);
2209	kfree(objp: ddrbuf);
2210	return ret;
2211	}
2212
2213	ret = nand_exec_op(chip, op: &op);
2214	if (!ret && force_8bit && nand_interface_is_nvddr(conf)) {
2215	u8 *dst = buf;
2216
2217	for (i = 0; i < len; i++)
2218	dst[i] = ddrbuf[i * 2];
2219	}
2220
2221	kfree(objp: ddrbuf);
2222
2223	return ret;
2224	}
2225
2226	if (check_only)
2227	return 0;
2228
2229	if (force_8bit) {
2230	u8 *p = buf;
2231	unsigned int i;
2232
2233	for (i = 0; i < len; i++)
2234	p[i] = chip->legacy.read_byte(chip);
2235	} else {
2236	chip->legacy.read_buf(chip, buf, len);
2237	}
2238
2239	return 0;
2240	}
2241	EXPORT_SYMBOL_GPL(nand_read_data_op);
2242
2243	/**
2244	* nand_write_data_op - Write data from the NAND
2245	* @chip: The NAND chip
2246	* @buf: buffer containing the data to send on the bus
2247	* @len: length of the buffer
2248	* @force_8bit: force 8-bit bus access
2249	*
2250	* This function does a raw data write on the bus. Usually used after launching
2251	* another NAND operation like nand_write_page_begin_op().
2252	* This function does not select/unselect the CS line.
2253	*
2254	* Returns 0 on success, a negative error code otherwise.
2255	*/
2256	int nand_write_data_op(struct nand_chip *chip, const void *buf,
2257	unsigned int len, bool force_8bit)
2258	{
2259	if (!len || !buf)
2260	return -EINVAL;
2261
2262	if (nand_has_exec_op(chip)) {
2263	struct nand_op_instr instrs[] = {
2264	NAND_OP_DATA_OUT(len, buf, 0),
2265	};
2266	struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
2267
2268	instrs[0].ctx.data.force_8bit = force_8bit;
2269
2270	return nand_exec_op(chip, op: &op);
2271	}
2272
2273	if (force_8bit) {
2274	const u8 *p = buf;
2275	unsigned int i;
2276
2277	for (i = 0; i < len; i++)
2278	chip->legacy.write_byte(chip, p[i]);
2279	} else {
2280	chip->legacy.write_buf(chip, buf, len);
2281	}
2282
2283	return 0;
2284	}
2285	EXPORT_SYMBOL_GPL(nand_write_data_op);
2286
2287	/**
2288	* struct nand_op_parser_ctx - Context used by the parser
2289	* @instrs: array of all the instructions that must be addressed
2290	* @ninstrs: length of the @instrs array
2291	* @subop: Sub-operation to be passed to the NAND controller
2292	*
2293	* This structure is used by the core to split NAND operations into
2294	* sub-operations that can be handled by the NAND controller.
2295	*/
2296	struct nand_op_parser_ctx {
2297	const struct nand_op_instr *instrs;
2298	unsigned int ninstrs;
2299	struct nand_subop subop;
2300	};
2301
2302	/**
2303	* nand_op_parser_must_split_instr - Checks if an instruction must be split
2304	* @pat: the parser pattern element that matches @instr
2305	* @instr: pointer to the instruction to check
2306	* @start_offset: this is an in/out parameter. If @instr has already been
2307	* split, then @start_offset is the offset from which to start
2308	* (either an address cycle or an offset in the data buffer).
2309	* Conversely, if the function returns true (ie. instr must be
2310	* split), this parameter is updated to point to the first
2311	* data/address cycle that has not been taken care of.
2312	*
2313	* Some NAND controllers are limited and cannot send X address cycles with a
2314	* unique operation, or cannot read/write more than Y bytes at the same time.
2315	* In this case, split the instruction that does not fit in a single
2316	* controller-operation into two or more chunks.
2317	*
2318	* Returns true if the instruction must be split, false otherwise.
2319	* The @start_offset parameter is also updated to the offset at which the next
2320	* bundle of instruction must start (if an address or a data instruction).
2321	*/
2322	static bool
2323	nand_op_parser_must_split_instr(const struct nand_op_parser_pattern_elem *pat,
2324	const struct nand_op_instr *instr,
2325	unsigned int *start_offset)
2326	{
2327	switch (pat->type) {
2328	case NAND_OP_ADDR_INSTR:
2329	if (!pat->ctx.addr.maxcycles)
2330	break;
2331
2332	if (instr->ctx.addr.naddrs - *start_offset >
2333	pat->ctx.addr.maxcycles) {
2334	*start_offset += pat->ctx.addr.maxcycles;
2335	return true;
2336	}
2337	break;
2338
2339	case NAND_OP_DATA_IN_INSTR:
2340	case NAND_OP_DATA_OUT_INSTR:
2341	if (!pat->ctx.data.maxlen)
2342	break;
2343
2344	if (instr->ctx.data.len - *start_offset >
2345	pat->ctx.data.maxlen) {
2346	*start_offset += pat->ctx.data.maxlen;
2347	return true;
2348	}
2349	break;
2350
2351	default:
2352	break;
2353	}
2354
2355	return false;
2356	}
2357
2358	/**
2359	* nand_op_parser_match_pat - Checks if a pattern matches the instructions
2360	* remaining in the parser context
2361	* @pat: the pattern to test
2362	* @ctx: the parser context structure to match with the pattern @pat
2363	*
2364	* Check if @pat matches the set or a sub-set of instructions remaining in @ctx.
2365	* Returns true if this is the case, false ortherwise. When true is returned,
2366	* @ctx->subop is updated with the set of instructions to be passed to the
2367	* controller driver.
2368	*/
2369	static bool
2370	nand_op_parser_match_pat(const struct nand_op_parser_pattern *pat,
2371	struct nand_op_parser_ctx *ctx)
2372	{
2373	unsigned int instr_offset = ctx->subop.first_instr_start_off;
2374	const struct nand_op_instr *end = ctx->instrs + ctx->ninstrs;
2375	const struct nand_op_instr *instr = ctx->subop.instrs;
2376	unsigned int i, ninstrs;
2377
2378	for (i = 0, ninstrs = 0; i < pat->nelems && instr < end; i++) {
2379	/*
2380	* The pattern instruction does not match the operation
2381	* instruction. If the instruction is marked optional in the
2382	* pattern definition, we skip the pattern element and continue
2383	* to the next one. If the element is mandatory, there's no
2384	* match and we can return false directly.
2385	*/
2386	if (instr->type != pat->elems[i].type) {
2387	if (!pat->elems[i].optional)
2388	return false;
2389
2390	continue;
2391	}
2392
2393	/*
2394	* Now check the pattern element constraints. If the pattern is
2395	* not able to handle the whole instruction in a single step,
2396	* we have to split it.
2397	* The last_instr_end_off value comes back updated to point to
2398	* the position where we have to split the instruction (the
2399	* start of the next subop chunk).
2400	*/
2401	if (nand_op_parser_must_split_instr(pat: &pat->elems[i], instr,
2402	start_offset: &instr_offset)) {
2403	ninstrs++;
2404	i++;
2405	break;
2406	}
2407
2408	instr++;
2409	ninstrs++;
2410	instr_offset = 0;
2411	}
2412
2413	/*
2414	* This can happen if all instructions of a pattern are optional.
2415	* Still, if there's not at least one instruction handled by this
2416	* pattern, this is not a match, and we should try the next one (if
2417	* any).
2418	*/
2419	if (!ninstrs)
2420	return false;
2421
2422	/*
2423	* We had a match on the pattern head, but the pattern may be longer
2424	* than the instructions we're asked to execute. We need to make sure
2425	* there's no mandatory elements in the pattern tail.
2426	*/
2427	for (; i < pat->nelems; i++) {
2428	if (!pat->elems[i].optional)
2429	return false;
2430	}
2431
2432	/*
2433	* We have a match: update the subop structure accordingly and return
2434	* true.
2435	*/
2436	ctx->subop.ninstrs = ninstrs;
2437	ctx->subop.last_instr_end_off = instr_offset;
2438
2439	return true;
2440	}
2441
2442	#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG)
2443	static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx)
2444	{
2445	const struct nand_op_instr *instr;
2446	char *prefix = " ";
2447	unsigned int i;
2448
2449	pr_debug("executing subop (CS%d):\n", ctx->subop.cs);
2450
2451	for (i = 0; i < ctx->ninstrs; i++) {
2452	instr = &ctx->instrs[i];
2453
2454	if (instr == &ctx->subop.instrs[0])
2455	prefix = " ->";
2456
2457	nand_op_trace(prefix, instr);
2458
2459	if (instr == &ctx->subop.instrs[ctx->subop.ninstrs - 1])
2460	prefix = " ";
2461	}
2462	}
2463	#else
2464	static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx)
2465	{
2466	/* NOP */
2467	}
2468	#endif
2469
2470	static int nand_op_parser_cmp_ctx(const struct nand_op_parser_ctx *a,
2471	const struct nand_op_parser_ctx *b)
2472	{
2473	if (a->subop.ninstrs < b->subop.ninstrs)
2474	return -1;
2475	else if (a->subop.ninstrs > b->subop.ninstrs)
2476	return 1;
2477
2478	if (a->subop.last_instr_end_off < b->subop.last_instr_end_off)
2479	return -1;
2480	else if (a->subop.last_instr_end_off > b->subop.last_instr_end_off)
2481	return 1;
2482
2483	return 0;
2484	}
2485
2486	/**
2487	* nand_op_parser_exec_op - exec_op parser
2488	* @chip: the NAND chip
2489	* @parser: patterns description provided by the controller driver
2490	* @op: the NAND operation to address
2491	* @check_only: when true, the function only checks if @op can be handled but
2492	* does not execute the operation
2493	*
2494	* Helper function designed to ease integration of NAND controller drivers that
2495	* only support a limited set of instruction sequences. The supported sequences
2496	* are described in @parser, and the framework takes care of splitting @op into
2497	* multiple sub-operations (if required) and pass them back to the ->exec()
2498	* callback of the matching pattern if @check_only is set to false.
2499	*
2500	* NAND controller drivers should call this function from their own ->exec_op()
2501	* implementation.
2502	*
2503	* Returns 0 on success, a negative error code otherwise. A failure can be
2504	* caused by an unsupported operation (none of the supported patterns is able
2505	* to handle the requested operation), or an error returned by one of the
2506	* matching pattern->exec() hook.
2507	*/
2508	int nand_op_parser_exec_op(struct nand_chip *chip,
2509	const struct nand_op_parser *parser,
2510	const struct nand_operation *op, bool check_only)
2511	{
2512	struct nand_op_parser_ctx ctx = {
2513	.subop.cs = op->cs,
2514	.subop.instrs = op->instrs,
2515	.instrs = op->instrs,
2516	.ninstrs = op->ninstrs,
2517	};
2518	unsigned int i;
2519
2520	while (ctx.subop.instrs < op->instrs + op->ninstrs) {
2521	const struct nand_op_parser_pattern *pattern;
2522	struct nand_op_parser_ctx best_ctx;
2523	int ret, best_pattern = -1;
2524
2525	for (i = 0; i < parser->npatterns; i++) {
2526	struct nand_op_parser_ctx test_ctx = ctx;
2527
2528	pattern = &parser->patterns[i];
2529	if (!nand_op_parser_match_pat(pat: pattern, ctx: &test_ctx))
2530	continue;
2531
2532	if (best_pattern >= 0 &&
2533	nand_op_parser_cmp_ctx(a: &test_ctx, b: &best_ctx) <= 0)
2534	continue;
2535
2536	best_pattern = i;
2537	best_ctx = test_ctx;
2538	}
2539
2540	if (best_pattern < 0) {
2541	pr_debug("->exec_op() parser: pattern not found!\n");
2542	return -ENOTSUPP;
2543	}
2544
2545	ctx = best_ctx;
2546	nand_op_parser_trace(ctx: &ctx);
2547
2548	if (!check_only) {
2549	pattern = &parser->patterns[best_pattern];
2550	ret = pattern->exec(chip, &ctx.subop);
2551	if (ret)
2552	return ret;
2553	}
2554
2555	/*
2556	* Update the context structure by pointing to the start of the
2557	* next subop.
2558	*/
2559	ctx.subop.instrs = ctx.subop.instrs + ctx.subop.ninstrs;
2560	if (ctx.subop.last_instr_end_off)
2561	ctx.subop.instrs -= 1;
2562
2563	ctx.subop.first_instr_start_off = ctx.subop.last_instr_end_off;
2564	}
2565
2566	return 0;
2567	}
2568	EXPORT_SYMBOL_GPL(nand_op_parser_exec_op);
2569
2570	static bool nand_instr_is_data(const struct nand_op_instr *instr)
2571	{
2572	return instr && (instr->type == NAND_OP_DATA_IN_INSTR ||
2573	instr->type == NAND_OP_DATA_OUT_INSTR);
2574	}
2575
2576	static bool nand_subop_instr_is_valid(const struct nand_subop *subop,
2577	unsigned int instr_idx)
2578	{
2579	return subop && instr_idx < subop->ninstrs;
2580	}
2581
2582	static unsigned int nand_subop_get_start_off(const struct nand_subop *subop,
2583	unsigned int instr_idx)
2584	{
2585	if (instr_idx)
2586	return 0;
2587
2588	return subop->first_instr_start_off;
2589	}
2590
2591	/**
2592	* nand_subop_get_addr_start_off - Get the start offset in an address array
2593	* @subop: The entire sub-operation
2594	* @instr_idx: Index of the instruction inside the sub-operation
2595	*
2596	* During driver development, one could be tempted to directly use the
2597	* ->addr.addrs field of address instructions. This is wrong as address
2598	* instructions might be split.
2599	*
2600	* Given an address instruction, returns the offset of the first cycle to issue.
2601	*/
2602	unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
2603	unsigned int instr_idx)
2604	{
2605	if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2606	subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR))
2607	return 0;
2608
2609	return nand_subop_get_start_off(subop, instr_idx);
2610	}
2611	EXPORT_SYMBOL_GPL(nand_subop_get_addr_start_off);
2612
2613	/**
2614	* nand_subop_get_num_addr_cyc - Get the remaining address cycles to assert
2615	* @subop: The entire sub-operation
2616	* @instr_idx: Index of the instruction inside the sub-operation
2617	*
2618	* During driver development, one could be tempted to directly use the
2619	* ->addr->naddrs field of a data instruction. This is wrong as instructions
2620	* might be split.
2621	*
2622	* Given an address instruction, returns the number of address cycle to issue.
2623	*/
2624	unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
2625	unsigned int instr_idx)
2626	{
2627	int start_off, end_off;
2628
2629	if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2630	subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR))
2631	return 0;
2632
2633	start_off = nand_subop_get_addr_start_off(subop, instr_idx);
2634
2635	if (instr_idx == subop->ninstrs - 1 &&
2636	subop->last_instr_end_off)
2637	end_off = subop->last_instr_end_off;
2638	else
2639	end_off = subop->instrs[instr_idx].ctx.addr.naddrs;
2640
2641	return end_off - start_off;
2642	}
2643	EXPORT_SYMBOL_GPL(nand_subop_get_num_addr_cyc);
2644
2645	/**
2646	* nand_subop_get_data_start_off - Get the start offset in a data array
2647	* @subop: The entire sub-operation
2648	* @instr_idx: Index of the instruction inside the sub-operation
2649	*
2650	* During driver development, one could be tempted to directly use the
2651	* ->data->buf.{in,out} field of data instructions. This is wrong as data
2652	* instructions might be split.
2653	*
2654	* Given a data instruction, returns the offset to start from.
2655	*/
2656	unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
2657	unsigned int instr_idx)
2658	{
2659	if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2660	!nand_instr_is_data(&subop->instrs[instr_idx])))
2661	return 0;
2662
2663	return nand_subop_get_start_off(subop, instr_idx);
2664	}
2665	EXPORT_SYMBOL_GPL(nand_subop_get_data_start_off);
2666
2667	/**
2668	* nand_subop_get_data_len - Get the number of bytes to retrieve
2669	* @subop: The entire sub-operation
2670	* @instr_idx: Index of the instruction inside the sub-operation
2671	*
2672	* During driver development, one could be tempted to directly use the
2673	* ->data->len field of a data instruction. This is wrong as data instructions
2674	* might be split.
2675	*
2676	* Returns the length of the chunk of data to send/receive.
2677	*/
2678	unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
2679	unsigned int instr_idx)
2680	{
2681	int start_off = 0, end_off;
2682
2683	if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||
2684	!nand_instr_is_data(&subop->instrs[instr_idx])))
2685	return 0;
2686
2687	start_off = nand_subop_get_data_start_off(subop, instr_idx);
2688
2689	if (instr_idx == subop->ninstrs - 1 &&
2690	subop->last_instr_end_off)
2691	end_off = subop->last_instr_end_off;
2692	else
2693	end_off = subop->instrs[instr_idx].ctx.data.len;
2694
2695	return end_off - start_off;
2696	}
2697	EXPORT_SYMBOL_GPL(nand_subop_get_data_len);
2698
2699	/**
2700	* nand_reset - Reset and initialize a NAND device
2701	* @chip: The NAND chip
2702	* @chipnr: Internal die id
2703	*
2704	* Save the timings data structure, then apply SDR timings mode 0 (see
2705	* nand_reset_interface for details), do the reset operation, and apply
2706	* back the previous timings.
2707	*
2708	* Returns 0 on success, a negative error code otherwise.
2709	*/
2710	int nand_reset(struct nand_chip *chip, int chipnr)
2711	{
2712	int ret;
2713
2714	ret = nand_reset_interface(chip, chipnr);
2715	if (ret)
2716	return ret;
2717
2718	/*
2719	* The CS line has to be released before we can apply the new NAND
2720	* interface settings, hence this weird nand_select_target()
2721	* nand_deselect_target() dance.
2722	*/
2723	nand_select_target(chip, chipnr);
2724	ret = nand_reset_op(chip);
2725	nand_deselect_target(chip);
2726	if (ret)
2727	return ret;
2728
2729	ret = nand_setup_interface(chip, chipnr);
2730	if (ret)
2731	return ret;
2732
2733	return 0;
2734	}
2735	EXPORT_SYMBOL_GPL(nand_reset);
2736
2737	/**
2738	* nand_get_features - wrapper to perform a GET_FEATURE
2739	* @chip: NAND chip info structure
2740	* @addr: feature address
2741	* @subfeature_param: the subfeature parameters, a four bytes array
2742	*
2743	* Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
2744	* operation cannot be handled.
2745	*/
2746	int nand_get_features(struct nand_chip *chip, int addr,
2747	u8 *subfeature_param)
2748	{
2749	if (!nand_supports_get_features(chip, addr))
2750	return -ENOTSUPP;
2751
2752	if (chip->legacy.get_features)
2753	return chip->legacy.get_features(chip, addr, subfeature_param);
2754
2755	return nand_get_features_op(chip, feature: addr, data: subfeature_param);
2756	}
2757
2758	/**
2759	* nand_set_features - wrapper to perform a SET_FEATURE
2760	* @chip: NAND chip info structure
2761	* @addr: feature address
2762	* @subfeature_param: the subfeature parameters, a four bytes array
2763	*
2764	* Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the
2765	* operation cannot be handled.
2766	*/
2767	int nand_set_features(struct nand_chip *chip, int addr,
2768	u8 *subfeature_param)
2769	{
2770	if (!nand_supports_set_features(chip, addr))
2771	return -ENOTSUPP;
2772
2773	if (chip->legacy.set_features)
2774	return chip->legacy.set_features(chip, addr, subfeature_param);
2775
2776	return nand_set_features_op(chip, feature: addr, data: subfeature_param);
2777	}
2778
2779	/**
2780	* nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
2781	* @buf: buffer to test
2782	* @len: buffer length
2783	* @bitflips_threshold: maximum number of bitflips
2784	*
2785	* Check if a buffer contains only 0xff, which means the underlying region
2786	* has been erased and is ready to be programmed.
2787	* The bitflips_threshold specify the maximum number of bitflips before
2788	* considering the region is not erased.
2789	* Note: The logic of this function has been extracted from the memweight
2790	* implementation, except that nand_check_erased_buf function exit before
2791	* testing the whole buffer if the number of bitflips exceed the
2792	* bitflips_threshold value.
2793	*
2794	* Returns a positive number of bitflips less than or equal to
2795	* bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
2796	* threshold.
2797	*/
2798	static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
2799	{
2800	const unsigned char *bitmap = buf;
2801	int bitflips = 0;
2802	int weight;
2803
2804	for (; len && ((uintptr_t)bitmap) % sizeof(long);
2805	len--, bitmap++) {
2806	weight = hweight8(*bitmap);
2807	bitflips += BITS_PER_BYTE - weight;
2808	if (unlikely(bitflips > bitflips_threshold))
2809	return -EBADMSG;
2810	}
2811
2812	for (; len >= sizeof(long);
2813	len -= sizeof(long), bitmap += sizeof(long)) {
2814	unsigned long d = *((unsigned long *)bitmap);
2815	if (d == ~0UL)
2816	continue;
2817	weight = hweight_long(w: d);
2818	bitflips += BITS_PER_LONG - weight;
2819	if (unlikely(bitflips > bitflips_threshold))
2820	return -EBADMSG;
2821	}
2822
2823	for (; len > 0; len--, bitmap++) {
2824	weight = hweight8(*bitmap);
2825	bitflips += BITS_PER_BYTE - weight;
2826	if (unlikely(bitflips > bitflips_threshold))
2827	return -EBADMSG;
2828	}
2829
2830	return bitflips;
2831	}
2832
2833	/**
2834	* nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
2835	* 0xff data
2836	* @data: data buffer to test
2837	* @datalen: data length
2838	* @ecc: ECC buffer
2839	* @ecclen: ECC length
2840	* @extraoob: extra OOB buffer
2841	* @extraooblen: extra OOB length
2842	* @bitflips_threshold: maximum number of bitflips
2843	*
2844	* Check if a data buffer and its associated ECC and OOB data contains only
2845	* 0xff pattern, which means the underlying region has been erased and is
2846	* ready to be programmed.
2847	* The bitflips_threshold specify the maximum number of bitflips before
2848	* considering the region as not erased.
2849	*
2850	* Note:
2851	* 1/ ECC algorithms are working on pre-defined block sizes which are usually
2852	* different from the NAND page size. When fixing bitflips, ECC engines will
2853	* report the number of errors per chunk, and the NAND core infrastructure
2854	* expect you to return the maximum number of bitflips for the whole page.
2855	* This is why you should always use this function on a single chunk and
2856	* not on the whole page. After checking each chunk you should update your
2857	* max_bitflips value accordingly.
2858	* 2/ When checking for bitflips in erased pages you should not only check
2859	* the payload data but also their associated ECC data, because a user might
2860	* have programmed almost all bits to 1 but a few. In this case, we
2861	* shouldn't consider the chunk as erased, and checking ECC bytes prevent
2862	* this case.
2863	* 3/ The extraoob argument is optional, and should be used if some of your OOB
2864	* data are protected by the ECC engine.
2865	* It could also be used if you support subpages and want to attach some
2866	* extra OOB data to an ECC chunk.
2867	*
2868	* Returns a positive number of bitflips less than or equal to
2869	* bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
2870	* threshold. In case of success, the passed buffers are filled with 0xff.
2871	*/
2872	int nand_check_erased_ecc_chunk(void *data, int datalen,
2873	void *ecc, int ecclen,
2874	void *extraoob, int extraooblen,
2875	int bitflips_threshold)
2876	{
2877	int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
2878
2879	data_bitflips = nand_check_erased_buf(buf: data, len: datalen,
2880	bitflips_threshold);
2881	if (data_bitflips < 0)
2882	return data_bitflips;
2883
2884	bitflips_threshold -= data_bitflips;
2885
2886	ecc_bitflips = nand_check_erased_buf(buf: ecc, len: ecclen, bitflips_threshold);
2887	if (ecc_bitflips < 0)
2888	return ecc_bitflips;
2889
2890	bitflips_threshold -= ecc_bitflips;
2891
2892	extraoob_bitflips = nand_check_erased_buf(buf: extraoob, len: extraooblen,
2893	bitflips_threshold);
2894	if (extraoob_bitflips < 0)
2895	return extraoob_bitflips;
2896
2897	if (data_bitflips)
2898	memset(data, 0xff, datalen);
2899
2900	if (ecc_bitflips)
2901	memset(ecc, 0xff, ecclen);
2902
2903	if (extraoob_bitflips)
2904	memset(extraoob, 0xff, extraooblen);
2905
2906	return data_bitflips + ecc_bitflips + extraoob_bitflips;
2907	}
2908	EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
2909
2910	/**
2911	* nand_read_page_raw_notsupp - dummy read raw page function
2912	* @chip: nand chip info structure
2913	* @buf: buffer to store read data
2914	* @oob_required: caller requires OOB data read to chip->oob_poi
2915	* @page: page number to read
2916	*
2917	* Returns -ENOTSUPP unconditionally.
2918	*/
2919	int nand_read_page_raw_notsupp(struct nand_chip *chip, u8 *buf,
2920	int oob_required, int page)
2921	{
2922	return -ENOTSUPP;
2923	}
2924
2925	/**
2926	* nand_read_page_raw - [INTERN] read raw page data without ecc
2927	* @chip: nand chip info structure
2928	* @buf: buffer to store read data
2929	* @oob_required: caller requires OOB data read to chip->oob_poi
2930	* @page: page number to read
2931	*
2932	* Not for syndrome calculating ECC controllers, which use a special oob layout.
2933	*/
2934	int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
2935	int page)
2936	{
2937	struct mtd_info *mtd = nand_to_mtd(chip);
2938	int ret;
2939
2940	ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize);
2941	if (ret)
2942	return ret;
2943
2944	if (oob_required) {
2945	ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,
2946	false, false);
2947	if (ret)
2948	return ret;
2949	}
2950
2951	return 0;
2952	}
2953	EXPORT_SYMBOL(nand_read_page_raw);
2954
2955	/**
2956	* nand_monolithic_read_page_raw - Monolithic page read in raw mode
2957	* @chip: NAND chip info structure
2958	* @buf: buffer to store read data
2959	* @oob_required: caller requires OOB data read to chip->oob_poi
2960	* @page: page number to read
2961	*
2962	* This is a raw page read, ie. without any error detection/correction.
2963	* Monolithic means we are requesting all the relevant data (main plus
2964	* eventually OOB) to be loaded in the NAND cache and sent over the
2965	* bus (from the NAND chip to the NAND controller) in a single
2966	* operation. This is an alternative to nand_read_page_raw(), which
2967	* first reads the main data, and if the OOB data is requested too,
2968	* then reads more data on the bus.
2969	*/
2970	int nand_monolithic_read_page_raw(struct nand_chip *chip, u8 *buf,
2971	int oob_required, int page)
2972	{
2973	struct mtd_info *mtd = nand_to_mtd(chip);
2974	unsigned int size = mtd->writesize;
2975	u8 *read_buf = buf;
2976	int ret;
2977
2978	if (oob_required) {
2979	size += mtd->oobsize;
2980
2981	if (buf != chip->data_buf)
2982	read_buf = nand_get_data_buf(chip);
2983	}
2984
2985	ret = nand_read_page_op(chip, page, 0, read_buf, size);
2986	if (ret)
2987	return ret;
2988
2989	if (buf != chip->data_buf)
2990	memcpy(buf, read_buf, mtd->writesize);
2991
2992	return 0;
2993	}
2994	EXPORT_SYMBOL(nand_monolithic_read_page_raw);
2995
2996	/**
2997	* nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
2998	* @chip: nand chip info structure
2999	* @buf: buffer to store read data
3000	* @oob_required: caller requires OOB data read to chip->oob_poi
3001	* @page: page number to read
3002	*
3003	* We need a special oob layout and handling even when OOB isn't used.
3004	*/
3005	static int nand_read_page_raw_syndrome(struct nand_chip *chip, uint8_t *buf,
3006	int oob_required, int page)
3007	{
3008	struct mtd_info *mtd = nand_to_mtd(chip);
3009	int eccsize = chip->ecc.size;
3010	int eccbytes = chip->ecc.bytes;
3011	uint8_t *oob = chip->oob_poi;
3012	int steps, size, ret;
3013
3014	ret = nand_read_page_op(chip, page, 0, NULL, 0);
3015	if (ret)
3016	return ret;
3017
3018	for (steps = chip->ecc.steps; steps > 0; steps--) {
3019	ret = nand_read_data_op(chip, buf, eccsize, false, false);
3020	if (ret)
3021	return ret;
3022
3023	buf += eccsize;
3024
3025	if (chip->ecc.prepad) {
3026	ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
3027	false, false);
3028	if (ret)
3029	return ret;
3030
3031	oob += chip->ecc.prepad;
3032	}
3033
3034	ret = nand_read_data_op(chip, oob, eccbytes, false, false);
3035	if (ret)
3036	return ret;
3037
3038	oob += eccbytes;
3039
3040	if (chip->ecc.postpad) {
3041	ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
3042	false, false);
3043	if (ret)
3044	return ret;
3045
3046	oob += chip->ecc.postpad;
3047	}
3048	}
3049
3050	size = mtd->oobsize - (oob - chip->oob_poi);
3051	if (size) {
3052	ret = nand_read_data_op(chip, oob, size, false, false);
3053	if (ret)
3054	return ret;
3055	}
3056
3057	return 0;
3058	}
3059
3060	/**
3061	* nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
3062	* @chip: nand chip info structure
3063	* @buf: buffer to store read data
3064	* @oob_required: caller requires OOB data read to chip->oob_poi
3065	* @page: page number to read
3066	*/
3067	static int nand_read_page_swecc(struct nand_chip *chip, uint8_t *buf,
3068	int oob_required, int page)
3069	{
3070	struct mtd_info *mtd = nand_to_mtd(chip);
3071	int i, eccsize = chip->ecc.size, ret;
3072	int eccbytes = chip->ecc.bytes;
3073	int eccsteps = chip->ecc.steps;
3074	uint8_t *p = buf;
3075	uint8_t *ecc_calc = chip->ecc.calc_buf;
3076	uint8_t *ecc_code = chip->ecc.code_buf;
3077	unsigned int max_bitflips = 0;
3078
3079	chip->ecc.read_page_raw(chip, buf, 1, page);
3080
3081	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
3082	chip->ecc.calculate(chip, p, &ecc_calc[i]);
3083
3084	ret = mtd_ooblayout_get_eccbytes(mtd, eccbuf: ecc_code, oobbuf: chip->oob_poi, start: 0,
3085	nbytes: chip->ecc.total);
3086	if (ret)
3087	return ret;
3088
3089	eccsteps = chip->ecc.steps;
3090	p = buf;
3091
3092	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3093	int stat;
3094
3095	stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
3096	if (stat < 0) {
3097	mtd->ecc_stats.failed++;
3098	} else {
3099	mtd->ecc_stats.corrected += stat;
3100	max_bitflips = max_t(unsigned int, max_bitflips, stat);
3101	}
3102	}
3103	return max_bitflips;
3104	}
3105
3106	/**
3107	* nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
3108	* @chip: nand chip info structure
3109	* @data_offs: offset of requested data within the page
3110	* @readlen: data length
3111	* @bufpoi: buffer to store read data
3112	* @page: page number to read
3113	*/
3114	static int nand_read_subpage(struct nand_chip *chip, uint32_t data_offs,
3115	uint32_t readlen, uint8_t *bufpoi, int page)
3116	{
3117	struct mtd_info *mtd = nand_to_mtd(chip);
3118	int start_step, end_step, num_steps, ret;
3119	uint8_t *p;
3120	int data_col_addr, i, gaps = 0;
3121	int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
3122	int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
3123	int index, section = 0;
3124	unsigned int max_bitflips = 0;
3125	struct mtd_oob_region oobregion = { };
3126
3127	/* Column address within the page aligned to ECC size (256bytes) */
3128	start_step = data_offs / chip->ecc.size;
3129	end_step = (data_offs + readlen - 1) / chip->ecc.size;
3130	num_steps = end_step - start_step + 1;
3131	index = start_step * chip->ecc.bytes;
3132
3133	/* Data size aligned to ECC ecc.size */
3134	datafrag_len = num_steps * chip->ecc.size;
3135	eccfrag_len = num_steps * chip->ecc.bytes;
3136
3137	data_col_addr = start_step * chip->ecc.size;
3138	/* If we read not a page aligned data */
3139	p = bufpoi + data_col_addr;
3140	ret = nand_read_page_op(chip, page, data_col_addr, p, datafrag_len);
3141	if (ret)
3142	return ret;
3143
3144	/* Calculate ECC */
3145	for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
3146	chip->ecc.calculate(chip, p, &chip->ecc.calc_buf[i]);
3147
3148	/*
3149	* The performance is faster if we position offsets according to
3150	* ecc.pos. Let's make sure that there are no gaps in ECC positions.
3151	*/
3152	ret = mtd_ooblayout_find_eccregion(mtd, eccbyte: index, section: &section, oobregion: &oobregion);
3153	if (ret)
3154	return ret;
3155
3156	if (oobregion.length < eccfrag_len)
3157	gaps = 1;
3158
3159	if (gaps) {
3160	ret = nand_change_read_column_op(chip, mtd->writesize,
3161	chip->oob_poi, mtd->oobsize,
3162	false);
3163	if (ret)
3164	return ret;
3165	} else {
3166	/*
3167	* Send the command to read the particular ECC bytes take care
3168	* about buswidth alignment in read_buf.
3169	*/
3170	aligned_pos = oobregion.offset & ~(busw - 1);
3171	aligned_len = eccfrag_len;
3172	if (oobregion.offset & (busw - 1))
3173	aligned_len++;
3174	if ((oobregion.offset + (num_steps * chip->ecc.bytes)) &
3175	(busw - 1))
3176	aligned_len++;
3177
3178	ret = nand_change_read_column_op(chip,
3179	mtd->writesize + aligned_pos,
3180	&chip->oob_poi[aligned_pos],
3181	aligned_len, false);
3182	if (ret)
3183	return ret;
3184	}
3185
3186	ret = mtd_ooblayout_get_eccbytes(mtd, eccbuf: chip->ecc.code_buf,
3187	oobbuf: chip->oob_poi, start: index, nbytes: eccfrag_len);
3188	if (ret)
3189	return ret;
3190
3191	p = bufpoi + data_col_addr;
3192	for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
3193	int stat;
3194
3195	stat = chip->ecc.correct(chip, p, &chip->ecc.code_buf[i],
3196	&chip->ecc.calc_buf[i]);
3197	if (stat == -EBADMSG &&
3198	(chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3199	/* check for empty pages with bitflips */
3200	stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
3201	&chip->ecc.code_buf[i],
3202	chip->ecc.bytes,
3203	NULL, 0,
3204	chip->ecc.strength);
3205	}
3206
3207	if (stat < 0) {
3208	mtd->ecc_stats.failed++;
3209	} else {
3210	mtd->ecc_stats.corrected += stat;
3211	max_bitflips = max_t(unsigned int, max_bitflips, stat);
3212	}
3213	}
3214	return max_bitflips;
3215	}
3216
3217	/**
3218	* nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
3219	* @chip: nand chip info structure
3220	* @buf: buffer to store read data
3221	* @oob_required: caller requires OOB data read to chip->oob_poi
3222	* @page: page number to read
3223	*
3224	* Not for syndrome calculating ECC controllers which need a special oob layout.
3225	*/
3226	static int nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,
3227	int oob_required, int page)
3228	{
3229	struct mtd_info *mtd = nand_to_mtd(chip);
3230	int i, eccsize = chip->ecc.size, ret;
3231	int eccbytes = chip->ecc.bytes;
3232	int eccsteps = chip->ecc.steps;
3233	uint8_t *p = buf;
3234	uint8_t *ecc_calc = chip->ecc.calc_buf;
3235	uint8_t *ecc_code = chip->ecc.code_buf;
3236	unsigned int max_bitflips = 0;
3237
3238	ret = nand_read_page_op(chip, page, 0, NULL, 0);
3239	if (ret)
3240	return ret;
3241
3242	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3243	chip->ecc.hwctl(chip, NAND_ECC_READ);
3244
3245	ret = nand_read_data_op(chip, p, eccsize, false, false);
3246	if (ret)
3247	return ret;
3248
3249	chip->ecc.calculate(chip, p, &ecc_calc[i]);
3250	}
3251
3252	ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false,
3253	false);
3254	if (ret)
3255	return ret;
3256
3257	ret = mtd_ooblayout_get_eccbytes(mtd, eccbuf: ecc_code, oobbuf: chip->oob_poi, start: 0,
3258	nbytes: chip->ecc.total);
3259	if (ret)
3260	return ret;
3261
3262	eccsteps = chip->ecc.steps;
3263	p = buf;
3264
3265	for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3266	int stat;
3267
3268	stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);
3269	if (stat == -EBADMSG &&
3270	(chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3271	/* check for empty pages with bitflips */
3272	stat = nand_check_erased_ecc_chunk(p, eccsize,
3273	&ecc_code[i], eccbytes,
3274	NULL, 0,
3275	chip->ecc.strength);
3276	}
3277
3278	if (stat < 0) {
3279	mtd->ecc_stats.failed++;
3280	} else {
3281	mtd->ecc_stats.corrected += stat;
3282	max_bitflips = max_t(unsigned int, max_bitflips, stat);
3283	}
3284	}
3285	return max_bitflips;
3286	}
3287
3288	/**
3289	* nand_read_page_hwecc_oob_first - Hardware ECC page read with ECC
3290	* data read from OOB area
3291	* @chip: nand chip info structure
3292	* @buf: buffer to store read data
3293	* @oob_required: caller requires OOB data read to chip->oob_poi
3294	* @page: page number to read
3295	*
3296	* Hardware ECC for large page chips, which requires the ECC data to be
3297	* extracted from the OOB before the actual data is read.
3298	*/
3299	int nand_read_page_hwecc_oob_first(struct nand_chip *chip, uint8_t *buf,
3300	int oob_required, int page)
3301	{
3302	struct mtd_info *mtd = nand_to_mtd(chip);
3303	int i, eccsize = chip->ecc.size, ret;
3304	int eccbytes = chip->ecc.bytes;
3305	int eccsteps = chip->ecc.steps;
3306	uint8_t *p = buf;
3307	uint8_t *ecc_code = chip->ecc.code_buf;
3308	unsigned int max_bitflips = 0;
3309
3310	/* Read the OOB area first */
3311	ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
3312	if (ret)
3313	return ret;
3314
3315	/* Move read cursor to start of page */
3316	ret = nand_change_read_column_op(chip, 0, NULL, 0, false);
3317	if (ret)
3318	return ret;
3319
3320	ret = mtd_ooblayout_get_eccbytes(mtd, eccbuf: ecc_code, oobbuf: chip->oob_poi, start: 0,
3321	nbytes: chip->ecc.total);
3322	if (ret)
3323	return ret;
3324
3325	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3326	int stat;
3327
3328	chip->ecc.hwctl(chip, NAND_ECC_READ);
3329
3330	ret = nand_read_data_op(chip, p, eccsize, false, false);
3331	if (ret)
3332	return ret;
3333
3334	stat = chip->ecc.correct(chip, p, &ecc_code[i], NULL);
3335	if (stat == -EBADMSG &&
3336	(chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3337	/* check for empty pages with bitflips */
3338	stat = nand_check_erased_ecc_chunk(p, eccsize,
3339	&ecc_code[i],
3340	eccbytes, NULL, 0,
3341	chip->ecc.strength);
3342	}
3343
3344	if (stat < 0) {
3345	mtd->ecc_stats.failed++;
3346	} else {
3347	mtd->ecc_stats.corrected += stat;
3348	max_bitflips = max_t(unsigned int, max_bitflips, stat);
3349	}
3350	}
3351	return max_bitflips;
3352	}
3353	EXPORT_SYMBOL_GPL(nand_read_page_hwecc_oob_first);
3354
3355	/**
3356	* nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
3357	* @chip: nand chip info structure
3358	* @buf: buffer to store read data
3359	* @oob_required: caller requires OOB data read to chip->oob_poi
3360	* @page: page number to read
3361	*
3362	* The hw generator calculates the error syndrome automatically. Therefore we
3363	* need a special oob layout and handling.
3364	*/
3365	static int nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf,
3366	int oob_required, int page)
3367	{
3368	struct mtd_info *mtd = nand_to_mtd(chip);
3369	int ret, i, eccsize = chip->ecc.size;
3370	int eccbytes = chip->ecc.bytes;
3371	int eccsteps = chip->ecc.steps;
3372	int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
3373	uint8_t *p = buf;
3374	uint8_t *oob = chip->oob_poi;
3375	unsigned int max_bitflips = 0;
3376
3377	ret = nand_read_page_op(chip, page, 0, NULL, 0);
3378	if (ret)
3379	return ret;
3380
3381	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
3382	int stat;
3383
3384	chip->ecc.hwctl(chip, NAND_ECC_READ);
3385
3386	ret = nand_read_data_op(chip, p, eccsize, false, false);
3387	if (ret)
3388	return ret;
3389
3390	if (chip->ecc.prepad) {
3391	ret = nand_read_data_op(chip, oob, chip->ecc.prepad,
3392	false, false);
3393	if (ret)
3394	return ret;
3395
3396	oob += chip->ecc.prepad;
3397	}
3398
3399	chip->ecc.hwctl(chip, NAND_ECC_READSYN);
3400
3401	ret = nand_read_data_op(chip, oob, eccbytes, false, false);
3402	if (ret)
3403	return ret;
3404
3405	stat = chip->ecc.correct(chip, p, oob, NULL);
3406
3407	oob += eccbytes;
3408
3409	if (chip->ecc.postpad) {
3410	ret = nand_read_data_op(chip, oob, chip->ecc.postpad,
3411	false, false);
3412	if (ret)
3413	return ret;
3414
3415	oob += chip->ecc.postpad;
3416	}
3417
3418	if (stat == -EBADMSG &&
3419	(chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
3420	/* check for empty pages with bitflips */
3421	stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
3422	oob - eccpadbytes,
3423	eccpadbytes,
3424	NULL, 0,
3425	chip->ecc.strength);
3426	}
3427
3428	if (stat < 0) {
3429	mtd->ecc_stats.failed++;
3430	} else {
3431	mtd->ecc_stats.corrected += stat;
3432	max_bitflips = max_t(unsigned int, max_bitflips, stat);
3433	}
3434	}
3435
3436	/* Calculate remaining oob bytes */
3437	i = mtd->oobsize - (oob - chip->oob_poi);
3438	if (i) {
3439	ret = nand_read_data_op(chip, oob, i, false, false);
3440	if (ret)
3441	return ret;
3442	}
3443
3444	return max_bitflips;
3445	}
3446
3447	/**
3448	* nand_transfer_oob - [INTERN] Transfer oob to client buffer
3449	* @chip: NAND chip object
3450	* @oob: oob destination address
3451	* @ops: oob ops structure
3452	* @len: size of oob to transfer
3453	*/
3454	static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
3455	struct mtd_oob_ops *ops, size_t len)
3456	{
3457	struct mtd_info *mtd = nand_to_mtd(chip);
3458	int ret;
3459
3460	switch (ops->mode) {
3461
3462	case MTD_OPS_PLACE_OOB:
3463	case MTD_OPS_RAW:
3464	memcpy(oob, chip->oob_poi + ops->ooboffs, len);
3465	return oob + len;
3466
3467	case MTD_OPS_AUTO_OOB:
3468	ret = mtd_ooblayout_get_databytes(mtd, databuf: oob, oobbuf: chip->oob_poi,
3469	start: ops->ooboffs, nbytes: len);
3470	BUG_ON(ret);
3471	return oob + len;
3472
3473	default:
3474	BUG();
3475	}
3476	return NULL;
3477	}
3478
3479	static void rawnand_enable_cont_reads(struct nand_chip *chip, unsigned int page,
3480	u32 readlen, int col)
3481	{
3482	struct mtd_info *mtd = nand_to_mtd(chip);
3483	unsigned int first_page, last_page;
3484
3485	chip->cont_read.ongoing = false;
3486
3487	if (!chip->controller->supported_op.cont_read)
3488	return;
3489
3490	/*
3491	* Don't bother making any calculations if the length is too small.
3492	* Side effect: avoids possible integer underflows below.
3493	*/
3494	if (readlen < (2 * mtd->writesize))
3495	return;
3496
3497	/* Derive the page where continuous read should start (the first full page read) */
3498	first_page = page;
3499	if (col)
3500	first_page++;
3501
3502	/* Derive the page where continuous read should stop (the last full page read) */
3503	last_page = page + ((col + readlen) / mtd->writesize) - 1;
3504
3505	/* Configure and enable continuous read when suitable */
3506	if (first_page < last_page) {
3507	chip->cont_read.first_page = first_page;
3508	chip->cont_read.last_page = last_page;
3509	chip->cont_read.ongoing = true;
3510	/* May reset the ongoing flag */
3511	rawnand_cap_cont_reads(chip);
3512	}
3513	}
3514
3515	static void rawnand_cont_read_skip_first_page(struct nand_chip *chip, unsigned int page)
3516	{
3517	if (!chip->cont_read.ongoing || page != chip->cont_read.first_page)
3518	return;
3519
3520	chip->cont_read.first_page++;
3521	rawnand_cap_cont_reads(chip);
3522	}
3523
3524	/**
3525	* nand_setup_read_retry - [INTERN] Set the READ RETRY mode
3526	* @chip: NAND chip object
3527	* @retry_mode: the retry mode to use
3528	*
3529	* Some vendors supply a special command to shift the Vt threshold, to be used
3530	* when there are too many bitflips in a page (i.e., ECC error). After setting
3531	* a new threshold, the host should retry reading the page.
3532	*/
3533	static int nand_setup_read_retry(struct nand_chip *chip, int retry_mode)
3534	{
3535	pr_debug("setting READ RETRY mode %d\n", retry_mode);
3536
3537	if (retry_mode >= chip->read_retries)
3538	return -EINVAL;
3539
3540	if (!chip->ops.setup_read_retry)
3541	return -EOPNOTSUPP;
3542
3543	return chip->ops.setup_read_retry(chip, retry_mode);
3544	}
3545
3546	static void nand_wait_readrdy(struct nand_chip *chip)
3547	{
3548	const struct nand_interface_config *conf;
3549
3550	if (!(chip->options & NAND_NEED_READRDY))
3551	return;
3552
3553	conf = nand_get_interface_config(chip);
3554	WARN_ON(nand_wait_rdy_op(chip, NAND_COMMON_TIMING_MS(conf, tR_max), 0));
3555	}
3556
3557	/**
3558	* nand_do_read_ops - [INTERN] Read data with ECC
3559	* @chip: NAND chip object
3560	* @from: offset to read from
3561	* @ops: oob ops structure
3562	*
3563	* Internal function. Called with chip held.
3564	*/
3565	static int nand_do_read_ops(struct nand_chip *chip, loff_t from,
3566	struct mtd_oob_ops *ops)
3567	{
3568	int chipnr, page, realpage, col, bytes, aligned, oob_required;
3569	struct mtd_info *mtd = nand_to_mtd(chip);
3570	int ret = 0;
3571	uint32_t readlen = ops->len;
3572	uint32_t oobreadlen = ops->ooblen;
3573	uint32_t max_oobsize = mtd_oobavail(mtd, ops);
3574
3575	uint8_t *bufpoi, *oob, *buf;
3576	int use_bounce_buf;
3577	unsigned int max_bitflips = 0;
3578	int retry_mode = 0;
3579	bool ecc_fail = false;
3580
3581	/* Check if the region is secured */
3582	if (nand_region_is_secured(chip, offset: from, size: readlen))
3583	return -EIO;
3584
3585	chipnr = (int)(from >> chip->chip_shift);
3586	nand_select_target(chip, chipnr);
3587
3588	realpage = (int)(from >> chip->page_shift);
3589	page = realpage & chip->pagemask;
3590
3591	col = (int)(from & (mtd->writesize - 1));
3592
3593	buf = ops->datbuf;
3594	oob = ops->oobbuf;
3595	oob_required = oob ? 1 : 0;
3596
3597	if (likely(ops->mode != MTD_OPS_RAW))
3598	rawnand_enable_cont_reads(chip, page, readlen, col);
3599
3600	while (1) {
3601	struct mtd_ecc_stats ecc_stats = mtd->ecc_stats;
3602
3603	bytes = min(mtd->writesize - col, readlen);
3604	aligned = (bytes == mtd->writesize);
3605
3606	if (!aligned)
3607	use_bounce_buf = 1;
3608	else if (chip->options & NAND_USES_DMA)
3609	use_bounce_buf = !virt_addr_valid(buf) ||
3610	!IS_ALIGNED((unsigned long)buf,
3611	chip->buf_align);
3612	else
3613	use_bounce_buf = 0;
3614
3615	/* Is the current page in the buffer? */
3616	if (realpage != chip->pagecache.page || oob) {
3617	bufpoi = use_bounce_buf ? chip->data_buf : buf;
3618
3619	if (use_bounce_buf && aligned)
3620	pr_debug("%s: using read bounce buffer for buf@%p\n",
3621	__func__, buf);
3622
3623	read_retry:
3624	/*
3625	* Now read the page into the buffer. Absent an error,
3626	* the read methods return max bitflips per ecc step.
3627	*/
3628	if (unlikely(ops->mode == MTD_OPS_RAW))
3629	ret = chip->ecc.read_page_raw(chip, bufpoi,
3630	oob_required,
3631	page);
3632	else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
3633	!oob)
3634	ret = chip->ecc.read_subpage(chip, col, bytes,
3635	bufpoi, page);
3636	else
3637	ret = chip->ecc.read_page(chip, bufpoi,
3638	oob_required, page);
3639	if (ret < 0) {
3640	if (use_bounce_buf)
3641	/* Invalidate page cache */
3642	chip->pagecache.page = -1;
3643	break;
3644	}
3645
3646	/*
3647	* Copy back the data in the initial buffer when reading
3648	* partial pages or when a bounce buffer is required.
3649	*/
3650	if (use_bounce_buf) {
3651	if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
3652	!(mtd->ecc_stats.failed - ecc_stats.failed) &&
3653	(ops->mode != MTD_OPS_RAW)) {
3654	chip->pagecache.page = realpage;
3655	chip->pagecache.bitflips = ret;
3656	} else {
3657	/* Invalidate page cache */
3658	chip->pagecache.page = -1;
3659	}
3660	memcpy(buf, bufpoi + col, bytes);
3661	}
3662
3663	if (unlikely(oob)) {
3664	int toread = min(oobreadlen, max_oobsize);
3665
3666	if (toread) {
3667	oob = nand_transfer_oob(chip, oob, ops,
3668	len: toread);
3669	oobreadlen -= toread;
3670	}
3671	}
3672
3673	nand_wait_readrdy(chip);
3674
3675	if (mtd->ecc_stats.failed - ecc_stats.failed) {
3676	if (retry_mode + 1 < chip->read_retries) {
3677	retry_mode++;
3678	ret = nand_setup_read_retry(chip,
3679	retry_mode);
3680	if (ret < 0)
3681	break;
3682
3683	/* Reset ecc_stats; retry */
3684	mtd->ecc_stats = ecc_stats;
3685	goto read_retry;
3686	} else {
3687	/* No more retry modes; real failure */
3688	ecc_fail = true;
3689	}
3690	}
3691
3692	buf += bytes;
3693	max_bitflips = max_t(unsigned int, max_bitflips, ret);
3694	} else {
3695	memcpy(buf, chip->data_buf + col, bytes);
3696	buf += bytes;
3697	max_bitflips = max_t(unsigned int, max_bitflips,
3698	chip->pagecache.bitflips);
3699
3700	rawnand_cont_read_skip_first_page(chip, page);
3701	}
3702
3703	readlen -= bytes;
3704
3705	/* Reset to retry mode 0 */
3706	if (retry_mode) {
3707	ret = nand_setup_read_retry(chip, retry_mode: 0);
3708	if (ret < 0)
3709	break;
3710	retry_mode = 0;
3711	}
3712
3713	if (!readlen)
3714	break;
3715
3716	/* For subsequent reads align to page boundary */
3717	col = 0;
3718	/* Increment page address */
3719	realpage++;
3720
3721	page = realpage & chip->pagemask;
3722	/* Check, if we cross a chip boundary */
3723	if (!page) {
3724	chipnr++;
3725	nand_deselect_target(chip);
3726	nand_select_target(chip, chipnr);
3727	}
3728	}
3729	nand_deselect_target(chip);
3730
3731	if (WARN_ON_ONCE(chip->cont_read.ongoing))
3732	chip->cont_read.ongoing = false;
3733
3734	ops->retlen = ops->len - (size_t) readlen;
3735	if (oob)
3736	ops->oobretlen = ops->ooblen - oobreadlen;
3737
3738	if (ret < 0)
3739	return ret;
3740
3741	if (ecc_fail)
3742	return -EBADMSG;
3743
3744	return max_bitflips;
3745	}
3746
3747	/**
3748	* nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
3749	* @chip: nand chip info structure
3750	* @page: page number to read
3751	*/
3752	int nand_read_oob_std(struct nand_chip *chip, int page)
3753	{
3754	struct mtd_info *mtd = nand_to_mtd(chip);
3755
3756	return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
3757	}
3758	EXPORT_SYMBOL(nand_read_oob_std);
3759
3760	/**
3761	* nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
3762	* with syndromes
3763	* @chip: nand chip info structure
3764	* @page: page number to read
3765	*/
3766	static int nand_read_oob_syndrome(struct nand_chip *chip, int page)
3767	{
3768	struct mtd_info *mtd = nand_to_mtd(chip);
3769	int length = mtd->oobsize;
3770	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
3771	int eccsize = chip->ecc.size;
3772	uint8_t *bufpoi = chip->oob_poi;
3773	int i, toread, sndrnd = 0, pos, ret;
3774
3775	ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0);
3776	if (ret)
3777	return ret;
3778
3779	for (i = 0; i < chip->ecc.steps; i++) {
3780	if (sndrnd) {
3781	int ret;
3782
3783	pos = eccsize + i * (eccsize + chunk);
3784	if (mtd->writesize > 512)
3785	ret = nand_change_read_column_op(chip, pos,
3786	NULL, 0,
3787	false);
3788	else
3789	ret = nand_read_page_op(chip, page, pos, NULL,
3790	0);
3791
3792	if (ret)
3793	return ret;
3794	} else
3795	sndrnd = 1;
3796	toread = min_t(int, length, chunk);
3797
3798	ret = nand_read_data_op(chip, bufpoi, toread, false, false);
3799	if (ret)
3800	return ret;
3801
3802	bufpoi += toread;
3803	length -= toread;
3804	}
3805	if (length > 0) {
3806	ret = nand_read_data_op(chip, bufpoi, length, false, false);
3807	if (ret)
3808	return ret;
3809	}
3810
3811	return 0;
3812	}
3813
3814	/**
3815	* nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
3816	* @chip: nand chip info structure
3817	* @page: page number to write
3818	*/
3819	int nand_write_oob_std(struct nand_chip *chip, int page)
3820	{
3821	struct mtd_info *mtd = nand_to_mtd(chip);
3822
3823	return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
3824	mtd->oobsize);
3825	}
3826	EXPORT_SYMBOL(nand_write_oob_std);
3827
3828	/**
3829	* nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
3830	* with syndrome - only for large page flash
3831	* @chip: nand chip info structure
3832	* @page: page number to write
3833	*/
3834	static int nand_write_oob_syndrome(struct nand_chip *chip, int page)
3835	{
3836	struct mtd_info *mtd = nand_to_mtd(chip);
3837	int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
3838	int eccsize = chip->ecc.size, length = mtd->oobsize;
3839	int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;
3840	const uint8_t *bufpoi = chip->oob_poi;
3841
3842	/*
3843	* data-ecc-data-ecc ... ecc-oob
3844	* or
3845	* data-pad-ecc-pad-data-pad .... ecc-pad-oob
3846	*/
3847	if (!chip->ecc.prepad && !chip->ecc.postpad) {
3848	pos = steps * (eccsize + chunk);
3849	steps = 0;
3850	} else
3851	pos = eccsize;
3852
3853	ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0);
3854	if (ret)
3855	return ret;
3856
3857	for (i = 0; i < steps; i++) {
3858	if (sndcmd) {
3859	if (mtd->writesize <= 512) {
3860	uint32_t fill = 0xFFFFFFFF;
3861
3862	len = eccsize;
3863	while (len > 0) {
3864	int num = min_t(int, len, 4);
3865
3866	ret = nand_write_data_op(chip, &fill,
3867	num, false);
3868	if (ret)
3869	return ret;
3870
3871	len -= num;
3872	}
3873	} else {
3874	pos = eccsize + i * (eccsize + chunk);
3875	ret = nand_change_write_column_op(chip, pos,
3876	NULL, 0,
3877	false);
3878	if (ret)
3879	return ret;
3880	}
3881	} else
3882	sndcmd = 1;
3883	len = min_t(int, length, chunk);
3884
3885	ret = nand_write_data_op(chip, bufpoi, len, false);
3886	if (ret)
3887	return ret;
3888
3889	bufpoi += len;
3890	length -= len;
3891	}
3892	if (length > 0) {
3893	ret = nand_write_data_op(chip, bufpoi, length, false);
3894	if (ret)
3895	return ret;
3896	}
3897
3898	return nand_prog_page_end_op(chip);
3899	}
3900
3901	/**
3902	* nand_do_read_oob - [INTERN] NAND read out-of-band
3903	* @chip: NAND chip object
3904	* @from: offset to read from
3905	* @ops: oob operations description structure
3906	*
3907	* NAND read out-of-band data from the spare area.
3908	*/
3909	static int nand_do_read_oob(struct nand_chip *chip, loff_t from,
3910	struct mtd_oob_ops *ops)
3911	{
3912	struct mtd_info *mtd = nand_to_mtd(chip);
3913	unsigned int max_bitflips = 0;
3914	int page, realpage, chipnr;
3915	struct mtd_ecc_stats stats;
3916	int readlen = ops->ooblen;
3917	int len;
3918	uint8_t *buf = ops->oobbuf;
3919	int ret = 0;
3920
3921	pr_debug("%s: from = 0x%08Lx, len = %i\n",
3922	__func__, (unsigned long long)from, readlen);
3923
3924	/* Check if the region is secured */
3925	if (nand_region_is_secured(chip, offset: from, size: readlen))
3926	return -EIO;
3927
3928	stats = mtd->ecc_stats;
3929
3930	len = mtd_oobavail(mtd, ops);
3931
3932	chipnr = (int)(from >> chip->chip_shift);
3933	nand_select_target(chip, chipnr);
3934
3935	/* Shift to get page */
3936	realpage = (int)(from >> chip->page_shift);
3937	page = realpage & chip->pagemask;
3938
3939	while (1) {
3940	if (ops->mode == MTD_OPS_RAW)
3941	ret = chip->ecc.read_oob_raw(chip, page);
3942	else
3943	ret = chip->ecc.read_oob(chip, page);
3944
3945	if (ret < 0)
3946	break;
3947
3948	len = min(len, readlen);
3949	buf = nand_transfer_oob(chip, oob: buf, ops, len);
3950
3951	nand_wait_readrdy(chip);
3952
3953	max_bitflips = max_t(unsigned int, max_bitflips, ret);
3954
3955	readlen -= len;
3956	if (!readlen)
3957	break;
3958
3959	/* Increment page address */
3960	realpage++;
3961
3962	page = realpage & chip->pagemask;
3963	/* Check, if we cross a chip boundary */
3964	if (!page) {
3965	chipnr++;
3966	nand_deselect_target(chip);
3967	nand_select_target(chip, chipnr);
3968	}
3969	}
3970	nand_deselect_target(chip);
3971
3972	ops->oobretlen = ops->ooblen - readlen;
3973
3974	if (ret < 0)
3975	return ret;
3976
3977	if (mtd->ecc_stats.failed - stats.failed)
3978	return -EBADMSG;
3979
3980	return max_bitflips;
3981	}
3982
3983	/**
3984	* nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
3985	* @mtd: MTD device structure
3986	* @from: offset to read from
3987	* @ops: oob operation description structure
3988	*
3989	* NAND read data and/or out-of-band data.
3990	*/
3991	static int nand_read_oob(struct mtd_info *mtd, loff_t from,
3992	struct mtd_oob_ops *ops)
3993	{
3994	struct nand_chip *chip = mtd_to_nand(mtd);
3995	struct mtd_ecc_stats old_stats;
3996	int ret;
3997
3998	ops->retlen = 0;
3999
4000	if (ops->mode != MTD_OPS_PLACE_OOB &&
4001	ops->mode != MTD_OPS_AUTO_OOB &&
4002	ops->mode != MTD_OPS_RAW)
4003	return -ENOTSUPP;
4004
4005	nand_get_device(chip);
4006
4007	old_stats = mtd->ecc_stats;
4008
4009	if (!ops->datbuf)
4010	ret = nand_do_read_oob(chip, from, ops);
4011	else
4012	ret = nand_do_read_ops(chip, from, ops);
4013
4014	if (ops->stats) {
4015	ops->stats->uncorrectable_errors +=
4016	mtd->ecc_stats.failed - old_stats.failed;
4017	ops->stats->corrected_bitflips +=
4018	mtd->ecc_stats.corrected - old_stats.corrected;
4019	}
4020
4021	nand_release_device(chip);
4022	return ret;
4023	}
4024
4025	/**
4026	* nand_write_page_raw_notsupp - dummy raw page write function
4027	* @chip: nand chip info structure
4028	* @buf: data buffer
4029	* @oob_required: must write chip->oob_poi to OOB
4030	* @page: page number to write
4031	*
4032	* Returns -ENOTSUPP unconditionally.
4033	*/
4034	int nand_write_page_raw_notsupp(struct nand_chip *chip, const u8 *buf,
4035	int oob_required, int page)
4036	{
4037	return -ENOTSUPP;
4038	}
4039
4040	/**
4041	* nand_write_page_raw - [INTERN] raw page write function
4042	* @chip: nand chip info structure
4043	* @buf: data buffer
4044	* @oob_required: must write chip->oob_poi to OOB
4045	* @page: page number to write
4046	*
4047	* Not for syndrome calculating ECC controllers, which use a special oob layout.
4048	*/
4049	int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
4050	int oob_required, int page)
4051	{
4052	struct mtd_info *mtd = nand_to_mtd(chip);
4053	int ret;
4054
4055	ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
4056	if (ret)
4057	return ret;
4058
4059	if (oob_required) {
4060	ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,
4061	false);
4062	if (ret)
4063	return ret;
4064	}
4065
4066	return nand_prog_page_end_op(chip);
4067	}
4068	EXPORT_SYMBOL(nand_write_page_raw);
4069
4070	/**
4071	* nand_monolithic_write_page_raw - Monolithic page write in raw mode
4072	* @chip: NAND chip info structure
4073	* @buf: data buffer to write
4074	* @oob_required: must write chip->oob_poi to OOB
4075	* @page: page number to write
4076	*
4077	* This is a raw page write, ie. without any error detection/correction.
4078	* Monolithic means we are requesting all the relevant data (main plus
4079	* eventually OOB) to be sent over the bus and effectively programmed
4080	* into the NAND chip arrays in a single operation. This is an
4081	* alternative to nand_write_page_raw(), which first sends the main
4082	* data, then eventually send the OOB data by latching more data
4083	* cycles on the NAND bus, and finally sends the program command to
4084	* synchronyze the NAND chip cache.
4085	*/
4086	int nand_monolithic_write_page_raw(struct nand_chip *chip, const u8 *buf,
4087	int oob_required, int page)
4088	{
4089	struct mtd_info *mtd = nand_to_mtd(chip);
4090	unsigned int size = mtd->writesize;
4091	u8 *write_buf = (u8 *)buf;
4092
4093	if (oob_required) {
4094	size += mtd->oobsize;
4095
4096	if (buf != chip->data_buf) {
4097	write_buf = nand_get_data_buf(chip);
4098	memcpy(write_buf, buf, mtd->writesize);
4099	}
4100	}
4101
4102	return nand_prog_page_op(chip, page, 0, write_buf, size);
4103	}
4104	EXPORT_SYMBOL(nand_monolithic_write_page_raw);
4105
4106	/**
4107	* nand_write_page_raw_syndrome - [INTERN] raw page write function
4108	* @chip: nand chip info structure
4109	* @buf: data buffer
4110	* @oob_required: must write chip->oob_poi to OOB
4111	* @page: page number to write
4112	*
4113	* We need a special oob layout and handling even when ECC isn't checked.
4114	*/
4115	static int nand_write_page_raw_syndrome(struct nand_chip *chip,
4116	const uint8_t *buf, int oob_required,
4117	int page)
4118	{
4119	struct mtd_info *mtd = nand_to_mtd(chip);
4120	int eccsize = chip->ecc.size;
4121	int eccbytes = chip->ecc.bytes;
4122	uint8_t *oob = chip->oob_poi;
4123	int steps, size, ret;
4124
4125	ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
4126	if (ret)
4127	return ret;
4128
4129	for (steps = chip->ecc.steps; steps > 0; steps--) {
4130	ret = nand_write_data_op(chip, buf, eccsize, false);
4131	if (ret)
4132	return ret;
4133
4134	buf += eccsize;
4135
4136	if (chip->ecc.prepad) {
4137	ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
4138	false);
4139	if (ret)
4140	return ret;
4141
4142	oob += chip->ecc.prepad;
4143	}
4144
4145	ret = nand_write_data_op(chip, oob, eccbytes, false);
4146	if (ret)
4147	return ret;
4148
4149	oob += eccbytes;
4150
4151	if (chip->ecc.postpad) {
4152	ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
4153	false);
4154	if (ret)
4155	return ret;
4156
4157	oob += chip->ecc.postpad;
4158	}
4159	}
4160
4161	size = mtd->oobsize - (oob - chip->oob_poi);
4162	if (size) {
4163	ret = nand_write_data_op(chip, oob, size, false);
4164	if (ret)
4165	return ret;
4166	}
4167
4168	return nand_prog_page_end_op(chip);
4169	}
4170	/**
4171	* nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
4172	* @chip: nand chip info structure
4173	* @buf: data buffer
4174	* @oob_required: must write chip->oob_poi to OOB
4175	* @page: page number to write
4176	*/
4177	static int nand_write_page_swecc(struct nand_chip *chip, const uint8_t *buf,
4178	int oob_required, int page)
4179	{
4180	struct mtd_info *mtd = nand_to_mtd(chip);
4181	int i, eccsize = chip->ecc.size, ret;
4182	int eccbytes = chip->ecc.bytes;
4183	int eccsteps = chip->ecc.steps;
4184	uint8_t *ecc_calc = chip->ecc.calc_buf;
4185	const uint8_t *p = buf;
4186
4187	/* Software ECC calculation */
4188	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
4189	chip->ecc.calculate(chip, p, &ecc_calc[i]);
4190
4191	ret = mtd_ooblayout_set_eccbytes(mtd, eccbuf: ecc_calc, oobbuf: chip->oob_poi, start: 0,
4192	nbytes: chip->ecc.total);
4193	if (ret)
4194	return ret;
4195
4196	return chip->ecc.write_page_raw(chip, buf, 1, page);
4197	}
4198
4199	/**
4200	* nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
4201	* @chip: nand chip info structure
4202	* @buf: data buffer
4203	* @oob_required: must write chip->oob_poi to OOB
4204	* @page: page number to write
4205	*/
4206	static int nand_write_page_hwecc(struct nand_chip *chip, const uint8_t *buf,
4207	int oob_required, int page)
4208	{
4209	struct mtd_info *mtd = nand_to_mtd(chip);
4210	int i, eccsize = chip->ecc.size, ret;
4211	int eccbytes = chip->ecc.bytes;
4212	int eccsteps = chip->ecc.steps;
4213	uint8_t *ecc_calc = chip->ecc.calc_buf;
4214	const uint8_t *p = buf;
4215
4216	ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
4217	if (ret)
4218	return ret;
4219
4220	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
4221	chip->ecc.hwctl(chip, NAND_ECC_WRITE);
4222
4223	ret = nand_write_data_op(chip, p, eccsize, false);
4224	if (ret)
4225	return ret;
4226
4227	chip->ecc.calculate(chip, p, &ecc_calc[i]);
4228	}
4229
4230	ret = mtd_ooblayout_set_eccbytes(mtd, eccbuf: ecc_calc, oobbuf: chip->oob_poi, start: 0,
4231	nbytes: chip->ecc.total);
4232	if (ret)
4233	return ret;
4234
4235	ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
4236	if (ret)
4237	return ret;
4238
4239	return nand_prog_page_end_op(chip);
4240	}
4241
4242
4243	/**
4244	* nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
4245	* @chip: nand chip info structure
4246	* @offset: column address of subpage within the page
4247	* @data_len: data length
4248	* @buf: data buffer
4249	* @oob_required: must write chip->oob_poi to OOB
4250	* @page: page number to write
4251	*/
4252	static int nand_write_subpage_hwecc(struct nand_chip *chip, uint32_t offset,
4253	uint32_t data_len, const uint8_t *buf,
4254	int oob_required, int page)
4255	{
4256	struct mtd_info *mtd = nand_to_mtd(chip);
4257	uint8_t *oob_buf = chip->oob_poi;
4258	uint8_t *ecc_calc = chip->ecc.calc_buf;
4259	int ecc_size = chip->ecc.size;
4260	int ecc_bytes = chip->ecc.bytes;
4261	int ecc_steps = chip->ecc.steps;
4262	uint32_t start_step = offset / ecc_size;
4263	uint32_t end_step = (offset + data_len - 1) / ecc_size;
4264	int oob_bytes = mtd->oobsize / ecc_steps;
4265	int step, ret;
4266
4267	ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
4268	if (ret)
4269	return ret;
4270
4271	for (step = 0; step < ecc_steps; step++) {
4272	/* configure controller for WRITE access */
4273	chip->ecc.hwctl(chip, NAND_ECC_WRITE);
4274
4275	/* write data (untouched subpages already masked by 0xFF) */
4276	ret = nand_write_data_op(chip, buf, ecc_size, false);
4277	if (ret)
4278	return ret;
4279
4280	/* mask ECC of un-touched subpages by padding 0xFF */
4281	if ((step < start_step) || (step > end_step))
4282	memset(ecc_calc, 0xff, ecc_bytes);
4283	else
4284	chip->ecc.calculate(chip, buf, ecc_calc);
4285
4286	/* mask OOB of un-touched subpages by padding 0xFF */
4287	/* if oob_required, preserve OOB metadata of written subpage */
4288	if (!oob_required || (step < start_step) || (step > end_step))
4289	memset(oob_buf, 0xff, oob_bytes);
4290
4291	buf += ecc_size;
4292	ecc_calc += ecc_bytes;
4293	oob_buf += oob_bytes;
4294	}
4295
4296	/* copy calculated ECC for whole page to chip->buffer->oob */
4297	/* this include masked-value(0xFF) for unwritten subpages */
4298	ecc_calc = chip->ecc.calc_buf;
4299	ret = mtd_ooblayout_set_eccbytes(mtd, eccbuf: ecc_calc, oobbuf: chip->oob_poi, start: 0,
4300	nbytes: chip->ecc.total);
4301	if (ret)
4302	return ret;
4303
4304	/* write OOB buffer to NAND device */
4305	ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
4306	if (ret)
4307	return ret;
4308
4309	return nand_prog_page_end_op(chip);
4310	}
4311
4312
4313	/**
4314	* nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
4315	* @chip: nand chip info structure
4316	* @buf: data buffer
4317	* @oob_required: must write chip->oob_poi to OOB
4318	* @page: page number to write
4319	*
4320	* The hw generator calculates the error syndrome automatically. Therefore we
4321	* need a special oob layout and handling.
4322	*/
4323	static int nand_write_page_syndrome(struct nand_chip *chip, const uint8_t *buf,
4324	int oob_required, int page)
4325	{
4326	struct mtd_info *mtd = nand_to_mtd(chip);
4327	int i, eccsize = chip->ecc.size;
4328	int eccbytes = chip->ecc.bytes;
4329	int eccsteps = chip->ecc.steps;
4330	const uint8_t *p = buf;
4331	uint8_t *oob = chip->oob_poi;
4332	int ret;
4333
4334	ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);
4335	if (ret)
4336	return ret;
4337
4338	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
4339	chip->ecc.hwctl(chip, NAND_ECC_WRITE);
4340
4341	ret = nand_write_data_op(chip, p, eccsize, false);
4342	if (ret)
4343	return ret;
4344
4345	if (chip->ecc.prepad) {
4346	ret = nand_write_data_op(chip, oob, chip->ecc.prepad,
4347	false);
4348	if (ret)
4349	return ret;
4350
4351	oob += chip->ecc.prepad;
4352	}
4353
4354	chip->ecc.calculate(chip, p, oob);
4355
4356	ret = nand_write_data_op(chip, oob, eccbytes, false);
4357	if (ret)
4358	return ret;
4359
4360	oob += eccbytes;
4361
4362	if (chip->ecc.postpad) {
4363	ret = nand_write_data_op(chip, oob, chip->ecc.postpad,
4364	false);
4365	if (ret)
4366	return ret;
4367
4368	oob += chip->ecc.postpad;
4369	}
4370	}
4371
4372	/* Calculate remaining oob bytes */
4373	i = mtd->oobsize - (oob - chip->oob_poi);
4374	if (i) {
4375	ret = nand_write_data_op(chip, oob, i, false);
4376	if (ret)
4377	return ret;
4378	}
4379
4380	return nand_prog_page_end_op(chip);
4381	}
4382
4383	/**
4384	* nand_write_page - write one page
4385	* @chip: NAND chip descriptor
4386	* @offset: address offset within the page
4387	* @data_len: length of actual data to be written
4388	* @buf: the data to write
4389	* @oob_required: must write chip->oob_poi to OOB
4390	* @page: page number to write
4391	* @raw: use _raw version of write_page
4392	*/
4393	static int nand_write_page(struct nand_chip *chip, uint32_t offset,
4394	int data_len, const uint8_t *buf, int oob_required,
4395	int page, int raw)
4396	{
4397	struct mtd_info *mtd = nand_to_mtd(chip);
4398	int status, subpage;
4399
4400	if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
4401	chip->ecc.write_subpage)
4402	subpage = offset || (data_len < mtd->writesize);
4403	else
4404	subpage = 0;
4405
4406	if (unlikely(raw))
4407	status = chip->ecc.write_page_raw(chip, buf, oob_required,
4408	page);
4409	else if (subpage)
4410	status = chip->ecc.write_subpage(chip, offset, data_len, buf,
4411	oob_required, page);
4412	else
4413	status = chip->ecc.write_page(chip, buf, oob_required, page);
4414
4415	if (status < 0)
4416	return status;
4417
4418	return 0;
4419	}
4420
4421	#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
4422
4423	/**
4424	* nand_do_write_ops - [INTERN] NAND write with ECC
4425	* @chip: NAND chip object
4426	* @to: offset to write to
4427	* @ops: oob operations description structure
4428	*
4429	* NAND write with ECC.
4430	*/
4431	static int nand_do_write_ops(struct nand_chip *chip, loff_t to,
4432	struct mtd_oob_ops *ops)
4433	{
4434	struct mtd_info *mtd = nand_to_mtd(chip);
4435	int chipnr, realpage, page, column;
4436	uint32_t writelen = ops->len;
4437
4438	uint32_t oobwritelen = ops->ooblen;
4439	uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
4440
4441	uint8_t *oob = ops->oobbuf;
4442	uint8_t *buf = ops->datbuf;
4443	int ret;
4444	int oob_required = oob ? 1 : 0;
4445
4446	ops->retlen = 0;
4447	if (!writelen)
4448	return 0;
4449
4450	/* Reject writes, which are not page aligned */
4451	if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
4452	pr_notice("%s: attempt to write non page aligned data\n",
4453	__func__);
4454	return -EINVAL;
4455	}
4456
4457	/* Check if the region is secured */
4458	if (nand_region_is_secured(chip, offset: to, size: writelen))
4459	return -EIO;
4460
4461	column = to & (mtd->writesize - 1);
4462
4463	chipnr = (int)(to >> chip->chip_shift);
4464	nand_select_target(chip, chipnr);
4465
4466	/* Check, if it is write protected */
4467	if (nand_check_wp(chip)) {
4468	ret = -EIO;
4469	goto err_out;
4470	}
4471
4472	realpage = (int)(to >> chip->page_shift);
4473	page = realpage & chip->pagemask;
4474
4475	/* Invalidate the page cache, when we write to the cached page */
4476	if (to <= ((loff_t)chip->pagecache.page << chip->page_shift) &&
4477	((loff_t)chip->pagecache.page << chip->page_shift) < (to + ops->len))
4478	chip->pagecache.page = -1;
4479
4480	/* Don't allow multipage oob writes with offset */
4481	if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
4482	ret = -EINVAL;
4483	goto err_out;
4484	}
4485
4486	while (1) {
4487	int bytes = mtd->writesize;
4488	uint8_t *wbuf = buf;
4489	int use_bounce_buf;
4490	int part_pagewr = (column || writelen < mtd->writesize);
4491
4492	if (part_pagewr)
4493	use_bounce_buf = 1;
4494	else if (chip->options & NAND_USES_DMA)
4495	use_bounce_buf = !virt_addr_valid(buf) ||
4496	!IS_ALIGNED((unsigned long)buf,
4497	chip->buf_align);
4498	else
4499	use_bounce_buf = 0;
4500
4501	/*
4502	* Copy the data from the initial buffer when doing partial page
4503	* writes or when a bounce buffer is required.
4504	*/
4505	if (use_bounce_buf) {
4506	pr_debug("%s: using write bounce buffer for buf@%p\n",
4507	__func__, buf);
4508	if (part_pagewr)
4509	bytes = min_t(int, bytes - column, writelen);
4510	wbuf = nand_get_data_buf(chip);
4511	memset(wbuf, 0xff, mtd->writesize);
4512	memcpy(&wbuf[column], buf, bytes);
4513	}
4514
4515	if (unlikely(oob)) {
4516	size_t len = min(oobwritelen, oobmaxlen);
4517	oob = nand_fill_oob(chip, oob, len, ops);
4518	oobwritelen -= len;
4519	} else {
4520	/* We still need to erase leftover OOB data */
4521	memset(chip->oob_poi, 0xff, mtd->oobsize);
4522	}
4523
4524	ret = nand_write_page(chip, offset: column, data_len: bytes, buf: wbuf,
4525	oob_required, page,
4526	raw: (ops->mode == MTD_OPS_RAW));
4527	if (ret)
4528	break;
4529
4530	writelen -= bytes;
4531	if (!writelen)
4532	break;
4533
4534	column = 0;
4535	buf += bytes;
4536	realpage++;
4537
4538	page = realpage & chip->pagemask;
4539	/* Check, if we cross a chip boundary */
4540	if (!page) {
4541	chipnr++;
4542	nand_deselect_target(chip);
4543	nand_select_target(chip, chipnr);
4544	}
4545	}
4546
4547	ops->retlen = ops->len - writelen;
4548	if (unlikely(oob))
4549	ops->oobretlen = ops->ooblen;
4550
4551	err_out:
4552	nand_deselect_target(chip);
4553	return ret;
4554	}
4555
4556	/**
4557	* panic_nand_write - [MTD Interface] NAND write with ECC
4558	* @mtd: MTD device structure
4559	* @to: offset to write to
4560	* @len: number of bytes to write
4561	* @retlen: pointer to variable to store the number of written bytes
4562	* @buf: the data to write
4563	*
4564	* NAND write with ECC. Used when performing writes in interrupt context, this
4565	* may for example be called by mtdoops when writing an oops while in panic.
4566	*/
4567	static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
4568	size_t *retlen, const uint8_t *buf)
4569	{
4570	struct nand_chip *chip = mtd_to_nand(mtd);
4571	int chipnr = (int)(to >> chip->chip_shift);
4572	struct mtd_oob_ops ops;
4573	int ret;
4574
4575	nand_select_target(chip, chipnr);
4576
4577	/* Wait for the device to get ready */
4578	panic_nand_wait(chip, timeo: 400);
4579
4580	memset(&ops, 0, sizeof(ops));
4581	ops.len = len;
4582	ops.datbuf = (uint8_t *)buf;
4583	ops.mode = MTD_OPS_PLACE_OOB;
4584
4585	ret = nand_do_write_ops(chip, to, ops: &ops);
4586
4587	*retlen = ops.retlen;
4588	return ret;
4589	}
4590
4591	/**
4592	* nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
4593	* @mtd: MTD device structure
4594	* @to: offset to write to
4595	* @ops: oob operation description structure
4596	*/
4597	static int nand_write_oob(struct mtd_info *mtd, loff_t to,
4598	struct mtd_oob_ops *ops)
4599	{
4600	struct nand_chip *chip = mtd_to_nand(mtd);
4601	int ret = 0;
4602
4603	ops->retlen = 0;
4604
4605	nand_get_device(chip);
4606
4607	switch (ops->mode) {
4608	case MTD_OPS_PLACE_OOB:
4609	case MTD_OPS_AUTO_OOB:
4610	case MTD_OPS_RAW:
4611	break;
4612
4613	default:
4614	goto out;
4615	}
4616
4617	if (!ops->datbuf)
4618	ret = nand_do_write_oob(chip, to, ops);
4619	else
4620	ret = nand_do_write_ops(chip, to, ops);
4621
4622	out:
4623	nand_release_device(chip);
4624	return ret;
4625	}
4626
4627	/**
4628	* nand_erase - [MTD Interface] erase block(s)
4629	* @mtd: MTD device structure
4630	* @instr: erase instruction
4631	*
4632	* Erase one ore more blocks.
4633	*/
4634	static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
4635	{
4636	return nand_erase_nand(chip: mtd_to_nand(mtd), instr, allowbbt: 0);
4637	}
4638
4639	/**
4640	* nand_erase_nand - [INTERN] erase block(s)
4641	* @chip: NAND chip object
4642	* @instr: erase instruction
4643	* @allowbbt: allow erasing the bbt area
4644	*
4645	* Erase one ore more blocks.
4646	*/
4647	int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
4648	int allowbbt)
4649	{
4650	int page, pages_per_block, ret, chipnr;
4651	loff_t len;
4652
4653	pr_debug("%s: start = 0x%012llx, len = %llu\n",
4654	__func__, (unsigned long long)instr->addr,
4655	(unsigned long long)instr->len);
4656
4657	if (check_offs_len(chip, ofs: instr->addr, len: instr->len))
4658	return -EINVAL;
4659
4660	/* Check if the region is secured */
4661	if (nand_region_is_secured(chip, offset: instr->addr, size: instr->len))
4662	return -EIO;
4663
4664	/* Grab the lock and see if the device is available */
4665	nand_get_device(chip);
4666
4667	/* Shift to get first page */
4668	page = (int)(instr->addr >> chip->page_shift);
4669	chipnr = (int)(instr->addr >> chip->chip_shift);
4670
4671	/* Calculate pages in each block */
4672	pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
4673
4674	/* Select the NAND device */
4675	nand_select_target(chip, chipnr);
4676
4677	/* Check, if it is write protected */
4678	if (nand_check_wp(chip)) {
4679	pr_debug("%s: device is write protected!\n",
4680	__func__);
4681	ret = -EIO;
4682	goto erase_exit;
4683	}
4684
4685	/* Loop through the pages */
4686	len = instr->len;
4687
4688	while (len) {
4689	loff_t ofs = (loff_t)page << chip->page_shift;
4690
4691	/* Check if we have a bad block, we do not erase bad blocks! */
4692	if (nand_block_checkbad(chip, ofs: ((loff_t) page) <<
4693	chip->page_shift, allowbbt)) {
4694	pr_warn("%s: attempt to erase a bad block at 0x%08llx\n",
4695	__func__, (unsigned long long)ofs);
4696	ret = -EIO;
4697	goto erase_exit;
4698	}
4699
4700	/*
4701	* Invalidate the page cache, if we erase the block which
4702	* contains the current cached page.
4703	*/
4704	if (page <= chip->pagecache.page && chip->pagecache.page <
4705	(page + pages_per_block))
4706	chip->pagecache.page = -1;
4707
4708	ret = nand_erase_op(chip, (page & chip->pagemask) >>
4709	(chip->phys_erase_shift - chip->page_shift));
4710	if (ret) {
4711	pr_debug("%s: failed erase, page 0x%08x\n",
4712	__func__, page);
4713	instr->fail_addr = ofs;
4714	goto erase_exit;
4715	}
4716
4717	/* Increment page address and decrement length */
4718	len -= (1ULL << chip->phys_erase_shift);
4719	page += pages_per_block;
4720
4721	/* Check, if we cross a chip boundary */
4722	if (len && !(page & chip->pagemask)) {
4723	chipnr++;
4724	nand_deselect_target(chip);
4725	nand_select_target(chip, chipnr);
4726	}
4727	}
4728
4729	ret = 0;
4730	erase_exit:
4731
4732	/* Deselect and wake up anyone waiting on the device */
4733	nand_deselect_target(chip);
4734	nand_release_device(chip);
4735
4736	/* Return more or less happy */
4737	return ret;
4738	}
4739
4740	/**
4741	* nand_sync - [MTD Interface] sync
4742	* @mtd: MTD device structure
4743	*
4744	* Sync is actually a wait for chip ready function.
4745	*/
4746	static void nand_sync(struct mtd_info *mtd)
4747	{
4748	struct nand_chip *chip = mtd_to_nand(mtd);
4749
4750	pr_debug("%s: called\n", __func__);
4751
4752	/* Grab the lock and see if the device is available */
4753	nand_get_device(chip);
4754	/* Release it and go back */
4755	nand_release_device(chip);
4756	}
4757
4758	/**
4759	* nand_block_isbad - [MTD Interface] Check if block at offset is bad
4760	* @mtd: MTD device structure
4761	* @offs: offset relative to mtd start
4762	*/
4763	static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
4764	{
4765	struct nand_chip *chip = mtd_to_nand(mtd);
4766	int chipnr = (int)(offs >> chip->chip_shift);
4767	int ret;
4768
4769	/* Select the NAND device */
4770	nand_get_device(chip);
4771
4772	nand_select_target(chip, chipnr);
4773
4774	ret = nand_block_checkbad(chip, ofs: offs, allowbbt: 0);
4775
4776	nand_deselect_target(chip);
4777	nand_release_device(chip);
4778
4779	return ret;
4780	}
4781
4782	/**
4783	* nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
4784	* @mtd: MTD device structure
4785	* @ofs: offset relative to mtd start
4786	*/
4787	static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
4788	{
4789	int ret;
4790
4791	ret = nand_block_isbad(mtd, offs: ofs);
4792	if (ret) {
4793	/* If it was bad already, return success and do nothing */
4794	if (ret > 0)
4795	return 0;
4796	return ret;
4797	}
4798
4799	return nand_block_markbad_lowlevel(chip: mtd_to_nand(mtd), ofs);
4800	}
4801
4802	/**
4803	* nand_suspend - [MTD Interface] Suspend the NAND flash
4804	* @mtd: MTD device structure
4805	*
4806	* Returns 0 for success or negative error code otherwise.
4807	*/
4808	static int nand_suspend(struct mtd_info *mtd)
4809	{
4810	struct nand_chip *chip = mtd_to_nand(mtd);
4811	int ret = 0;
4812
4813	mutex_lock(&chip->lock);
4814	if (chip->ops.suspend)
4815	ret = chip->ops.suspend(chip);
4816	if (!ret)
4817	chip->suspended = 1;
4818	mutex_unlock(lock: &chip->lock);
4819
4820	return ret;
4821	}
4822
4823	/**
4824	* nand_resume - [MTD Interface] Resume the NAND flash
4825	* @mtd: MTD device structure
4826	*/
4827	static void nand_resume(struct mtd_info *mtd)
4828	{
4829	struct nand_chip *chip = mtd_to_nand(mtd);
4830
4831	mutex_lock(&chip->lock);
4832	if (chip->suspended) {
4833	if (chip->ops.resume)
4834	chip->ops.resume(chip);
4835	chip->suspended = 0;
4836	} else {
4837	pr_err("%s called for a chip which is not in suspended state\n",
4838	__func__);
4839	}
4840	mutex_unlock(lock: &chip->lock);
4841
4842	wake_up_all(&chip->resume_wq);
4843	}
4844
4845	/**
4846	* nand_shutdown - [MTD Interface] Finish the current NAND operation and
4847	* prevent further operations
4848	* @mtd: MTD device structure
4849	*/
4850	static void nand_shutdown(struct mtd_info *mtd)
4851	{
4852	nand_suspend(mtd);
4853	}
4854
4855	/**
4856	* nand_lock - [MTD Interface] Lock the NAND flash
4857	* @mtd: MTD device structure
4858	* @ofs: offset byte address
4859	* @len: number of bytes to lock (must be a multiple of block/page size)
4860	*/
4861	static int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
4862	{
4863	struct nand_chip *chip = mtd_to_nand(mtd);
4864
4865	if (!chip->ops.lock_area)
4866	return -ENOTSUPP;
4867
4868	return chip->ops.lock_area(chip, ofs, len);
4869	}
4870
4871	/**
4872	* nand_unlock - [MTD Interface] Unlock the NAND flash
4873	* @mtd: MTD device structure
4874	* @ofs: offset byte address
4875	* @len: number of bytes to unlock (must be a multiple of block/page size)
4876	*/
4877	static int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
4878	{
4879	struct nand_chip *chip = mtd_to_nand(mtd);
4880
4881	if (!chip->ops.unlock_area)
4882	return -ENOTSUPP;
4883
4884	return chip->ops.unlock_area(chip, ofs, len);
4885	}
4886
4887	/* Set default functions */
4888	static void nand_set_defaults(struct nand_chip *chip)
4889	{
4890	/* If no controller is provided, use the dummy, legacy one. */
4891	if (!chip->controller) {
4892	chip->controller = &chip->legacy.dummy_controller;
4893	nand_controller_init(nfc: chip->controller);
4894	}
4895
4896	nand_legacy_set_defaults(chip);
4897
4898	if (!chip->buf_align)
4899	chip->buf_align = 1;
4900	}
4901
4902	/* Sanitize ONFI strings so we can safely print them */
4903	void sanitize_string(uint8_t *s, size_t len)
4904	{
4905	ssize_t i;
4906
4907	/* Null terminate */
4908	s[len - 1] = 0;
4909
4910	/* Remove non printable chars */
4911	for (i = 0; i < len - 1; i++) {
4912	if (s[i] < ' ' || s[i] > 127)
4913	s[i] = '?';
4914	}
4915
4916	/* Remove trailing spaces */
4917	strim(s);
4918	}
4919
4920	/*
4921	* nand_id_has_period - Check if an ID string has a given wraparound period
4922	* @id_data: the ID string
4923	* @arrlen: the length of the @id_data array
4924	* @period: the period of repitition
4925	*
4926	* Check if an ID string is repeated within a given sequence of bytes at
4927	* specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
4928	* period of 3). This is a helper function for nand_id_len(). Returns non-zero
4929	* if the repetition has a period of @period; otherwise, returns zero.
4930	*/
4931	static int nand_id_has_period(u8 *id_data, int arrlen, int period)
4932	{
4933	int i, j;
4934	for (i = 0; i < period; i++)
4935	for (j = i + period; j < arrlen; j += period)
4936	if (id_data[i] != id_data[j])
4937	return 0;
4938	return 1;
4939	}
4940
4941	/*
4942	* nand_id_len - Get the length of an ID string returned by CMD_READID
4943	* @id_data: the ID string
4944	* @arrlen: the length of the @id_data array
4945
4946	* Returns the length of the ID string, according to known wraparound/trailing
4947	* zero patterns. If no pattern exists, returns the length of the array.
4948	*/
4949	static int nand_id_len(u8 *id_data, int arrlen)
4950	{
4951	int last_nonzero, period;
4952
4953	/* Find last non-zero byte */
4954	for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
4955	if (id_data[last_nonzero])
4956	break;
4957
4958	/* All zeros */
4959	if (last_nonzero < 0)
4960	return 0;
4961
4962	/* Calculate wraparound period */
4963	for (period = 1; period < arrlen; period++)
4964	if (nand_id_has_period(id_data, arrlen, period))
4965	break;
4966
4967	/* There's a repeated pattern */
4968	if (period < arrlen)
4969	return period;
4970
4971	/* There are trailing zeros */
4972	if (last_nonzero < arrlen - 1)
4973	return last_nonzero + 1;
4974
4975	/* No pattern detected */
4976	return arrlen;
4977	}
4978
4979	/* Extract the bits of per cell from the 3rd byte of the extended ID */
4980	static int nand_get_bits_per_cell(u8 cellinfo)
4981	{
4982	int bits;
4983
4984	bits = cellinfo & NAND_CI_CELLTYPE_MSK;
4985	bits >>= NAND_CI_CELLTYPE_SHIFT;
4986	return bits + 1;
4987	}
4988
4989	/*
4990	* Many new NAND share similar device ID codes, which represent the size of the
4991	* chip. The rest of the parameters must be decoded according to generic or
4992	* manufacturer-specific "extended ID" decoding patterns.
4993	*/
4994	void nand_decode_ext_id(struct nand_chip *chip)
4995	{
4996	struct nand_memory_organization *memorg;
4997	struct mtd_info *mtd = nand_to_mtd(chip);
4998	int extid;
4999	u8 *id_data = chip->id.data;
5000
5001	memorg = nanddev_get_memorg(nand: &chip->base);
5002
5003	/* The 3rd id byte holds MLC / multichip data */
5004	memorg->bits_per_cell = nand_get_bits_per_cell(cellinfo: id_data[2]);
5005	/* The 4th id byte is the important one */
5006	extid = id_data[3];
5007
5008	/* Calc pagesize */
5009	memorg->pagesize = 1024 << (extid & 0x03);
5010	mtd->writesize = memorg->pagesize;
5011	extid >>= 2;
5012	/* Calc oobsize */
5013	memorg->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
5014	mtd->oobsize = memorg->oobsize;
5015	extid >>= 2;
5016	/* Calc blocksize. Blocksize is multiples of 64KiB */
5017	memorg->pages_per_eraseblock = ((64 * 1024) << (extid & 0x03)) /
5018	memorg->pagesize;
5019	mtd->erasesize = (64 * 1024) << (extid & 0x03);
5020	extid >>= 2;
5021	/* Get buswidth information */
5022	if (extid & 0x1)
5023	chip->options |= NAND_BUSWIDTH_16;
5024	}
5025	EXPORT_SYMBOL_GPL(nand_decode_ext_id);
5026
5027	/*
5028	* Old devices have chip data hardcoded in the device ID table. nand_decode_id
5029	* decodes a matching ID table entry and assigns the MTD size parameters for
5030	* the chip.
5031	*/
5032	static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type)
5033	{
5034	struct mtd_info *mtd = nand_to_mtd(chip);
5035	struct nand_memory_organization *memorg;
5036
5037	memorg = nanddev_get_memorg(nand: &chip->base);
5038
5039	memorg->pages_per_eraseblock = type->erasesize / type->pagesize;
5040	mtd->erasesize = type->erasesize;
5041	memorg->pagesize = type->pagesize;
5042	mtd->writesize = memorg->pagesize;
5043	memorg->oobsize = memorg->pagesize / 32;
5044	mtd->oobsize = memorg->oobsize;
5045
5046	/* All legacy ID NAND are small-page, SLC */
5047	memorg->bits_per_cell = 1;
5048	}
5049
5050	/*
5051	* Set the bad block marker/indicator (BBM/BBI) patterns according to some
5052	* heuristic patterns using various detected parameters (e.g., manufacturer,
5053	* page size, cell-type information).
5054	*/
5055	static void nand_decode_bbm_options(struct nand_chip *chip)
5056	{
5057	struct mtd_info *mtd = nand_to_mtd(chip);
5058
5059	/* Set the bad block position */
5060	if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
5061	chip->badblockpos = NAND_BBM_POS_LARGE;
5062	else
5063	chip->badblockpos = NAND_BBM_POS_SMALL;
5064	}
5065
5066	static inline bool is_full_id_nand(struct nand_flash_dev *type)
5067	{
5068	return type->id_len;
5069	}
5070
5071	static bool find_full_id_nand(struct nand_chip *chip,
5072	struct nand_flash_dev *type)
5073	{
5074	struct nand_device *base = &chip->base;
5075	struct nand_ecc_props requirements;
5076	struct mtd_info *mtd = nand_to_mtd(chip);
5077	struct nand_memory_organization *memorg;
5078	u8 *id_data = chip->id.data;
5079
5080	memorg = nanddev_get_memorg(nand: &chip->base);
5081
5082	if (!strncmp(type->id, id_data, type->id_len)) {
5083	memorg->pagesize = type->pagesize;
5084	mtd->writesize = memorg->pagesize;
5085	memorg->pages_per_eraseblock = type->erasesize /
5086	type->pagesize;
5087	mtd->erasesize = type->erasesize;
5088	memorg->oobsize = type->oobsize;
5089	mtd->oobsize = memorg->oobsize;
5090
5091	memorg->bits_per_cell = nand_get_bits_per_cell(cellinfo: id_data[2]);
5092	memorg->eraseblocks_per_lun =
5093	DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,
5094	memorg->pagesize *
5095	memorg->pages_per_eraseblock);
5096	chip->options |= type->options;
5097	requirements.strength = NAND_ECC_STRENGTH(type);
5098	requirements.step_size = NAND_ECC_STEP(type);
5099	nanddev_set_ecc_requirements(nand: base, reqs: &requirements);
5100
5101	chip->parameters.model = kstrdup(s: type->name, GFP_KERNEL);
5102	if (!chip->parameters.model)
5103	return false;
5104
5105	return true;
5106	}
5107	return false;
5108	}
5109
5110	/*
5111	* Manufacturer detection. Only used when the NAND is not ONFI or JEDEC
5112	* compliant and does not have a full-id or legacy-id entry in the nand_ids
5113	* table.
5114	*/
5115	static void nand_manufacturer_detect(struct nand_chip *chip)
5116	{
5117	/*
5118	* Try manufacturer detection if available and use
5119	* nand_decode_ext_id() otherwise.
5120	*/
5121	if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
5122	chip->manufacturer.desc->ops->detect) {
5123	struct nand_memory_organization *memorg;
5124
5125	memorg = nanddev_get_memorg(nand: &chip->base);
5126
5127	/* The 3rd id byte holds MLC / multichip data */
5128	memorg->bits_per_cell = nand_get_bits_per_cell(cellinfo: chip->id.data[2]);
5129	chip->manufacturer.desc->ops->detect(chip);
5130	} else {
5131	nand_decode_ext_id(chip);
5132	}
5133	}
5134
5135	/*
5136	* Manufacturer initialization. This function is called for all NANDs including
5137	* ONFI and JEDEC compliant ones.
5138	* Manufacturer drivers should put all their specific initialization code in
5139	* their ->init() hook.
5140	*/
5141	static int nand_manufacturer_init(struct nand_chip *chip)
5142	{
5143	if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops ||
5144	!chip->manufacturer.desc->ops->init)
5145	return 0;
5146
5147	return chip->manufacturer.desc->ops->init(chip);
5148	}
5149
5150	/*
5151	* Manufacturer cleanup. This function is called for all NANDs including
5152	* ONFI and JEDEC compliant ones.
5153	* Manufacturer drivers should put all their specific cleanup code in their
5154	* ->cleanup() hook.
5155	*/
5156	static void nand_manufacturer_cleanup(struct nand_chip *chip)
5157	{
5158	/* Release manufacturer private data */
5159	if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&
5160	chip->manufacturer.desc->ops->cleanup)
5161	chip->manufacturer.desc->ops->cleanup(chip);
5162	}
5163
5164	static const char *
5165	nand_manufacturer_name(const struct nand_manufacturer_desc *manufacturer_desc)
5166	{
5167	return manufacturer_desc ? manufacturer_desc->name : "Unknown";
5168	}
5169
5170	static void rawnand_check_data_only_read_support(struct nand_chip *chip)
5171	{
5172	/* Use an arbitrary size for the check */
5173	if (!nand_read_data_op(chip, NULL, SZ_512, true, true))
5174	chip->controller->supported_op.data_only_read = 1;
5175	}
5176
5177	static void rawnand_early_check_supported_ops(struct nand_chip *chip)
5178	{
5179	/* The supported_op fields should not be set by individual drivers */
5180	WARN_ON_ONCE(chip->controller->supported_op.data_only_read);
5181
5182	if (!nand_has_exec_op(chip))
5183	return;
5184
5185	rawnand_check_data_only_read_support(chip);
5186	}
5187
5188	static void rawnand_check_cont_read_support(struct nand_chip *chip)
5189	{
5190	struct mtd_info *mtd = nand_to_mtd(chip);
5191
5192	if (!chip->parameters.supports_read_cache)
5193	return;
5194
5195	if (chip->read_retries)
5196	return;
5197
5198	if (!nand_lp_exec_cont_read_page_op(chip, page: 0, offset_in_page: 0, NULL,
5199	len: mtd->writesize, check_only: true))
5200	chip->controller->supported_op.cont_read = 1;
5201	}
5202
5203	static void rawnand_late_check_supported_ops(struct nand_chip *chip)
5204	{
5205	/* The supported_op fields should not be set by individual drivers */
5206	WARN_ON_ONCE(chip->controller->supported_op.cont_read);
5207
5208	/*
5209	* Too many devices do not support sequential cached reads with on-die
5210	* ECC correction enabled, so in this case refuse to perform the
5211	* automation.
5212	*/
5213	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE)
5214	return;
5215
5216	if (!nand_has_exec_op(chip))
5217	return;
5218
5219	/*
5220	* For now, continuous reads can only be used with the core page helpers.
5221	* This can be extended later.
5222	*/
5223	if (!(chip->ecc.read_page == nand_read_page_hwecc ||
5224	chip->ecc.read_page == nand_read_page_syndrome ||
5225	chip->ecc.read_page == nand_read_page_swecc))
5226	return;
5227
5228	rawnand_check_cont_read_support(chip);
5229	}
5230
5231	/*
5232	* Get the flash and manufacturer id and lookup if the type is supported.
5233	*/
5234	static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
5235	{
5236	const struct nand_manufacturer_desc *manufacturer_desc;
5237	struct mtd_info *mtd = nand_to_mtd(chip);
5238	struct nand_memory_organization *memorg;
5239	int busw, ret;
5240	u8 *id_data = chip->id.data;
5241	u8 maf_id, dev_id;
5242	u64 targetsize;
5243
5244	/*
5245	* Let's start by initializing memorg fields that might be left
5246	* unassigned by the ID-based detection logic.
5247	*/
5248	memorg = nanddev_get_memorg(nand: &chip->base);
5249	memorg->planes_per_lun = 1;
5250	memorg->luns_per_target = 1;
5251
5252	/*
5253	* Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
5254	* after power-up.
5255	*/
5256	ret = nand_reset(chip, 0);
5257	if (ret)
5258	return ret;
5259
5260	/* Select the device */
5261	nand_select_target(chip, 0);
5262
5263	rawnand_early_check_supported_ops(chip);
5264
5265	/* Send the command for reading device ID */
5266	ret = nand_readid_op(chip, 0, id_data, 2);
5267	if (ret)
5268	return ret;
5269
5270	/* Read manufacturer and device IDs */
5271	maf_id = id_data[0];
5272	dev_id = id_data[1];
5273
5274	/*
5275	* Try again to make sure, as some systems the bus-hold or other
5276	* interface concerns can cause random data which looks like a
5277	* possibly credible NAND flash to appear. If the two results do
5278	* not match, ignore the device completely.
5279	*/
5280
5281	/* Read entire ID string */
5282	ret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data));
5283	if (ret)
5284	return ret;
5285
5286	if (id_data[0] != maf_id || id_data[1] != dev_id) {
5287	pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
5288	maf_id, dev_id, id_data[0], id_data[1]);
5289	return -ENODEV;
5290	}
5291
5292	chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data));
5293
5294	/* Try to identify manufacturer */
5295	manufacturer_desc = nand_get_manufacturer_desc(id: maf_id);
5296	chip->manufacturer.desc = manufacturer_desc;
5297
5298	if (!type)
5299	type = nand_flash_ids;
5300
5301	/*
5302	* Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic
5303	* override it.
5304	* This is required to make sure initial NAND bus width set by the
5305	* NAND controller driver is coherent with the real NAND bus width
5306	* (extracted by auto-detection code).
5307	*/
5308	busw = chip->options & NAND_BUSWIDTH_16;
5309
5310	/*
5311	* The flag is only set (never cleared), reset it to its default value
5312	* before starting auto-detection.
5313	*/
5314	chip->options &= ~NAND_BUSWIDTH_16;
5315
5316	for (; type->name != NULL; type++) {
5317	if (is_full_id_nand(type)) {
5318	if (find_full_id_nand(chip, type))
5319	goto ident_done;
5320	} else if (dev_id == type->dev_id) {
5321	break;
5322	}
5323	}
5324
5325	if (!type->name || !type->pagesize) {
5326	/* Check if the chip is ONFI compliant */
5327	ret = nand_onfi_detect(chip);
5328	if (ret < 0)
5329	return ret;
5330	else if (ret)
5331	goto ident_done;
5332
5333	/* Check if the chip is JEDEC compliant */
5334	ret = nand_jedec_detect(chip);
5335	if (ret < 0)
5336	return ret;
5337	else if (ret)
5338	goto ident_done;
5339	}
5340
5341	if (!type->name)
5342	return -ENODEV;
5343
5344	chip->parameters.model = kstrdup(s: type->name, GFP_KERNEL);
5345	if (!chip->parameters.model)
5346	return -ENOMEM;
5347
5348	if (!type->pagesize)
5349	nand_manufacturer_detect(chip);
5350	else
5351	nand_decode_id(chip, type);
5352
5353	/* Get chip options */
5354	chip->options |= type->options;
5355
5356	memorg->eraseblocks_per_lun =
5357	DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,
5358	memorg->pagesize *
5359	memorg->pages_per_eraseblock);
5360
5361	ident_done:
5362	if (!mtd->name)
5363	mtd->name = chip->parameters.model;
5364
5365	if (chip->options & NAND_BUSWIDTH_AUTO) {
5366	WARN_ON(busw & NAND_BUSWIDTH_16);
5367	nand_set_defaults(chip);
5368	} else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
5369	/*
5370	* Check, if buswidth is correct. Hardware drivers should set
5371	* chip correct!
5372	*/
5373	pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
5374	maf_id, dev_id);
5375	pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc),
5376	mtd->name);
5377	pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8,
5378	(chip->options & NAND_BUSWIDTH_16) ? 16 : 8);
5379	ret = -EINVAL;
5380
5381	goto free_detect_allocation;
5382	}
5383
5384	nand_decode_bbm_options(chip);
5385
5386	/* Calculate the address shift from the page size */
5387	chip->page_shift = ffs(mtd->writesize) - 1;
5388	/* Convert chipsize to number of pages per chip -1 */
5389	targetsize = nanddev_target_size(nand: &chip->base);
5390	chip->pagemask = (targetsize >> chip->page_shift) - 1;
5391
5392	chip->bbt_erase_shift = chip->phys_erase_shift =
5393	ffs(mtd->erasesize) - 1;
5394	if (targetsize & 0xffffffff)
5395	chip->chip_shift = ffs((unsigned)targetsize) - 1;
5396	else {
5397	chip->chip_shift = ffs((unsigned)(targetsize >> 32));
5398	chip->chip_shift += 32 - 1;
5399	}
5400
5401	if (chip->chip_shift - chip->page_shift > 16)
5402	chip->options |= NAND_ROW_ADDR_3;
5403
5404	chip->badblockbits = 8;
5405
5406	nand_legacy_adjust_cmdfunc(chip);
5407
5408	pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
5409	maf_id, dev_id);
5410	pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc),
5411	chip->parameters.model);
5412	pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
5413	(int)(targetsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
5414	mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
5415	return 0;
5416
5417	free_detect_allocation:
5418	kfree(objp: chip->parameters.model);
5419
5420	return ret;
5421	}
5422
5423	static enum nand_ecc_engine_type
5424	of_get_rawnand_ecc_engine_type_legacy(struct device_node *np)
5425	{
5426	enum nand_ecc_legacy_mode {
5427	NAND_ECC_INVALID,
5428	NAND_ECC_NONE,
5429	NAND_ECC_SOFT,
5430	NAND_ECC_SOFT_BCH,
5431	NAND_ECC_HW,
5432	NAND_ECC_HW_SYNDROME,
5433	NAND_ECC_ON_DIE,
5434	};
5435	const char * const nand_ecc_legacy_modes[] = {
5436	[NAND_ECC_NONE] = "none",
5437	[NAND_ECC_SOFT] = "soft",
5438	[NAND_ECC_SOFT_BCH] = "soft_bch",
5439	[NAND_ECC_HW] = "hw",
5440	[NAND_ECC_HW_SYNDROME] = "hw_syndrome",
5441	[NAND_ECC_ON_DIE] = "on-die",
5442	};
5443	enum nand_ecc_legacy_mode eng_type;
5444	const char *pm;
5445	int err;
5446
5447	err = of_property_read_string(np, propname: "nand-ecc-mode", out_string: &pm);
5448	if (err)
5449	return NAND_ECC_ENGINE_TYPE_INVALID;
5450
5451	for (eng_type = NAND_ECC_NONE;
5452	eng_type < ARRAY_SIZE(nand_ecc_legacy_modes); eng_type++) {
5453	if (!strcasecmp(s1: pm, s2: nand_ecc_legacy_modes[eng_type])) {
5454	switch (eng_type) {
5455	case NAND_ECC_NONE:
5456	return NAND_ECC_ENGINE_TYPE_NONE;
5457	case NAND_ECC_SOFT:
5458	case NAND_ECC_SOFT_BCH:
5459	return NAND_ECC_ENGINE_TYPE_SOFT;
5460	case NAND_ECC_HW:
5461	case NAND_ECC_HW_SYNDROME:
5462	return NAND_ECC_ENGINE_TYPE_ON_HOST;
5463	case NAND_ECC_ON_DIE:
5464	return NAND_ECC_ENGINE_TYPE_ON_DIE;
5465	default:
5466	break;
5467	}
5468	}
5469	}
5470
5471	return NAND_ECC_ENGINE_TYPE_INVALID;
5472	}
5473
5474	static enum nand_ecc_placement
5475	of_get_rawnand_ecc_placement_legacy(struct device_node *np)
5476	{
5477	const char *pm;
5478	int err;
5479
5480	err = of_property_read_string(np, propname: "nand-ecc-mode", out_string: &pm);
5481	if (!err) {
5482	if (!strcasecmp(s1: pm, s2: "hw_syndrome"))
5483	return NAND_ECC_PLACEMENT_INTERLEAVED;
5484	}
5485
5486	return NAND_ECC_PLACEMENT_UNKNOWN;
5487	}
5488
5489	static enum nand_ecc_algo of_get_rawnand_ecc_algo_legacy(struct device_node *np)
5490	{
5491	const char *pm;
5492	int err;
5493
5494	err = of_property_read_string(np, propname: "nand-ecc-mode", out_string: &pm);
5495	if (!err) {
5496	if (!strcasecmp(s1: pm, s2: "soft"))
5497	return NAND_ECC_ALGO_HAMMING;
5498	else if (!strcasecmp(s1: pm, s2: "soft_bch"))
5499	return NAND_ECC_ALGO_BCH;
5500	}
5501
5502	return NAND_ECC_ALGO_UNKNOWN;
5503	}
5504
5505	static void of_get_nand_ecc_legacy_user_config(struct nand_chip *chip)
5506	{
5507	struct device_node *dn = nand_get_flash_node(chip);
5508	struct nand_ecc_props *user_conf = &chip->base.ecc.user_conf;
5509
5510	if (user_conf->engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
5511	user_conf->engine_type = of_get_rawnand_ecc_engine_type_legacy(np: dn);
5512
5513	if (user_conf->algo == NAND_ECC_ALGO_UNKNOWN)
5514	user_conf->algo = of_get_rawnand_ecc_algo_legacy(np: dn);
5515
5516	if (user_conf->placement == NAND_ECC_PLACEMENT_UNKNOWN)
5517	user_conf->placement = of_get_rawnand_ecc_placement_legacy(np: dn);
5518	}
5519
5520	static int of_get_nand_bus_width(struct nand_chip *chip)
5521	{
5522	struct device_node *dn = nand_get_flash_node(chip);
5523	u32 val;
5524	int ret;
5525
5526	ret = of_property_read_u32(np: dn, propname: "nand-bus-width", out_value: &val);
5527	if (ret == -EINVAL)
5528	/* Buswidth defaults to 8 if the property does not exist .*/
5529	return 0;
5530	else if (ret)
5531	return ret;
5532
5533	if (val == 16)
5534	chip->options |= NAND_BUSWIDTH_16;
5535	else if (val != 8)
5536	return -EINVAL;
5537	return 0;
5538	}
5539
5540	static int of_get_nand_secure_regions(struct nand_chip *chip)
5541	{
5542	struct device_node *dn = nand_get_flash_node(chip);
5543	struct property *prop;
5544	int nr_elem, i, j;
5545
5546	/* Only proceed if the "secure-regions" property is present in DT */
5547	prop = of_find_property(np: dn, name: "secure-regions", NULL);
5548	if (!prop)
5549	return 0;
5550
5551	nr_elem = of_property_count_elems_of_size(np: dn, propname: "secure-regions", elem_size: sizeof(u64));
5552	if (nr_elem <= 0)
5553	return nr_elem;
5554
5555	chip->nr_secure_regions = nr_elem / 2;
5556	chip->secure_regions = kcalloc(n: chip->nr_secure_regions, size: sizeof(*chip->secure_regions),
5557	GFP_KERNEL);
5558	if (!chip->secure_regions)
5559	return -ENOMEM;
5560
5561	for (i = 0, j = 0; i < chip->nr_secure_regions; i++, j += 2) {
5562	of_property_read_u64_index(np: dn, propname: "secure-regions", index: j,
5563	out_value: &chip->secure_regions[i].offset);
5564	of_property_read_u64_index(np: dn, propname: "secure-regions", index: j + 1,
5565	out_value: &chip->secure_regions[i].size);
5566	}
5567
5568	return 0;
5569	}
5570
5571	/**
5572	* rawnand_dt_parse_gpio_cs - Parse the gpio-cs property of a controller
5573	* @dev: Device that will be parsed. Also used for managed allocations.
5574	* @cs_array: Array of GPIO desc pointers allocated on success
5575	* @ncs_array: Number of entries in @cs_array updated on success.
5576	* @return 0 on success, an error otherwise.
5577	*/
5578	int rawnand_dt_parse_gpio_cs(struct device *dev, struct gpio_desc ***cs_array,
5579	unsigned int *ncs_array)
5580	{
5581	struct gpio_desc **descs;
5582	int ndescs, i;
5583
5584	ndescs = gpiod_count(dev, con_id: "cs");
5585	if (ndescs < 0) {
5586	dev_dbg(dev, "No valid cs-gpios property\n");
5587	return 0;
5588	}
5589
5590	descs = devm_kcalloc(dev, n: ndescs, size: sizeof(*descs), GFP_KERNEL);
5591	if (!descs)
5592	return -ENOMEM;
5593
5594	for (i = 0; i < ndescs; i++) {
5595	descs[i] = gpiod_get_index_optional(dev, con_id: "cs", index: i,
5596	flags: GPIOD_OUT_HIGH);
5597	if (IS_ERR(ptr: descs[i]))
5598	return PTR_ERR(ptr: descs[i]);
5599	}
5600
5601	*ncs_array = ndescs;
5602	*cs_array = descs;
5603
5604	return 0;
5605	}
5606	EXPORT_SYMBOL(rawnand_dt_parse_gpio_cs);
5607
5608	static int rawnand_dt_init(struct nand_chip *chip)
5609	{
5610	struct nand_device *nand = mtd_to_nanddev(mtd: nand_to_mtd(chip));
5611	struct device_node *dn = nand_get_flash_node(chip);
5612	int ret;
5613
5614	if (!dn)
5615	return 0;
5616
5617	ret = of_get_nand_bus_width(chip);
5618	if (ret)
5619	return ret;
5620
5621	if (of_property_read_bool(np: dn, propname: "nand-is-boot-medium"))
5622	chip->options |= NAND_IS_BOOT_MEDIUM;
5623
5624	if (of_property_read_bool(np: dn, propname: "nand-on-flash-bbt"))
5625	chip->bbt_options |= NAND_BBT_USE_FLASH;
5626
5627	of_get_nand_ecc_user_config(nand);
5628	of_get_nand_ecc_legacy_user_config(chip);
5629
5630	/*
5631	* If neither the user nor the NAND controller have requested a specific
5632	* ECC engine type, we will default to NAND_ECC_ENGINE_TYPE_ON_HOST.
5633	*/
5634	nand->ecc.defaults.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
5635
5636	/*
5637	* Use the user requested engine type, unless there is none, in this
5638	* case default to the NAND controller choice, otherwise fallback to
5639	* the raw NAND default one.
5640	*/
5641	if (nand->ecc.user_conf.engine_type != NAND_ECC_ENGINE_TYPE_INVALID)
5642	chip->ecc.engine_type = nand->ecc.user_conf.engine_type;
5643	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
5644	chip->ecc.engine_type = nand->ecc.defaults.engine_type;
5645
5646	chip->ecc.placement = nand->ecc.user_conf.placement;
5647	chip->ecc.algo = nand->ecc.user_conf.algo;
5648	chip->ecc.strength = nand->ecc.user_conf.strength;
5649	chip->ecc.size = nand->ecc.user_conf.step_size;
5650
5651	return 0;
5652	}
5653
5654	/**
5655	* nand_scan_ident - Scan for the NAND device
5656	* @chip: NAND chip object
5657	* @maxchips: number of chips to scan for
5658	* @table: alternative NAND ID table
5659	*
5660	* This is the first phase of the normal nand_scan() function. It reads the
5661	* flash ID and sets up MTD fields accordingly.
5662	*
5663	* This helper used to be called directly from controller drivers that needed
5664	* to tweak some ECC-related parameters before nand_scan_tail(). This separation
5665	* prevented dynamic allocations during this phase which was unconvenient and
5666	* as been banned for the benefit of the ->init_ecc()/cleanup_ecc() hooks.
5667	*/
5668	static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips,
5669	struct nand_flash_dev *table)
5670	{
5671	struct mtd_info *mtd = nand_to_mtd(chip);
5672	struct nand_memory_organization *memorg;
5673	int nand_maf_id, nand_dev_id;
5674	unsigned int i;
5675	int ret;
5676
5677	memorg = nanddev_get_memorg(nand: &chip->base);
5678
5679	/* Assume all dies are deselected when we enter nand_scan_ident(). */
5680	chip->cur_cs = -1;
5681
5682	mutex_init(&chip->lock);
5683	init_waitqueue_head(&chip->resume_wq);
5684
5685	/* Enforce the right timings for reset/detection */
5686	chip->current_interface_config = nand_get_reset_interface_config();
5687
5688	ret = rawnand_dt_init(chip);
5689	if (ret)
5690	return ret;
5691
5692	if (!mtd->name && mtd->dev.parent)
5693	mtd->name = dev_name(dev: mtd->dev.parent);
5694
5695	/* Set the default functions */
5696	nand_set_defaults(chip);
5697
5698	ret = nand_legacy_check_hooks(chip);
5699	if (ret)
5700	return ret;
5701
5702	memorg->ntargets = maxchips;
5703
5704	/* Read the flash type */
5705	ret = nand_detect(chip, type: table);
5706	if (ret) {
5707	if (!(chip->options & NAND_SCAN_SILENT_NODEV))
5708	pr_warn("No NAND device found\n");
5709	nand_deselect_target(chip);
5710	return ret;
5711	}
5712
5713	nand_maf_id = chip->id.data[0];
5714	nand_dev_id = chip->id.data[1];
5715
5716	nand_deselect_target(chip);
5717
5718	/* Check for a chip array */
5719	for (i = 1; i < maxchips; i++) {
5720	u8 id[2];
5721
5722	/* See comment in nand_get_flash_type for reset */
5723	ret = nand_reset(chip, i);
5724	if (ret)
5725	break;
5726
5727	nand_select_target(chip, i);
5728	/* Send the command for reading device ID */
5729	ret = nand_readid_op(chip, 0, id, sizeof(id));
5730	if (ret)
5731	break;
5732	/* Read manufacturer and device IDs */
5733	if (nand_maf_id != id[0] || nand_dev_id != id[1]) {
5734	nand_deselect_target(chip);
5735	break;
5736	}
5737	nand_deselect_target(chip);
5738	}
5739	if (i > 1)
5740	pr_info("%d chips detected\n", i);
5741
5742	/* Store the number of chips and calc total size for mtd */
5743	memorg->ntargets = i;
5744	mtd->size = i * nanddev_target_size(nand: &chip->base);
5745
5746	return 0;
5747	}
5748
5749	static void nand_scan_ident_cleanup(struct nand_chip *chip)
5750	{
5751	kfree(objp: chip->parameters.model);
5752	kfree(objp: chip->parameters.onfi);
5753	}
5754
5755	int rawnand_sw_hamming_init(struct nand_chip *chip)
5756	{
5757	struct nand_ecc_sw_hamming_conf *engine_conf;
5758	struct nand_device *base = &chip->base;
5759	int ret;
5760
5761	base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
5762	base->ecc.user_conf.algo = NAND_ECC_ALGO_HAMMING;
5763	base->ecc.user_conf.strength = chip->ecc.strength;
5764	base->ecc.user_conf.step_size = chip->ecc.size;
5765
5766	ret = nand_ecc_sw_hamming_init_ctx(nand: base);
5767	if (ret)
5768	return ret;
5769
5770	engine_conf = base->ecc.ctx.priv;
5771
5772	if (chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER)
5773	engine_conf->sm_order = true;
5774
5775	chip->ecc.size = base->ecc.ctx.conf.step_size;
5776	chip->ecc.strength = base->ecc.ctx.conf.strength;
5777	chip->ecc.total = base->ecc.ctx.total;
5778	chip->ecc.steps = nanddev_get_ecc_nsteps(nand: base);
5779	chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(nand: base);
5780
5781	return 0;
5782	}
5783	EXPORT_SYMBOL(rawnand_sw_hamming_init);
5784
5785	int rawnand_sw_hamming_calculate(struct nand_chip *chip,
5786	const unsigned char *buf,
5787	unsigned char *code)
5788	{
5789	struct nand_device *base = &chip->base;
5790
5791	return nand_ecc_sw_hamming_calculate(nand: base, buf, code);
5792	}
5793	EXPORT_SYMBOL(rawnand_sw_hamming_calculate);
5794
5795	int rawnand_sw_hamming_correct(struct nand_chip *chip,
5796	unsigned char *buf,
5797	unsigned char *read_ecc,
5798	unsigned char *calc_ecc)
5799	{
5800	struct nand_device *base = &chip->base;
5801
5802	return nand_ecc_sw_hamming_correct(nand: base, buf, read_ecc, calc_ecc);
5803	}
5804	EXPORT_SYMBOL(rawnand_sw_hamming_correct);
5805
5806	void rawnand_sw_hamming_cleanup(struct nand_chip *chip)
5807	{
5808	struct nand_device *base = &chip->base;
5809
5810	nand_ecc_sw_hamming_cleanup_ctx(nand: base);
5811	}
5812	EXPORT_SYMBOL(rawnand_sw_hamming_cleanup);
5813
5814	int rawnand_sw_bch_init(struct nand_chip *chip)
5815	{
5816	struct nand_device *base = &chip->base;
5817	const struct nand_ecc_props *ecc_conf = nanddev_get_ecc_conf(nand: base);
5818	int ret;
5819
5820	base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
5821	base->ecc.user_conf.algo = NAND_ECC_ALGO_BCH;
5822	base->ecc.user_conf.step_size = chip->ecc.size;
5823	base->ecc.user_conf.strength = chip->ecc.strength;
5824
5825	ret = nand_ecc_sw_bch_init_ctx(nand: base);
5826	if (ret)
5827	return ret;
5828
5829	chip->ecc.size = ecc_conf->step_size;
5830	chip->ecc.strength = ecc_conf->strength;
5831	chip->ecc.total = base->ecc.ctx.total;
5832	chip->ecc.steps = nanddev_get_ecc_nsteps(nand: base);
5833	chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(nand: base);
5834
5835	return 0;
5836	}
5837	EXPORT_SYMBOL(rawnand_sw_bch_init);
5838
5839	static int rawnand_sw_bch_calculate(struct nand_chip *chip,
5840	const unsigned char *buf,
5841	unsigned char *code)
5842	{
5843	struct nand_device *base = &chip->base;
5844
5845	return nand_ecc_sw_bch_calculate(nand: base, buf, code);
5846	}
5847
5848	int rawnand_sw_bch_correct(struct nand_chip *chip, unsigned char *buf,
5849	unsigned char *read_ecc, unsigned char *calc_ecc)
5850	{
5851	struct nand_device *base = &chip->base;
5852
5853	return nand_ecc_sw_bch_correct(nand: base, buf, read_ecc, calc_ecc);
5854	}
5855	EXPORT_SYMBOL(rawnand_sw_bch_correct);
5856
5857	void rawnand_sw_bch_cleanup(struct nand_chip *chip)
5858	{
5859	struct nand_device *base = &chip->base;
5860
5861	nand_ecc_sw_bch_cleanup_ctx(nand: base);
5862	}
5863	EXPORT_SYMBOL(rawnand_sw_bch_cleanup);
5864
5865	static int nand_set_ecc_on_host_ops(struct nand_chip *chip)
5866	{
5867	struct nand_ecc_ctrl *ecc = &chip->ecc;
5868
5869	switch (ecc->placement) {
5870	case NAND_ECC_PLACEMENT_UNKNOWN:
5871	case NAND_ECC_PLACEMENT_OOB:
5872	/* Use standard hwecc read page function? */
5873	if (!ecc->read_page)
5874	ecc->read_page = nand_read_page_hwecc;
5875	if (!ecc->write_page)
5876	ecc->write_page = nand_write_page_hwecc;
5877	if (!ecc->read_page_raw)
5878	ecc->read_page_raw = nand_read_page_raw;
5879	if (!ecc->write_page_raw)
5880	ecc->write_page_raw = nand_write_page_raw;
5881	if (!ecc->read_oob)
5882	ecc->read_oob = nand_read_oob_std;
5883	if (!ecc->write_oob)
5884	ecc->write_oob = nand_write_oob_std;
5885	if (!ecc->read_subpage)
5886	ecc->read_subpage = nand_read_subpage;
5887	if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
5888	ecc->write_subpage = nand_write_subpage_hwecc;
5889	fallthrough;
5890
5891	case NAND_ECC_PLACEMENT_INTERLEAVED:
5892	if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
5893	(!ecc->read_page ||
5894	ecc->read_page == nand_read_page_hwecc ||
5895	!ecc->write_page ||
5896	ecc->write_page == nand_write_page_hwecc)) {
5897	WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
5898	return -EINVAL;
5899	}
5900	/* Use standard syndrome read/write page function? */
5901	if (!ecc->read_page)
5902	ecc->read_page = nand_read_page_syndrome;
5903	if (!ecc->write_page)
5904	ecc->write_page = nand_write_page_syndrome;
5905	if (!ecc->read_page_raw)
5906	ecc->read_page_raw = nand_read_page_raw_syndrome;
5907	if (!ecc->write_page_raw)
5908	ecc->write_page_raw = nand_write_page_raw_syndrome;
5909	if (!ecc->read_oob)
5910	ecc->read_oob = nand_read_oob_syndrome;
5911	if (!ecc->write_oob)
5912	ecc->write_oob = nand_write_oob_syndrome;
5913	break;
5914
5915	default:
5916	pr_warn("Invalid NAND_ECC_PLACEMENT %d\n",
5917	ecc->placement);
5918	return -EINVAL;
5919	}
5920
5921	return 0;
5922	}
5923
5924	static int nand_set_ecc_soft_ops(struct nand_chip *chip)
5925	{
5926	struct mtd_info *mtd = nand_to_mtd(chip);
5927	struct nand_device *nanddev = mtd_to_nanddev(mtd);
5928	struct nand_ecc_ctrl *ecc = &chip->ecc;
5929	int ret;
5930
5931	if (WARN_ON(ecc->engine_type != NAND_ECC_ENGINE_TYPE_SOFT))
5932	return -EINVAL;
5933
5934	switch (ecc->algo) {
5935	case NAND_ECC_ALGO_HAMMING:
5936	ecc->calculate = rawnand_sw_hamming_calculate;
5937	ecc->correct = rawnand_sw_hamming_correct;
5938	ecc->read_page = nand_read_page_swecc;
5939	ecc->read_subpage = nand_read_subpage;
5940	ecc->write_page = nand_write_page_swecc;
5941	if (!ecc->read_page_raw)
5942	ecc->read_page_raw = nand_read_page_raw;
5943	if (!ecc->write_page_raw)
5944	ecc->write_page_raw = nand_write_page_raw;
5945	ecc->read_oob = nand_read_oob_std;
5946	ecc->write_oob = nand_write_oob_std;
5947	if (!ecc->size)
5948	ecc->size = 256;
5949	ecc->bytes = 3;
5950	ecc->strength = 1;
5951
5952	if (IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC))
5953	ecc->options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
5954
5955	ret = rawnand_sw_hamming_init(chip);
5956	if (ret) {
5957	WARN(1, "Hamming ECC initialization failed!\n");
5958	return ret;
5959	}
5960
5961	return 0;
5962	case NAND_ECC_ALGO_BCH:
5963	if (!IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_BCH)) {
5964	WARN(1, "CONFIG_MTD_NAND_ECC_SW_BCH not enabled\n");
5965	return -EINVAL;
5966	}
5967	ecc->calculate = rawnand_sw_bch_calculate;
5968	ecc->correct = rawnand_sw_bch_correct;
5969	ecc->read_page = nand_read_page_swecc;
5970	ecc->read_subpage = nand_read_subpage;
5971	ecc->write_page = nand_write_page_swecc;
5972	if (!ecc->read_page_raw)
5973	ecc->read_page_raw = nand_read_page_raw;
5974	if (!ecc->write_page_raw)
5975	ecc->write_page_raw = nand_write_page_raw;
5976	ecc->read_oob = nand_read_oob_std;
5977	ecc->write_oob = nand_write_oob_std;
5978
5979	/*
5980	* We can only maximize ECC config when the default layout is
5981	* used, otherwise we don't know how many bytes can really be
5982	* used.
5983	*/
5984	if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH &&
5985	mtd->ooblayout != nand_get_large_page_ooblayout())
5986	nanddev->ecc.user_conf.flags &= ~NAND_ECC_MAXIMIZE_STRENGTH;
5987
5988	ret = rawnand_sw_bch_init(chip);
5989	if (ret) {
5990	WARN(1, "BCH ECC initialization failed!\n");
5991	return ret;
5992	}
5993
5994	return 0;
5995	default:
5996	WARN(1, "Unsupported ECC algorithm!\n");
5997	return -EINVAL;
5998	}
5999	}
6000
6001	/**
6002	* nand_check_ecc_caps - check the sanity of preset ECC settings
6003	* @chip: nand chip info structure
6004	* @caps: ECC caps info structure
6005	* @oobavail: OOB size that the ECC engine can use
6006	*
6007	* When ECC step size and strength are already set, check if they are supported
6008	* by the controller and the calculated ECC bytes fit within the chip's OOB.
6009	* On success, the calculated ECC bytes is set.
6010	*/
6011	static int
6012	nand_check_ecc_caps(struct nand_chip *chip,
6013	const struct nand_ecc_caps *caps, int oobavail)
6014	{
6015	struct mtd_info *mtd = nand_to_mtd(chip);
6016	const struct nand_ecc_step_info *stepinfo;
6017	int preset_step = chip->ecc.size;
6018	int preset_strength = chip->ecc.strength;
6019	int ecc_bytes, nsteps = mtd->writesize / preset_step;
6020	int i, j;
6021
6022	for (i = 0; i < caps->nstepinfos; i++) {
6023	stepinfo = &caps->stepinfos[i];
6024
6025	if (stepinfo->stepsize != preset_step)
6026	continue;
6027
6028	for (j = 0; j < stepinfo->nstrengths; j++) {
6029	if (stepinfo->strengths[j] != preset_strength)
6030	continue;
6031
6032	ecc_bytes = caps->calc_ecc_bytes(preset_step,
6033	preset_strength);
6034	if (WARN_ON_ONCE(ecc_bytes < 0))
6035	return ecc_bytes;
6036
6037	if (ecc_bytes * nsteps > oobavail) {
6038	pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
6039	preset_step, preset_strength);
6040	return -ENOSPC;
6041	}
6042
6043	chip->ecc.bytes = ecc_bytes;
6044
6045	return 0;
6046	}
6047	}
6048
6049	pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
6050	preset_step, preset_strength);
6051
6052	return -ENOTSUPP;
6053	}
6054
6055	/**
6056	* nand_match_ecc_req - meet the chip's requirement with least ECC bytes
6057	* @chip: nand chip info structure
6058	* @caps: ECC engine caps info structure
6059	* @oobavail: OOB size that the ECC engine can use
6060	*
6061	* If a chip's ECC requirement is provided, try to meet it with the least
6062	* number of ECC bytes (i.e. with the largest number of OOB-free bytes).
6063	* On success, the chosen ECC settings are set.
6064	*/
6065	static int
6066	nand_match_ecc_req(struct nand_chip *chip,
6067	const struct nand_ecc_caps *caps, int oobavail)
6068	{
6069	const struct nand_ecc_props *requirements =
6070	nanddev_get_ecc_requirements(nand: &chip->base);
6071	struct mtd_info *mtd = nand_to_mtd(chip);
6072	const struct nand_ecc_step_info *stepinfo;
6073	int req_step = requirements->step_size;
6074	int req_strength = requirements->strength;
6075	int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
6076	int best_step = 0, best_strength = 0, best_ecc_bytes = 0;
6077	int best_ecc_bytes_total = INT_MAX;
6078	int i, j;
6079
6080	/* No information provided by the NAND chip */
6081	if (!req_step || !req_strength)
6082	return -ENOTSUPP;
6083
6084	/* number of correctable bits the chip requires in a page */
6085	req_corr = mtd->writesize / req_step * req_strength;
6086
6087	for (i = 0; i < caps->nstepinfos; i++) {
6088	stepinfo = &caps->stepinfos[i];
6089	step_size = stepinfo->stepsize;
6090
6091	for (j = 0; j < stepinfo->nstrengths; j++) {
6092	strength = stepinfo->strengths[j];
6093
6094	/*
6095	* If both step size and strength are smaller than the
6096	* chip's requirement, it is not easy to compare the
6097	* resulted reliability.
6098	*/
6099	if (step_size < req_step && strength < req_strength)
6100	continue;
6101
6102	if (mtd->writesize % step_size)
6103	continue;
6104
6105	nsteps = mtd->writesize / step_size;
6106
6107	ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
6108	if (WARN_ON_ONCE(ecc_bytes < 0))
6109	continue;
6110	ecc_bytes_total = ecc_bytes * nsteps;
6111
6112	if (ecc_bytes_total > oobavail ||
6113	strength * nsteps < req_corr)
6114	continue;
6115
6116	/*
6117	* We assume the best is to meet the chip's requrement
6118	* with the least number of ECC bytes.
6119	*/
6120	if (ecc_bytes_total < best_ecc_bytes_total) {
6121	best_ecc_bytes_total = ecc_bytes_total;
6122	best_step = step_size;
6123	best_strength = strength;
6124	best_ecc_bytes = ecc_bytes;
6125	}
6126	}
6127	}
6128
6129	if (best_ecc_bytes_total == INT_MAX)
6130	return -ENOTSUPP;
6131
6132	chip->ecc.size = best_step;
6133	chip->ecc.strength = best_strength;
6134	chip->ecc.bytes = best_ecc_bytes;
6135
6136	return 0;
6137	}
6138
6139	/**
6140	* nand_maximize_ecc - choose the max ECC strength available
6141	* @chip: nand chip info structure
6142	* @caps: ECC engine caps info structure
6143	* @oobavail: OOB size that the ECC engine can use
6144	*
6145	* Choose the max ECC strength that is supported on the controller, and can fit
6146	* within the chip's OOB. On success, the chosen ECC settings are set.
6147	*/
6148	static int
6149	nand_maximize_ecc(struct nand_chip *chip,
6150	const struct nand_ecc_caps *caps, int oobavail)
6151	{
6152	struct mtd_info *mtd = nand_to_mtd(chip);
6153	const struct nand_ecc_step_info *stepinfo;
6154	int step_size, strength, nsteps, ecc_bytes, corr;
6155	int best_corr = 0;
6156	int best_step = 0;
6157	int best_strength = 0, best_ecc_bytes = 0;
6158	int i, j;
6159
6160	for (i = 0; i < caps->nstepinfos; i++) {
6161	stepinfo = &caps->stepinfos[i];
6162	step_size = stepinfo->stepsize;
6163
6164	/* If chip->ecc.size is already set, respect it */
6165	if (chip->ecc.size && step_size != chip->ecc.size)
6166	continue;
6167
6168	for (j = 0; j < stepinfo->nstrengths; j++) {
6169	strength = stepinfo->strengths[j];
6170
6171	if (mtd->writesize % step_size)
6172	continue;
6173
6174	nsteps = mtd->writesize / step_size;
6175
6176	ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
6177	if (WARN_ON_ONCE(ecc_bytes < 0))
6178	continue;
6179
6180	if (ecc_bytes * nsteps > oobavail)
6181	continue;
6182
6183	corr = strength * nsteps;
6184
6185	/*
6186	* If the number of correctable bits is the same,
6187	* bigger step_size has more reliability.
6188	*/
6189	if (corr > best_corr ||
6190	(corr == best_corr && step_size > best_step)) {
6191	best_corr = corr;
6192	best_step = step_size;
6193	best_strength = strength;
6194	best_ecc_bytes = ecc_bytes;
6195	}
6196	}
6197	}
6198
6199	if (!best_corr)
6200	return -ENOTSUPP;
6201
6202	chip->ecc.size = best_step;
6203	chip->ecc.strength = best_strength;
6204	chip->ecc.bytes = best_ecc_bytes;
6205
6206	return 0;
6207	}
6208
6209	/**
6210	* nand_ecc_choose_conf - Set the ECC strength and ECC step size
6211	* @chip: nand chip info structure
6212	* @caps: ECC engine caps info structure
6213	* @oobavail: OOB size that the ECC engine can use
6214	*
6215	* Choose the ECC configuration according to following logic.
6216	*
6217	* 1. If both ECC step size and ECC strength are already set (usually by DT)
6218	* then check if it is supported by this controller.
6219	* 2. If the user provided the nand-ecc-maximize property, then select maximum
6220	* ECC strength.
6221	* 3. Otherwise, try to match the ECC step size and ECC strength closest
6222	* to the chip's requirement. If available OOB size can't fit the chip
6223	* requirement then fallback to the maximum ECC step size and ECC strength.
6224	*
6225	* On success, the chosen ECC settings are set.
6226	*/
6227	int nand_ecc_choose_conf(struct nand_chip *chip,
6228	const struct nand_ecc_caps *caps, int oobavail)
6229	{
6230	struct mtd_info *mtd = nand_to_mtd(chip);
6231	struct nand_device *nanddev = mtd_to_nanddev(mtd);
6232
6233	if (WARN_ON(oobavail < 0 || oobavail > mtd->oobsize))
6234	return -EINVAL;
6235
6236	if (chip->ecc.size && chip->ecc.strength)
6237	return nand_check_ecc_caps(chip, caps, oobavail);
6238
6239	if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH)
6240	return nand_maximize_ecc(chip, caps, oobavail);
6241
6242	if (!nand_match_ecc_req(chip, caps, oobavail))
6243	return 0;
6244
6245	return nand_maximize_ecc(chip, caps, oobavail);
6246	}
6247	EXPORT_SYMBOL_GPL(nand_ecc_choose_conf);
6248
6249	static int rawnand_erase(struct nand_device *nand, const struct nand_pos *pos)
6250	{
6251	struct nand_chip *chip = container_of(nand, struct nand_chip,
6252	base);
6253	unsigned int eb = nanddev_pos_to_row(nand, pos);
6254	int ret;
6255
6256	eb >>= nand->rowconv.eraseblock_addr_shift;
6257
6258	nand_select_target(chip, pos->target);
6259	ret = nand_erase_op(chip, eb);
6260	nand_deselect_target(chip);
6261
6262	return ret;
6263	}
6264
6265	static int rawnand_markbad(struct nand_device *nand,
6266	const struct nand_pos *pos)
6267	{
6268	struct nand_chip *chip = container_of(nand, struct nand_chip,
6269	base);
6270
6271	return nand_markbad_bbm(chip, ofs: nanddev_pos_to_offs(nand, pos));
6272	}
6273
6274	static bool rawnand_isbad(struct nand_device *nand, const struct nand_pos *pos)
6275	{
6276	struct nand_chip *chip = container_of(nand, struct nand_chip,
6277	base);
6278	int ret;
6279
6280	nand_select_target(chip, pos->target);
6281	ret = nand_isbad_bbm(chip, ofs: nanddev_pos_to_offs(nand, pos));
6282	nand_deselect_target(chip);
6283
6284	return ret;
6285	}
6286
6287	static const struct nand_ops rawnand_ops = {
6288	.erase = rawnand_erase,
6289	.markbad = rawnand_markbad,
6290	.isbad = rawnand_isbad,
6291	};
6292
6293	/**
6294	* nand_scan_tail - Scan for the NAND device
6295	* @chip: NAND chip object
6296	*
6297	* This is the second phase of the normal nand_scan() function. It fills out
6298	* all the uninitialized function pointers with the defaults and scans for a
6299	* bad block table if appropriate.
6300	*/
6301	static int nand_scan_tail(struct nand_chip *chip)
6302	{
6303	struct mtd_info *mtd = nand_to_mtd(chip);
6304	struct nand_ecc_ctrl *ecc = &chip->ecc;
6305	int ret, i;
6306
6307	/* New bad blocks should be marked in OOB, flash-based BBT, or both */
6308	if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
6309	!(chip->bbt_options & NAND_BBT_USE_FLASH))) {
6310	return -EINVAL;
6311	}
6312
6313	chip->data_buf = kmalloc(size: mtd->writesize + mtd->oobsize, GFP_KERNEL);
6314	if (!chip->data_buf)
6315	return -ENOMEM;
6316
6317	/*
6318	* FIXME: some NAND manufacturer drivers expect the first die to be
6319	* selected when manufacturer->init() is called. They should be fixed
6320	* to explictly select the relevant die when interacting with the NAND
6321	* chip.
6322	*/
6323	nand_select_target(chip, 0);
6324	ret = nand_manufacturer_init(chip);
6325	nand_deselect_target(chip);
6326	if (ret)
6327	goto err_free_buf;
6328
6329	/* Set the internal oob buffer location, just after the page data */
6330	chip->oob_poi = chip->data_buf + mtd->writesize;
6331
6332	/*
6333	* If no default placement scheme is given, select an appropriate one.
6334	*/
6335	if (!mtd->ooblayout &&
6336	!(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
6337	ecc->algo == NAND_ECC_ALGO_BCH) &&
6338	!(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
6339	ecc->algo == NAND_ECC_ALGO_HAMMING)) {
6340	switch (mtd->oobsize) {
6341	case 8:
6342	case 16:
6343	mtd_set_ooblayout(mtd, ooblayout: nand_get_small_page_ooblayout());
6344	break;
6345	case 64:
6346	case 128:
6347	mtd_set_ooblayout(mtd,
6348	ooblayout: nand_get_large_page_hamming_ooblayout());
6349	break;
6350	default:
6351	/*
6352	* Expose the whole OOB area to users if ECC_NONE
6353	* is passed. We could do that for all kind of
6354	* ->oobsize, but we must keep the old large/small
6355	* page with ECC layout when ->oobsize <= 128 for
6356	* compatibility reasons.
6357	*/
6358	if (ecc->engine_type == NAND_ECC_ENGINE_TYPE_NONE) {
6359	mtd_set_ooblayout(mtd,
6360	ooblayout: nand_get_large_page_ooblayout());
6361	break;
6362	}
6363
6364	WARN(1, "No oob scheme defined for oobsize %d\n",
6365	mtd->oobsize);
6366	ret = -EINVAL;
6367	goto err_nand_manuf_cleanup;
6368	}
6369	}
6370
6371	/*
6372	* Check ECC mode, default to software if 3byte/512byte hardware ECC is
6373	* selected and we have 256 byte pagesize fallback to software ECC
6374	*/
6375
6376	switch (ecc->engine_type) {
6377	case NAND_ECC_ENGINE_TYPE_ON_HOST:
6378	ret = nand_set_ecc_on_host_ops(chip);
6379	if (ret)
6380	goto err_nand_manuf_cleanup;
6381
6382	if (mtd->writesize >= ecc->size) {
6383	if (!ecc->strength) {
6384	WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
6385	ret = -EINVAL;
6386	goto err_nand_manuf_cleanup;
6387	}
6388	break;
6389	}
6390	pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
6391	ecc->size, mtd->writesize);
6392	ecc->engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
6393	ecc->algo = NAND_ECC_ALGO_HAMMING;
6394	fallthrough;
6395
6396	case NAND_ECC_ENGINE_TYPE_SOFT:
6397	ret = nand_set_ecc_soft_ops(chip);
6398	if (ret)
6399	goto err_nand_manuf_cleanup;
6400	break;
6401
6402	case NAND_ECC_ENGINE_TYPE_ON_DIE:
6403	if (!ecc->read_page || !ecc->write_page) {
6404	WARN(1, "No ECC functions supplied; on-die ECC not possible\n");
6405	ret = -EINVAL;
6406	goto err_nand_manuf_cleanup;
6407	}
6408	if (!ecc->read_oob)
6409	ecc->read_oob = nand_read_oob_std;
6410	if (!ecc->write_oob)
6411	ecc->write_oob = nand_write_oob_std;
6412	break;
6413
6414	case NAND_ECC_ENGINE_TYPE_NONE:
6415	pr_warn("NAND_ECC_ENGINE_TYPE_NONE selected by board driver. This is not recommended!\n");
6416	ecc->read_page = nand_read_page_raw;
6417	ecc->write_page = nand_write_page_raw;
6418	ecc->read_oob = nand_read_oob_std;
6419	ecc->read_page_raw = nand_read_page_raw;
6420	ecc->write_page_raw = nand_write_page_raw;
6421	ecc->write_oob = nand_write_oob_std;
6422	ecc->size = mtd->writesize;
6423	ecc->bytes = 0;
6424	ecc->strength = 0;
6425	break;
6426
6427	default:
6428	WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->engine_type);
6429	ret = -EINVAL;
6430	goto err_nand_manuf_cleanup;
6431	}
6432
6433	if (ecc->correct || ecc->calculate) {
6434	ecc->calc_buf = kmalloc(size: mtd->oobsize, GFP_KERNEL);
6435	ecc->code_buf = kmalloc(size: mtd->oobsize, GFP_KERNEL);
6436	if (!ecc->calc_buf || !ecc->code_buf) {
6437	ret = -ENOMEM;
6438	goto err_nand_manuf_cleanup;
6439	}
6440	}
6441
6442	/* For many systems, the standard OOB write also works for raw */
6443	if (!ecc->read_oob_raw)
6444	ecc->read_oob_raw = ecc->read_oob;
6445	if (!ecc->write_oob_raw)
6446	ecc->write_oob_raw = ecc->write_oob;
6447
6448	/* propagate ecc info to mtd_info */
6449	mtd->ecc_strength = ecc->strength;
6450	mtd->ecc_step_size = ecc->size;
6451
6452	/*
6453	* Set the number of read / write steps for one page depending on ECC
6454	* mode.
6455	*/
6456	if (!ecc->steps)
6457	ecc->steps = mtd->writesize / ecc->size;
6458	if (ecc->steps * ecc->size != mtd->writesize) {
6459	WARN(1, "Invalid ECC parameters\n");
6460	ret = -EINVAL;
6461	goto err_nand_manuf_cleanup;
6462	}
6463
6464	if (!ecc->total) {
6465	ecc->total = ecc->steps * ecc->bytes;
6466	chip->base.ecc.ctx.total = ecc->total;
6467	}
6468
6469	if (ecc->total > mtd->oobsize) {
6470	WARN(1, "Total number of ECC bytes exceeded oobsize\n");
6471	ret = -EINVAL;
6472	goto err_nand_manuf_cleanup;
6473	}
6474
6475	/*
6476	* The number of bytes available for a client to place data into
6477	* the out of band area.
6478	*/
6479	ret = mtd_ooblayout_count_freebytes(mtd);
6480	if (ret < 0)
6481	ret = 0;
6482
6483	mtd->oobavail = ret;
6484
6485	/* ECC sanity check: warn if it's too weak */
6486	if (!nand_ecc_is_strong_enough(nand: &chip->base))
6487	pr_warn("WARNING: %s: the ECC used on your system (%db/%dB) is too weak compared to the one required by the NAND chip (%db/%dB)\n",
6488	mtd->name, chip->ecc.strength, chip->ecc.size,
6489	nanddev_get_ecc_requirements(&chip->base)->strength,
6490	nanddev_get_ecc_requirements(&chip->base)->step_size);
6491
6492	/* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
6493	if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
6494	switch (ecc->steps) {
6495	case 2:
6496	mtd->subpage_sft = 1;
6497	break;
6498	case 4:
6499	case 8:
6500	case 16:
6501	mtd->subpage_sft = 2;
6502	break;
6503	}
6504	}
6505	chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
6506
6507	/* Invalidate the pagebuffer reference */
6508	chip->pagecache.page = -1;
6509
6510	/* Large page NAND with SOFT_ECC should support subpage reads */
6511	switch (ecc->engine_type) {
6512	case NAND_ECC_ENGINE_TYPE_SOFT:
6513	if (chip->page_shift > 9)
6514	chip->options |= NAND_SUBPAGE_READ;
6515	break;
6516
6517	default:
6518	break;
6519	}
6520
6521	ret = nanddev_init(nand: &chip->base, ops: &rawnand_ops, owner: mtd->owner);
6522	if (ret)
6523	goto err_nand_manuf_cleanup;
6524
6525	/* Adjust the MTD_CAP_ flags when NAND_ROM is set. */
6526	if (chip->options & NAND_ROM)
6527	mtd->flags = MTD_CAP_ROM;
6528
6529	/* Fill in remaining MTD driver data */
6530	mtd->_erase = nand_erase;
6531	mtd->_point = NULL;
6532	mtd->_unpoint = NULL;
6533	mtd->_panic_write = panic_nand_write;
6534	mtd->_read_oob = nand_read_oob;
6535	mtd->_write_oob = nand_write_oob;
6536	mtd->_sync = nand_sync;
6537	mtd->_lock = nand_lock;
6538	mtd->_unlock = nand_unlock;
6539	mtd->_suspend = nand_suspend;
6540	mtd->_resume = nand_resume;
6541	mtd->_reboot = nand_shutdown;
6542	mtd->_block_isreserved = nand_block_isreserved;
6543	mtd->_block_isbad = nand_block_isbad;
6544	mtd->_block_markbad = nand_block_markbad;
6545	mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks;
6546
6547	/*
6548	* Initialize bitflip_threshold to its default prior scan_bbt() call.
6549	* scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
6550	* properly set.
6551	*/
6552	if (!mtd->bitflip_threshold)
6553	mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
6554
6555	/* Find the fastest data interface for this chip */
6556	ret = nand_choose_interface_config(chip);
6557	if (ret)
6558	goto err_nanddev_cleanup;
6559
6560	/* Enter fastest possible mode on all dies. */
6561	for (i = 0; i < nanddev_ntargets(nand: &chip->base); i++) {
6562	ret = nand_setup_interface(chip, chipnr: i);
6563	if (ret)
6564	goto err_free_interface_config;
6565	}
6566
6567	rawnand_late_check_supported_ops(chip);
6568
6569	/*
6570	* Look for secure regions in the NAND chip. These regions are supposed
6571	* to be protected by a secure element like Trustzone. So the read/write
6572	* accesses to these regions will be blocked in the runtime by this
6573	* driver.
6574	*/
6575	ret = of_get_nand_secure_regions(chip);
6576	if (ret)
6577	goto err_free_interface_config;
6578
6579	/* Check, if we should skip the bad block table scan */
6580	if (chip->options & NAND_SKIP_BBTSCAN)
6581	return 0;
6582
6583	/* Build bad block table */
6584	ret = nand_create_bbt(chip);
6585	if (ret)
6586	goto err_free_secure_regions;
6587
6588	return 0;
6589
6590	err_free_secure_regions:
6591	kfree(objp: chip->secure_regions);
6592
6593	err_free_interface_config:
6594	kfree(objp: chip->best_interface_config);
6595
6596	err_nanddev_cleanup:
6597	nanddev_cleanup(nand: &chip->base);
6598
6599	err_nand_manuf_cleanup:
6600	nand_manufacturer_cleanup(chip);
6601
6602	err_free_buf:
6603	kfree(objp: chip->data_buf);
6604	kfree(objp: ecc->code_buf);
6605	kfree(objp: ecc->calc_buf);
6606
6607	return ret;
6608	}
6609
6610	static int nand_attach(struct nand_chip *chip)
6611	{
6612	if (chip->controller->ops && chip->controller->ops->attach_chip)
6613	return chip->controller->ops->attach_chip(chip);
6614
6615	return 0;
6616	}
6617
6618	static void nand_detach(struct nand_chip *chip)
6619	{
6620	if (chip->controller->ops && chip->controller->ops->detach_chip)
6621	chip->controller->ops->detach_chip(chip);
6622	}
6623
6624	/**
6625	* nand_scan_with_ids - [NAND Interface] Scan for the NAND device
6626	* @chip: NAND chip object
6627	* @maxchips: number of chips to scan for.
6628	* @ids: optional flash IDs table
6629	*
6630	* This fills out all the uninitialized function pointers with the defaults.
6631	* The flash ID is read and the mtd/chip structures are filled with the
6632	* appropriate values.
6633	*/
6634	int nand_scan_with_ids(struct nand_chip *chip, unsigned int maxchips,
6635	struct nand_flash_dev *ids)
6636	{
6637	int ret;
6638
6639	if (!maxchips)
6640	return -EINVAL;
6641
6642	ret = nand_scan_ident(chip, maxchips, table: ids);
6643	if (ret)
6644	return ret;
6645
6646	ret = nand_attach(chip);
6647	if (ret)
6648	goto cleanup_ident;
6649
6650	ret = nand_scan_tail(chip);
6651	if (ret)
6652	goto detach_chip;
6653
6654	return 0;
6655
6656	detach_chip:
6657	nand_detach(chip);
6658	cleanup_ident:
6659	nand_scan_ident_cleanup(chip);
6660
6661	return ret;
6662	}
6663	EXPORT_SYMBOL(nand_scan_with_ids);
6664
6665	/**
6666	* nand_cleanup - [NAND Interface] Free resources held by the NAND device
6667	* @chip: NAND chip object
6668	*/
6669	void nand_cleanup(struct nand_chip *chip)
6670	{
6671	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT) {
6672	if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING)
6673	rawnand_sw_hamming_cleanup(chip);
6674	else if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
6675	rawnand_sw_bch_cleanup(chip);
6676	}
6677
6678	nanddev_cleanup(nand: &chip->base);
6679
6680	/* Free secure regions data */
6681	kfree(objp: chip->secure_regions);
6682
6683	/* Free bad block table memory */
6684	kfree(objp: chip->bbt);
6685	kfree(objp: chip->data_buf);
6686	kfree(objp: chip->ecc.code_buf);
6687	kfree(objp: chip->ecc.calc_buf);
6688
6689	/* Free bad block descriptor memory */
6690	if (chip->badblock_pattern && chip->badblock_pattern->options
6691	& NAND_BBT_DYNAMICSTRUCT)
6692	kfree(objp: chip->badblock_pattern);
6693
6694	/* Free the data interface */
6695	kfree(objp: chip->best_interface_config);
6696
6697	/* Free manufacturer priv data. */
6698	nand_manufacturer_cleanup(chip);
6699
6700	/* Free controller specific allocations after chip identification */
6701	nand_detach(chip);
6702
6703	/* Free identification phase allocations */
6704	nand_scan_ident_cleanup(chip);
6705	}
6706
6707	EXPORT_SYMBOL_GPL(nand_cleanup);
6708
6709	MODULE_LICENSE("GPL");
6710	MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
6711	MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
6712	MODULE_DESCRIPTION("Generic NAND flash driver code");
6713