1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) STMicroelectronics 2018 |
4 | * Author: Christophe Kerello <christophe.kerello@st.com> |
5 | */ |
6 | |
7 | #include <linux/bitfield.h> |
8 | #include <linux/clk.h> |
9 | #include <linux/dmaengine.h> |
10 | #include <linux/dma-mapping.h> |
11 | #include <linux/errno.h> |
12 | #include <linux/gpio/consumer.h> |
13 | #include <linux/interrupt.h> |
14 | #include <linux/iopoll.h> |
15 | #include <linux/mfd/syscon.h> |
16 | #include <linux/module.h> |
17 | #include <linux/mtd/rawnand.h> |
18 | #include <linux/of_address.h> |
19 | #include <linux/of_device.h> |
20 | #include <linux/pinctrl/consumer.h> |
21 | #include <linux/platform_device.h> |
22 | #include <linux/regmap.h> |
23 | #include <linux/reset.h> |
24 | |
25 | /* Bad block marker length */ |
26 | #define FMC2_BBM_LEN 2 |
27 | |
28 | /* ECC step size */ |
29 | #define FMC2_ECC_STEP_SIZE 512 |
30 | |
31 | /* BCHDSRx registers length */ |
32 | #define FMC2_BCHDSRS_LEN 20 |
33 | |
34 | /* HECCR length */ |
35 | #define FMC2_HECCR_LEN 4 |
36 | |
37 | /* Max requests done for a 8k nand page size */ |
38 | #define FMC2_MAX_SG 16 |
39 | |
40 | /* Max chip enable */ |
41 | #define FMC2_MAX_CE 4 |
42 | |
43 | /* Max ECC buffer length */ |
44 | #define FMC2_MAX_ECC_BUF_LEN (FMC2_BCHDSRS_LEN * FMC2_MAX_SG) |
45 | |
46 | #define FMC2_TIMEOUT_MS 5000 |
47 | |
48 | /* Timings */ |
49 | #define FMC2_THIZ 1 |
50 | #define FMC2_TIO 8000 |
51 | #define FMC2_TSYNC 3000 |
52 | #define FMC2_PCR_TIMING_MASK 0xf |
53 | #define FMC2_PMEM_PATT_TIMING_MASK 0xff |
54 | |
55 | /* FMC2 Controller Registers */ |
56 | #define FMC2_BCR1 0x0 |
57 | #define FMC2_PCR 0x80 |
58 | #define FMC2_SR 0x84 |
59 | #define FMC2_PMEM 0x88 |
60 | #define FMC2_PATT 0x8c |
61 | #define FMC2_HECCR 0x94 |
62 | #define FMC2_ISR 0x184 |
63 | #define FMC2_ICR 0x188 |
64 | #define FMC2_CSQCR 0x200 |
65 | #define FMC2_CSQCFGR1 0x204 |
66 | #define FMC2_CSQCFGR2 0x208 |
67 | #define FMC2_CSQCFGR3 0x20c |
68 | #define FMC2_CSQAR1 0x210 |
69 | #define FMC2_CSQAR2 0x214 |
70 | #define FMC2_CSQIER 0x220 |
71 | #define FMC2_CSQISR 0x224 |
72 | #define FMC2_CSQICR 0x228 |
73 | #define FMC2_CSQEMSR 0x230 |
74 | #define FMC2_BCHIER 0x250 |
75 | #define FMC2_BCHISR 0x254 |
76 | #define FMC2_BCHICR 0x258 |
77 | #define FMC2_BCHPBR1 0x260 |
78 | #define FMC2_BCHPBR2 0x264 |
79 | #define FMC2_BCHPBR3 0x268 |
80 | #define FMC2_BCHPBR4 0x26c |
81 | #define FMC2_BCHDSR0 0x27c |
82 | #define FMC2_BCHDSR1 0x280 |
83 | #define FMC2_BCHDSR2 0x284 |
84 | #define FMC2_BCHDSR3 0x288 |
85 | #define FMC2_BCHDSR4 0x28c |
86 | |
87 | /* Register: FMC2_BCR1 */ |
88 | #define FMC2_BCR1_FMC2EN BIT(31) |
89 | |
90 | /* Register: FMC2_PCR */ |
91 | #define FMC2_PCR_PWAITEN BIT(1) |
92 | #define FMC2_PCR_PBKEN BIT(2) |
93 | #define FMC2_PCR_PWID GENMASK(5, 4) |
94 | #define FMC2_PCR_PWID_BUSWIDTH_8 0 |
95 | #define FMC2_PCR_PWID_BUSWIDTH_16 1 |
96 | #define FMC2_PCR_ECCEN BIT(6) |
97 | #define FMC2_PCR_ECCALG BIT(8) |
98 | #define FMC2_PCR_TCLR GENMASK(12, 9) |
99 | #define FMC2_PCR_TCLR_DEFAULT 0xf |
100 | #define FMC2_PCR_TAR GENMASK(16, 13) |
101 | #define FMC2_PCR_TAR_DEFAULT 0xf |
102 | #define FMC2_PCR_ECCSS GENMASK(19, 17) |
103 | #define FMC2_PCR_ECCSS_512 1 |
104 | #define FMC2_PCR_ECCSS_2048 3 |
105 | #define FMC2_PCR_BCHECC BIT(24) |
106 | #define FMC2_PCR_WEN BIT(25) |
107 | |
108 | /* Register: FMC2_SR */ |
109 | #define FMC2_SR_NWRF BIT(6) |
110 | |
111 | /* Register: FMC2_PMEM */ |
112 | #define FMC2_PMEM_MEMSET GENMASK(7, 0) |
113 | #define FMC2_PMEM_MEMWAIT GENMASK(15, 8) |
114 | #define FMC2_PMEM_MEMHOLD GENMASK(23, 16) |
115 | #define FMC2_PMEM_MEMHIZ GENMASK(31, 24) |
116 | #define FMC2_PMEM_DEFAULT 0x0a0a0a0a |
117 | |
118 | /* Register: FMC2_PATT */ |
119 | #define FMC2_PATT_ATTSET GENMASK(7, 0) |
120 | #define FMC2_PATT_ATTWAIT GENMASK(15, 8) |
121 | #define FMC2_PATT_ATTHOLD GENMASK(23, 16) |
122 | #define FMC2_PATT_ATTHIZ GENMASK(31, 24) |
123 | #define FMC2_PATT_DEFAULT 0x0a0a0a0a |
124 | |
125 | /* Register: FMC2_ISR */ |
126 | #define FMC2_ISR_IHLF BIT(1) |
127 | |
128 | /* Register: FMC2_ICR */ |
129 | #define FMC2_ICR_CIHLF BIT(1) |
130 | |
131 | /* Register: FMC2_CSQCR */ |
132 | #define FMC2_CSQCR_CSQSTART BIT(0) |
133 | |
134 | /* Register: FMC2_CSQCFGR1 */ |
135 | #define FMC2_CSQCFGR1_CMD2EN BIT(1) |
136 | #define FMC2_CSQCFGR1_DMADEN BIT(2) |
137 | #define FMC2_CSQCFGR1_ACYNBR GENMASK(6, 4) |
138 | #define FMC2_CSQCFGR1_CMD1 GENMASK(15, 8) |
139 | #define FMC2_CSQCFGR1_CMD2 GENMASK(23, 16) |
140 | #define FMC2_CSQCFGR1_CMD1T BIT(24) |
141 | #define FMC2_CSQCFGR1_CMD2T BIT(25) |
142 | |
143 | /* Register: FMC2_CSQCFGR2 */ |
144 | #define FMC2_CSQCFGR2_SQSDTEN BIT(0) |
145 | #define FMC2_CSQCFGR2_RCMD2EN BIT(1) |
146 | #define FMC2_CSQCFGR2_DMASEN BIT(2) |
147 | #define FMC2_CSQCFGR2_RCMD1 GENMASK(15, 8) |
148 | #define FMC2_CSQCFGR2_RCMD2 GENMASK(23, 16) |
149 | #define FMC2_CSQCFGR2_RCMD1T BIT(24) |
150 | #define FMC2_CSQCFGR2_RCMD2T BIT(25) |
151 | |
152 | /* Register: FMC2_CSQCFGR3 */ |
153 | #define FMC2_CSQCFGR3_SNBR GENMASK(13, 8) |
154 | #define FMC2_CSQCFGR3_AC1T BIT(16) |
155 | #define FMC2_CSQCFGR3_AC2T BIT(17) |
156 | #define FMC2_CSQCFGR3_AC3T BIT(18) |
157 | #define FMC2_CSQCFGR3_AC4T BIT(19) |
158 | #define FMC2_CSQCFGR3_AC5T BIT(20) |
159 | #define FMC2_CSQCFGR3_SDT BIT(21) |
160 | #define FMC2_CSQCFGR3_RAC1T BIT(22) |
161 | #define FMC2_CSQCFGR3_RAC2T BIT(23) |
162 | |
163 | /* Register: FMC2_CSQCAR1 */ |
164 | #define FMC2_CSQCAR1_ADDC1 GENMASK(7, 0) |
165 | #define FMC2_CSQCAR1_ADDC2 GENMASK(15, 8) |
166 | #define FMC2_CSQCAR1_ADDC3 GENMASK(23, 16) |
167 | #define FMC2_CSQCAR1_ADDC4 GENMASK(31, 24) |
168 | |
169 | /* Register: FMC2_CSQCAR2 */ |
170 | #define FMC2_CSQCAR2_ADDC5 GENMASK(7, 0) |
171 | #define FMC2_CSQCAR2_NANDCEN GENMASK(11, 10) |
172 | #define FMC2_CSQCAR2_SAO GENMASK(31, 16) |
173 | |
174 | /* Register: FMC2_CSQIER */ |
175 | #define FMC2_CSQIER_TCIE BIT(0) |
176 | |
177 | /* Register: FMC2_CSQICR */ |
178 | #define FMC2_CSQICR_CLEAR_IRQ GENMASK(4, 0) |
179 | |
180 | /* Register: FMC2_CSQEMSR */ |
181 | #define FMC2_CSQEMSR_SEM GENMASK(15, 0) |
182 | |
183 | /* Register: FMC2_BCHIER */ |
184 | #define FMC2_BCHIER_DERIE BIT(1) |
185 | #define FMC2_BCHIER_EPBRIE BIT(4) |
186 | |
187 | /* Register: FMC2_BCHICR */ |
188 | #define FMC2_BCHICR_CLEAR_IRQ GENMASK(4, 0) |
189 | |
190 | /* Register: FMC2_BCHDSR0 */ |
191 | #define FMC2_BCHDSR0_DUE BIT(0) |
192 | #define FMC2_BCHDSR0_DEF BIT(1) |
193 | #define FMC2_BCHDSR0_DEN GENMASK(7, 4) |
194 | |
195 | /* Register: FMC2_BCHDSR1 */ |
196 | #define FMC2_BCHDSR1_EBP1 GENMASK(12, 0) |
197 | #define FMC2_BCHDSR1_EBP2 GENMASK(28, 16) |
198 | |
199 | /* Register: FMC2_BCHDSR2 */ |
200 | #define FMC2_BCHDSR2_EBP3 GENMASK(12, 0) |
201 | #define FMC2_BCHDSR2_EBP4 GENMASK(28, 16) |
202 | |
203 | /* Register: FMC2_BCHDSR3 */ |
204 | #define FMC2_BCHDSR3_EBP5 GENMASK(12, 0) |
205 | #define FMC2_BCHDSR3_EBP6 GENMASK(28, 16) |
206 | |
207 | /* Register: FMC2_BCHDSR4 */ |
208 | #define FMC2_BCHDSR4_EBP7 GENMASK(12, 0) |
209 | #define FMC2_BCHDSR4_EBP8 GENMASK(28, 16) |
210 | |
211 | enum stm32_fmc2_ecc { |
212 | FMC2_ECC_HAM = 1, |
213 | FMC2_ECC_BCH4 = 4, |
214 | FMC2_ECC_BCH8 = 8 |
215 | }; |
216 | |
217 | enum stm32_fmc2_irq_state { |
218 | FMC2_IRQ_UNKNOWN = 0, |
219 | FMC2_IRQ_BCH, |
220 | FMC2_IRQ_SEQ |
221 | }; |
222 | |
223 | struct stm32_fmc2_timings { |
224 | u8 tclr; |
225 | u8 tar; |
226 | u8 thiz; |
227 | u8 twait; |
228 | u8 thold_mem; |
229 | u8 tset_mem; |
230 | u8 thold_att; |
231 | u8 tset_att; |
232 | }; |
233 | |
234 | struct stm32_fmc2_nand { |
235 | struct nand_chip chip; |
236 | struct gpio_desc *wp_gpio; |
237 | struct stm32_fmc2_timings timings; |
238 | int ncs; |
239 | int cs_used[FMC2_MAX_CE]; |
240 | }; |
241 | |
242 | static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip) |
243 | { |
244 | return container_of(chip, struct stm32_fmc2_nand, chip); |
245 | } |
246 | |
247 | struct stm32_fmc2_nfc; |
248 | |
249 | struct stm32_fmc2_nfc_data { |
250 | int max_ncs; |
251 | int (*set_cdev)(struct stm32_fmc2_nfc *nfc); |
252 | }; |
253 | |
254 | struct stm32_fmc2_nfc { |
255 | struct nand_controller base; |
256 | struct stm32_fmc2_nand nand; |
257 | struct device *dev; |
258 | struct device *cdev; |
259 | struct regmap *regmap; |
260 | void __iomem *data_base[FMC2_MAX_CE]; |
261 | void __iomem *cmd_base[FMC2_MAX_CE]; |
262 | void __iomem *addr_base[FMC2_MAX_CE]; |
263 | phys_addr_t io_phys_addr; |
264 | phys_addr_t data_phys_addr[FMC2_MAX_CE]; |
265 | struct clk *clk; |
266 | u8 irq_state; |
267 | const struct stm32_fmc2_nfc_data *data; |
268 | |
269 | struct dma_chan *dma_tx_ch; |
270 | struct dma_chan *dma_rx_ch; |
271 | struct dma_chan *dma_ecc_ch; |
272 | struct sg_table dma_data_sg; |
273 | struct sg_table dma_ecc_sg; |
274 | u8 *ecc_buf; |
275 | int dma_ecc_len; |
276 | u32 tx_dma_max_burst; |
277 | u32 rx_dma_max_burst; |
278 | |
279 | struct completion complete; |
280 | struct completion dma_data_complete; |
281 | struct completion dma_ecc_complete; |
282 | |
283 | u8 cs_assigned; |
284 | int cs_sel; |
285 | }; |
286 | |
287 | static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_controller *base) |
288 | { |
289 | return container_of(base, struct stm32_fmc2_nfc, base); |
290 | } |
291 | |
292 | static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip) |
293 | { |
294 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
295 | struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); |
296 | struct stm32_fmc2_timings *timings = &nand->timings; |
297 | u32 pmem, patt; |
298 | |
299 | /* Set tclr/tar timings */ |
300 | regmap_update_bits(map: nfc->regmap, FMC2_PCR, |
301 | FMC2_PCR_TCLR | FMC2_PCR_TAR, |
302 | FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) | |
303 | FIELD_PREP(FMC2_PCR_TAR, timings->tar)); |
304 | |
305 | /* Set tset/twait/thold/thiz timings in common bank */ |
306 | pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem); |
307 | pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait); |
308 | pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem); |
309 | pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz); |
310 | regmap_write(map: nfc->regmap, FMC2_PMEM, val: pmem); |
311 | |
312 | /* Set tset/twait/thold/thiz timings in attribut bank */ |
313 | patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att); |
314 | patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait); |
315 | patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att); |
316 | patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz); |
317 | regmap_write(map: nfc->regmap, FMC2_PATT, val: patt); |
318 | } |
319 | |
320 | static void stm32_fmc2_nfc_setup(struct nand_chip *chip) |
321 | { |
322 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
323 | u32 pcr = 0, pcr_mask; |
324 | |
325 | /* Configure ECC algorithm (default configuration is Hamming) */ |
326 | pcr_mask = FMC2_PCR_ECCALG; |
327 | pcr_mask |= FMC2_PCR_BCHECC; |
328 | if (chip->ecc.strength == FMC2_ECC_BCH8) { |
329 | pcr |= FMC2_PCR_ECCALG; |
330 | pcr |= FMC2_PCR_BCHECC; |
331 | } else if (chip->ecc.strength == FMC2_ECC_BCH4) { |
332 | pcr |= FMC2_PCR_ECCALG; |
333 | } |
334 | |
335 | /* Set buswidth */ |
336 | pcr_mask |= FMC2_PCR_PWID; |
337 | if (chip->options & NAND_BUSWIDTH_16) |
338 | pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16); |
339 | |
340 | /* Set ECC sector size */ |
341 | pcr_mask |= FMC2_PCR_ECCSS; |
342 | pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512); |
343 | |
344 | regmap_update_bits(map: nfc->regmap, FMC2_PCR, mask: pcr_mask, val: pcr); |
345 | } |
346 | |
347 | static int stm32_fmc2_nfc_select_chip(struct nand_chip *chip, int chipnr) |
348 | { |
349 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
350 | struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); |
351 | struct dma_slave_config dma_cfg; |
352 | int ret; |
353 | |
354 | if (nand->cs_used[chipnr] == nfc->cs_sel) |
355 | return 0; |
356 | |
357 | nfc->cs_sel = nand->cs_used[chipnr]; |
358 | stm32_fmc2_nfc_setup(chip); |
359 | stm32_fmc2_nfc_timings_init(chip); |
360 | |
361 | if (nfc->dma_tx_ch) { |
362 | memset(&dma_cfg, 0, sizeof(dma_cfg)); |
363 | dma_cfg.dst_addr = nfc->data_phys_addr[nfc->cs_sel]; |
364 | dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
365 | dma_cfg.dst_maxburst = nfc->tx_dma_max_burst / |
366 | dma_cfg.dst_addr_width; |
367 | |
368 | ret = dmaengine_slave_config(chan: nfc->dma_tx_ch, config: &dma_cfg); |
369 | if (ret) { |
370 | dev_err(nfc->dev, "tx DMA engine slave config failed\n" ); |
371 | return ret; |
372 | } |
373 | } |
374 | |
375 | if (nfc->dma_rx_ch) { |
376 | memset(&dma_cfg, 0, sizeof(dma_cfg)); |
377 | dma_cfg.src_addr = nfc->data_phys_addr[nfc->cs_sel]; |
378 | dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
379 | dma_cfg.src_maxburst = nfc->rx_dma_max_burst / |
380 | dma_cfg.src_addr_width; |
381 | |
382 | ret = dmaengine_slave_config(chan: nfc->dma_rx_ch, config: &dma_cfg); |
383 | if (ret) { |
384 | dev_err(nfc->dev, "rx DMA engine slave config failed\n" ); |
385 | return ret; |
386 | } |
387 | } |
388 | |
389 | if (nfc->dma_ecc_ch) { |
390 | /* |
391 | * Hamming: we read HECCR register |
392 | * BCH4/BCH8: we read BCHDSRSx registers |
393 | */ |
394 | memset(&dma_cfg, 0, sizeof(dma_cfg)); |
395 | dma_cfg.src_addr = nfc->io_phys_addr; |
396 | dma_cfg.src_addr += chip->ecc.strength == FMC2_ECC_HAM ? |
397 | FMC2_HECCR : FMC2_BCHDSR0; |
398 | dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
399 | |
400 | ret = dmaengine_slave_config(chan: nfc->dma_ecc_ch, config: &dma_cfg); |
401 | if (ret) { |
402 | dev_err(nfc->dev, "ECC DMA engine slave config failed\n" ); |
403 | return ret; |
404 | } |
405 | |
406 | /* Calculate ECC length needed for one sector */ |
407 | nfc->dma_ecc_len = chip->ecc.strength == FMC2_ECC_HAM ? |
408 | FMC2_HECCR_LEN : FMC2_BCHDSRS_LEN; |
409 | } |
410 | |
411 | return 0; |
412 | } |
413 | |
414 | static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc, bool set) |
415 | { |
416 | u32 pcr; |
417 | |
418 | pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) : |
419 | FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8); |
420 | |
421 | regmap_update_bits(map: nfc->regmap, FMC2_PCR, FMC2_PCR_PWID, val: pcr); |
422 | } |
423 | |
424 | static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable) |
425 | { |
426 | regmap_update_bits(map: nfc->regmap, FMC2_PCR, FMC2_PCR_ECCEN, |
427 | val: enable ? FMC2_PCR_ECCEN : 0); |
428 | } |
429 | |
430 | static void stm32_fmc2_nfc_enable_seq_irq(struct stm32_fmc2_nfc *nfc) |
431 | { |
432 | nfc->irq_state = FMC2_IRQ_SEQ; |
433 | |
434 | regmap_update_bits(map: nfc->regmap, FMC2_CSQIER, |
435 | FMC2_CSQIER_TCIE, FMC2_CSQIER_TCIE); |
436 | } |
437 | |
438 | static void stm32_fmc2_nfc_disable_seq_irq(struct stm32_fmc2_nfc *nfc) |
439 | { |
440 | regmap_update_bits(map: nfc->regmap, FMC2_CSQIER, FMC2_CSQIER_TCIE, val: 0); |
441 | |
442 | nfc->irq_state = FMC2_IRQ_UNKNOWN; |
443 | } |
444 | |
445 | static void stm32_fmc2_nfc_clear_seq_irq(struct stm32_fmc2_nfc *nfc) |
446 | { |
447 | regmap_write(map: nfc->regmap, FMC2_CSQICR, FMC2_CSQICR_CLEAR_IRQ); |
448 | } |
449 | |
450 | static void stm32_fmc2_nfc_enable_bch_irq(struct stm32_fmc2_nfc *nfc, int mode) |
451 | { |
452 | nfc->irq_state = FMC2_IRQ_BCH; |
453 | |
454 | if (mode == NAND_ECC_WRITE) |
455 | regmap_update_bits(map: nfc->regmap, FMC2_BCHIER, |
456 | FMC2_BCHIER_EPBRIE, FMC2_BCHIER_EPBRIE); |
457 | else |
458 | regmap_update_bits(map: nfc->regmap, FMC2_BCHIER, |
459 | FMC2_BCHIER_DERIE, FMC2_BCHIER_DERIE); |
460 | } |
461 | |
462 | static void stm32_fmc2_nfc_disable_bch_irq(struct stm32_fmc2_nfc *nfc) |
463 | { |
464 | regmap_update_bits(map: nfc->regmap, FMC2_BCHIER, |
465 | FMC2_BCHIER_DERIE | FMC2_BCHIER_EPBRIE, val: 0); |
466 | |
467 | nfc->irq_state = FMC2_IRQ_UNKNOWN; |
468 | } |
469 | |
470 | static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc) |
471 | { |
472 | regmap_write(map: nfc->regmap, FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ); |
473 | } |
474 | |
475 | /* |
476 | * Enable ECC logic and reset syndrome/parity bits previously calculated |
477 | * Syndrome/parity bits is cleared by setting the ECCEN bit to 0 |
478 | */ |
479 | static void stm32_fmc2_nfc_hwctl(struct nand_chip *chip, int mode) |
480 | { |
481 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
482 | |
483 | stm32_fmc2_nfc_set_ecc(nfc, enable: false); |
484 | |
485 | if (chip->ecc.strength != FMC2_ECC_HAM) { |
486 | regmap_update_bits(map: nfc->regmap, FMC2_PCR, FMC2_PCR_WEN, |
487 | val: mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0); |
488 | |
489 | reinit_completion(x: &nfc->complete); |
490 | stm32_fmc2_nfc_clear_bch_irq(nfc); |
491 | stm32_fmc2_nfc_enable_bch_irq(nfc, mode); |
492 | } |
493 | |
494 | stm32_fmc2_nfc_set_ecc(nfc, enable: true); |
495 | } |
496 | |
497 | /* |
498 | * ECC Hamming calculation |
499 | * ECC is 3 bytes for 512 bytes of data (supports error correction up to |
500 | * max of 1-bit) |
501 | */ |
502 | static void stm32_fmc2_nfc_ham_set_ecc(const u32 ecc_sta, u8 *ecc) |
503 | { |
504 | ecc[0] = ecc_sta; |
505 | ecc[1] = ecc_sta >> 8; |
506 | ecc[2] = ecc_sta >> 16; |
507 | } |
508 | |
509 | static int stm32_fmc2_nfc_ham_calculate(struct nand_chip *chip, const u8 *data, |
510 | u8 *ecc) |
511 | { |
512 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
513 | u32 sr, heccr; |
514 | int ret; |
515 | |
516 | ret = regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr, |
517 | sr & FMC2_SR_NWRF, 1, |
518 | 1000 * FMC2_TIMEOUT_MS); |
519 | if (ret) { |
520 | dev_err(nfc->dev, "ham timeout\n" ); |
521 | return ret; |
522 | } |
523 | |
524 | regmap_read(map: nfc->regmap, FMC2_HECCR, val: &heccr); |
525 | stm32_fmc2_nfc_ham_set_ecc(ecc_sta: heccr, ecc); |
526 | stm32_fmc2_nfc_set_ecc(nfc, enable: false); |
527 | |
528 | return 0; |
529 | } |
530 | |
531 | static int stm32_fmc2_nfc_ham_correct(struct nand_chip *chip, u8 *dat, |
532 | u8 *read_ecc, u8 *calc_ecc) |
533 | { |
534 | u8 bit_position = 0, b0, b1, b2; |
535 | u32 byte_addr = 0, b; |
536 | u32 i, shifting = 1; |
537 | |
538 | /* Indicate which bit and byte is faulty (if any) */ |
539 | b0 = read_ecc[0] ^ calc_ecc[0]; |
540 | b1 = read_ecc[1] ^ calc_ecc[1]; |
541 | b2 = read_ecc[2] ^ calc_ecc[2]; |
542 | b = b0 | (b1 << 8) | (b2 << 16); |
543 | |
544 | /* No errors */ |
545 | if (likely(!b)) |
546 | return 0; |
547 | |
548 | /* Calculate bit position */ |
549 | for (i = 0; i < 3; i++) { |
550 | switch (b % 4) { |
551 | case 2: |
552 | bit_position += shifting; |
553 | break; |
554 | case 1: |
555 | break; |
556 | default: |
557 | return -EBADMSG; |
558 | } |
559 | shifting <<= 1; |
560 | b >>= 2; |
561 | } |
562 | |
563 | /* Calculate byte position */ |
564 | shifting = 1; |
565 | for (i = 0; i < 9; i++) { |
566 | switch (b % 4) { |
567 | case 2: |
568 | byte_addr += shifting; |
569 | break; |
570 | case 1: |
571 | break; |
572 | default: |
573 | return -EBADMSG; |
574 | } |
575 | shifting <<= 1; |
576 | b >>= 2; |
577 | } |
578 | |
579 | /* Flip the bit */ |
580 | dat[byte_addr] ^= (1 << bit_position); |
581 | |
582 | return 1; |
583 | } |
584 | |
585 | /* |
586 | * ECC BCH calculation and correction |
587 | * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to |
588 | * max of 4-bit/8-bit) |
589 | */ |
590 | static int stm32_fmc2_nfc_bch_calculate(struct nand_chip *chip, const u8 *data, |
591 | u8 *ecc) |
592 | { |
593 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
594 | u32 bchpbr; |
595 | |
596 | /* Wait until the BCH code is ready */ |
597 | if (!wait_for_completion_timeout(x: &nfc->complete, |
598 | timeout: msecs_to_jiffies(FMC2_TIMEOUT_MS))) { |
599 | dev_err(nfc->dev, "bch timeout\n" ); |
600 | stm32_fmc2_nfc_disable_bch_irq(nfc); |
601 | return -ETIMEDOUT; |
602 | } |
603 | |
604 | /* Read parity bits */ |
605 | regmap_read(map: nfc->regmap, FMC2_BCHPBR1, val: &bchpbr); |
606 | ecc[0] = bchpbr; |
607 | ecc[1] = bchpbr >> 8; |
608 | ecc[2] = bchpbr >> 16; |
609 | ecc[3] = bchpbr >> 24; |
610 | |
611 | regmap_read(map: nfc->regmap, FMC2_BCHPBR2, val: &bchpbr); |
612 | ecc[4] = bchpbr; |
613 | ecc[5] = bchpbr >> 8; |
614 | ecc[6] = bchpbr >> 16; |
615 | |
616 | if (chip->ecc.strength == FMC2_ECC_BCH8) { |
617 | ecc[7] = bchpbr >> 24; |
618 | |
619 | regmap_read(map: nfc->regmap, FMC2_BCHPBR3, val: &bchpbr); |
620 | ecc[8] = bchpbr; |
621 | ecc[9] = bchpbr >> 8; |
622 | ecc[10] = bchpbr >> 16; |
623 | ecc[11] = bchpbr >> 24; |
624 | |
625 | regmap_read(map: nfc->regmap, FMC2_BCHPBR4, val: &bchpbr); |
626 | ecc[12] = bchpbr; |
627 | } |
628 | |
629 | stm32_fmc2_nfc_set_ecc(nfc, enable: false); |
630 | |
631 | return 0; |
632 | } |
633 | |
634 | static int stm32_fmc2_nfc_bch_decode(int eccsize, u8 *dat, u32 *ecc_sta) |
635 | { |
636 | u32 bchdsr0 = ecc_sta[0]; |
637 | u32 bchdsr1 = ecc_sta[1]; |
638 | u32 bchdsr2 = ecc_sta[2]; |
639 | u32 bchdsr3 = ecc_sta[3]; |
640 | u32 bchdsr4 = ecc_sta[4]; |
641 | u16 pos[8]; |
642 | int i, den; |
643 | unsigned int nb_errs = 0; |
644 | |
645 | /* No errors found */ |
646 | if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF))) |
647 | return 0; |
648 | |
649 | /* Too many errors detected */ |
650 | if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE)) |
651 | return -EBADMSG; |
652 | |
653 | pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1); |
654 | pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1); |
655 | pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2); |
656 | pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2); |
657 | pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3); |
658 | pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3); |
659 | pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4); |
660 | pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4); |
661 | |
662 | den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0); |
663 | for (i = 0; i < den; i++) { |
664 | if (pos[i] < eccsize * 8) { |
665 | change_bit(nr: pos[i], addr: (unsigned long *)dat); |
666 | nb_errs++; |
667 | } |
668 | } |
669 | |
670 | return nb_errs; |
671 | } |
672 | |
673 | static int stm32_fmc2_nfc_bch_correct(struct nand_chip *chip, u8 *dat, |
674 | u8 *read_ecc, u8 *calc_ecc) |
675 | { |
676 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
677 | u32 ecc_sta[5]; |
678 | |
679 | /* Wait until the decoding error is ready */ |
680 | if (!wait_for_completion_timeout(x: &nfc->complete, |
681 | timeout: msecs_to_jiffies(FMC2_TIMEOUT_MS))) { |
682 | dev_err(nfc->dev, "bch timeout\n" ); |
683 | stm32_fmc2_nfc_disable_bch_irq(nfc); |
684 | return -ETIMEDOUT; |
685 | } |
686 | |
687 | regmap_bulk_read(map: nfc->regmap, FMC2_BCHDSR0, val: ecc_sta, val_count: 5); |
688 | |
689 | stm32_fmc2_nfc_set_ecc(nfc, enable: false); |
690 | |
691 | return stm32_fmc2_nfc_bch_decode(eccsize: chip->ecc.size, dat, ecc_sta); |
692 | } |
693 | |
694 | static int stm32_fmc2_nfc_read_page(struct nand_chip *chip, u8 *buf, |
695 | int oob_required, int page) |
696 | { |
697 | struct mtd_info *mtd = nand_to_mtd(chip); |
698 | int ret, i, s, stat, eccsize = chip->ecc.size; |
699 | int eccbytes = chip->ecc.bytes; |
700 | int eccsteps = chip->ecc.steps; |
701 | int eccstrength = chip->ecc.strength; |
702 | u8 *p = buf; |
703 | u8 *ecc_calc = chip->ecc.calc_buf; |
704 | u8 *ecc_code = chip->ecc.code_buf; |
705 | unsigned int max_bitflips = 0; |
706 | |
707 | ret = nand_read_page_op(chip, page, offset_in_page: 0, NULL, len: 0); |
708 | if (ret) |
709 | return ret; |
710 | |
711 | for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps; |
712 | s++, i += eccbytes, p += eccsize) { |
713 | chip->ecc.hwctl(chip, NAND_ECC_READ); |
714 | |
715 | /* Read the nand page sector (512 bytes) */ |
716 | ret = nand_change_read_column_op(chip, offset_in_page: s * eccsize, buf: p, |
717 | len: eccsize, force_8bit: false); |
718 | if (ret) |
719 | return ret; |
720 | |
721 | /* Read the corresponding ECC bytes */ |
722 | ret = nand_change_read_column_op(chip, offset_in_page: i, buf: ecc_code, |
723 | len: eccbytes, force_8bit: false); |
724 | if (ret) |
725 | return ret; |
726 | |
727 | /* Correct the data */ |
728 | stat = chip->ecc.correct(chip, p, ecc_code, ecc_calc); |
729 | if (stat == -EBADMSG) |
730 | /* Check for empty pages with bitflips */ |
731 | stat = nand_check_erased_ecc_chunk(data: p, datalen: eccsize, |
732 | ecc: ecc_code, ecclen: eccbytes, |
733 | NULL, extraooblen: 0, |
734 | threshold: eccstrength); |
735 | |
736 | if (stat < 0) { |
737 | mtd->ecc_stats.failed++; |
738 | } else { |
739 | mtd->ecc_stats.corrected += stat; |
740 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
741 | } |
742 | } |
743 | |
744 | /* Read oob */ |
745 | if (oob_required) { |
746 | ret = nand_change_read_column_op(chip, offset_in_page: mtd->writesize, |
747 | buf: chip->oob_poi, len: mtd->oobsize, |
748 | force_8bit: false); |
749 | if (ret) |
750 | return ret; |
751 | } |
752 | |
753 | return max_bitflips; |
754 | } |
755 | |
756 | /* Sequencer read/write configuration */ |
757 | static void stm32_fmc2_nfc_rw_page_init(struct nand_chip *chip, int page, |
758 | int raw, bool write_data) |
759 | { |
760 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
761 | struct mtd_info *mtd = nand_to_mtd(chip); |
762 | u32 ecc_offset = mtd->writesize + FMC2_BBM_LEN; |
763 | /* |
764 | * cfg[0] => csqcfgr1, cfg[1] => csqcfgr2, cfg[2] => csqcfgr3 |
765 | * cfg[3] => csqar1, cfg[4] => csqar2 |
766 | */ |
767 | u32 cfg[5]; |
768 | |
769 | regmap_update_bits(map: nfc->regmap, FMC2_PCR, FMC2_PCR_WEN, |
770 | val: write_data ? FMC2_PCR_WEN : 0); |
771 | |
772 | /* |
773 | * - Set Program Page/Page Read command |
774 | * - Enable DMA request data |
775 | * - Set timings |
776 | */ |
777 | cfg[0] = FMC2_CSQCFGR1_DMADEN | FMC2_CSQCFGR1_CMD1T; |
778 | if (write_data) |
779 | cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_SEQIN); |
780 | else |
781 | cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_CMD1, NAND_CMD_READ0) | |
782 | FMC2_CSQCFGR1_CMD2EN | |
783 | FIELD_PREP(FMC2_CSQCFGR1_CMD2, NAND_CMD_READSTART) | |
784 | FMC2_CSQCFGR1_CMD2T; |
785 | |
786 | /* |
787 | * - Set Random Data Input/Random Data Read command |
788 | * - Enable the sequencer to access the Spare data area |
789 | * - Enable DMA request status decoding for read |
790 | * - Set timings |
791 | */ |
792 | if (write_data) |
793 | cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDIN); |
794 | else |
795 | cfg[1] = FIELD_PREP(FMC2_CSQCFGR2_RCMD1, NAND_CMD_RNDOUT) | |
796 | FMC2_CSQCFGR2_RCMD2EN | |
797 | FIELD_PREP(FMC2_CSQCFGR2_RCMD2, NAND_CMD_RNDOUTSTART) | |
798 | FMC2_CSQCFGR2_RCMD1T | |
799 | FMC2_CSQCFGR2_RCMD2T; |
800 | if (!raw) { |
801 | cfg[1] |= write_data ? 0 : FMC2_CSQCFGR2_DMASEN; |
802 | cfg[1] |= FMC2_CSQCFGR2_SQSDTEN; |
803 | } |
804 | |
805 | /* |
806 | * - Set the number of sectors to be written |
807 | * - Set timings |
808 | */ |
809 | cfg[2] = FIELD_PREP(FMC2_CSQCFGR3_SNBR, chip->ecc.steps - 1); |
810 | if (write_data) { |
811 | cfg[2] |= FMC2_CSQCFGR3_RAC2T; |
812 | if (chip->options & NAND_ROW_ADDR_3) |
813 | cfg[2] |= FMC2_CSQCFGR3_AC5T; |
814 | else |
815 | cfg[2] |= FMC2_CSQCFGR3_AC4T; |
816 | } |
817 | |
818 | /* |
819 | * Set the fourth first address cycles |
820 | * Byte 1 and byte 2 => column, we start at 0x0 |
821 | * Byte 3 and byte 4 => page |
822 | */ |
823 | cfg[3] = FIELD_PREP(FMC2_CSQCAR1_ADDC3, page); |
824 | cfg[3] |= FIELD_PREP(FMC2_CSQCAR1_ADDC4, page >> 8); |
825 | |
826 | /* |
827 | * - Set chip enable number |
828 | * - Set ECC byte offset in the spare area |
829 | * - Calculate the number of address cycles to be issued |
830 | * - Set byte 5 of address cycle if needed |
831 | */ |
832 | cfg[4] = FIELD_PREP(FMC2_CSQCAR2_NANDCEN, nfc->cs_sel); |
833 | if (chip->options & NAND_BUSWIDTH_16) |
834 | cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset >> 1); |
835 | else |
836 | cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_SAO, ecc_offset); |
837 | if (chip->options & NAND_ROW_ADDR_3) { |
838 | cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 5); |
839 | cfg[4] |= FIELD_PREP(FMC2_CSQCAR2_ADDC5, page >> 16); |
840 | } else { |
841 | cfg[0] |= FIELD_PREP(FMC2_CSQCFGR1_ACYNBR, 4); |
842 | } |
843 | |
844 | regmap_bulk_write(map: nfc->regmap, FMC2_CSQCFGR1, val: cfg, val_count: 5); |
845 | } |
846 | |
847 | static void stm32_fmc2_nfc_dma_callback(void *arg) |
848 | { |
849 | complete((struct completion *)arg); |
850 | } |
851 | |
852 | /* Read/write data from/to a page */ |
853 | static int stm32_fmc2_nfc_xfer(struct nand_chip *chip, const u8 *buf, |
854 | int raw, bool write_data) |
855 | { |
856 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
857 | struct dma_async_tx_descriptor *desc_data, *desc_ecc; |
858 | struct scatterlist *sg; |
859 | struct dma_chan *dma_ch = nfc->dma_rx_ch; |
860 | enum dma_data_direction dma_data_dir = DMA_FROM_DEVICE; |
861 | enum dma_transfer_direction dma_transfer_dir = DMA_DEV_TO_MEM; |
862 | int eccsteps = chip->ecc.steps; |
863 | int eccsize = chip->ecc.size; |
864 | unsigned long timeout = msecs_to_jiffies(FMC2_TIMEOUT_MS); |
865 | const u8 *p = buf; |
866 | int s, ret; |
867 | |
868 | /* Configure DMA data */ |
869 | if (write_data) { |
870 | dma_data_dir = DMA_TO_DEVICE; |
871 | dma_transfer_dir = DMA_MEM_TO_DEV; |
872 | dma_ch = nfc->dma_tx_ch; |
873 | } |
874 | |
875 | for_each_sg(nfc->dma_data_sg.sgl, sg, eccsteps, s) { |
876 | sg_set_buf(sg, buf: p, buflen: eccsize); |
877 | p += eccsize; |
878 | } |
879 | |
880 | ret = dma_map_sg(nfc->dev, nfc->dma_data_sg.sgl, |
881 | eccsteps, dma_data_dir); |
882 | if (!ret) |
883 | return -EIO; |
884 | |
885 | desc_data = dmaengine_prep_slave_sg(chan: dma_ch, sgl: nfc->dma_data_sg.sgl, |
886 | sg_len: eccsteps, dir: dma_transfer_dir, |
887 | flags: DMA_PREP_INTERRUPT); |
888 | if (!desc_data) { |
889 | ret = -ENOMEM; |
890 | goto err_unmap_data; |
891 | } |
892 | |
893 | reinit_completion(x: &nfc->dma_data_complete); |
894 | reinit_completion(x: &nfc->complete); |
895 | desc_data->callback = stm32_fmc2_nfc_dma_callback; |
896 | desc_data->callback_param = &nfc->dma_data_complete; |
897 | ret = dma_submit_error(cookie: dmaengine_submit(desc: desc_data)); |
898 | if (ret) |
899 | goto err_unmap_data; |
900 | |
901 | dma_async_issue_pending(chan: dma_ch); |
902 | |
903 | if (!write_data && !raw) { |
904 | /* Configure DMA ECC status */ |
905 | p = nfc->ecc_buf; |
906 | for_each_sg(nfc->dma_ecc_sg.sgl, sg, eccsteps, s) { |
907 | sg_set_buf(sg, buf: p, buflen: nfc->dma_ecc_len); |
908 | p += nfc->dma_ecc_len; |
909 | } |
910 | |
911 | ret = dma_map_sg(nfc->dev, nfc->dma_ecc_sg.sgl, |
912 | eccsteps, dma_data_dir); |
913 | if (!ret) { |
914 | ret = -EIO; |
915 | goto err_unmap_data; |
916 | } |
917 | |
918 | desc_ecc = dmaengine_prep_slave_sg(chan: nfc->dma_ecc_ch, |
919 | sgl: nfc->dma_ecc_sg.sgl, |
920 | sg_len: eccsteps, dir: dma_transfer_dir, |
921 | flags: DMA_PREP_INTERRUPT); |
922 | if (!desc_ecc) { |
923 | ret = -ENOMEM; |
924 | goto err_unmap_ecc; |
925 | } |
926 | |
927 | reinit_completion(x: &nfc->dma_ecc_complete); |
928 | desc_ecc->callback = stm32_fmc2_nfc_dma_callback; |
929 | desc_ecc->callback_param = &nfc->dma_ecc_complete; |
930 | ret = dma_submit_error(cookie: dmaengine_submit(desc: desc_ecc)); |
931 | if (ret) |
932 | goto err_unmap_ecc; |
933 | |
934 | dma_async_issue_pending(chan: nfc->dma_ecc_ch); |
935 | } |
936 | |
937 | stm32_fmc2_nfc_clear_seq_irq(nfc); |
938 | stm32_fmc2_nfc_enable_seq_irq(nfc); |
939 | |
940 | /* Start the transfer */ |
941 | regmap_update_bits(map: nfc->regmap, FMC2_CSQCR, |
942 | FMC2_CSQCR_CSQSTART, FMC2_CSQCR_CSQSTART); |
943 | |
944 | /* Wait end of sequencer transfer */ |
945 | if (!wait_for_completion_timeout(x: &nfc->complete, timeout)) { |
946 | dev_err(nfc->dev, "seq timeout\n" ); |
947 | stm32_fmc2_nfc_disable_seq_irq(nfc); |
948 | dmaengine_terminate_all(chan: dma_ch); |
949 | if (!write_data && !raw) |
950 | dmaengine_terminate_all(chan: nfc->dma_ecc_ch); |
951 | ret = -ETIMEDOUT; |
952 | goto err_unmap_ecc; |
953 | } |
954 | |
955 | /* Wait DMA data transfer completion */ |
956 | if (!wait_for_completion_timeout(x: &nfc->dma_data_complete, timeout)) { |
957 | dev_err(nfc->dev, "data DMA timeout\n" ); |
958 | dmaengine_terminate_all(chan: dma_ch); |
959 | ret = -ETIMEDOUT; |
960 | } |
961 | |
962 | /* Wait DMA ECC transfer completion */ |
963 | if (!write_data && !raw) { |
964 | if (!wait_for_completion_timeout(x: &nfc->dma_ecc_complete, |
965 | timeout)) { |
966 | dev_err(nfc->dev, "ECC DMA timeout\n" ); |
967 | dmaengine_terminate_all(chan: nfc->dma_ecc_ch); |
968 | ret = -ETIMEDOUT; |
969 | } |
970 | } |
971 | |
972 | err_unmap_ecc: |
973 | if (!write_data && !raw) |
974 | dma_unmap_sg(nfc->dev, nfc->dma_ecc_sg.sgl, |
975 | eccsteps, dma_data_dir); |
976 | |
977 | err_unmap_data: |
978 | dma_unmap_sg(nfc->dev, nfc->dma_data_sg.sgl, eccsteps, dma_data_dir); |
979 | |
980 | return ret; |
981 | } |
982 | |
983 | static int stm32_fmc2_nfc_seq_write(struct nand_chip *chip, const u8 *buf, |
984 | int oob_required, int page, int raw) |
985 | { |
986 | struct mtd_info *mtd = nand_to_mtd(chip); |
987 | int ret; |
988 | |
989 | /* Configure the sequencer */ |
990 | stm32_fmc2_nfc_rw_page_init(chip, page, raw, write_data: true); |
991 | |
992 | /* Write the page */ |
993 | ret = stm32_fmc2_nfc_xfer(chip, buf, raw, write_data: true); |
994 | if (ret) |
995 | return ret; |
996 | |
997 | /* Write oob */ |
998 | if (oob_required) { |
999 | ret = nand_change_write_column_op(chip, offset_in_page: mtd->writesize, |
1000 | buf: chip->oob_poi, len: mtd->oobsize, |
1001 | force_8bit: false); |
1002 | if (ret) |
1003 | return ret; |
1004 | } |
1005 | |
1006 | return nand_prog_page_end_op(chip); |
1007 | } |
1008 | |
1009 | static int stm32_fmc2_nfc_seq_write_page(struct nand_chip *chip, const u8 *buf, |
1010 | int oob_required, int page) |
1011 | { |
1012 | int ret; |
1013 | |
1014 | ret = stm32_fmc2_nfc_select_chip(chip, chipnr: chip->cur_cs); |
1015 | if (ret) |
1016 | return ret; |
1017 | |
1018 | return stm32_fmc2_nfc_seq_write(chip, buf, oob_required, page, raw: false); |
1019 | } |
1020 | |
1021 | static int stm32_fmc2_nfc_seq_write_page_raw(struct nand_chip *chip, |
1022 | const u8 *buf, int oob_required, |
1023 | int page) |
1024 | { |
1025 | int ret; |
1026 | |
1027 | ret = stm32_fmc2_nfc_select_chip(chip, chipnr: chip->cur_cs); |
1028 | if (ret) |
1029 | return ret; |
1030 | |
1031 | return stm32_fmc2_nfc_seq_write(chip, buf, oob_required, page, raw: true); |
1032 | } |
1033 | |
1034 | /* Get a status indicating which sectors have errors */ |
1035 | static u16 stm32_fmc2_nfc_get_mapping_status(struct stm32_fmc2_nfc *nfc) |
1036 | { |
1037 | u32 csqemsr; |
1038 | |
1039 | regmap_read(map: nfc->regmap, FMC2_CSQEMSR, val: &csqemsr); |
1040 | |
1041 | return FIELD_GET(FMC2_CSQEMSR_SEM, csqemsr); |
1042 | } |
1043 | |
1044 | static int stm32_fmc2_nfc_seq_correct(struct nand_chip *chip, u8 *dat, |
1045 | u8 *read_ecc, u8 *calc_ecc) |
1046 | { |
1047 | struct mtd_info *mtd = nand_to_mtd(chip); |
1048 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
1049 | int eccbytes = chip->ecc.bytes; |
1050 | int eccsteps = chip->ecc.steps; |
1051 | int eccstrength = chip->ecc.strength; |
1052 | int i, s, eccsize = chip->ecc.size; |
1053 | u32 *ecc_sta = (u32 *)nfc->ecc_buf; |
1054 | u16 sta_map = stm32_fmc2_nfc_get_mapping_status(nfc); |
1055 | unsigned int max_bitflips = 0; |
1056 | |
1057 | for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, dat += eccsize) { |
1058 | int stat = 0; |
1059 | |
1060 | if (eccstrength == FMC2_ECC_HAM) { |
1061 | /* Ecc_sta = FMC2_HECCR */ |
1062 | if (sta_map & BIT(s)) { |
1063 | stm32_fmc2_nfc_ham_set_ecc(ecc_sta: *ecc_sta, |
1064 | ecc: &calc_ecc[i]); |
1065 | stat = stm32_fmc2_nfc_ham_correct(chip, dat, |
1066 | read_ecc: &read_ecc[i], |
1067 | calc_ecc: &calc_ecc[i]); |
1068 | } |
1069 | ecc_sta++; |
1070 | } else { |
1071 | /* |
1072 | * Ecc_sta[0] = FMC2_BCHDSR0 |
1073 | * Ecc_sta[1] = FMC2_BCHDSR1 |
1074 | * Ecc_sta[2] = FMC2_BCHDSR2 |
1075 | * Ecc_sta[3] = FMC2_BCHDSR3 |
1076 | * Ecc_sta[4] = FMC2_BCHDSR4 |
1077 | */ |
1078 | if (sta_map & BIT(s)) |
1079 | stat = stm32_fmc2_nfc_bch_decode(eccsize, dat, |
1080 | ecc_sta); |
1081 | ecc_sta += 5; |
1082 | } |
1083 | |
1084 | if (stat == -EBADMSG) |
1085 | /* Check for empty pages with bitflips */ |
1086 | stat = nand_check_erased_ecc_chunk(data: dat, datalen: eccsize, |
1087 | ecc: &read_ecc[i], |
1088 | ecclen: eccbytes, |
1089 | NULL, extraooblen: 0, |
1090 | threshold: eccstrength); |
1091 | |
1092 | if (stat < 0) { |
1093 | mtd->ecc_stats.failed++; |
1094 | } else { |
1095 | mtd->ecc_stats.corrected += stat; |
1096 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
1097 | } |
1098 | } |
1099 | |
1100 | return max_bitflips; |
1101 | } |
1102 | |
1103 | static int stm32_fmc2_nfc_seq_read_page(struct nand_chip *chip, u8 *buf, |
1104 | int oob_required, int page) |
1105 | { |
1106 | struct mtd_info *mtd = nand_to_mtd(chip); |
1107 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
1108 | u8 *ecc_calc = chip->ecc.calc_buf; |
1109 | u8 *ecc_code = chip->ecc.code_buf; |
1110 | u16 sta_map; |
1111 | int ret; |
1112 | |
1113 | ret = stm32_fmc2_nfc_select_chip(chip, chipnr: chip->cur_cs); |
1114 | if (ret) |
1115 | return ret; |
1116 | |
1117 | /* Configure the sequencer */ |
1118 | stm32_fmc2_nfc_rw_page_init(chip, page, raw: 0, write_data: false); |
1119 | |
1120 | /* Read the page */ |
1121 | ret = stm32_fmc2_nfc_xfer(chip, buf, raw: 0, write_data: false); |
1122 | if (ret) |
1123 | return ret; |
1124 | |
1125 | sta_map = stm32_fmc2_nfc_get_mapping_status(nfc); |
1126 | |
1127 | /* Check if errors happen */ |
1128 | if (likely(!sta_map)) { |
1129 | if (oob_required) |
1130 | return nand_change_read_column_op(chip, offset_in_page: mtd->writesize, |
1131 | buf: chip->oob_poi, |
1132 | len: mtd->oobsize, force_8bit: false); |
1133 | |
1134 | return 0; |
1135 | } |
1136 | |
1137 | /* Read oob */ |
1138 | ret = nand_change_read_column_op(chip, offset_in_page: mtd->writesize, |
1139 | buf: chip->oob_poi, len: mtd->oobsize, force_8bit: false); |
1140 | if (ret) |
1141 | return ret; |
1142 | |
1143 | ret = mtd_ooblayout_get_eccbytes(mtd, eccbuf: ecc_code, oobbuf: chip->oob_poi, start: 0, |
1144 | nbytes: chip->ecc.total); |
1145 | if (ret) |
1146 | return ret; |
1147 | |
1148 | /* Correct data */ |
1149 | return chip->ecc.correct(chip, buf, ecc_code, ecc_calc); |
1150 | } |
1151 | |
1152 | static int stm32_fmc2_nfc_seq_read_page_raw(struct nand_chip *chip, u8 *buf, |
1153 | int oob_required, int page) |
1154 | { |
1155 | struct mtd_info *mtd = nand_to_mtd(chip); |
1156 | int ret; |
1157 | |
1158 | ret = stm32_fmc2_nfc_select_chip(chip, chipnr: chip->cur_cs); |
1159 | if (ret) |
1160 | return ret; |
1161 | |
1162 | /* Configure the sequencer */ |
1163 | stm32_fmc2_nfc_rw_page_init(chip, page, raw: 1, write_data: false); |
1164 | |
1165 | /* Read the page */ |
1166 | ret = stm32_fmc2_nfc_xfer(chip, buf, raw: 1, write_data: false); |
1167 | if (ret) |
1168 | return ret; |
1169 | |
1170 | /* Read oob */ |
1171 | if (oob_required) |
1172 | return nand_change_read_column_op(chip, offset_in_page: mtd->writesize, |
1173 | buf: chip->oob_poi, len: mtd->oobsize, |
1174 | force_8bit: false); |
1175 | |
1176 | return 0; |
1177 | } |
1178 | |
1179 | static irqreturn_t stm32_fmc2_nfc_irq(int irq, void *dev_id) |
1180 | { |
1181 | struct stm32_fmc2_nfc *nfc = (struct stm32_fmc2_nfc *)dev_id; |
1182 | |
1183 | if (nfc->irq_state == FMC2_IRQ_SEQ) |
1184 | /* Sequencer is used */ |
1185 | stm32_fmc2_nfc_disable_seq_irq(nfc); |
1186 | else if (nfc->irq_state == FMC2_IRQ_BCH) |
1187 | /* BCH is used */ |
1188 | stm32_fmc2_nfc_disable_bch_irq(nfc); |
1189 | |
1190 | complete(&nfc->complete); |
1191 | |
1192 | return IRQ_HANDLED; |
1193 | } |
1194 | |
1195 | static void stm32_fmc2_nfc_read_data(struct nand_chip *chip, void *buf, |
1196 | unsigned int len, bool force_8bit) |
1197 | { |
1198 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
1199 | void __iomem *io_addr_r = nfc->data_base[nfc->cs_sel]; |
1200 | |
1201 | if (force_8bit && chip->options & NAND_BUSWIDTH_16) |
1202 | /* Reconfigure bus width to 8-bit */ |
1203 | stm32_fmc2_nfc_set_buswidth_16(nfc, set: false); |
1204 | |
1205 | if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) { |
1206 | if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) { |
1207 | *(u8 *)buf = readb_relaxed(io_addr_r); |
1208 | buf += sizeof(u8); |
1209 | len -= sizeof(u8); |
1210 | } |
1211 | |
1212 | if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) && |
1213 | len >= sizeof(u16)) { |
1214 | *(u16 *)buf = readw_relaxed(io_addr_r); |
1215 | buf += sizeof(u16); |
1216 | len -= sizeof(u16); |
1217 | } |
1218 | } |
1219 | |
1220 | /* Buf is aligned */ |
1221 | while (len >= sizeof(u32)) { |
1222 | *(u32 *)buf = readl_relaxed(io_addr_r); |
1223 | buf += sizeof(u32); |
1224 | len -= sizeof(u32); |
1225 | } |
1226 | |
1227 | /* Read remaining bytes */ |
1228 | if (len >= sizeof(u16)) { |
1229 | *(u16 *)buf = readw_relaxed(io_addr_r); |
1230 | buf += sizeof(u16); |
1231 | len -= sizeof(u16); |
1232 | } |
1233 | |
1234 | if (len) |
1235 | *(u8 *)buf = readb_relaxed(io_addr_r); |
1236 | |
1237 | if (force_8bit && chip->options & NAND_BUSWIDTH_16) |
1238 | /* Reconfigure bus width to 16-bit */ |
1239 | stm32_fmc2_nfc_set_buswidth_16(nfc, set: true); |
1240 | } |
1241 | |
1242 | static void stm32_fmc2_nfc_write_data(struct nand_chip *chip, const void *buf, |
1243 | unsigned int len, bool force_8bit) |
1244 | { |
1245 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
1246 | void __iomem *io_addr_w = nfc->data_base[nfc->cs_sel]; |
1247 | |
1248 | if (force_8bit && chip->options & NAND_BUSWIDTH_16) |
1249 | /* Reconfigure bus width to 8-bit */ |
1250 | stm32_fmc2_nfc_set_buswidth_16(nfc, set: false); |
1251 | |
1252 | if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32))) { |
1253 | if (!IS_ALIGNED((uintptr_t)buf, sizeof(u16)) && len) { |
1254 | writeb_relaxed(*(u8 *)buf, io_addr_w); |
1255 | buf += sizeof(u8); |
1256 | len -= sizeof(u8); |
1257 | } |
1258 | |
1259 | if (!IS_ALIGNED((uintptr_t)buf, sizeof(u32)) && |
1260 | len >= sizeof(u16)) { |
1261 | writew_relaxed(*(u16 *)buf, io_addr_w); |
1262 | buf += sizeof(u16); |
1263 | len -= sizeof(u16); |
1264 | } |
1265 | } |
1266 | |
1267 | /* Buf is aligned */ |
1268 | while (len >= sizeof(u32)) { |
1269 | writel_relaxed(*(u32 *)buf, io_addr_w); |
1270 | buf += sizeof(u32); |
1271 | len -= sizeof(u32); |
1272 | } |
1273 | |
1274 | /* Write remaining bytes */ |
1275 | if (len >= sizeof(u16)) { |
1276 | writew_relaxed(*(u16 *)buf, io_addr_w); |
1277 | buf += sizeof(u16); |
1278 | len -= sizeof(u16); |
1279 | } |
1280 | |
1281 | if (len) |
1282 | writeb_relaxed(*(u8 *)buf, io_addr_w); |
1283 | |
1284 | if (force_8bit && chip->options & NAND_BUSWIDTH_16) |
1285 | /* Reconfigure bus width to 16-bit */ |
1286 | stm32_fmc2_nfc_set_buswidth_16(nfc, set: true); |
1287 | } |
1288 | |
1289 | static int stm32_fmc2_nfc_waitrdy(struct nand_chip *chip, |
1290 | unsigned long timeout_ms) |
1291 | { |
1292 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
1293 | const struct nand_sdr_timings *timings; |
1294 | u32 isr, sr; |
1295 | |
1296 | /* Check if there is no pending requests to the NAND flash */ |
1297 | if (regmap_read_poll_timeout(nfc->regmap, FMC2_SR, sr, |
1298 | sr & FMC2_SR_NWRF, 1, |
1299 | 1000 * FMC2_TIMEOUT_MS)) |
1300 | dev_warn(nfc->dev, "Waitrdy timeout\n" ); |
1301 | |
1302 | /* Wait tWB before R/B# signal is low */ |
1303 | timings = nand_get_sdr_timings(conf: nand_get_interface_config(chip)); |
1304 | ndelay(PSEC_TO_NSEC(timings->tWB_max)); |
1305 | |
1306 | /* R/B# signal is low, clear high level flag */ |
1307 | regmap_write(map: nfc->regmap, FMC2_ICR, FMC2_ICR_CIHLF); |
1308 | |
1309 | /* Wait R/B# signal is high */ |
1310 | return regmap_read_poll_timeout(nfc->regmap, FMC2_ISR, isr, |
1311 | isr & FMC2_ISR_IHLF, 5, |
1312 | 1000 * FMC2_TIMEOUT_MS); |
1313 | } |
1314 | |
1315 | static int stm32_fmc2_nfc_exec_op(struct nand_chip *chip, |
1316 | const struct nand_operation *op, |
1317 | bool check_only) |
1318 | { |
1319 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
1320 | const struct nand_op_instr *instr = NULL; |
1321 | unsigned int op_id, i, timeout; |
1322 | int ret; |
1323 | |
1324 | if (check_only) |
1325 | return 0; |
1326 | |
1327 | ret = stm32_fmc2_nfc_select_chip(chip, chipnr: op->cs); |
1328 | if (ret) |
1329 | return ret; |
1330 | |
1331 | for (op_id = 0; op_id < op->ninstrs; op_id++) { |
1332 | instr = &op->instrs[op_id]; |
1333 | |
1334 | switch (instr->type) { |
1335 | case NAND_OP_CMD_INSTR: |
1336 | writeb_relaxed(instr->ctx.cmd.opcode, |
1337 | nfc->cmd_base[nfc->cs_sel]); |
1338 | break; |
1339 | |
1340 | case NAND_OP_ADDR_INSTR: |
1341 | for (i = 0; i < instr->ctx.addr.naddrs; i++) |
1342 | writeb_relaxed(instr->ctx.addr.addrs[i], |
1343 | nfc->addr_base[nfc->cs_sel]); |
1344 | break; |
1345 | |
1346 | case NAND_OP_DATA_IN_INSTR: |
1347 | stm32_fmc2_nfc_read_data(chip, buf: instr->ctx.data.buf.in, |
1348 | len: instr->ctx.data.len, |
1349 | force_8bit: instr->ctx.data.force_8bit); |
1350 | break; |
1351 | |
1352 | case NAND_OP_DATA_OUT_INSTR: |
1353 | stm32_fmc2_nfc_write_data(chip, buf: instr->ctx.data.buf.out, |
1354 | len: instr->ctx.data.len, |
1355 | force_8bit: instr->ctx.data.force_8bit); |
1356 | break; |
1357 | |
1358 | case NAND_OP_WAITRDY_INSTR: |
1359 | timeout = instr->ctx.waitrdy.timeout_ms; |
1360 | ret = stm32_fmc2_nfc_waitrdy(chip, timeout_ms: timeout); |
1361 | break; |
1362 | } |
1363 | } |
1364 | |
1365 | return ret; |
1366 | } |
1367 | |
1368 | static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc) |
1369 | { |
1370 | u32 pcr; |
1371 | |
1372 | regmap_read(map: nfc->regmap, FMC2_PCR, val: &pcr); |
1373 | |
1374 | /* Set CS used to undefined */ |
1375 | nfc->cs_sel = -1; |
1376 | |
1377 | /* Enable wait feature and nand flash memory bank */ |
1378 | pcr |= FMC2_PCR_PWAITEN; |
1379 | pcr |= FMC2_PCR_PBKEN; |
1380 | |
1381 | /* Set buswidth to 8 bits mode for identification */ |
1382 | pcr &= ~FMC2_PCR_PWID; |
1383 | |
1384 | /* ECC logic is disabled */ |
1385 | pcr &= ~FMC2_PCR_ECCEN; |
1386 | |
1387 | /* Default mode */ |
1388 | pcr &= ~FMC2_PCR_ECCALG; |
1389 | pcr &= ~FMC2_PCR_BCHECC; |
1390 | pcr &= ~FMC2_PCR_WEN; |
1391 | |
1392 | /* Set default ECC sector size */ |
1393 | pcr &= ~FMC2_PCR_ECCSS; |
1394 | pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048); |
1395 | |
1396 | /* Set default tclr/tar timings */ |
1397 | pcr &= ~FMC2_PCR_TCLR; |
1398 | pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT); |
1399 | pcr &= ~FMC2_PCR_TAR; |
1400 | pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT); |
1401 | |
1402 | /* Enable FMC2 controller */ |
1403 | if (nfc->dev == nfc->cdev) |
1404 | regmap_update_bits(map: nfc->regmap, FMC2_BCR1, |
1405 | FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN); |
1406 | |
1407 | regmap_write(map: nfc->regmap, FMC2_PCR, val: pcr); |
1408 | regmap_write(map: nfc->regmap, FMC2_PMEM, FMC2_PMEM_DEFAULT); |
1409 | regmap_write(map: nfc->regmap, FMC2_PATT, FMC2_PATT_DEFAULT); |
1410 | } |
1411 | |
1412 | static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip, |
1413 | const struct nand_sdr_timings *sdrt) |
1414 | { |
1415 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
1416 | struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); |
1417 | struct stm32_fmc2_timings *tims = &nand->timings; |
1418 | unsigned long hclk = clk_get_rate(clk: nfc->clk); |
1419 | unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000); |
1420 | unsigned long timing, tar, tclr, thiz, twait; |
1421 | unsigned long tset_mem, tset_att, thold_mem, thold_att; |
1422 | |
1423 | tar = max_t(unsigned long, hclkp, sdrt->tAR_min); |
1424 | timing = DIV_ROUND_UP(tar, hclkp) - 1; |
1425 | tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK); |
1426 | |
1427 | tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min); |
1428 | timing = DIV_ROUND_UP(tclr, hclkp) - 1; |
1429 | tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK); |
1430 | |
1431 | tims->thiz = FMC2_THIZ; |
1432 | thiz = (tims->thiz + 1) * hclkp; |
1433 | |
1434 | /* |
1435 | * tWAIT > tRP |
1436 | * tWAIT > tWP |
1437 | * tWAIT > tREA + tIO |
1438 | */ |
1439 | twait = max_t(unsigned long, hclkp, sdrt->tRP_min); |
1440 | twait = max_t(unsigned long, twait, sdrt->tWP_min); |
1441 | twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO); |
1442 | timing = DIV_ROUND_UP(twait, hclkp); |
1443 | tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); |
1444 | |
1445 | /* |
1446 | * tSETUP_MEM > tCS - tWAIT |
1447 | * tSETUP_MEM > tALS - tWAIT |
1448 | * tSETUP_MEM > tDS - (tWAIT - tHIZ) |
1449 | */ |
1450 | tset_mem = hclkp; |
1451 | if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait)) |
1452 | tset_mem = sdrt->tCS_min - twait; |
1453 | if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait)) |
1454 | tset_mem = sdrt->tALS_min - twait; |
1455 | if (twait > thiz && (sdrt->tDS_min > twait - thiz) && |
1456 | (tset_mem < sdrt->tDS_min - (twait - thiz))) |
1457 | tset_mem = sdrt->tDS_min - (twait - thiz); |
1458 | timing = DIV_ROUND_UP(tset_mem, hclkp); |
1459 | tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); |
1460 | |
1461 | /* |
1462 | * tHOLD_MEM > tCH |
1463 | * tHOLD_MEM > tREH - tSETUP_MEM |
1464 | * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT) |
1465 | */ |
1466 | thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min); |
1467 | if (sdrt->tREH_min > tset_mem && |
1468 | (thold_mem < sdrt->tREH_min - tset_mem)) |
1469 | thold_mem = sdrt->tREH_min - tset_mem; |
1470 | if ((sdrt->tRC_min > tset_mem + twait) && |
1471 | (thold_mem < sdrt->tRC_min - (tset_mem + twait))) |
1472 | thold_mem = sdrt->tRC_min - (tset_mem + twait); |
1473 | if ((sdrt->tWC_min > tset_mem + twait) && |
1474 | (thold_mem < sdrt->tWC_min - (tset_mem + twait))) |
1475 | thold_mem = sdrt->tWC_min - (tset_mem + twait); |
1476 | timing = DIV_ROUND_UP(thold_mem, hclkp); |
1477 | tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); |
1478 | |
1479 | /* |
1480 | * tSETUP_ATT > tCS - tWAIT |
1481 | * tSETUP_ATT > tCLS - tWAIT |
1482 | * tSETUP_ATT > tALS - tWAIT |
1483 | * tSETUP_ATT > tRHW - tHOLD_MEM |
1484 | * tSETUP_ATT > tDS - (tWAIT - tHIZ) |
1485 | */ |
1486 | tset_att = hclkp; |
1487 | if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait)) |
1488 | tset_att = sdrt->tCS_min - twait; |
1489 | if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait)) |
1490 | tset_att = sdrt->tCLS_min - twait; |
1491 | if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait)) |
1492 | tset_att = sdrt->tALS_min - twait; |
1493 | if (sdrt->tRHW_min > thold_mem && |
1494 | (tset_att < sdrt->tRHW_min - thold_mem)) |
1495 | tset_att = sdrt->tRHW_min - thold_mem; |
1496 | if (twait > thiz && (sdrt->tDS_min > twait - thiz) && |
1497 | (tset_att < sdrt->tDS_min - (twait - thiz))) |
1498 | tset_att = sdrt->tDS_min - (twait - thiz); |
1499 | timing = DIV_ROUND_UP(tset_att, hclkp); |
1500 | tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); |
1501 | |
1502 | /* |
1503 | * tHOLD_ATT > tALH |
1504 | * tHOLD_ATT > tCH |
1505 | * tHOLD_ATT > tCLH |
1506 | * tHOLD_ATT > tCOH |
1507 | * tHOLD_ATT > tDH |
1508 | * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM |
1509 | * tHOLD_ATT > tADL - tSETUP_MEM |
1510 | * tHOLD_ATT > tWH - tSETUP_MEM |
1511 | * tHOLD_ATT > tWHR - tSETUP_MEM |
1512 | * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT) |
1513 | * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT) |
1514 | */ |
1515 | thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min); |
1516 | thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min); |
1517 | thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min); |
1518 | thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min); |
1519 | thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min); |
1520 | if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) && |
1521 | (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem)) |
1522 | thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem; |
1523 | if (sdrt->tADL_min > tset_mem && |
1524 | (thold_att < sdrt->tADL_min - tset_mem)) |
1525 | thold_att = sdrt->tADL_min - tset_mem; |
1526 | if (sdrt->tWH_min > tset_mem && |
1527 | (thold_att < sdrt->tWH_min - tset_mem)) |
1528 | thold_att = sdrt->tWH_min - tset_mem; |
1529 | if (sdrt->tWHR_min > tset_mem && |
1530 | (thold_att < sdrt->tWHR_min - tset_mem)) |
1531 | thold_att = sdrt->tWHR_min - tset_mem; |
1532 | if ((sdrt->tRC_min > tset_att + twait) && |
1533 | (thold_att < sdrt->tRC_min - (tset_att + twait))) |
1534 | thold_att = sdrt->tRC_min - (tset_att + twait); |
1535 | if ((sdrt->tWC_min > tset_att + twait) && |
1536 | (thold_att < sdrt->tWC_min - (tset_att + twait))) |
1537 | thold_att = sdrt->tWC_min - (tset_att + twait); |
1538 | timing = DIV_ROUND_UP(thold_att, hclkp); |
1539 | tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); |
1540 | } |
1541 | |
1542 | static int stm32_fmc2_nfc_setup_interface(struct nand_chip *chip, int chipnr, |
1543 | const struct nand_interface_config *conf) |
1544 | { |
1545 | const struct nand_sdr_timings *sdrt; |
1546 | |
1547 | sdrt = nand_get_sdr_timings(conf); |
1548 | if (IS_ERR(ptr: sdrt)) |
1549 | return PTR_ERR(ptr: sdrt); |
1550 | |
1551 | if (conf->timings.mode > 3) |
1552 | return -EOPNOTSUPP; |
1553 | |
1554 | if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) |
1555 | return 0; |
1556 | |
1557 | stm32_fmc2_nfc_calc_timings(chip, sdrt); |
1558 | stm32_fmc2_nfc_timings_init(chip); |
1559 | |
1560 | return 0; |
1561 | } |
1562 | |
1563 | static int stm32_fmc2_nfc_dma_setup(struct stm32_fmc2_nfc *nfc) |
1564 | { |
1565 | struct dma_slave_caps caps; |
1566 | int ret = 0; |
1567 | |
1568 | nfc->dma_tx_ch = dma_request_chan(dev: nfc->dev, name: "tx" ); |
1569 | if (IS_ERR(ptr: nfc->dma_tx_ch)) { |
1570 | ret = PTR_ERR(ptr: nfc->dma_tx_ch); |
1571 | if (ret != -ENODEV && ret != -EPROBE_DEFER) |
1572 | dev_err(nfc->dev, |
1573 | "failed to request tx DMA channel: %d\n" , ret); |
1574 | nfc->dma_tx_ch = NULL; |
1575 | goto err_dma; |
1576 | } |
1577 | |
1578 | ret = dma_get_slave_caps(chan: nfc->dma_tx_ch, caps: &caps); |
1579 | if (ret) |
1580 | return ret; |
1581 | nfc->tx_dma_max_burst = caps.max_burst; |
1582 | |
1583 | nfc->dma_rx_ch = dma_request_chan(dev: nfc->dev, name: "rx" ); |
1584 | if (IS_ERR(ptr: nfc->dma_rx_ch)) { |
1585 | ret = PTR_ERR(ptr: nfc->dma_rx_ch); |
1586 | if (ret != -ENODEV && ret != -EPROBE_DEFER) |
1587 | dev_err(nfc->dev, |
1588 | "failed to request rx DMA channel: %d\n" , ret); |
1589 | nfc->dma_rx_ch = NULL; |
1590 | goto err_dma; |
1591 | } |
1592 | |
1593 | ret = dma_get_slave_caps(chan: nfc->dma_rx_ch, caps: &caps); |
1594 | if (ret) |
1595 | return ret; |
1596 | nfc->rx_dma_max_burst = caps.max_burst; |
1597 | |
1598 | nfc->dma_ecc_ch = dma_request_chan(dev: nfc->dev, name: "ecc" ); |
1599 | if (IS_ERR(ptr: nfc->dma_ecc_ch)) { |
1600 | ret = PTR_ERR(ptr: nfc->dma_ecc_ch); |
1601 | if (ret != -ENODEV && ret != -EPROBE_DEFER) |
1602 | dev_err(nfc->dev, |
1603 | "failed to request ecc DMA channel: %d\n" , ret); |
1604 | nfc->dma_ecc_ch = NULL; |
1605 | goto err_dma; |
1606 | } |
1607 | |
1608 | ret = sg_alloc_table(&nfc->dma_ecc_sg, FMC2_MAX_SG, GFP_KERNEL); |
1609 | if (ret) |
1610 | return ret; |
1611 | |
1612 | /* Allocate a buffer to store ECC status registers */ |
1613 | nfc->ecc_buf = devm_kzalloc(dev: nfc->dev, FMC2_MAX_ECC_BUF_LEN, GFP_KERNEL); |
1614 | if (!nfc->ecc_buf) |
1615 | return -ENOMEM; |
1616 | |
1617 | ret = sg_alloc_table(&nfc->dma_data_sg, FMC2_MAX_SG, GFP_KERNEL); |
1618 | if (ret) |
1619 | return ret; |
1620 | |
1621 | init_completion(x: &nfc->dma_data_complete); |
1622 | init_completion(x: &nfc->dma_ecc_complete); |
1623 | |
1624 | return 0; |
1625 | |
1626 | err_dma: |
1627 | if (ret == -ENODEV) { |
1628 | dev_warn(nfc->dev, |
1629 | "DMAs not defined in the DT, polling mode is used\n" ); |
1630 | ret = 0; |
1631 | } |
1632 | |
1633 | return ret; |
1634 | } |
1635 | |
1636 | static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip) |
1637 | { |
1638 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
1639 | |
1640 | /* |
1641 | * Specific callbacks to read/write a page depending on |
1642 | * the mode (polling/sequencer) and the algo used (Hamming, BCH). |
1643 | */ |
1644 | if (nfc->dma_tx_ch && nfc->dma_rx_ch && nfc->dma_ecc_ch) { |
1645 | /* DMA => use sequencer mode callbacks */ |
1646 | chip->ecc.correct = stm32_fmc2_nfc_seq_correct; |
1647 | chip->ecc.write_page = stm32_fmc2_nfc_seq_write_page; |
1648 | chip->ecc.read_page = stm32_fmc2_nfc_seq_read_page; |
1649 | chip->ecc.write_page_raw = stm32_fmc2_nfc_seq_write_page_raw; |
1650 | chip->ecc.read_page_raw = stm32_fmc2_nfc_seq_read_page_raw; |
1651 | } else { |
1652 | /* No DMA => use polling mode callbacks */ |
1653 | chip->ecc.hwctl = stm32_fmc2_nfc_hwctl; |
1654 | if (chip->ecc.strength == FMC2_ECC_HAM) { |
1655 | /* Hamming is used */ |
1656 | chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate; |
1657 | chip->ecc.correct = stm32_fmc2_nfc_ham_correct; |
1658 | chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK; |
1659 | } else { |
1660 | /* BCH is used */ |
1661 | chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate; |
1662 | chip->ecc.correct = stm32_fmc2_nfc_bch_correct; |
1663 | chip->ecc.read_page = stm32_fmc2_nfc_read_page; |
1664 | } |
1665 | } |
1666 | |
1667 | /* Specific configurations depending on the algo used */ |
1668 | if (chip->ecc.strength == FMC2_ECC_HAM) |
1669 | chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3; |
1670 | else if (chip->ecc.strength == FMC2_ECC_BCH8) |
1671 | chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13; |
1672 | else |
1673 | chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7; |
1674 | } |
1675 | |
1676 | static int stm32_fmc2_nfc_ooblayout_ecc(struct mtd_info *mtd, int section, |
1677 | struct mtd_oob_region *oobregion) |
1678 | { |
1679 | struct nand_chip *chip = mtd_to_nand(mtd); |
1680 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
1681 | |
1682 | if (section) |
1683 | return -ERANGE; |
1684 | |
1685 | oobregion->length = ecc->total; |
1686 | oobregion->offset = FMC2_BBM_LEN; |
1687 | |
1688 | return 0; |
1689 | } |
1690 | |
1691 | static int stm32_fmc2_nfc_ooblayout_free(struct mtd_info *mtd, int section, |
1692 | struct mtd_oob_region *oobregion) |
1693 | { |
1694 | struct nand_chip *chip = mtd_to_nand(mtd); |
1695 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
1696 | |
1697 | if (section) |
1698 | return -ERANGE; |
1699 | |
1700 | oobregion->length = mtd->oobsize - ecc->total - FMC2_BBM_LEN; |
1701 | oobregion->offset = ecc->total + FMC2_BBM_LEN; |
1702 | |
1703 | return 0; |
1704 | } |
1705 | |
1706 | static const struct mtd_ooblayout_ops stm32_fmc2_nfc_ooblayout_ops = { |
1707 | .ecc = stm32_fmc2_nfc_ooblayout_ecc, |
1708 | .free = stm32_fmc2_nfc_ooblayout_free, |
1709 | }; |
1710 | |
1711 | static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength) |
1712 | { |
1713 | /* Hamming */ |
1714 | if (strength == FMC2_ECC_HAM) |
1715 | return 4; |
1716 | |
1717 | /* BCH8 */ |
1718 | if (strength == FMC2_ECC_BCH8) |
1719 | return 14; |
1720 | |
1721 | /* BCH4 */ |
1722 | return 8; |
1723 | } |
1724 | |
1725 | NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes, |
1726 | FMC2_ECC_STEP_SIZE, |
1727 | FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8); |
1728 | |
1729 | static int stm32_fmc2_nfc_attach_chip(struct nand_chip *chip) |
1730 | { |
1731 | struct stm32_fmc2_nfc *nfc = to_stm32_nfc(base: chip->controller); |
1732 | struct mtd_info *mtd = nand_to_mtd(chip); |
1733 | int ret; |
1734 | |
1735 | /* |
1736 | * Only NAND_ECC_ENGINE_TYPE_ON_HOST mode is actually supported |
1737 | * Hamming => ecc.strength = 1 |
1738 | * BCH4 => ecc.strength = 4 |
1739 | * BCH8 => ecc.strength = 8 |
1740 | * ECC sector size = 512 |
1741 | */ |
1742 | if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) { |
1743 | dev_err(nfc->dev, |
1744 | "nand_ecc_engine_type is not well defined in the DT\n" ); |
1745 | return -EINVAL; |
1746 | } |
1747 | |
1748 | /* Default ECC settings in case they are not set in the device tree */ |
1749 | if (!chip->ecc.size) |
1750 | chip->ecc.size = FMC2_ECC_STEP_SIZE; |
1751 | |
1752 | if (!chip->ecc.strength) |
1753 | chip->ecc.strength = FMC2_ECC_BCH8; |
1754 | |
1755 | ret = nand_ecc_choose_conf(chip, caps: &stm32_fmc2_nfc_ecc_caps, |
1756 | oobavail: mtd->oobsize - FMC2_BBM_LEN); |
1757 | if (ret) { |
1758 | dev_err(nfc->dev, "no valid ECC settings set\n" ); |
1759 | return ret; |
1760 | } |
1761 | |
1762 | if (mtd->writesize / chip->ecc.size > FMC2_MAX_SG) { |
1763 | dev_err(nfc->dev, "nand page size is not supported\n" ); |
1764 | return -EINVAL; |
1765 | } |
1766 | |
1767 | if (chip->bbt_options & NAND_BBT_USE_FLASH) |
1768 | chip->bbt_options |= NAND_BBT_NO_OOB; |
1769 | |
1770 | stm32_fmc2_nfc_nand_callbacks_setup(chip); |
1771 | |
1772 | mtd_set_ooblayout(mtd, ooblayout: &stm32_fmc2_nfc_ooblayout_ops); |
1773 | |
1774 | stm32_fmc2_nfc_setup(chip); |
1775 | |
1776 | return 0; |
1777 | } |
1778 | |
1779 | static const struct nand_controller_ops stm32_fmc2_nfc_controller_ops = { |
1780 | .attach_chip = stm32_fmc2_nfc_attach_chip, |
1781 | .exec_op = stm32_fmc2_nfc_exec_op, |
1782 | .setup_interface = stm32_fmc2_nfc_setup_interface, |
1783 | }; |
1784 | |
1785 | static void stm32_fmc2_nfc_wp_enable(struct stm32_fmc2_nand *nand) |
1786 | { |
1787 | if (nand->wp_gpio) |
1788 | gpiod_set_value(desc: nand->wp_gpio, value: 1); |
1789 | } |
1790 | |
1791 | static void stm32_fmc2_nfc_wp_disable(struct stm32_fmc2_nand *nand) |
1792 | { |
1793 | if (nand->wp_gpio) |
1794 | gpiod_set_value(desc: nand->wp_gpio, value: 0); |
1795 | } |
1796 | |
1797 | static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, |
1798 | struct device_node *dn) |
1799 | { |
1800 | struct stm32_fmc2_nand *nand = &nfc->nand; |
1801 | u32 cs; |
1802 | int ret, i; |
1803 | |
1804 | if (!of_get_property(node: dn, name: "reg" , lenp: &nand->ncs)) |
1805 | return -EINVAL; |
1806 | |
1807 | nand->ncs /= sizeof(u32); |
1808 | if (!nand->ncs) { |
1809 | dev_err(nfc->dev, "invalid reg property size\n" ); |
1810 | return -EINVAL; |
1811 | } |
1812 | |
1813 | for (i = 0; i < nand->ncs; i++) { |
1814 | ret = of_property_read_u32_index(np: dn, propname: "reg" , index: i, out_value: &cs); |
1815 | if (ret) { |
1816 | dev_err(nfc->dev, "could not retrieve reg property: %d\n" , |
1817 | ret); |
1818 | return ret; |
1819 | } |
1820 | |
1821 | if (cs >= nfc->data->max_ncs) { |
1822 | dev_err(nfc->dev, "invalid reg value: %d\n" , cs); |
1823 | return -EINVAL; |
1824 | } |
1825 | |
1826 | if (nfc->cs_assigned & BIT(cs)) { |
1827 | dev_err(nfc->dev, "cs already assigned: %d\n" , cs); |
1828 | return -EINVAL; |
1829 | } |
1830 | |
1831 | nfc->cs_assigned |= BIT(cs); |
1832 | nand->cs_used[i] = cs; |
1833 | } |
1834 | |
1835 | nand->wp_gpio = devm_fwnode_gpiod_get(dev: nfc->dev, of_fwnode_handle(dn), |
1836 | con_id: "wp" , flags: GPIOD_OUT_HIGH, label: "wp" ); |
1837 | if (IS_ERR(ptr: nand->wp_gpio)) { |
1838 | ret = PTR_ERR(ptr: nand->wp_gpio); |
1839 | if (ret != -ENOENT) |
1840 | return dev_err_probe(dev: nfc->dev, err: ret, |
1841 | fmt: "failed to request WP GPIO\n" ); |
1842 | |
1843 | nand->wp_gpio = NULL; |
1844 | } |
1845 | |
1846 | nand_set_flash_node(chip: &nand->chip, np: dn); |
1847 | |
1848 | return 0; |
1849 | } |
1850 | |
1851 | static int stm32_fmc2_nfc_parse_dt(struct stm32_fmc2_nfc *nfc) |
1852 | { |
1853 | struct device_node *dn = nfc->dev->of_node; |
1854 | struct device_node *child; |
1855 | int nchips = of_get_child_count(np: dn); |
1856 | int ret = 0; |
1857 | |
1858 | if (!nchips) { |
1859 | dev_err(nfc->dev, "NAND chip not defined\n" ); |
1860 | return -EINVAL; |
1861 | } |
1862 | |
1863 | if (nchips > 1) { |
1864 | dev_err(nfc->dev, "too many NAND chips defined\n" ); |
1865 | return -EINVAL; |
1866 | } |
1867 | |
1868 | for_each_child_of_node(dn, child) { |
1869 | ret = stm32_fmc2_nfc_parse_child(nfc, dn: child); |
1870 | if (ret < 0) { |
1871 | of_node_put(node: child); |
1872 | return ret; |
1873 | } |
1874 | } |
1875 | |
1876 | return ret; |
1877 | } |
1878 | |
1879 | static int stm32_fmc2_nfc_set_cdev(struct stm32_fmc2_nfc *nfc) |
1880 | { |
1881 | struct device *dev = nfc->dev; |
1882 | bool ebi_found = false; |
1883 | |
1884 | if (dev->parent && of_device_is_compatible(device: dev->parent->of_node, |
1885 | "st,stm32mp1-fmc2-ebi" )) |
1886 | ebi_found = true; |
1887 | |
1888 | if (of_device_is_compatible(device: dev->of_node, "st,stm32mp1-fmc2-nfc" )) { |
1889 | if (ebi_found) { |
1890 | nfc->cdev = dev->parent; |
1891 | |
1892 | return 0; |
1893 | } |
1894 | |
1895 | return -EINVAL; |
1896 | } |
1897 | |
1898 | if (ebi_found) |
1899 | return -EINVAL; |
1900 | |
1901 | nfc->cdev = dev; |
1902 | |
1903 | return 0; |
1904 | } |
1905 | |
1906 | static int stm32_fmc2_nfc_probe(struct platform_device *pdev) |
1907 | { |
1908 | struct device *dev = &pdev->dev; |
1909 | struct reset_control *rstc; |
1910 | struct stm32_fmc2_nfc *nfc; |
1911 | struct stm32_fmc2_nand *nand; |
1912 | struct resource *res; |
1913 | struct mtd_info *mtd; |
1914 | struct nand_chip *chip; |
1915 | struct resource cres; |
1916 | int chip_cs, mem_region, ret, irq; |
1917 | int start_region = 0; |
1918 | |
1919 | nfc = devm_kzalloc(dev, size: sizeof(*nfc), GFP_KERNEL); |
1920 | if (!nfc) |
1921 | return -ENOMEM; |
1922 | |
1923 | nfc->dev = dev; |
1924 | nand_controller_init(nfc: &nfc->base); |
1925 | nfc->base.ops = &stm32_fmc2_nfc_controller_ops; |
1926 | |
1927 | nfc->data = of_device_get_match_data(dev); |
1928 | if (!nfc->data) |
1929 | return -EINVAL; |
1930 | |
1931 | if (nfc->data->set_cdev) { |
1932 | ret = nfc->data->set_cdev(nfc); |
1933 | if (ret) |
1934 | return ret; |
1935 | } else { |
1936 | nfc->cdev = dev->parent; |
1937 | } |
1938 | |
1939 | ret = stm32_fmc2_nfc_parse_dt(nfc); |
1940 | if (ret) |
1941 | return ret; |
1942 | |
1943 | ret = of_address_to_resource(dev: nfc->cdev->of_node, index: 0, r: &cres); |
1944 | if (ret) |
1945 | return ret; |
1946 | |
1947 | nfc->io_phys_addr = cres.start; |
1948 | |
1949 | nfc->regmap = device_node_to_regmap(np: nfc->cdev->of_node); |
1950 | if (IS_ERR(ptr: nfc->regmap)) |
1951 | return PTR_ERR(ptr: nfc->regmap); |
1952 | |
1953 | if (nfc->dev == nfc->cdev) |
1954 | start_region = 1; |
1955 | |
1956 | for (chip_cs = 0, mem_region = start_region; chip_cs < nfc->data->max_ncs; |
1957 | chip_cs++, mem_region += 3) { |
1958 | if (!(nfc->cs_assigned & BIT(chip_cs))) |
1959 | continue; |
1960 | |
1961 | nfc->data_base[chip_cs] = devm_platform_get_and_ioremap_resource(pdev, |
1962 | index: mem_region, res: &res); |
1963 | if (IS_ERR(ptr: nfc->data_base[chip_cs])) |
1964 | return PTR_ERR(ptr: nfc->data_base[chip_cs]); |
1965 | |
1966 | nfc->data_phys_addr[chip_cs] = res->start; |
1967 | |
1968 | nfc->cmd_base[chip_cs] = devm_platform_ioremap_resource(pdev, index: mem_region + 1); |
1969 | if (IS_ERR(ptr: nfc->cmd_base[chip_cs])) |
1970 | return PTR_ERR(ptr: nfc->cmd_base[chip_cs]); |
1971 | |
1972 | nfc->addr_base[chip_cs] = devm_platform_ioremap_resource(pdev, index: mem_region + 2); |
1973 | if (IS_ERR(ptr: nfc->addr_base[chip_cs])) |
1974 | return PTR_ERR(ptr: nfc->addr_base[chip_cs]); |
1975 | } |
1976 | |
1977 | irq = platform_get_irq(pdev, 0); |
1978 | if (irq < 0) |
1979 | return irq; |
1980 | |
1981 | ret = devm_request_irq(dev, irq, handler: stm32_fmc2_nfc_irq, irqflags: 0, |
1982 | devname: dev_name(dev), dev_id: nfc); |
1983 | if (ret) { |
1984 | dev_err(dev, "failed to request irq\n" ); |
1985 | return ret; |
1986 | } |
1987 | |
1988 | init_completion(x: &nfc->complete); |
1989 | |
1990 | nfc->clk = devm_clk_get_enabled(dev: nfc->cdev, NULL); |
1991 | if (IS_ERR(ptr: nfc->clk)) { |
1992 | dev_err(dev, "can not get and enable the clock\n" ); |
1993 | return PTR_ERR(ptr: nfc->clk); |
1994 | } |
1995 | |
1996 | rstc = devm_reset_control_get(dev, NULL); |
1997 | if (IS_ERR(ptr: rstc)) { |
1998 | ret = PTR_ERR(ptr: rstc); |
1999 | if (ret == -EPROBE_DEFER) |
2000 | return ret; |
2001 | } else { |
2002 | reset_control_assert(rstc); |
2003 | reset_control_deassert(rstc); |
2004 | } |
2005 | |
2006 | ret = stm32_fmc2_nfc_dma_setup(nfc); |
2007 | if (ret) |
2008 | goto err_release_dma; |
2009 | |
2010 | stm32_fmc2_nfc_init(nfc); |
2011 | |
2012 | nand = &nfc->nand; |
2013 | chip = &nand->chip; |
2014 | mtd = nand_to_mtd(chip); |
2015 | mtd->dev.parent = dev; |
2016 | |
2017 | chip->controller = &nfc->base; |
2018 | chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE | |
2019 | NAND_USES_DMA; |
2020 | |
2021 | stm32_fmc2_nfc_wp_disable(nand); |
2022 | |
2023 | /* Scan to find existence of the device */ |
2024 | ret = nand_scan(chip, max_chips: nand->ncs); |
2025 | if (ret) |
2026 | goto err_wp_enable; |
2027 | |
2028 | ret = mtd_device_register(mtd, NULL, 0); |
2029 | if (ret) |
2030 | goto err_nand_cleanup; |
2031 | |
2032 | platform_set_drvdata(pdev, data: nfc); |
2033 | |
2034 | return 0; |
2035 | |
2036 | err_nand_cleanup: |
2037 | nand_cleanup(chip); |
2038 | |
2039 | err_wp_enable: |
2040 | stm32_fmc2_nfc_wp_enable(nand); |
2041 | |
2042 | err_release_dma: |
2043 | if (nfc->dma_ecc_ch) |
2044 | dma_release_channel(chan: nfc->dma_ecc_ch); |
2045 | if (nfc->dma_tx_ch) |
2046 | dma_release_channel(chan: nfc->dma_tx_ch); |
2047 | if (nfc->dma_rx_ch) |
2048 | dma_release_channel(chan: nfc->dma_rx_ch); |
2049 | |
2050 | sg_free_table(&nfc->dma_data_sg); |
2051 | sg_free_table(&nfc->dma_ecc_sg); |
2052 | |
2053 | return ret; |
2054 | } |
2055 | |
2056 | static void stm32_fmc2_nfc_remove(struct platform_device *pdev) |
2057 | { |
2058 | struct stm32_fmc2_nfc *nfc = platform_get_drvdata(pdev); |
2059 | struct stm32_fmc2_nand *nand = &nfc->nand; |
2060 | struct nand_chip *chip = &nand->chip; |
2061 | int ret; |
2062 | |
2063 | ret = mtd_device_unregister(master: nand_to_mtd(chip)); |
2064 | WARN_ON(ret); |
2065 | nand_cleanup(chip); |
2066 | |
2067 | if (nfc->dma_ecc_ch) |
2068 | dma_release_channel(chan: nfc->dma_ecc_ch); |
2069 | if (nfc->dma_tx_ch) |
2070 | dma_release_channel(chan: nfc->dma_tx_ch); |
2071 | if (nfc->dma_rx_ch) |
2072 | dma_release_channel(chan: nfc->dma_rx_ch); |
2073 | |
2074 | sg_free_table(&nfc->dma_data_sg); |
2075 | sg_free_table(&nfc->dma_ecc_sg); |
2076 | |
2077 | stm32_fmc2_nfc_wp_enable(nand); |
2078 | } |
2079 | |
2080 | static int __maybe_unused stm32_fmc2_nfc_suspend(struct device *dev) |
2081 | { |
2082 | struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev); |
2083 | struct stm32_fmc2_nand *nand = &nfc->nand; |
2084 | |
2085 | clk_disable_unprepare(clk: nfc->clk); |
2086 | |
2087 | stm32_fmc2_nfc_wp_enable(nand); |
2088 | |
2089 | pinctrl_pm_select_sleep_state(dev); |
2090 | |
2091 | return 0; |
2092 | } |
2093 | |
2094 | static int __maybe_unused stm32_fmc2_nfc_resume(struct device *dev) |
2095 | { |
2096 | struct stm32_fmc2_nfc *nfc = dev_get_drvdata(dev); |
2097 | struct stm32_fmc2_nand *nand = &nfc->nand; |
2098 | int chip_cs, ret; |
2099 | |
2100 | pinctrl_pm_select_default_state(dev); |
2101 | |
2102 | ret = clk_prepare_enable(clk: nfc->clk); |
2103 | if (ret) { |
2104 | dev_err(dev, "can not enable the clock\n" ); |
2105 | return ret; |
2106 | } |
2107 | |
2108 | stm32_fmc2_nfc_init(nfc); |
2109 | |
2110 | stm32_fmc2_nfc_wp_disable(nand); |
2111 | |
2112 | for (chip_cs = 0; chip_cs < nfc->data->max_ncs; chip_cs++) { |
2113 | if (!(nfc->cs_assigned & BIT(chip_cs))) |
2114 | continue; |
2115 | |
2116 | nand_reset(chip: &nand->chip, chipnr: chip_cs); |
2117 | } |
2118 | |
2119 | return 0; |
2120 | } |
2121 | |
2122 | static SIMPLE_DEV_PM_OPS(stm32_fmc2_nfc_pm_ops, stm32_fmc2_nfc_suspend, |
2123 | stm32_fmc2_nfc_resume); |
2124 | |
2125 | static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp1_data = { |
2126 | .max_ncs = 2, |
2127 | .set_cdev = stm32_fmc2_nfc_set_cdev, |
2128 | }; |
2129 | |
2130 | static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp25_data = { |
2131 | .max_ncs = 4, |
2132 | }; |
2133 | |
2134 | static const struct of_device_id stm32_fmc2_nfc_match[] = { |
2135 | { |
2136 | .compatible = "st,stm32mp15-fmc2" , |
2137 | .data = &stm32_fmc2_nfc_mp1_data, |
2138 | }, |
2139 | { |
2140 | .compatible = "st,stm32mp1-fmc2-nfc" , |
2141 | .data = &stm32_fmc2_nfc_mp1_data, |
2142 | }, |
2143 | { |
2144 | .compatible = "st,stm32mp25-fmc2-nfc" , |
2145 | .data = &stm32_fmc2_nfc_mp25_data, |
2146 | }, |
2147 | {} |
2148 | }; |
2149 | MODULE_DEVICE_TABLE(of, stm32_fmc2_nfc_match); |
2150 | |
2151 | static struct platform_driver stm32_fmc2_nfc_driver = { |
2152 | .probe = stm32_fmc2_nfc_probe, |
2153 | .remove_new = stm32_fmc2_nfc_remove, |
2154 | .driver = { |
2155 | .name = "stm32_fmc2_nfc" , |
2156 | .of_match_table = stm32_fmc2_nfc_match, |
2157 | .pm = &stm32_fmc2_nfc_pm_ops, |
2158 | }, |
2159 | }; |
2160 | module_platform_driver(stm32_fmc2_nfc_driver); |
2161 | |
2162 | MODULE_ALIAS("platform:stm32_fmc2_nfc" ); |
2163 | MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>" ); |
2164 | MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 NFC driver" ); |
2165 | MODULE_LICENSE("GPL v2" ); |
2166 | |