1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) 2005, Intec Automation Inc. |
4 | * Copyright (C) 2014, Freescale Semiconductor, Inc. |
5 | */ |
6 | |
7 | #include <linux/bitfield.h> |
8 | #include <linux/device.h> |
9 | #include <linux/errno.h> |
10 | #include <linux/mtd/spi-nor.h> |
11 | |
12 | #include "core.h" |
13 | |
14 | /* flash_info mfr_flag. Used to clear sticky prorietary SR bits. */ |
15 | #define USE_CLSR BIT(0) |
16 | #define USE_CLPEF BIT(1) |
17 | |
18 | #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ |
19 | #define SPINOR_OP_CLPEF 0x82 /* Clear program/erase failure flags */ |
20 | #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ |
21 | #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ |
22 | #define SPINOR_REG_CYPRESS_VREG 0x00800000 |
23 | #define SPINOR_REG_CYPRESS_STR1 0x0 |
24 | #define SPINOR_REG_CYPRESS_STR1V \ |
25 | (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_STR1) |
26 | #define SPINOR_REG_CYPRESS_CFR1 0x2 |
27 | #define SPINOR_REG_CYPRESS_CFR1_QUAD_EN BIT(1) /* Quad Enable */ |
28 | #define SPINOR_REG_CYPRESS_CFR2 0x3 |
29 | #define SPINOR_REG_CYPRESS_CFR2V \ |
30 | (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR2) |
31 | #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK GENMASK(3, 0) |
32 | #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb |
33 | #define SPINOR_REG_CYPRESS_CFR2_ADRBYT BIT(7) |
34 | #define SPINOR_REG_CYPRESS_CFR3 0x4 |
35 | #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */ |
36 | #define SPINOR_REG_CYPRESS_CFR5 0x6 |
37 | #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6) |
38 | #define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1) |
39 | #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0) |
40 | #define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN \ |
41 | (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \ |
42 | SPINOR_REG_CYPRESS_CFR5_OPI) |
43 | #define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS SPINOR_REG_CYPRESS_CFR5_BIT6 |
44 | #define SPINOR_OP_CYPRESS_RD_FAST 0xee |
45 | #define SPINOR_REG_CYPRESS_ARCFN 0x00000006 |
46 | |
47 | /* Cypress SPI NOR flash operations. */ |
48 | #define CYPRESS_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \ |
49 | SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 0), \ |
50 | SPI_MEM_OP_ADDR(naddr, addr, 0), \ |
51 | SPI_MEM_OP_NO_DUMMY, \ |
52 | SPI_MEM_OP_DATA_OUT(ndata, buf, 0)) |
53 | |
54 | #define CYPRESS_NOR_RD_ANY_REG_OP(naddr, addr, ndummy, buf) \ |
55 | SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 0), \ |
56 | SPI_MEM_OP_ADDR(naddr, addr, 0), \ |
57 | SPI_MEM_OP_DUMMY(ndummy, 0), \ |
58 | SPI_MEM_OP_DATA_IN(1, buf, 0)) |
59 | |
60 | #define SPANSION_OP(opcode) \ |
61 | SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ |
62 | SPI_MEM_OP_NO_ADDR, \ |
63 | SPI_MEM_OP_NO_DUMMY, \ |
64 | SPI_MEM_OP_NO_DATA) |
65 | |
66 | /** |
67 | * struct spansion_nor_params - Spansion private parameters. |
68 | * @clsr: Clear Status Register or Clear Program and Erase Failure Flag |
69 | * opcode. |
70 | */ |
71 | struct spansion_nor_params { |
72 | u8 clsr; |
73 | }; |
74 | |
75 | /** |
76 | * spansion_nor_clear_sr() - Clear the Status Register. |
77 | * @nor: pointer to 'struct spi_nor'. |
78 | */ |
79 | static void spansion_nor_clear_sr(struct spi_nor *nor) |
80 | { |
81 | const struct spansion_nor_params *priv_params = nor->params->priv; |
82 | int ret; |
83 | |
84 | if (nor->spimem) { |
85 | struct spi_mem_op op = SPANSION_OP(priv_params->clsr); |
86 | |
87 | spi_nor_spimem_setup_op(nor, op: &op, proto: nor->reg_proto); |
88 | |
89 | ret = spi_mem_exec_op(mem: nor->spimem, op: &op); |
90 | } else { |
91 | ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR, |
92 | NULL, len: 0); |
93 | } |
94 | |
95 | if (ret) |
96 | dev_dbg(nor->dev, "error %d clearing SR\n" , ret); |
97 | } |
98 | |
99 | static int cypress_nor_sr_ready_and_clear_reg(struct spi_nor *nor, u64 addr) |
100 | { |
101 | struct spi_nor_flash_parameter *params = nor->params; |
102 | struct spi_mem_op op = |
103 | CYPRESS_NOR_RD_ANY_REG_OP(params->addr_mode_nbytes, addr, |
104 | 0, nor->bouncebuf); |
105 | int ret; |
106 | |
107 | if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { |
108 | op.dummy.nbytes = params->rdsr_dummy; |
109 | op.data.nbytes = 2; |
110 | } |
111 | |
112 | ret = spi_nor_read_any_reg(nor, op: &op, proto: nor->reg_proto); |
113 | if (ret) |
114 | return ret; |
115 | |
116 | if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { |
117 | if (nor->bouncebuf[0] & SR_E_ERR) |
118 | dev_err(nor->dev, "Erase Error occurred\n" ); |
119 | else |
120 | dev_err(nor->dev, "Programming Error occurred\n" ); |
121 | |
122 | spansion_nor_clear_sr(nor); |
123 | |
124 | ret = spi_nor_write_disable(nor); |
125 | if (ret) |
126 | return ret; |
127 | |
128 | return -EIO; |
129 | } |
130 | |
131 | return !(nor->bouncebuf[0] & SR_WIP); |
132 | } |
133 | /** |
134 | * cypress_nor_sr_ready_and_clear() - Query the Status Register of each die by |
135 | * using Read Any Register command to see if the whole flash is ready for new |
136 | * commands and clear it if there are any errors. |
137 | * @nor: pointer to 'struct spi_nor'. |
138 | * |
139 | * Return: 1 if ready, 0 if not ready, -errno on errors. |
140 | */ |
141 | static int cypress_nor_sr_ready_and_clear(struct spi_nor *nor) |
142 | { |
143 | struct spi_nor_flash_parameter *params = nor->params; |
144 | u64 addr; |
145 | int ret; |
146 | u8 i; |
147 | |
148 | for (i = 0; i < params->n_dice; i++) { |
149 | addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_STR1; |
150 | ret = cypress_nor_sr_ready_and_clear_reg(nor, addr); |
151 | if (ret < 0) |
152 | return ret; |
153 | else if (ret == 0) |
154 | return 0; |
155 | } |
156 | |
157 | return 1; |
158 | } |
159 | |
160 | static int cypress_nor_set_memlat(struct spi_nor *nor, u64 addr) |
161 | { |
162 | struct spi_mem_op op; |
163 | u8 *buf = nor->bouncebuf; |
164 | int ret; |
165 | u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; |
166 | |
167 | op = (struct spi_mem_op) |
168 | CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, buf); |
169 | |
170 | ret = spi_nor_read_any_reg(nor, op: &op, proto: nor->reg_proto); |
171 | if (ret) |
172 | return ret; |
173 | |
174 | /* Use 24 dummy cycles for memory array reads. */ |
175 | *buf &= ~SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK; |
176 | *buf |= FIELD_PREP(SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK, |
177 | SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24); |
178 | op = (struct spi_mem_op) |
179 | CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, addr, 1, buf); |
180 | |
181 | ret = spi_nor_write_any_volatile_reg(nor, op: &op, proto: nor->reg_proto); |
182 | if (ret) |
183 | return ret; |
184 | |
185 | nor->read_dummy = 24; |
186 | |
187 | return 0; |
188 | } |
189 | |
190 | static int cypress_nor_set_octal_dtr_bits(struct spi_nor *nor, u64 addr) |
191 | { |
192 | struct spi_mem_op op; |
193 | u8 *buf = nor->bouncebuf; |
194 | |
195 | /* Set the octal and DTR enable bits. */ |
196 | buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN; |
197 | op = (struct spi_mem_op) |
198 | CYPRESS_NOR_WR_ANY_REG_OP(nor->params->addr_mode_nbytes, |
199 | addr, 1, buf); |
200 | |
201 | return spi_nor_write_any_volatile_reg(nor, op: &op, proto: nor->reg_proto); |
202 | } |
203 | |
204 | static int cypress_nor_octal_dtr_en(struct spi_nor *nor) |
205 | { |
206 | const struct spi_nor_flash_parameter *params = nor->params; |
207 | u8 *buf = nor->bouncebuf; |
208 | u64 addr; |
209 | int i, ret; |
210 | |
211 | for (i = 0; i < params->n_dice; i++) { |
212 | addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR2; |
213 | ret = cypress_nor_set_memlat(nor, addr); |
214 | if (ret) |
215 | return ret; |
216 | |
217 | addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; |
218 | ret = cypress_nor_set_octal_dtr_bits(nor, addr); |
219 | if (ret) |
220 | return ret; |
221 | } |
222 | |
223 | /* Read flash ID to make sure the switch was successful. */ |
224 | ret = spi_nor_read_id(nor, naddr: nor->addr_nbytes, ndummy: 3, id: buf, |
225 | reg_proto: SNOR_PROTO_8_8_8_DTR); |
226 | if (ret) { |
227 | dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n" , ret); |
228 | return ret; |
229 | } |
230 | |
231 | if (memcmp(p: buf, q: nor->info->id->bytes, size: nor->info->id->len)) |
232 | return -EINVAL; |
233 | |
234 | return 0; |
235 | } |
236 | |
237 | static int cypress_nor_set_single_spi_bits(struct spi_nor *nor, u64 addr) |
238 | { |
239 | struct spi_mem_op op; |
240 | u8 *buf = nor->bouncebuf; |
241 | |
242 | /* |
243 | * The register is 1-byte wide, but 1-byte transactions are not allowed |
244 | * in 8D-8D-8D mode. Since there is no register at the next location, |
245 | * just initialize the value to 0 and let the transaction go on. |
246 | */ |
247 | buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS; |
248 | buf[1] = 0; |
249 | op = (struct spi_mem_op) |
250 | CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, addr, 2, buf); |
251 | return spi_nor_write_any_volatile_reg(nor, op: &op, proto: SNOR_PROTO_8_8_8_DTR); |
252 | } |
253 | |
254 | static int cypress_nor_octal_dtr_dis(struct spi_nor *nor) |
255 | { |
256 | const struct spi_nor_flash_parameter *params = nor->params; |
257 | u8 *buf = nor->bouncebuf; |
258 | u64 addr; |
259 | int i, ret; |
260 | |
261 | for (i = 0; i < params->n_dice; i++) { |
262 | addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; |
263 | ret = cypress_nor_set_single_spi_bits(nor, addr); |
264 | if (ret) |
265 | return ret; |
266 | } |
267 | |
268 | /* Read flash ID to make sure the switch was successful. */ |
269 | ret = spi_nor_read_id(nor, naddr: 0, ndummy: 0, id: buf, reg_proto: SNOR_PROTO_1_1_1); |
270 | if (ret) { |
271 | dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n" , ret); |
272 | return ret; |
273 | } |
274 | |
275 | if (memcmp(p: buf, q: nor->info->id->bytes, size: nor->info->id->len)) |
276 | return -EINVAL; |
277 | |
278 | return 0; |
279 | } |
280 | |
281 | static int cypress_nor_quad_enable_volatile_reg(struct spi_nor *nor, u64 addr) |
282 | { |
283 | struct spi_mem_op op; |
284 | u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; |
285 | u8 cfr1v_written; |
286 | int ret; |
287 | |
288 | op = (struct spi_mem_op) |
289 | CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, |
290 | nor->bouncebuf); |
291 | |
292 | ret = spi_nor_read_any_reg(nor, op: &op, proto: nor->reg_proto); |
293 | if (ret) |
294 | return ret; |
295 | |
296 | if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1_QUAD_EN) |
297 | return 0; |
298 | |
299 | /* Update the Quad Enable bit. */ |
300 | nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1_QUAD_EN; |
301 | op = (struct spi_mem_op) |
302 | CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, addr, 1, |
303 | nor->bouncebuf); |
304 | ret = spi_nor_write_any_volatile_reg(nor, op: &op, proto: nor->reg_proto); |
305 | if (ret) |
306 | return ret; |
307 | |
308 | cfr1v_written = nor->bouncebuf[0]; |
309 | |
310 | /* Read back and check it. */ |
311 | op = (struct spi_mem_op) |
312 | CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, |
313 | nor->bouncebuf); |
314 | ret = spi_nor_read_any_reg(nor, op: &op, proto: nor->reg_proto); |
315 | if (ret) |
316 | return ret; |
317 | |
318 | if (nor->bouncebuf[0] != cfr1v_written) { |
319 | dev_err(nor->dev, "CFR1: Read back test failed\n" ); |
320 | return -EIO; |
321 | } |
322 | |
323 | return 0; |
324 | } |
325 | |
326 | /** |
327 | * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile |
328 | * register. |
329 | * @nor: pointer to a 'struct spi_nor' |
330 | * |
331 | * It is recommended to update volatile registers in the field application due |
332 | * to a risk of the non-volatile registers corruption by power interrupt. This |
333 | * function sets Quad Enable bit in CFR1 volatile. If users set the Quad Enable |
334 | * bit in the CFR1 non-volatile in advance (typically by a Flash programmer |
335 | * before mounting Flash on PCB), the Quad Enable bit in the CFR1 volatile is |
336 | * also set during Flash power-up. |
337 | * |
338 | * Return: 0 on success, -errno otherwise. |
339 | */ |
340 | static int cypress_nor_quad_enable_volatile(struct spi_nor *nor) |
341 | { |
342 | struct spi_nor_flash_parameter *params = nor->params; |
343 | u64 addr; |
344 | u8 i; |
345 | int ret; |
346 | |
347 | for (i = 0; i < params->n_dice; i++) { |
348 | addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR1; |
349 | ret = cypress_nor_quad_enable_volatile_reg(nor, addr); |
350 | if (ret) |
351 | return ret; |
352 | } |
353 | |
354 | return 0; |
355 | } |
356 | |
357 | /** |
358 | * cypress_nor_determine_addr_mode_by_sr1() - Determine current address mode |
359 | * (3 or 4-byte) by querying status |
360 | * register 1 (SR1). |
361 | * @nor: pointer to a 'struct spi_nor' |
362 | * @addr_mode: ponter to a buffer where we return the determined |
363 | * address mode. |
364 | * |
365 | * This function tries to determine current address mode by comparing SR1 value |
366 | * from RDSR1(no address), RDAR(3-byte address), and RDAR(4-byte address). |
367 | * |
368 | * Return: 0 on success, -errno otherwise. |
369 | */ |
370 | static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor, |
371 | u8 *addr_mode) |
372 | { |
373 | struct spi_mem_op op = |
374 | CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_STR1V, 0, |
375 | nor->bouncebuf); |
376 | bool is3byte, is4byte; |
377 | int ret; |
378 | |
379 | ret = spi_nor_read_sr(nor, sr: &nor->bouncebuf[1]); |
380 | if (ret) |
381 | return ret; |
382 | |
383 | ret = spi_nor_read_any_reg(nor, op: &op, proto: nor->reg_proto); |
384 | if (ret) |
385 | return ret; |
386 | |
387 | is3byte = (nor->bouncebuf[0] == nor->bouncebuf[1]); |
388 | |
389 | op = (struct spi_mem_op) |
390 | CYPRESS_NOR_RD_ANY_REG_OP(4, SPINOR_REG_CYPRESS_STR1V, 0, |
391 | nor->bouncebuf); |
392 | ret = spi_nor_read_any_reg(nor, op: &op, proto: nor->reg_proto); |
393 | if (ret) |
394 | return ret; |
395 | |
396 | is4byte = (nor->bouncebuf[0] == nor->bouncebuf[1]); |
397 | |
398 | if (is3byte == is4byte) |
399 | return -EIO; |
400 | if (is3byte) |
401 | *addr_mode = 3; |
402 | else |
403 | *addr_mode = 4; |
404 | |
405 | return 0; |
406 | } |
407 | |
408 | /** |
409 | * cypress_nor_set_addr_mode_nbytes() - Set the number of address bytes mode of |
410 | * current address mode. |
411 | * @nor: pointer to a 'struct spi_nor' |
412 | * |
413 | * Determine current address mode by reading SR1 with different methods, then |
414 | * query CFR2V[7] to confirm. If determination is failed, force enter to 4-byte |
415 | * address mode. |
416 | * |
417 | * Return: 0 on success, -errno otherwise. |
418 | */ |
419 | static int cypress_nor_set_addr_mode_nbytes(struct spi_nor *nor) |
420 | { |
421 | struct spi_mem_op op; |
422 | u8 addr_mode; |
423 | int ret; |
424 | |
425 | /* |
426 | * Read SR1 by RDSR1 and RDAR(3- AND 4-byte addr). Use write enable |
427 | * that sets bit-1 in SR1. |
428 | */ |
429 | ret = spi_nor_write_enable(nor); |
430 | if (ret) |
431 | return ret; |
432 | ret = cypress_nor_determine_addr_mode_by_sr1(nor, addr_mode: &addr_mode); |
433 | if (ret) { |
434 | ret = spi_nor_set_4byte_addr_mode(nor, enable: true); |
435 | if (ret) |
436 | return ret; |
437 | return spi_nor_write_disable(nor); |
438 | } |
439 | ret = spi_nor_write_disable(nor); |
440 | if (ret) |
441 | return ret; |
442 | |
443 | /* |
444 | * Query CFR2V and make sure no contradiction between determined address |
445 | * mode and CFR2V[7]. |
446 | */ |
447 | op = (struct spi_mem_op) |
448 | CYPRESS_NOR_RD_ANY_REG_OP(addr_mode, SPINOR_REG_CYPRESS_CFR2V, |
449 | 0, nor->bouncebuf); |
450 | ret = spi_nor_read_any_reg(nor, op: &op, proto: nor->reg_proto); |
451 | if (ret) |
452 | return ret; |
453 | |
454 | if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR2_ADRBYT) { |
455 | if (addr_mode != 4) |
456 | return spi_nor_set_4byte_addr_mode(nor, enable: true); |
457 | } else { |
458 | if (addr_mode != 3) |
459 | return spi_nor_set_4byte_addr_mode(nor, enable: true); |
460 | } |
461 | |
462 | nor->params->addr_nbytes = addr_mode; |
463 | nor->params->addr_mode_nbytes = addr_mode; |
464 | |
465 | return 0; |
466 | } |
467 | |
468 | /** |
469 | * cypress_nor_get_page_size() - Get flash page size configuration. |
470 | * @nor: pointer to a 'struct spi_nor' |
471 | * |
472 | * The BFPT table advertises a 512B or 256B page size depending on part but the |
473 | * page size is actually configurable (with the default being 256B). Read from |
474 | * CFR3V[4] and set the correct size. |
475 | * |
476 | * Return: 0 on success, -errno otherwise. |
477 | */ |
478 | static int cypress_nor_get_page_size(struct spi_nor *nor) |
479 | { |
480 | struct spi_mem_op op = |
481 | CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, |
482 | 0, 0, nor->bouncebuf); |
483 | struct spi_nor_flash_parameter *params = nor->params; |
484 | int ret; |
485 | u8 i; |
486 | |
487 | /* |
488 | * Use the minimum common page size configuration. Programming 256-byte |
489 | * under 512-byte page size configuration is safe. |
490 | */ |
491 | params->page_size = 256; |
492 | for (i = 0; i < params->n_dice; i++) { |
493 | op.addr.val = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR3; |
494 | |
495 | ret = spi_nor_read_any_reg(nor, op: &op, proto: nor->reg_proto); |
496 | if (ret) |
497 | return ret; |
498 | |
499 | if (!(nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ)) |
500 | return 0; |
501 | } |
502 | |
503 | params->page_size = 512; |
504 | |
505 | return 0; |
506 | } |
507 | |
508 | static void cypress_nor_ecc_init(struct spi_nor *nor) |
509 | { |
510 | /* |
511 | * Programming is supported only in 16-byte ECC data unit granularity. |
512 | * Byte-programming, bit-walking, or multiple program operations to the |
513 | * same ECC data unit without an erase are not allowed. |
514 | */ |
515 | nor->params->writesize = 16; |
516 | nor->flags |= SNOR_F_ECC; |
517 | } |
518 | |
519 | static int |
520 | s25fs256t_post_bfpt_fixup(struct spi_nor *nor, |
521 | const struct sfdp_parameter_header *, |
522 | const struct sfdp_bfpt *bfpt) |
523 | { |
524 | struct spi_mem_op op; |
525 | int ret; |
526 | |
527 | ret = cypress_nor_set_addr_mode_nbytes(nor); |
528 | if (ret) |
529 | return ret; |
530 | |
531 | /* Read Architecture Configuration Register (ARCFN) */ |
532 | op = (struct spi_mem_op) |
533 | CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, |
534 | SPINOR_REG_CYPRESS_ARCFN, 1, |
535 | nor->bouncebuf); |
536 | ret = spi_nor_read_any_reg(nor, op: &op, proto: nor->reg_proto); |
537 | if (ret) |
538 | return ret; |
539 | |
540 | /* ARCFN value must be 0 if uniform sector is selected */ |
541 | if (nor->bouncebuf[0]) |
542 | return -ENODEV; |
543 | |
544 | return 0; |
545 | } |
546 | |
547 | static int s25fs256t_post_sfdp_fixup(struct spi_nor *nor) |
548 | { |
549 | struct spi_nor_flash_parameter *params = nor->params; |
550 | |
551 | /* |
552 | * S25FS256T does not define the SCCR map, but we would like to use the |
553 | * same code base for both single and multi chip package devices, thus |
554 | * set the vreg_offset and n_dice to be able to do so. |
555 | */ |
556 | params->vreg_offset = devm_kmalloc(dev: nor->dev, size: sizeof(u32), GFP_KERNEL); |
557 | if (!params->vreg_offset) |
558 | return -ENOMEM; |
559 | |
560 | params->vreg_offset[0] = SPINOR_REG_CYPRESS_VREG; |
561 | params->n_dice = 1; |
562 | |
563 | /* PP_1_1_4_4B is supported but missing in 4BAIT. */ |
564 | params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; |
565 | spi_nor_set_pp_settings(pp: ¶ms->page_programs[SNOR_CMD_PP_1_1_4], |
566 | SPINOR_OP_PP_1_1_4_4B, |
567 | proto: SNOR_PROTO_1_1_4); |
568 | |
569 | return cypress_nor_get_page_size(nor); |
570 | } |
571 | |
572 | static int s25fs256t_late_init(struct spi_nor *nor) |
573 | { |
574 | cypress_nor_ecc_init(nor); |
575 | |
576 | return 0; |
577 | } |
578 | |
579 | static struct spi_nor_fixups s25fs256t_fixups = { |
580 | .post_bfpt = s25fs256t_post_bfpt_fixup, |
581 | .post_sfdp = s25fs256t_post_sfdp_fixup, |
582 | .late_init = s25fs256t_late_init, |
583 | }; |
584 | |
585 | static int |
586 | s25hx_t_post_bfpt_fixup(struct spi_nor *nor, |
587 | const struct sfdp_parameter_header *, |
588 | const struct sfdp_bfpt *bfpt) |
589 | { |
590 | int ret; |
591 | |
592 | ret = cypress_nor_set_addr_mode_nbytes(nor); |
593 | if (ret) |
594 | return ret; |
595 | |
596 | /* Replace Quad Enable with volatile version */ |
597 | nor->params->quad_enable = cypress_nor_quad_enable_volatile; |
598 | |
599 | return 0; |
600 | } |
601 | |
602 | static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor) |
603 | { |
604 | struct spi_nor_flash_parameter *params = nor->params; |
605 | struct spi_nor_erase_type *erase_type = params->erase_map.erase_type; |
606 | unsigned int i; |
607 | |
608 | if (!params->n_dice || !params->vreg_offset) { |
609 | dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n" , |
610 | __func__); |
611 | return -EOPNOTSUPP; |
612 | } |
613 | |
614 | /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ |
615 | if (params->size == SZ_256M) |
616 | params->n_dice = 2; |
617 | |
618 | /* |
619 | * In some parts, 3byte erase opcodes are advertised by 4BAIT. |
620 | * Convert them to 4byte erase opcodes. |
621 | */ |
622 | for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) { |
623 | switch (erase_type[i].opcode) { |
624 | case SPINOR_OP_SE: |
625 | erase_type[i].opcode = SPINOR_OP_SE_4B; |
626 | break; |
627 | case SPINOR_OP_BE_4K: |
628 | erase_type[i].opcode = SPINOR_OP_BE_4K_4B; |
629 | break; |
630 | default: |
631 | break; |
632 | } |
633 | } |
634 | |
635 | return cypress_nor_get_page_size(nor); |
636 | } |
637 | |
638 | static int s25hx_t_late_init(struct spi_nor *nor) |
639 | { |
640 | struct spi_nor_flash_parameter *params = nor->params; |
641 | |
642 | /* Fast Read 4B requires mode cycles */ |
643 | params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; |
644 | params->ready = cypress_nor_sr_ready_and_clear; |
645 | cypress_nor_ecc_init(nor); |
646 | |
647 | return 0; |
648 | } |
649 | |
650 | static struct spi_nor_fixups s25hx_t_fixups = { |
651 | .post_bfpt = s25hx_t_post_bfpt_fixup, |
652 | .post_sfdp = s25hx_t_post_sfdp_fixup, |
653 | .late_init = s25hx_t_late_init, |
654 | }; |
655 | |
656 | /** |
657 | * cypress_nor_set_octal_dtr() - Enable or disable octal DTR on Cypress flashes. |
658 | * @nor: pointer to a 'struct spi_nor' |
659 | * @enable: whether to enable or disable Octal DTR |
660 | * |
661 | * This also sets the memory access latency cycles to 24 to allow the flash to |
662 | * run at up to 200MHz. |
663 | * |
664 | * Return: 0 on success, -errno otherwise. |
665 | */ |
666 | static int cypress_nor_set_octal_dtr(struct spi_nor *nor, bool enable) |
667 | { |
668 | return enable ? cypress_nor_octal_dtr_en(nor) : |
669 | cypress_nor_octal_dtr_dis(nor); |
670 | } |
671 | |
672 | static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor) |
673 | { |
674 | struct spi_nor_flash_parameter *params = nor->params; |
675 | |
676 | if (!params->n_dice || !params->vreg_offset) { |
677 | dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n" , |
678 | __func__); |
679 | return -EOPNOTSUPP; |
680 | } |
681 | |
682 | /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */ |
683 | if (params->size == SZ_256M) |
684 | params->n_dice = 2; |
685 | |
686 | /* |
687 | * On older versions of the flash the xSPI Profile 1.0 table has the |
688 | * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. |
689 | */ |
690 | if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0) |
691 | params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode = |
692 | SPINOR_OP_CYPRESS_RD_FAST; |
693 | |
694 | /* This flash is also missing the 4-byte Page Program opcode bit. */ |
695 | spi_nor_set_pp_settings(pp: ¶ms->page_programs[SNOR_CMD_PP], |
696 | SPINOR_OP_PP_4B, proto: SNOR_PROTO_1_1_1); |
697 | /* |
698 | * Since xSPI Page Program opcode is backward compatible with |
699 | * Legacy SPI, use Legacy SPI opcode there as well. |
700 | */ |
701 | spi_nor_set_pp_settings(pp: ¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], |
702 | SPINOR_OP_PP_4B, proto: SNOR_PROTO_8_8_8_DTR); |
703 | |
704 | /* |
705 | * The xSPI Profile 1.0 table advertises the number of additional |
706 | * address bytes needed for Read Status Register command as 0 but the |
707 | * actual value for that is 4. |
708 | */ |
709 | params->rdsr_addr_nbytes = 4; |
710 | |
711 | return cypress_nor_get_page_size(nor); |
712 | } |
713 | |
714 | static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor, |
715 | const struct sfdp_parameter_header *, |
716 | const struct sfdp_bfpt *bfpt) |
717 | { |
718 | return cypress_nor_set_addr_mode_nbytes(nor); |
719 | } |
720 | |
721 | static int s28hx_t_late_init(struct spi_nor *nor) |
722 | { |
723 | struct spi_nor_flash_parameter *params = nor->params; |
724 | |
725 | params->set_octal_dtr = cypress_nor_set_octal_dtr; |
726 | params->ready = cypress_nor_sr_ready_and_clear; |
727 | cypress_nor_ecc_init(nor); |
728 | |
729 | return 0; |
730 | } |
731 | |
732 | static const struct spi_nor_fixups s28hx_t_fixups = { |
733 | .post_sfdp = s28hx_t_post_sfdp_fixup, |
734 | .post_bfpt = s28hx_t_post_bfpt_fixup, |
735 | .late_init = s28hx_t_late_init, |
736 | }; |
737 | |
738 | static int |
739 | s25fs_s_nor_post_bfpt_fixups(struct spi_nor *nor, |
740 | const struct sfdp_parameter_header *, |
741 | const struct sfdp_bfpt *bfpt) |
742 | { |
743 | /* |
744 | * The S25FS-S chip family reports 512-byte pages in BFPT but |
745 | * in reality the write buffer still wraps at the safe default |
746 | * of 256 bytes. Overwrite the page size advertised by BFPT |
747 | * to get the writes working. |
748 | */ |
749 | nor->params->page_size = 256; |
750 | |
751 | return 0; |
752 | } |
753 | |
754 | static const struct spi_nor_fixups s25fs_s_nor_fixups = { |
755 | .post_bfpt = s25fs_s_nor_post_bfpt_fixups, |
756 | }; |
757 | |
758 | static const struct flash_info spansion_nor_parts[] = { |
759 | { |
760 | .id = SNOR_ID(0x01, 0x02, 0x12), |
761 | .name = "s25sl004a" , |
762 | .size = SZ_512K, |
763 | }, { |
764 | .id = SNOR_ID(0x01, 0x02, 0x13), |
765 | .name = "s25sl008a" , |
766 | .size = SZ_1M, |
767 | }, { |
768 | .id = SNOR_ID(0x01, 0x02, 0x14), |
769 | .name = "s25sl016a" , |
770 | .size = SZ_2M, |
771 | }, { |
772 | .id = SNOR_ID(0x01, 0x02, 0x15, 0x4d, 0x00), |
773 | .name = "s25sl032p" , |
774 | .size = SZ_4M, |
775 | .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
776 | }, { |
777 | .id = SNOR_ID(0x01, 0x02, 0x15), |
778 | .name = "s25sl032a" , |
779 | .size = SZ_4M, |
780 | }, { |
781 | .id = SNOR_ID(0x01, 0x02, 0x16, 0x4d, 0x00), |
782 | .name = "s25sl064p" , |
783 | .size = SZ_8M, |
784 | .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
785 | }, { |
786 | .id = SNOR_ID(0x01, 0x02, 0x16), |
787 | .name = "s25sl064a" , |
788 | .size = SZ_8M, |
789 | }, { |
790 | .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x00, 0x80), |
791 | .name = "s25fl256s0" , |
792 | .size = SZ_32M, |
793 | .sector_size = SZ_256K, |
794 | .no_sfdp_flags = SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
795 | .mfr_flags = USE_CLSR, |
796 | }, { |
797 | .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x00, 0x81), |
798 | .name = "s25fs256s0" , |
799 | .size = SZ_32M, |
800 | .sector_size = SZ_256K, |
801 | .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
802 | .mfr_flags = USE_CLSR, |
803 | }, { |
804 | .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x01, 0x80), |
805 | .name = "s25fl256s1" , |
806 | .size = SZ_32M, |
807 | .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
808 | .mfr_flags = USE_CLSR, |
809 | }, { |
810 | .id = SNOR_ID(0x01, 0x02, 0x19, 0x4d, 0x01, 0x81), |
811 | .name = "s25fs256s1" , |
812 | .size = SZ_32M, |
813 | .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
814 | .mfr_flags = USE_CLSR, |
815 | }, { |
816 | .id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x80), |
817 | .name = "s25fl512s" , |
818 | .size = SZ_64M, |
819 | .sector_size = SZ_256K, |
820 | .flags = SPI_NOR_HAS_LOCK, |
821 | .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
822 | .mfr_flags = USE_CLSR, |
823 | }, { |
824 | .id = SNOR_ID(0x01, 0x02, 0x20, 0x4d, 0x00, 0x81), |
825 | .name = "s25fs512s" , |
826 | .size = SZ_64M, |
827 | .sector_size = SZ_256K, |
828 | .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
829 | .mfr_flags = USE_CLSR, |
830 | .fixups = &s25fs_s_nor_fixups, |
831 | }, { |
832 | .id = SNOR_ID(0x01, 0x20, 0x18, 0x03, 0x00), |
833 | .name = "s25sl12800" , |
834 | .size = SZ_16M, |
835 | .sector_size = SZ_256K, |
836 | }, { |
837 | .id = SNOR_ID(0x01, 0x20, 0x18, 0x03, 0x01), |
838 | .name = "s25sl12801" , |
839 | .size = SZ_16M, |
840 | }, { |
841 | .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x00, 0x80), |
842 | .name = "s25fl128s0" , |
843 | .size = SZ_16M, |
844 | .sector_size = SZ_256K, |
845 | .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
846 | .mfr_flags = USE_CLSR, |
847 | }, { |
848 | .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x00), |
849 | .name = "s25fl129p0" , |
850 | .size = SZ_16M, |
851 | .sector_size = SZ_256K, |
852 | .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
853 | .mfr_flags = USE_CLSR, |
854 | }, { |
855 | .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x80), |
856 | .name = "s25fl128s1" , |
857 | .size = SZ_16M, |
858 | .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
859 | .mfr_flags = USE_CLSR, |
860 | }, { |
861 | .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01, 0x81), |
862 | .name = "s25fs128s1" , |
863 | .size = SZ_16M, |
864 | .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
865 | .mfr_flags = USE_CLSR, |
866 | .fixups = &s25fs_s_nor_fixups, |
867 | }, { |
868 | .id = SNOR_ID(0x01, 0x20, 0x18, 0x4d, 0x01), |
869 | .name = "s25fl129p1" , |
870 | .size = SZ_16M, |
871 | .no_sfdp_flags = SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
872 | .mfr_flags = USE_CLSR, |
873 | }, { |
874 | .id = SNOR_ID(0x01, 0x40, 0x13), |
875 | .name = "s25fl204k" , |
876 | .size = SZ_512K, |
877 | .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ, |
878 | }, { |
879 | .id = SNOR_ID(0x01, 0x40, 0x14), |
880 | .name = "s25fl208k" , |
881 | .size = SZ_1M, |
882 | .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ, |
883 | }, { |
884 | .id = SNOR_ID(0x01, 0x40, 0x15), |
885 | .name = "s25fl116k" , |
886 | .size = SZ_2M, |
887 | .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
888 | }, { |
889 | .id = SNOR_ID(0x01, 0x40, 0x16), |
890 | .name = "s25fl132k" , |
891 | .size = SZ_4M, |
892 | .no_sfdp_flags = SECT_4K, |
893 | }, { |
894 | .id = SNOR_ID(0x01, 0x40, 0x17), |
895 | .name = "s25fl164k" , |
896 | .size = SZ_8M, |
897 | .no_sfdp_flags = SECT_4K, |
898 | }, { |
899 | .id = SNOR_ID(0x01, 0x60, 0x17), |
900 | .name = "s25fl064l" , |
901 | .size = SZ_8M, |
902 | .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
903 | .fixup_flags = SPI_NOR_4B_OPCODES, |
904 | }, { |
905 | .id = SNOR_ID(0x01, 0x60, 0x18), |
906 | .name = "s25fl128l" , |
907 | .size = SZ_16M, |
908 | .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
909 | .fixup_flags = SPI_NOR_4B_OPCODES, |
910 | }, { |
911 | .id = SNOR_ID(0x01, 0x60, 0x19), |
912 | .name = "s25fl256l" , |
913 | .size = SZ_32M, |
914 | .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
915 | .fixup_flags = SPI_NOR_4B_OPCODES, |
916 | }, { |
917 | .id = SNOR_ID(0x04, 0x2c, 0xc2, 0x7f, 0x7f, 0x7f), |
918 | .name = "cy15x104q" , |
919 | .size = SZ_512K, |
920 | .sector_size = SZ_512K, |
921 | .flags = SPI_NOR_NO_ERASE, |
922 | }, { |
923 | .id = SNOR_ID(0x34, 0x2a, 0x1a, 0x0f, 0x03, 0x90), |
924 | .name = "s25hl512t" , |
925 | .mfr_flags = USE_CLPEF, |
926 | .fixups = &s25hx_t_fixups |
927 | }, { |
928 | .id = SNOR_ID(0x34, 0x2a, 0x1b, 0x0f, 0x03, 0x90), |
929 | .name = "s25hl01gt" , |
930 | .mfr_flags = USE_CLPEF, |
931 | .fixups = &s25hx_t_fixups |
932 | }, { |
933 | .id = SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90), |
934 | .name = "s25hl02gt" , |
935 | .mfr_flags = USE_CLPEF, |
936 | .flags = NO_CHIP_ERASE, |
937 | .fixups = &s25hx_t_fixups |
938 | }, { |
939 | .id = SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90), |
940 | .name = "s25fs256t" , |
941 | .mfr_flags = USE_CLPEF, |
942 | .fixups = &s25fs256t_fixups |
943 | }, { |
944 | .id = SNOR_ID(0x34, 0x2b, 0x1a, 0x0f, 0x03, 0x90), |
945 | .name = "s25hs512t" , |
946 | .mfr_flags = USE_CLPEF, |
947 | .fixups = &s25hx_t_fixups |
948 | }, { |
949 | .id = SNOR_ID(0x34, 0x2b, 0x1b, 0x0f, 0x03, 0x90), |
950 | .name = "s25hs01gt" , |
951 | .mfr_flags = USE_CLPEF, |
952 | .fixups = &s25hx_t_fixups |
953 | }, { |
954 | .id = SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90), |
955 | .name = "s25hs02gt" , |
956 | .mfr_flags = USE_CLPEF, |
957 | .flags = NO_CHIP_ERASE, |
958 | .fixups = &s25hx_t_fixups |
959 | }, { |
960 | .id = SNOR_ID(0x34, 0x5a, 0x1a), |
961 | .name = "s28hl512t" , |
962 | .mfr_flags = USE_CLPEF, |
963 | .fixups = &s28hx_t_fixups, |
964 | }, { |
965 | .id = SNOR_ID(0x34, 0x5a, 0x1b), |
966 | .name = "s28hl01gt" , |
967 | .mfr_flags = USE_CLPEF, |
968 | .fixups = &s28hx_t_fixups, |
969 | }, { |
970 | .id = SNOR_ID(0x34, 0x5b, 0x1a), |
971 | .name = "s28hs512t" , |
972 | .mfr_flags = USE_CLPEF, |
973 | .fixups = &s28hx_t_fixups, |
974 | }, { |
975 | .id = SNOR_ID(0x34, 0x5b, 0x1b), |
976 | .name = "s28hs01gt" , |
977 | .mfr_flags = USE_CLPEF, |
978 | .fixups = &s28hx_t_fixups, |
979 | }, { |
980 | .id = SNOR_ID(0x34, 0x5b, 0x1c), |
981 | .name = "s28hs02gt" , |
982 | .mfr_flags = USE_CLPEF, |
983 | .fixups = &s28hx_t_fixups, |
984 | }, { |
985 | .id = SNOR_ID(0xef, 0x40, 0x13), |
986 | .name = "s25fl004k" , |
987 | .size = SZ_512K, |
988 | .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
989 | }, { |
990 | .id = SNOR_ID(0xef, 0x40, 0x14), |
991 | .name = "s25fl008k" , |
992 | .size = SZ_1M, |
993 | .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
994 | }, { |
995 | .id = SNOR_ID(0xef, 0x40, 0x15), |
996 | .name = "s25fl016k" , |
997 | .size = SZ_2M, |
998 | .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
999 | }, { |
1000 | .id = SNOR_ID(0xef, 0x40, 0x17), |
1001 | .name = "s25fl064k" , |
1002 | .size = SZ_8M, |
1003 | .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, |
1004 | } |
1005 | }; |
1006 | |
1007 | /** |
1008 | * spansion_nor_sr_ready_and_clear() - Query the Status Register to see if the |
1009 | * flash is ready for new commands and clear it if there are any errors. |
1010 | * @nor: pointer to 'struct spi_nor'. |
1011 | * |
1012 | * Return: 1 if ready, 0 if not ready, -errno on errors. |
1013 | */ |
1014 | static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor) |
1015 | { |
1016 | int ret; |
1017 | |
1018 | ret = spi_nor_read_sr(nor, sr: nor->bouncebuf); |
1019 | if (ret) |
1020 | return ret; |
1021 | |
1022 | if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { |
1023 | if (nor->bouncebuf[0] & SR_E_ERR) |
1024 | dev_err(nor->dev, "Erase Error occurred\n" ); |
1025 | else |
1026 | dev_err(nor->dev, "Programming Error occurred\n" ); |
1027 | |
1028 | spansion_nor_clear_sr(nor); |
1029 | |
1030 | /* |
1031 | * WEL bit remains set to one when an erase or page program |
1032 | * error occurs. Issue a Write Disable command to protect |
1033 | * against inadvertent writes that can possibly corrupt the |
1034 | * contents of the memory. |
1035 | */ |
1036 | ret = spi_nor_write_disable(nor); |
1037 | if (ret) |
1038 | return ret; |
1039 | |
1040 | return -EIO; |
1041 | } |
1042 | |
1043 | return !(nor->bouncebuf[0] & SR_WIP); |
1044 | } |
1045 | |
1046 | static int spansion_nor_late_init(struct spi_nor *nor) |
1047 | { |
1048 | struct spi_nor_flash_parameter *params = nor->params; |
1049 | struct spansion_nor_params *priv_params; |
1050 | u8 mfr_flags = nor->info->mfr_flags; |
1051 | |
1052 | if (params->size > SZ_16M) { |
1053 | nor->flags |= SNOR_F_4B_OPCODES; |
1054 | /* No small sector erase for 4-byte command set */ |
1055 | nor->erase_opcode = SPINOR_OP_SE; |
1056 | nor->mtd.erasesize = nor->info->sector_size ?: |
1057 | SPI_NOR_DEFAULT_SECTOR_SIZE; |
1058 | } |
1059 | |
1060 | if (mfr_flags & (USE_CLSR | USE_CLPEF)) { |
1061 | priv_params = devm_kmalloc(dev: nor->dev, size: sizeof(*priv_params), |
1062 | GFP_KERNEL); |
1063 | if (!priv_params) |
1064 | return -ENOMEM; |
1065 | |
1066 | if (mfr_flags & USE_CLSR) |
1067 | priv_params->clsr = SPINOR_OP_CLSR; |
1068 | else if (mfr_flags & USE_CLPEF) |
1069 | priv_params->clsr = SPINOR_OP_CLPEF; |
1070 | |
1071 | params->priv = priv_params; |
1072 | params->ready = spansion_nor_sr_ready_and_clear; |
1073 | } |
1074 | |
1075 | return 0; |
1076 | } |
1077 | |
1078 | static const struct spi_nor_fixups spansion_nor_fixups = { |
1079 | .late_init = spansion_nor_late_init, |
1080 | }; |
1081 | |
1082 | const struct spi_nor_manufacturer spi_nor_spansion = { |
1083 | .name = "spansion" , |
1084 | .parts = spansion_nor_parts, |
1085 | .nparts = ARRAY_SIZE(spansion_nor_parts), |
1086 | .fixups = &spansion_nor_fixups, |
1087 | }; |
1088 | |