1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Microchip switch driver main logic |
4 | * |
5 | * Copyright (C) 2017-2019 Microchip Technology Inc. |
6 | */ |
7 | |
8 | #include <linux/delay.h> |
9 | #include <linux/dsa/ksz_common.h> |
10 | #include <linux/export.h> |
11 | #include <linux/gpio/consumer.h> |
12 | #include <linux/kernel.h> |
13 | #include <linux/module.h> |
14 | #include <linux/platform_data/microchip-ksz.h> |
15 | #include <linux/phy.h> |
16 | #include <linux/etherdevice.h> |
17 | #include <linux/if_bridge.h> |
18 | #include <linux/if_vlan.h> |
19 | #include <linux/if_hsr.h> |
20 | #include <linux/irq.h> |
21 | #include <linux/irqdomain.h> |
22 | #include <linux/of.h> |
23 | #include <linux/of_mdio.h> |
24 | #include <linux/of_net.h> |
25 | #include <linux/micrel_phy.h> |
26 | #include <net/dsa.h> |
27 | #include <net/pkt_cls.h> |
28 | #include <net/switchdev.h> |
29 | |
30 | #include "ksz_common.h" |
31 | #include "ksz_ptp.h" |
32 | #include "ksz8.h" |
33 | #include "ksz9477.h" |
34 | #include "lan937x.h" |
35 | |
36 | #define MIB_COUNTER_NUM 0x20 |
37 | |
38 | struct ksz_stats_raw { |
39 | u64 rx_hi; |
40 | u64 rx_undersize; |
41 | u64 rx_fragments; |
42 | u64 rx_oversize; |
43 | u64 rx_jabbers; |
44 | u64 rx_symbol_err; |
45 | u64 rx_crc_err; |
46 | u64 rx_align_err; |
47 | u64 rx_mac_ctrl; |
48 | u64 rx_pause; |
49 | u64 rx_bcast; |
50 | u64 rx_mcast; |
51 | u64 rx_ucast; |
52 | u64 rx_64_or_less; |
53 | u64 rx_65_127; |
54 | u64 rx_128_255; |
55 | u64 rx_256_511; |
56 | u64 rx_512_1023; |
57 | u64 rx_1024_1522; |
58 | u64 rx_1523_2000; |
59 | u64 rx_2001; |
60 | u64 tx_hi; |
61 | u64 tx_late_col; |
62 | u64 tx_pause; |
63 | u64 tx_bcast; |
64 | u64 tx_mcast; |
65 | u64 tx_ucast; |
66 | u64 tx_deferred; |
67 | u64 tx_total_col; |
68 | u64 tx_exc_col; |
69 | u64 tx_single_col; |
70 | u64 tx_mult_col; |
71 | u64 rx_total; |
72 | u64 tx_total; |
73 | u64 rx_discards; |
74 | u64 tx_discards; |
75 | }; |
76 | |
77 | struct ksz88xx_stats_raw { |
78 | u64 rx; |
79 | u64 rx_hi; |
80 | u64 rx_undersize; |
81 | u64 rx_fragments; |
82 | u64 rx_oversize; |
83 | u64 rx_jabbers; |
84 | u64 rx_symbol_err; |
85 | u64 rx_crc_err; |
86 | u64 rx_align_err; |
87 | u64 rx_mac_ctrl; |
88 | u64 rx_pause; |
89 | u64 rx_bcast; |
90 | u64 rx_mcast; |
91 | u64 rx_ucast; |
92 | u64 rx_64_or_less; |
93 | u64 rx_65_127; |
94 | u64 rx_128_255; |
95 | u64 rx_256_511; |
96 | u64 rx_512_1023; |
97 | u64 rx_1024_1522; |
98 | u64 tx; |
99 | u64 tx_hi; |
100 | u64 tx_late_col; |
101 | u64 tx_pause; |
102 | u64 tx_bcast; |
103 | u64 tx_mcast; |
104 | u64 tx_ucast; |
105 | u64 tx_deferred; |
106 | u64 tx_total_col; |
107 | u64 tx_exc_col; |
108 | u64 tx_single_col; |
109 | u64 tx_mult_col; |
110 | u64 rx_discards; |
111 | u64 tx_discards; |
112 | }; |
113 | |
114 | static const struct ksz_mib_names ksz88xx_mib_names[] = { |
115 | { 0x00, "rx" }, |
116 | { 0x01, "rx_hi" }, |
117 | { 0x02, "rx_undersize" }, |
118 | { 0x03, "rx_fragments" }, |
119 | { 0x04, "rx_oversize" }, |
120 | { 0x05, "rx_jabbers" }, |
121 | { 0x06, "rx_symbol_err" }, |
122 | { 0x07, "rx_crc_err" }, |
123 | { 0x08, "rx_align_err" }, |
124 | { 0x09, "rx_mac_ctrl" }, |
125 | { 0x0a, "rx_pause" }, |
126 | { 0x0b, "rx_bcast" }, |
127 | { 0x0c, "rx_mcast" }, |
128 | { 0x0d, "rx_ucast" }, |
129 | { 0x0e, "rx_64_or_less" }, |
130 | { 0x0f, "rx_65_127" }, |
131 | { 0x10, "rx_128_255" }, |
132 | { 0x11, "rx_256_511" }, |
133 | { 0x12, "rx_512_1023" }, |
134 | { 0x13, "rx_1024_1522" }, |
135 | { 0x14, "tx" }, |
136 | { 0x15, "tx_hi" }, |
137 | { 0x16, "tx_late_col" }, |
138 | { 0x17, "tx_pause" }, |
139 | { 0x18, "tx_bcast" }, |
140 | { 0x19, "tx_mcast" }, |
141 | { 0x1a, "tx_ucast" }, |
142 | { 0x1b, "tx_deferred" }, |
143 | { 0x1c, "tx_total_col" }, |
144 | { 0x1d, "tx_exc_col" }, |
145 | { 0x1e, "tx_single_col" }, |
146 | { 0x1f, "tx_mult_col" }, |
147 | { 0x100, "rx_discards" }, |
148 | { 0x101, "tx_discards" }, |
149 | }; |
150 | |
151 | static const struct ksz_mib_names ksz9477_mib_names[] = { |
152 | { 0x00, "rx_hi" }, |
153 | { 0x01, "rx_undersize" }, |
154 | { 0x02, "rx_fragments" }, |
155 | { 0x03, "rx_oversize" }, |
156 | { 0x04, "rx_jabbers" }, |
157 | { 0x05, "rx_symbol_err" }, |
158 | { 0x06, "rx_crc_err" }, |
159 | { 0x07, "rx_align_err" }, |
160 | { 0x08, "rx_mac_ctrl" }, |
161 | { 0x09, "rx_pause" }, |
162 | { 0x0A, "rx_bcast" }, |
163 | { 0x0B, "rx_mcast" }, |
164 | { 0x0C, "rx_ucast" }, |
165 | { 0x0D, "rx_64_or_less" }, |
166 | { 0x0E, "rx_65_127" }, |
167 | { 0x0F, "rx_128_255" }, |
168 | { 0x10, "rx_256_511" }, |
169 | { 0x11, "rx_512_1023" }, |
170 | { 0x12, "rx_1024_1522" }, |
171 | { 0x13, "rx_1523_2000" }, |
172 | { 0x14, "rx_2001" }, |
173 | { 0x15, "tx_hi" }, |
174 | { 0x16, "tx_late_col" }, |
175 | { 0x17, "tx_pause" }, |
176 | { 0x18, "tx_bcast" }, |
177 | { 0x19, "tx_mcast" }, |
178 | { 0x1A, "tx_ucast" }, |
179 | { 0x1B, "tx_deferred" }, |
180 | { 0x1C, "tx_total_col" }, |
181 | { 0x1D, "tx_exc_col" }, |
182 | { 0x1E, "tx_single_col" }, |
183 | { 0x1F, "tx_mult_col" }, |
184 | { 0x80, "rx_total" }, |
185 | { 0x81, "tx_total" }, |
186 | { 0x82, "rx_discards" }, |
187 | { 0x83, "tx_discards" }, |
188 | }; |
189 | |
190 | struct ksz_driver_strength_prop { |
191 | const char *name; |
192 | int offset; |
193 | int value; |
194 | }; |
195 | |
196 | enum ksz_driver_strength_type { |
197 | KSZ_DRIVER_STRENGTH_HI, |
198 | KSZ_DRIVER_STRENGTH_LO, |
199 | KSZ_DRIVER_STRENGTH_IO, |
200 | }; |
201 | |
202 | /** |
203 | * struct ksz_drive_strength - drive strength mapping |
204 | * @reg_val: register value |
205 | * @microamp: microamp value |
206 | */ |
207 | struct ksz_drive_strength { |
208 | u32 reg_val; |
209 | u32 microamp; |
210 | }; |
211 | |
212 | /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants |
213 | * |
214 | * This values are not documented in KSZ9477 variants but confirmed by |
215 | * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 |
216 | * and KSZ8563 are using same register (drive strength) settings like KSZ8795. |
217 | * |
218 | * Documentation in KSZ8795CLX provides more information with some |
219 | * recommendations: |
220 | * - for high speed signals |
221 | * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using |
222 | * 2.5V or 3.3V VDDIO. |
223 | * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with |
224 | * using 1.8V VDDIO. |
225 | * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V |
226 | * or 3.3V VDDIO. |
227 | * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. |
228 | * 5. In same interface, the heavy loading should use higher one of the |
229 | * drive current strength. |
230 | * - for low speed signals |
231 | * 1. 3.3V VDDIO, use either 4 mA or 8 mA. |
232 | * 2. 2.5V VDDIO, use either 8 mA or 12 mA. |
233 | * 3. 1.8V VDDIO, use either 12 mA or 16 mA. |
234 | * 4. If it is heavy loading, can use higher drive current strength. |
235 | */ |
236 | static const struct ksz_drive_strength ksz9477_drive_strengths[] = { |
237 | { SW_DRIVE_STRENGTH_2MA, 2000 }, |
238 | { SW_DRIVE_STRENGTH_4MA, 4000 }, |
239 | { SW_DRIVE_STRENGTH_8MA, 8000 }, |
240 | { SW_DRIVE_STRENGTH_12MA, 12000 }, |
241 | { SW_DRIVE_STRENGTH_16MA, 16000 }, |
242 | { SW_DRIVE_STRENGTH_20MA, 20000 }, |
243 | { SW_DRIVE_STRENGTH_24MA, 24000 }, |
244 | { SW_DRIVE_STRENGTH_28MA, 28000 }, |
245 | }; |
246 | |
247 | /* ksz8830_drive_strengths - Drive strength mapping for KSZ8830, KSZ8873, .. |
248 | * variants. |
249 | * This values are documented in KSZ8873 and KSZ8863 datasheets. |
250 | */ |
251 | static const struct ksz_drive_strength ksz8830_drive_strengths[] = { |
252 | { 0, 8000 }, |
253 | { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, |
254 | }; |
255 | |
256 | static const struct ksz_dev_ops ksz8_dev_ops = { |
257 | .setup = ksz8_setup, |
258 | .get_port_addr = ksz8_get_port_addr, |
259 | .cfg_port_member = ksz8_cfg_port_member, |
260 | .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, |
261 | .port_setup = ksz8_port_setup, |
262 | .r_phy = ksz8_r_phy, |
263 | .w_phy = ksz8_w_phy, |
264 | .r_mib_cnt = ksz8_r_mib_cnt, |
265 | .r_mib_pkt = ksz8_r_mib_pkt, |
266 | .r_mib_stat64 = ksz88xx_r_mib_stats64, |
267 | .freeze_mib = ksz8_freeze_mib, |
268 | .port_init_cnt = ksz8_port_init_cnt, |
269 | .fdb_dump = ksz8_fdb_dump, |
270 | .fdb_add = ksz8_fdb_add, |
271 | .fdb_del = ksz8_fdb_del, |
272 | .mdb_add = ksz8_mdb_add, |
273 | .mdb_del = ksz8_mdb_del, |
274 | .vlan_filtering = ksz8_port_vlan_filtering, |
275 | .vlan_add = ksz8_port_vlan_add, |
276 | .vlan_del = ksz8_port_vlan_del, |
277 | .mirror_add = ksz8_port_mirror_add, |
278 | .mirror_del = ksz8_port_mirror_del, |
279 | .get_caps = ksz8_get_caps, |
280 | .phylink_mac_link_up = ksz8_phylink_mac_link_up, |
281 | .config_cpu_port = ksz8_config_cpu_port, |
282 | .enable_stp_addr = ksz8_enable_stp_addr, |
283 | .reset = ksz8_reset_switch, |
284 | .init = ksz8_switch_init, |
285 | .exit = ksz8_switch_exit, |
286 | .change_mtu = ksz8_change_mtu, |
287 | }; |
288 | |
289 | static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, |
290 | unsigned int mode, |
291 | phy_interface_t interface, |
292 | struct phy_device *phydev, int speed, |
293 | int duplex, bool tx_pause, |
294 | bool rx_pause); |
295 | |
296 | static const struct ksz_dev_ops ksz9477_dev_ops = { |
297 | .setup = ksz9477_setup, |
298 | .get_port_addr = ksz9477_get_port_addr, |
299 | .cfg_port_member = ksz9477_cfg_port_member, |
300 | .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, |
301 | .port_setup = ksz9477_port_setup, |
302 | .set_ageing_time = ksz9477_set_ageing_time, |
303 | .r_phy = ksz9477_r_phy, |
304 | .w_phy = ksz9477_w_phy, |
305 | .r_mib_cnt = ksz9477_r_mib_cnt, |
306 | .r_mib_pkt = ksz9477_r_mib_pkt, |
307 | .r_mib_stat64 = ksz_r_mib_stats64, |
308 | .freeze_mib = ksz9477_freeze_mib, |
309 | .port_init_cnt = ksz9477_port_init_cnt, |
310 | .vlan_filtering = ksz9477_port_vlan_filtering, |
311 | .vlan_add = ksz9477_port_vlan_add, |
312 | .vlan_del = ksz9477_port_vlan_del, |
313 | .mirror_add = ksz9477_port_mirror_add, |
314 | .mirror_del = ksz9477_port_mirror_del, |
315 | .get_caps = ksz9477_get_caps, |
316 | .fdb_dump = ksz9477_fdb_dump, |
317 | .fdb_add = ksz9477_fdb_add, |
318 | .fdb_del = ksz9477_fdb_del, |
319 | .mdb_add = ksz9477_mdb_add, |
320 | .mdb_del = ksz9477_mdb_del, |
321 | .change_mtu = ksz9477_change_mtu, |
322 | .phylink_mac_link_up = ksz9477_phylink_mac_link_up, |
323 | .get_wol = ksz9477_get_wol, |
324 | .set_wol = ksz9477_set_wol, |
325 | .wol_pre_shutdown = ksz9477_wol_pre_shutdown, |
326 | .config_cpu_port = ksz9477_config_cpu_port, |
327 | .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, |
328 | .enable_stp_addr = ksz9477_enable_stp_addr, |
329 | .reset = ksz9477_reset_switch, |
330 | .init = ksz9477_switch_init, |
331 | .exit = ksz9477_switch_exit, |
332 | }; |
333 | |
334 | static const struct ksz_dev_ops lan937x_dev_ops = { |
335 | .setup = lan937x_setup, |
336 | .teardown = lan937x_teardown, |
337 | .get_port_addr = ksz9477_get_port_addr, |
338 | .cfg_port_member = ksz9477_cfg_port_member, |
339 | .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, |
340 | .port_setup = lan937x_port_setup, |
341 | .set_ageing_time = lan937x_set_ageing_time, |
342 | .r_phy = lan937x_r_phy, |
343 | .w_phy = lan937x_w_phy, |
344 | .r_mib_cnt = ksz9477_r_mib_cnt, |
345 | .r_mib_pkt = ksz9477_r_mib_pkt, |
346 | .r_mib_stat64 = ksz_r_mib_stats64, |
347 | .freeze_mib = ksz9477_freeze_mib, |
348 | .port_init_cnt = ksz9477_port_init_cnt, |
349 | .vlan_filtering = ksz9477_port_vlan_filtering, |
350 | .vlan_add = ksz9477_port_vlan_add, |
351 | .vlan_del = ksz9477_port_vlan_del, |
352 | .mirror_add = ksz9477_port_mirror_add, |
353 | .mirror_del = ksz9477_port_mirror_del, |
354 | .get_caps = lan937x_phylink_get_caps, |
355 | .setup_rgmii_delay = lan937x_setup_rgmii_delay, |
356 | .fdb_dump = ksz9477_fdb_dump, |
357 | .fdb_add = ksz9477_fdb_add, |
358 | .fdb_del = ksz9477_fdb_del, |
359 | .mdb_add = ksz9477_mdb_add, |
360 | .mdb_del = ksz9477_mdb_del, |
361 | .change_mtu = lan937x_change_mtu, |
362 | .phylink_mac_link_up = ksz9477_phylink_mac_link_up, |
363 | .config_cpu_port = lan937x_config_cpu_port, |
364 | .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, |
365 | .enable_stp_addr = ksz9477_enable_stp_addr, |
366 | .reset = lan937x_reset_switch, |
367 | .init = lan937x_switch_init, |
368 | .exit = lan937x_switch_exit, |
369 | }; |
370 | |
371 | static const u16 ksz8795_regs[] = { |
372 | [REG_SW_MAC_ADDR] = 0x68, |
373 | [REG_IND_CTRL_0] = 0x6E, |
374 | [REG_IND_DATA_8] = 0x70, |
375 | [REG_IND_DATA_CHECK] = 0x72, |
376 | [REG_IND_DATA_HI] = 0x71, |
377 | [REG_IND_DATA_LO] = 0x75, |
378 | [REG_IND_MIB_CHECK] = 0x74, |
379 | [REG_IND_BYTE] = 0xA0, |
380 | [P_FORCE_CTRL] = 0x0C, |
381 | [P_LINK_STATUS] = 0x0E, |
382 | [P_LOCAL_CTRL] = 0x07, |
383 | [P_NEG_RESTART_CTRL] = 0x0D, |
384 | [P_REMOTE_STATUS] = 0x08, |
385 | [P_SPEED_STATUS] = 0x09, |
386 | [S_TAIL_TAG_CTRL] = 0x0C, |
387 | [P_STP_CTRL] = 0x02, |
388 | [S_START_CTRL] = 0x01, |
389 | [S_BROADCAST_CTRL] = 0x06, |
390 | [S_MULTICAST_CTRL] = 0x04, |
391 | [P_XMII_CTRL_0] = 0x06, |
392 | [P_XMII_CTRL_1] = 0x06, |
393 | }; |
394 | |
395 | static const u32 ksz8795_masks[] = { |
396 | [PORT_802_1P_REMAPPING] = BIT(7), |
397 | [SW_TAIL_TAG_ENABLE] = BIT(1), |
398 | [MIB_COUNTER_OVERFLOW] = BIT(6), |
399 | [MIB_COUNTER_VALID] = BIT(5), |
400 | [VLAN_TABLE_FID] = GENMASK(6, 0), |
401 | [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), |
402 | [VLAN_TABLE_VALID] = BIT(12), |
403 | [STATIC_MAC_TABLE_VALID] = BIT(21), |
404 | [STATIC_MAC_TABLE_USE_FID] = BIT(23), |
405 | [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), |
406 | [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), |
407 | [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), |
408 | [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), |
409 | [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), |
410 | [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), |
411 | [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), |
412 | [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), |
413 | [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), |
414 | [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), |
415 | [P_MII_TX_FLOW_CTRL] = BIT(5), |
416 | [P_MII_RX_FLOW_CTRL] = BIT(5), |
417 | }; |
418 | |
419 | static const u8 ksz8795_xmii_ctrl0[] = { |
420 | [P_MII_100MBIT] = 0, |
421 | [P_MII_10MBIT] = 1, |
422 | [P_MII_FULL_DUPLEX] = 0, |
423 | [P_MII_HALF_DUPLEX] = 1, |
424 | }; |
425 | |
426 | static const u8 ksz8795_xmii_ctrl1[] = { |
427 | [P_RGMII_SEL] = 3, |
428 | [P_GMII_SEL] = 2, |
429 | [P_RMII_SEL] = 1, |
430 | [P_MII_SEL] = 0, |
431 | [P_GMII_1GBIT] = 1, |
432 | [P_GMII_NOT_1GBIT] = 0, |
433 | }; |
434 | |
435 | static const u8 ksz8795_shifts[] = { |
436 | [VLAN_TABLE_MEMBERSHIP_S] = 7, |
437 | [VLAN_TABLE] = 16, |
438 | [STATIC_MAC_FWD_PORTS] = 16, |
439 | [STATIC_MAC_FID] = 24, |
440 | [DYNAMIC_MAC_ENTRIES_H] = 3, |
441 | [DYNAMIC_MAC_ENTRIES] = 29, |
442 | [DYNAMIC_MAC_FID] = 16, |
443 | [DYNAMIC_MAC_TIMESTAMP] = 27, |
444 | [DYNAMIC_MAC_SRC_PORT] = 24, |
445 | }; |
446 | |
447 | static const u16 ksz8863_regs[] = { |
448 | [REG_SW_MAC_ADDR] = 0x70, |
449 | [REG_IND_CTRL_0] = 0x79, |
450 | [REG_IND_DATA_8] = 0x7B, |
451 | [REG_IND_DATA_CHECK] = 0x7B, |
452 | [REG_IND_DATA_HI] = 0x7C, |
453 | [REG_IND_DATA_LO] = 0x80, |
454 | [REG_IND_MIB_CHECK] = 0x80, |
455 | [P_FORCE_CTRL] = 0x0C, |
456 | [P_LINK_STATUS] = 0x0E, |
457 | [P_LOCAL_CTRL] = 0x0C, |
458 | [P_NEG_RESTART_CTRL] = 0x0D, |
459 | [P_REMOTE_STATUS] = 0x0E, |
460 | [P_SPEED_STATUS] = 0x0F, |
461 | [S_TAIL_TAG_CTRL] = 0x03, |
462 | [P_STP_CTRL] = 0x02, |
463 | [S_START_CTRL] = 0x01, |
464 | [S_BROADCAST_CTRL] = 0x06, |
465 | [S_MULTICAST_CTRL] = 0x04, |
466 | }; |
467 | |
468 | static const u32 ksz8863_masks[] = { |
469 | [PORT_802_1P_REMAPPING] = BIT(3), |
470 | [SW_TAIL_TAG_ENABLE] = BIT(6), |
471 | [MIB_COUNTER_OVERFLOW] = BIT(7), |
472 | [MIB_COUNTER_VALID] = BIT(6), |
473 | [VLAN_TABLE_FID] = GENMASK(15, 12), |
474 | [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), |
475 | [VLAN_TABLE_VALID] = BIT(19), |
476 | [STATIC_MAC_TABLE_VALID] = BIT(19), |
477 | [STATIC_MAC_TABLE_USE_FID] = BIT(21), |
478 | [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), |
479 | [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), |
480 | [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), |
481 | [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), |
482 | [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), |
483 | [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), |
484 | [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), |
485 | [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), |
486 | [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), |
487 | [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), |
488 | }; |
489 | |
490 | static u8 ksz8863_shifts[] = { |
491 | [VLAN_TABLE_MEMBERSHIP_S] = 16, |
492 | [STATIC_MAC_FWD_PORTS] = 16, |
493 | [STATIC_MAC_FID] = 22, |
494 | [DYNAMIC_MAC_ENTRIES_H] = 8, |
495 | [DYNAMIC_MAC_ENTRIES] = 24, |
496 | [DYNAMIC_MAC_FID] = 16, |
497 | [DYNAMIC_MAC_TIMESTAMP] = 22, |
498 | [DYNAMIC_MAC_SRC_PORT] = 20, |
499 | }; |
500 | |
501 | static const u16 ksz9477_regs[] = { |
502 | [REG_SW_MAC_ADDR] = 0x0302, |
503 | [P_STP_CTRL] = 0x0B04, |
504 | [S_START_CTRL] = 0x0300, |
505 | [S_BROADCAST_CTRL] = 0x0332, |
506 | [S_MULTICAST_CTRL] = 0x0331, |
507 | [P_XMII_CTRL_0] = 0x0300, |
508 | [P_XMII_CTRL_1] = 0x0301, |
509 | }; |
510 | |
511 | static const u32 ksz9477_masks[] = { |
512 | [ALU_STAT_WRITE] = 0, |
513 | [ALU_STAT_READ] = 1, |
514 | [P_MII_TX_FLOW_CTRL] = BIT(5), |
515 | [P_MII_RX_FLOW_CTRL] = BIT(3), |
516 | }; |
517 | |
518 | static const u8 ksz9477_shifts[] = { |
519 | [ALU_STAT_INDEX] = 16, |
520 | }; |
521 | |
522 | static const u8 ksz9477_xmii_ctrl0[] = { |
523 | [P_MII_100MBIT] = 1, |
524 | [P_MII_10MBIT] = 0, |
525 | [P_MII_FULL_DUPLEX] = 1, |
526 | [P_MII_HALF_DUPLEX] = 0, |
527 | }; |
528 | |
529 | static const u8 ksz9477_xmii_ctrl1[] = { |
530 | [P_RGMII_SEL] = 0, |
531 | [P_RMII_SEL] = 1, |
532 | [P_GMII_SEL] = 2, |
533 | [P_MII_SEL] = 3, |
534 | [P_GMII_1GBIT] = 0, |
535 | [P_GMII_NOT_1GBIT] = 1, |
536 | }; |
537 | |
538 | static const u32 lan937x_masks[] = { |
539 | [ALU_STAT_WRITE] = 1, |
540 | [ALU_STAT_READ] = 2, |
541 | [P_MII_TX_FLOW_CTRL] = BIT(5), |
542 | [P_MII_RX_FLOW_CTRL] = BIT(3), |
543 | }; |
544 | |
545 | static const u8 lan937x_shifts[] = { |
546 | [ALU_STAT_INDEX] = 8, |
547 | }; |
548 | |
549 | static const struct regmap_range ksz8563_valid_regs[] = { |
550 | regmap_reg_range(0x0000, 0x0003), |
551 | regmap_reg_range(0x0006, 0x0006), |
552 | regmap_reg_range(0x000f, 0x001f), |
553 | regmap_reg_range(0x0100, 0x0100), |
554 | regmap_reg_range(0x0104, 0x0107), |
555 | regmap_reg_range(0x010d, 0x010d), |
556 | regmap_reg_range(0x0110, 0x0113), |
557 | regmap_reg_range(0x0120, 0x012b), |
558 | regmap_reg_range(0x0201, 0x0201), |
559 | regmap_reg_range(0x0210, 0x0213), |
560 | regmap_reg_range(0x0300, 0x0300), |
561 | regmap_reg_range(0x0302, 0x031b), |
562 | regmap_reg_range(0x0320, 0x032b), |
563 | regmap_reg_range(0x0330, 0x0336), |
564 | regmap_reg_range(0x0338, 0x033e), |
565 | regmap_reg_range(0x0340, 0x035f), |
566 | regmap_reg_range(0x0370, 0x0370), |
567 | regmap_reg_range(0x0378, 0x0378), |
568 | regmap_reg_range(0x037c, 0x037d), |
569 | regmap_reg_range(0x0390, 0x0393), |
570 | regmap_reg_range(0x0400, 0x040e), |
571 | regmap_reg_range(0x0410, 0x042f), |
572 | regmap_reg_range(0x0500, 0x0519), |
573 | regmap_reg_range(0x0520, 0x054b), |
574 | regmap_reg_range(0x0550, 0x05b3), |
575 | |
576 | /* port 1 */ |
577 | regmap_reg_range(0x1000, 0x1001), |
578 | regmap_reg_range(0x1004, 0x100b), |
579 | regmap_reg_range(0x1013, 0x1013), |
580 | regmap_reg_range(0x1017, 0x1017), |
581 | regmap_reg_range(0x101b, 0x101b), |
582 | regmap_reg_range(0x101f, 0x1021), |
583 | regmap_reg_range(0x1030, 0x1030), |
584 | regmap_reg_range(0x1100, 0x1111), |
585 | regmap_reg_range(0x111a, 0x111d), |
586 | regmap_reg_range(0x1122, 0x1127), |
587 | regmap_reg_range(0x112a, 0x112b), |
588 | regmap_reg_range(0x1136, 0x1139), |
589 | regmap_reg_range(0x113e, 0x113f), |
590 | regmap_reg_range(0x1400, 0x1401), |
591 | regmap_reg_range(0x1403, 0x1403), |
592 | regmap_reg_range(0x1410, 0x1417), |
593 | regmap_reg_range(0x1420, 0x1423), |
594 | regmap_reg_range(0x1500, 0x1507), |
595 | regmap_reg_range(0x1600, 0x1612), |
596 | regmap_reg_range(0x1800, 0x180f), |
597 | regmap_reg_range(0x1900, 0x1907), |
598 | regmap_reg_range(0x1914, 0x191b), |
599 | regmap_reg_range(0x1a00, 0x1a03), |
600 | regmap_reg_range(0x1a04, 0x1a08), |
601 | regmap_reg_range(0x1b00, 0x1b01), |
602 | regmap_reg_range(0x1b04, 0x1b04), |
603 | regmap_reg_range(0x1c00, 0x1c05), |
604 | regmap_reg_range(0x1c08, 0x1c1b), |
605 | |
606 | /* port 2 */ |
607 | regmap_reg_range(0x2000, 0x2001), |
608 | regmap_reg_range(0x2004, 0x200b), |
609 | regmap_reg_range(0x2013, 0x2013), |
610 | regmap_reg_range(0x2017, 0x2017), |
611 | regmap_reg_range(0x201b, 0x201b), |
612 | regmap_reg_range(0x201f, 0x2021), |
613 | regmap_reg_range(0x2030, 0x2030), |
614 | regmap_reg_range(0x2100, 0x2111), |
615 | regmap_reg_range(0x211a, 0x211d), |
616 | regmap_reg_range(0x2122, 0x2127), |
617 | regmap_reg_range(0x212a, 0x212b), |
618 | regmap_reg_range(0x2136, 0x2139), |
619 | regmap_reg_range(0x213e, 0x213f), |
620 | regmap_reg_range(0x2400, 0x2401), |
621 | regmap_reg_range(0x2403, 0x2403), |
622 | regmap_reg_range(0x2410, 0x2417), |
623 | regmap_reg_range(0x2420, 0x2423), |
624 | regmap_reg_range(0x2500, 0x2507), |
625 | regmap_reg_range(0x2600, 0x2612), |
626 | regmap_reg_range(0x2800, 0x280f), |
627 | regmap_reg_range(0x2900, 0x2907), |
628 | regmap_reg_range(0x2914, 0x291b), |
629 | regmap_reg_range(0x2a00, 0x2a03), |
630 | regmap_reg_range(0x2a04, 0x2a08), |
631 | regmap_reg_range(0x2b00, 0x2b01), |
632 | regmap_reg_range(0x2b04, 0x2b04), |
633 | regmap_reg_range(0x2c00, 0x2c05), |
634 | regmap_reg_range(0x2c08, 0x2c1b), |
635 | |
636 | /* port 3 */ |
637 | regmap_reg_range(0x3000, 0x3001), |
638 | regmap_reg_range(0x3004, 0x300b), |
639 | regmap_reg_range(0x3013, 0x3013), |
640 | regmap_reg_range(0x3017, 0x3017), |
641 | regmap_reg_range(0x301b, 0x301b), |
642 | regmap_reg_range(0x301f, 0x3021), |
643 | regmap_reg_range(0x3030, 0x3030), |
644 | regmap_reg_range(0x3300, 0x3301), |
645 | regmap_reg_range(0x3303, 0x3303), |
646 | regmap_reg_range(0x3400, 0x3401), |
647 | regmap_reg_range(0x3403, 0x3403), |
648 | regmap_reg_range(0x3410, 0x3417), |
649 | regmap_reg_range(0x3420, 0x3423), |
650 | regmap_reg_range(0x3500, 0x3507), |
651 | regmap_reg_range(0x3600, 0x3612), |
652 | regmap_reg_range(0x3800, 0x380f), |
653 | regmap_reg_range(0x3900, 0x3907), |
654 | regmap_reg_range(0x3914, 0x391b), |
655 | regmap_reg_range(0x3a00, 0x3a03), |
656 | regmap_reg_range(0x3a04, 0x3a08), |
657 | regmap_reg_range(0x3b00, 0x3b01), |
658 | regmap_reg_range(0x3b04, 0x3b04), |
659 | regmap_reg_range(0x3c00, 0x3c05), |
660 | regmap_reg_range(0x3c08, 0x3c1b), |
661 | }; |
662 | |
663 | static const struct regmap_access_table ksz8563_register_set = { |
664 | .yes_ranges = ksz8563_valid_regs, |
665 | .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), |
666 | }; |
667 | |
668 | static const struct regmap_range ksz9477_valid_regs[] = { |
669 | regmap_reg_range(0x0000, 0x0003), |
670 | regmap_reg_range(0x0006, 0x0006), |
671 | regmap_reg_range(0x0010, 0x001f), |
672 | regmap_reg_range(0x0100, 0x0100), |
673 | regmap_reg_range(0x0103, 0x0107), |
674 | regmap_reg_range(0x010d, 0x010d), |
675 | regmap_reg_range(0x0110, 0x0113), |
676 | regmap_reg_range(0x0120, 0x012b), |
677 | regmap_reg_range(0x0201, 0x0201), |
678 | regmap_reg_range(0x0210, 0x0213), |
679 | regmap_reg_range(0x0300, 0x0300), |
680 | regmap_reg_range(0x0302, 0x031b), |
681 | regmap_reg_range(0x0320, 0x032b), |
682 | regmap_reg_range(0x0330, 0x0336), |
683 | regmap_reg_range(0x0338, 0x033b), |
684 | regmap_reg_range(0x033e, 0x033e), |
685 | regmap_reg_range(0x0340, 0x035f), |
686 | regmap_reg_range(0x0370, 0x0370), |
687 | regmap_reg_range(0x0378, 0x0378), |
688 | regmap_reg_range(0x037c, 0x037d), |
689 | regmap_reg_range(0x0390, 0x0393), |
690 | regmap_reg_range(0x0400, 0x040e), |
691 | regmap_reg_range(0x0410, 0x042f), |
692 | regmap_reg_range(0x0444, 0x044b), |
693 | regmap_reg_range(0x0450, 0x046f), |
694 | regmap_reg_range(0x0500, 0x0519), |
695 | regmap_reg_range(0x0520, 0x054b), |
696 | regmap_reg_range(0x0550, 0x05b3), |
697 | regmap_reg_range(0x0604, 0x060b), |
698 | regmap_reg_range(0x0610, 0x0612), |
699 | regmap_reg_range(0x0614, 0x062c), |
700 | regmap_reg_range(0x0640, 0x0645), |
701 | regmap_reg_range(0x0648, 0x064d), |
702 | |
703 | /* port 1 */ |
704 | regmap_reg_range(0x1000, 0x1001), |
705 | regmap_reg_range(0x1013, 0x1013), |
706 | regmap_reg_range(0x1017, 0x1017), |
707 | regmap_reg_range(0x101b, 0x101b), |
708 | regmap_reg_range(0x101f, 0x1020), |
709 | regmap_reg_range(0x1030, 0x1030), |
710 | regmap_reg_range(0x1100, 0x1115), |
711 | regmap_reg_range(0x111a, 0x111f), |
712 | regmap_reg_range(0x1120, 0x112b), |
713 | regmap_reg_range(0x1134, 0x113b), |
714 | regmap_reg_range(0x113c, 0x113f), |
715 | regmap_reg_range(0x1400, 0x1401), |
716 | regmap_reg_range(0x1403, 0x1403), |
717 | regmap_reg_range(0x1410, 0x1417), |
718 | regmap_reg_range(0x1420, 0x1423), |
719 | regmap_reg_range(0x1500, 0x1507), |
720 | regmap_reg_range(0x1600, 0x1613), |
721 | regmap_reg_range(0x1800, 0x180f), |
722 | regmap_reg_range(0x1820, 0x1827), |
723 | regmap_reg_range(0x1830, 0x1837), |
724 | regmap_reg_range(0x1840, 0x184b), |
725 | regmap_reg_range(0x1900, 0x1907), |
726 | regmap_reg_range(0x1914, 0x191b), |
727 | regmap_reg_range(0x1920, 0x1920), |
728 | regmap_reg_range(0x1923, 0x1927), |
729 | regmap_reg_range(0x1a00, 0x1a03), |
730 | regmap_reg_range(0x1a04, 0x1a07), |
731 | regmap_reg_range(0x1b00, 0x1b01), |
732 | regmap_reg_range(0x1b04, 0x1b04), |
733 | regmap_reg_range(0x1c00, 0x1c05), |
734 | regmap_reg_range(0x1c08, 0x1c1b), |
735 | |
736 | /* port 2 */ |
737 | regmap_reg_range(0x2000, 0x2001), |
738 | regmap_reg_range(0x2013, 0x2013), |
739 | regmap_reg_range(0x2017, 0x2017), |
740 | regmap_reg_range(0x201b, 0x201b), |
741 | regmap_reg_range(0x201f, 0x2020), |
742 | regmap_reg_range(0x2030, 0x2030), |
743 | regmap_reg_range(0x2100, 0x2115), |
744 | regmap_reg_range(0x211a, 0x211f), |
745 | regmap_reg_range(0x2120, 0x212b), |
746 | regmap_reg_range(0x2134, 0x213b), |
747 | regmap_reg_range(0x213c, 0x213f), |
748 | regmap_reg_range(0x2400, 0x2401), |
749 | regmap_reg_range(0x2403, 0x2403), |
750 | regmap_reg_range(0x2410, 0x2417), |
751 | regmap_reg_range(0x2420, 0x2423), |
752 | regmap_reg_range(0x2500, 0x2507), |
753 | regmap_reg_range(0x2600, 0x2613), |
754 | regmap_reg_range(0x2800, 0x280f), |
755 | regmap_reg_range(0x2820, 0x2827), |
756 | regmap_reg_range(0x2830, 0x2837), |
757 | regmap_reg_range(0x2840, 0x284b), |
758 | regmap_reg_range(0x2900, 0x2907), |
759 | regmap_reg_range(0x2914, 0x291b), |
760 | regmap_reg_range(0x2920, 0x2920), |
761 | regmap_reg_range(0x2923, 0x2927), |
762 | regmap_reg_range(0x2a00, 0x2a03), |
763 | regmap_reg_range(0x2a04, 0x2a07), |
764 | regmap_reg_range(0x2b00, 0x2b01), |
765 | regmap_reg_range(0x2b04, 0x2b04), |
766 | regmap_reg_range(0x2c00, 0x2c05), |
767 | regmap_reg_range(0x2c08, 0x2c1b), |
768 | |
769 | /* port 3 */ |
770 | regmap_reg_range(0x3000, 0x3001), |
771 | regmap_reg_range(0x3013, 0x3013), |
772 | regmap_reg_range(0x3017, 0x3017), |
773 | regmap_reg_range(0x301b, 0x301b), |
774 | regmap_reg_range(0x301f, 0x3020), |
775 | regmap_reg_range(0x3030, 0x3030), |
776 | regmap_reg_range(0x3100, 0x3115), |
777 | regmap_reg_range(0x311a, 0x311f), |
778 | regmap_reg_range(0x3120, 0x312b), |
779 | regmap_reg_range(0x3134, 0x313b), |
780 | regmap_reg_range(0x313c, 0x313f), |
781 | regmap_reg_range(0x3400, 0x3401), |
782 | regmap_reg_range(0x3403, 0x3403), |
783 | regmap_reg_range(0x3410, 0x3417), |
784 | regmap_reg_range(0x3420, 0x3423), |
785 | regmap_reg_range(0x3500, 0x3507), |
786 | regmap_reg_range(0x3600, 0x3613), |
787 | regmap_reg_range(0x3800, 0x380f), |
788 | regmap_reg_range(0x3820, 0x3827), |
789 | regmap_reg_range(0x3830, 0x3837), |
790 | regmap_reg_range(0x3840, 0x384b), |
791 | regmap_reg_range(0x3900, 0x3907), |
792 | regmap_reg_range(0x3914, 0x391b), |
793 | regmap_reg_range(0x3920, 0x3920), |
794 | regmap_reg_range(0x3923, 0x3927), |
795 | regmap_reg_range(0x3a00, 0x3a03), |
796 | regmap_reg_range(0x3a04, 0x3a07), |
797 | regmap_reg_range(0x3b00, 0x3b01), |
798 | regmap_reg_range(0x3b04, 0x3b04), |
799 | regmap_reg_range(0x3c00, 0x3c05), |
800 | regmap_reg_range(0x3c08, 0x3c1b), |
801 | |
802 | /* port 4 */ |
803 | regmap_reg_range(0x4000, 0x4001), |
804 | regmap_reg_range(0x4013, 0x4013), |
805 | regmap_reg_range(0x4017, 0x4017), |
806 | regmap_reg_range(0x401b, 0x401b), |
807 | regmap_reg_range(0x401f, 0x4020), |
808 | regmap_reg_range(0x4030, 0x4030), |
809 | regmap_reg_range(0x4100, 0x4115), |
810 | regmap_reg_range(0x411a, 0x411f), |
811 | regmap_reg_range(0x4120, 0x412b), |
812 | regmap_reg_range(0x4134, 0x413b), |
813 | regmap_reg_range(0x413c, 0x413f), |
814 | regmap_reg_range(0x4400, 0x4401), |
815 | regmap_reg_range(0x4403, 0x4403), |
816 | regmap_reg_range(0x4410, 0x4417), |
817 | regmap_reg_range(0x4420, 0x4423), |
818 | regmap_reg_range(0x4500, 0x4507), |
819 | regmap_reg_range(0x4600, 0x4613), |
820 | regmap_reg_range(0x4800, 0x480f), |
821 | regmap_reg_range(0x4820, 0x4827), |
822 | regmap_reg_range(0x4830, 0x4837), |
823 | regmap_reg_range(0x4840, 0x484b), |
824 | regmap_reg_range(0x4900, 0x4907), |
825 | regmap_reg_range(0x4914, 0x491b), |
826 | regmap_reg_range(0x4920, 0x4920), |
827 | regmap_reg_range(0x4923, 0x4927), |
828 | regmap_reg_range(0x4a00, 0x4a03), |
829 | regmap_reg_range(0x4a04, 0x4a07), |
830 | regmap_reg_range(0x4b00, 0x4b01), |
831 | regmap_reg_range(0x4b04, 0x4b04), |
832 | regmap_reg_range(0x4c00, 0x4c05), |
833 | regmap_reg_range(0x4c08, 0x4c1b), |
834 | |
835 | /* port 5 */ |
836 | regmap_reg_range(0x5000, 0x5001), |
837 | regmap_reg_range(0x5013, 0x5013), |
838 | regmap_reg_range(0x5017, 0x5017), |
839 | regmap_reg_range(0x501b, 0x501b), |
840 | regmap_reg_range(0x501f, 0x5020), |
841 | regmap_reg_range(0x5030, 0x5030), |
842 | regmap_reg_range(0x5100, 0x5115), |
843 | regmap_reg_range(0x511a, 0x511f), |
844 | regmap_reg_range(0x5120, 0x512b), |
845 | regmap_reg_range(0x5134, 0x513b), |
846 | regmap_reg_range(0x513c, 0x513f), |
847 | regmap_reg_range(0x5400, 0x5401), |
848 | regmap_reg_range(0x5403, 0x5403), |
849 | regmap_reg_range(0x5410, 0x5417), |
850 | regmap_reg_range(0x5420, 0x5423), |
851 | regmap_reg_range(0x5500, 0x5507), |
852 | regmap_reg_range(0x5600, 0x5613), |
853 | regmap_reg_range(0x5800, 0x580f), |
854 | regmap_reg_range(0x5820, 0x5827), |
855 | regmap_reg_range(0x5830, 0x5837), |
856 | regmap_reg_range(0x5840, 0x584b), |
857 | regmap_reg_range(0x5900, 0x5907), |
858 | regmap_reg_range(0x5914, 0x591b), |
859 | regmap_reg_range(0x5920, 0x5920), |
860 | regmap_reg_range(0x5923, 0x5927), |
861 | regmap_reg_range(0x5a00, 0x5a03), |
862 | regmap_reg_range(0x5a04, 0x5a07), |
863 | regmap_reg_range(0x5b00, 0x5b01), |
864 | regmap_reg_range(0x5b04, 0x5b04), |
865 | regmap_reg_range(0x5c00, 0x5c05), |
866 | regmap_reg_range(0x5c08, 0x5c1b), |
867 | |
868 | /* port 6 */ |
869 | regmap_reg_range(0x6000, 0x6001), |
870 | regmap_reg_range(0x6013, 0x6013), |
871 | regmap_reg_range(0x6017, 0x6017), |
872 | regmap_reg_range(0x601b, 0x601b), |
873 | regmap_reg_range(0x601f, 0x6020), |
874 | regmap_reg_range(0x6030, 0x6030), |
875 | regmap_reg_range(0x6300, 0x6301), |
876 | regmap_reg_range(0x6400, 0x6401), |
877 | regmap_reg_range(0x6403, 0x6403), |
878 | regmap_reg_range(0x6410, 0x6417), |
879 | regmap_reg_range(0x6420, 0x6423), |
880 | regmap_reg_range(0x6500, 0x6507), |
881 | regmap_reg_range(0x6600, 0x6613), |
882 | regmap_reg_range(0x6800, 0x680f), |
883 | regmap_reg_range(0x6820, 0x6827), |
884 | regmap_reg_range(0x6830, 0x6837), |
885 | regmap_reg_range(0x6840, 0x684b), |
886 | regmap_reg_range(0x6900, 0x6907), |
887 | regmap_reg_range(0x6914, 0x691b), |
888 | regmap_reg_range(0x6920, 0x6920), |
889 | regmap_reg_range(0x6923, 0x6927), |
890 | regmap_reg_range(0x6a00, 0x6a03), |
891 | regmap_reg_range(0x6a04, 0x6a07), |
892 | regmap_reg_range(0x6b00, 0x6b01), |
893 | regmap_reg_range(0x6b04, 0x6b04), |
894 | regmap_reg_range(0x6c00, 0x6c05), |
895 | regmap_reg_range(0x6c08, 0x6c1b), |
896 | |
897 | /* port 7 */ |
898 | regmap_reg_range(0x7000, 0x7001), |
899 | regmap_reg_range(0x7013, 0x7013), |
900 | regmap_reg_range(0x7017, 0x7017), |
901 | regmap_reg_range(0x701b, 0x701b), |
902 | regmap_reg_range(0x701f, 0x7020), |
903 | regmap_reg_range(0x7030, 0x7030), |
904 | regmap_reg_range(0x7200, 0x7203), |
905 | regmap_reg_range(0x7206, 0x7207), |
906 | regmap_reg_range(0x7300, 0x7301), |
907 | regmap_reg_range(0x7400, 0x7401), |
908 | regmap_reg_range(0x7403, 0x7403), |
909 | regmap_reg_range(0x7410, 0x7417), |
910 | regmap_reg_range(0x7420, 0x7423), |
911 | regmap_reg_range(0x7500, 0x7507), |
912 | regmap_reg_range(0x7600, 0x7613), |
913 | regmap_reg_range(0x7800, 0x780f), |
914 | regmap_reg_range(0x7820, 0x7827), |
915 | regmap_reg_range(0x7830, 0x7837), |
916 | regmap_reg_range(0x7840, 0x784b), |
917 | regmap_reg_range(0x7900, 0x7907), |
918 | regmap_reg_range(0x7914, 0x791b), |
919 | regmap_reg_range(0x7920, 0x7920), |
920 | regmap_reg_range(0x7923, 0x7927), |
921 | regmap_reg_range(0x7a00, 0x7a03), |
922 | regmap_reg_range(0x7a04, 0x7a07), |
923 | regmap_reg_range(0x7b00, 0x7b01), |
924 | regmap_reg_range(0x7b04, 0x7b04), |
925 | regmap_reg_range(0x7c00, 0x7c05), |
926 | regmap_reg_range(0x7c08, 0x7c1b), |
927 | }; |
928 | |
929 | static const struct regmap_access_table ksz9477_register_set = { |
930 | .yes_ranges = ksz9477_valid_regs, |
931 | .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), |
932 | }; |
933 | |
934 | static const struct regmap_range ksz9896_valid_regs[] = { |
935 | regmap_reg_range(0x0000, 0x0003), |
936 | regmap_reg_range(0x0006, 0x0006), |
937 | regmap_reg_range(0x0010, 0x001f), |
938 | regmap_reg_range(0x0100, 0x0100), |
939 | regmap_reg_range(0x0103, 0x0107), |
940 | regmap_reg_range(0x010d, 0x010d), |
941 | regmap_reg_range(0x0110, 0x0113), |
942 | regmap_reg_range(0x0120, 0x0127), |
943 | regmap_reg_range(0x0201, 0x0201), |
944 | regmap_reg_range(0x0210, 0x0213), |
945 | regmap_reg_range(0x0300, 0x0300), |
946 | regmap_reg_range(0x0302, 0x030b), |
947 | regmap_reg_range(0x0310, 0x031b), |
948 | regmap_reg_range(0x0320, 0x032b), |
949 | regmap_reg_range(0x0330, 0x0336), |
950 | regmap_reg_range(0x0338, 0x033b), |
951 | regmap_reg_range(0x033e, 0x033e), |
952 | regmap_reg_range(0x0340, 0x035f), |
953 | regmap_reg_range(0x0370, 0x0370), |
954 | regmap_reg_range(0x0378, 0x0378), |
955 | regmap_reg_range(0x037c, 0x037d), |
956 | regmap_reg_range(0x0390, 0x0393), |
957 | regmap_reg_range(0x0400, 0x040e), |
958 | regmap_reg_range(0x0410, 0x042f), |
959 | |
960 | /* port 1 */ |
961 | regmap_reg_range(0x1000, 0x1001), |
962 | regmap_reg_range(0x1013, 0x1013), |
963 | regmap_reg_range(0x1017, 0x1017), |
964 | regmap_reg_range(0x101b, 0x101b), |
965 | regmap_reg_range(0x101f, 0x1020), |
966 | regmap_reg_range(0x1030, 0x1030), |
967 | regmap_reg_range(0x1100, 0x1115), |
968 | regmap_reg_range(0x111a, 0x111f), |
969 | regmap_reg_range(0x1122, 0x1127), |
970 | regmap_reg_range(0x112a, 0x112b), |
971 | regmap_reg_range(0x1136, 0x1139), |
972 | regmap_reg_range(0x113e, 0x113f), |
973 | regmap_reg_range(0x1400, 0x1401), |
974 | regmap_reg_range(0x1403, 0x1403), |
975 | regmap_reg_range(0x1410, 0x1417), |
976 | regmap_reg_range(0x1420, 0x1423), |
977 | regmap_reg_range(0x1500, 0x1507), |
978 | regmap_reg_range(0x1600, 0x1612), |
979 | regmap_reg_range(0x1800, 0x180f), |
980 | regmap_reg_range(0x1820, 0x1827), |
981 | regmap_reg_range(0x1830, 0x1837), |
982 | regmap_reg_range(0x1840, 0x184b), |
983 | regmap_reg_range(0x1900, 0x1907), |
984 | regmap_reg_range(0x1914, 0x1915), |
985 | regmap_reg_range(0x1a00, 0x1a03), |
986 | regmap_reg_range(0x1a04, 0x1a07), |
987 | regmap_reg_range(0x1b00, 0x1b01), |
988 | regmap_reg_range(0x1b04, 0x1b04), |
989 | |
990 | /* port 2 */ |
991 | regmap_reg_range(0x2000, 0x2001), |
992 | regmap_reg_range(0x2013, 0x2013), |
993 | regmap_reg_range(0x2017, 0x2017), |
994 | regmap_reg_range(0x201b, 0x201b), |
995 | regmap_reg_range(0x201f, 0x2020), |
996 | regmap_reg_range(0x2030, 0x2030), |
997 | regmap_reg_range(0x2100, 0x2115), |
998 | regmap_reg_range(0x211a, 0x211f), |
999 | regmap_reg_range(0x2122, 0x2127), |
1000 | regmap_reg_range(0x212a, 0x212b), |
1001 | regmap_reg_range(0x2136, 0x2139), |
1002 | regmap_reg_range(0x213e, 0x213f), |
1003 | regmap_reg_range(0x2400, 0x2401), |
1004 | regmap_reg_range(0x2403, 0x2403), |
1005 | regmap_reg_range(0x2410, 0x2417), |
1006 | regmap_reg_range(0x2420, 0x2423), |
1007 | regmap_reg_range(0x2500, 0x2507), |
1008 | regmap_reg_range(0x2600, 0x2612), |
1009 | regmap_reg_range(0x2800, 0x280f), |
1010 | regmap_reg_range(0x2820, 0x2827), |
1011 | regmap_reg_range(0x2830, 0x2837), |
1012 | regmap_reg_range(0x2840, 0x284b), |
1013 | regmap_reg_range(0x2900, 0x2907), |
1014 | regmap_reg_range(0x2914, 0x2915), |
1015 | regmap_reg_range(0x2a00, 0x2a03), |
1016 | regmap_reg_range(0x2a04, 0x2a07), |
1017 | regmap_reg_range(0x2b00, 0x2b01), |
1018 | regmap_reg_range(0x2b04, 0x2b04), |
1019 | |
1020 | /* port 3 */ |
1021 | regmap_reg_range(0x3000, 0x3001), |
1022 | regmap_reg_range(0x3013, 0x3013), |
1023 | regmap_reg_range(0x3017, 0x3017), |
1024 | regmap_reg_range(0x301b, 0x301b), |
1025 | regmap_reg_range(0x301f, 0x3020), |
1026 | regmap_reg_range(0x3030, 0x3030), |
1027 | regmap_reg_range(0x3100, 0x3115), |
1028 | regmap_reg_range(0x311a, 0x311f), |
1029 | regmap_reg_range(0x3122, 0x3127), |
1030 | regmap_reg_range(0x312a, 0x312b), |
1031 | regmap_reg_range(0x3136, 0x3139), |
1032 | regmap_reg_range(0x313e, 0x313f), |
1033 | regmap_reg_range(0x3400, 0x3401), |
1034 | regmap_reg_range(0x3403, 0x3403), |
1035 | regmap_reg_range(0x3410, 0x3417), |
1036 | regmap_reg_range(0x3420, 0x3423), |
1037 | regmap_reg_range(0x3500, 0x3507), |
1038 | regmap_reg_range(0x3600, 0x3612), |
1039 | regmap_reg_range(0x3800, 0x380f), |
1040 | regmap_reg_range(0x3820, 0x3827), |
1041 | regmap_reg_range(0x3830, 0x3837), |
1042 | regmap_reg_range(0x3840, 0x384b), |
1043 | regmap_reg_range(0x3900, 0x3907), |
1044 | regmap_reg_range(0x3914, 0x3915), |
1045 | regmap_reg_range(0x3a00, 0x3a03), |
1046 | regmap_reg_range(0x3a04, 0x3a07), |
1047 | regmap_reg_range(0x3b00, 0x3b01), |
1048 | regmap_reg_range(0x3b04, 0x3b04), |
1049 | |
1050 | /* port 4 */ |
1051 | regmap_reg_range(0x4000, 0x4001), |
1052 | regmap_reg_range(0x4013, 0x4013), |
1053 | regmap_reg_range(0x4017, 0x4017), |
1054 | regmap_reg_range(0x401b, 0x401b), |
1055 | regmap_reg_range(0x401f, 0x4020), |
1056 | regmap_reg_range(0x4030, 0x4030), |
1057 | regmap_reg_range(0x4100, 0x4115), |
1058 | regmap_reg_range(0x411a, 0x411f), |
1059 | regmap_reg_range(0x4122, 0x4127), |
1060 | regmap_reg_range(0x412a, 0x412b), |
1061 | regmap_reg_range(0x4136, 0x4139), |
1062 | regmap_reg_range(0x413e, 0x413f), |
1063 | regmap_reg_range(0x4400, 0x4401), |
1064 | regmap_reg_range(0x4403, 0x4403), |
1065 | regmap_reg_range(0x4410, 0x4417), |
1066 | regmap_reg_range(0x4420, 0x4423), |
1067 | regmap_reg_range(0x4500, 0x4507), |
1068 | regmap_reg_range(0x4600, 0x4612), |
1069 | regmap_reg_range(0x4800, 0x480f), |
1070 | regmap_reg_range(0x4820, 0x4827), |
1071 | regmap_reg_range(0x4830, 0x4837), |
1072 | regmap_reg_range(0x4840, 0x484b), |
1073 | regmap_reg_range(0x4900, 0x4907), |
1074 | regmap_reg_range(0x4914, 0x4915), |
1075 | regmap_reg_range(0x4a00, 0x4a03), |
1076 | regmap_reg_range(0x4a04, 0x4a07), |
1077 | regmap_reg_range(0x4b00, 0x4b01), |
1078 | regmap_reg_range(0x4b04, 0x4b04), |
1079 | |
1080 | /* port 5 */ |
1081 | regmap_reg_range(0x5000, 0x5001), |
1082 | regmap_reg_range(0x5013, 0x5013), |
1083 | regmap_reg_range(0x5017, 0x5017), |
1084 | regmap_reg_range(0x501b, 0x501b), |
1085 | regmap_reg_range(0x501f, 0x5020), |
1086 | regmap_reg_range(0x5030, 0x5030), |
1087 | regmap_reg_range(0x5100, 0x5115), |
1088 | regmap_reg_range(0x511a, 0x511f), |
1089 | regmap_reg_range(0x5122, 0x5127), |
1090 | regmap_reg_range(0x512a, 0x512b), |
1091 | regmap_reg_range(0x5136, 0x5139), |
1092 | regmap_reg_range(0x513e, 0x513f), |
1093 | regmap_reg_range(0x5400, 0x5401), |
1094 | regmap_reg_range(0x5403, 0x5403), |
1095 | regmap_reg_range(0x5410, 0x5417), |
1096 | regmap_reg_range(0x5420, 0x5423), |
1097 | regmap_reg_range(0x5500, 0x5507), |
1098 | regmap_reg_range(0x5600, 0x5612), |
1099 | regmap_reg_range(0x5800, 0x580f), |
1100 | regmap_reg_range(0x5820, 0x5827), |
1101 | regmap_reg_range(0x5830, 0x5837), |
1102 | regmap_reg_range(0x5840, 0x584b), |
1103 | regmap_reg_range(0x5900, 0x5907), |
1104 | regmap_reg_range(0x5914, 0x5915), |
1105 | regmap_reg_range(0x5a00, 0x5a03), |
1106 | regmap_reg_range(0x5a04, 0x5a07), |
1107 | regmap_reg_range(0x5b00, 0x5b01), |
1108 | regmap_reg_range(0x5b04, 0x5b04), |
1109 | |
1110 | /* port 6 */ |
1111 | regmap_reg_range(0x6000, 0x6001), |
1112 | regmap_reg_range(0x6013, 0x6013), |
1113 | regmap_reg_range(0x6017, 0x6017), |
1114 | regmap_reg_range(0x601b, 0x601b), |
1115 | regmap_reg_range(0x601f, 0x6020), |
1116 | regmap_reg_range(0x6030, 0x6030), |
1117 | regmap_reg_range(0x6100, 0x6115), |
1118 | regmap_reg_range(0x611a, 0x611f), |
1119 | regmap_reg_range(0x6122, 0x6127), |
1120 | regmap_reg_range(0x612a, 0x612b), |
1121 | regmap_reg_range(0x6136, 0x6139), |
1122 | regmap_reg_range(0x613e, 0x613f), |
1123 | regmap_reg_range(0x6300, 0x6301), |
1124 | regmap_reg_range(0x6400, 0x6401), |
1125 | regmap_reg_range(0x6403, 0x6403), |
1126 | regmap_reg_range(0x6410, 0x6417), |
1127 | regmap_reg_range(0x6420, 0x6423), |
1128 | regmap_reg_range(0x6500, 0x6507), |
1129 | regmap_reg_range(0x6600, 0x6612), |
1130 | regmap_reg_range(0x6800, 0x680f), |
1131 | regmap_reg_range(0x6820, 0x6827), |
1132 | regmap_reg_range(0x6830, 0x6837), |
1133 | regmap_reg_range(0x6840, 0x684b), |
1134 | regmap_reg_range(0x6900, 0x6907), |
1135 | regmap_reg_range(0x6914, 0x6915), |
1136 | regmap_reg_range(0x6a00, 0x6a03), |
1137 | regmap_reg_range(0x6a04, 0x6a07), |
1138 | regmap_reg_range(0x6b00, 0x6b01), |
1139 | regmap_reg_range(0x6b04, 0x6b04), |
1140 | }; |
1141 | |
1142 | static const struct regmap_access_table ksz9896_register_set = { |
1143 | .yes_ranges = ksz9896_valid_regs, |
1144 | .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), |
1145 | }; |
1146 | |
1147 | static const struct regmap_range ksz8873_valid_regs[] = { |
1148 | regmap_reg_range(0x00, 0x01), |
1149 | /* global control register */ |
1150 | regmap_reg_range(0x02, 0x0f), |
1151 | |
1152 | /* port registers */ |
1153 | regmap_reg_range(0x10, 0x1d), |
1154 | regmap_reg_range(0x1e, 0x1f), |
1155 | regmap_reg_range(0x20, 0x2d), |
1156 | regmap_reg_range(0x2e, 0x2f), |
1157 | regmap_reg_range(0x30, 0x39), |
1158 | regmap_reg_range(0x3f, 0x3f), |
1159 | |
1160 | /* advanced control registers */ |
1161 | regmap_reg_range(0x60, 0x6f), |
1162 | regmap_reg_range(0x70, 0x75), |
1163 | regmap_reg_range(0x76, 0x78), |
1164 | regmap_reg_range(0x79, 0x7a), |
1165 | regmap_reg_range(0x7b, 0x83), |
1166 | regmap_reg_range(0x8e, 0x99), |
1167 | regmap_reg_range(0x9a, 0xa5), |
1168 | regmap_reg_range(0xa6, 0xa6), |
1169 | regmap_reg_range(0xa7, 0xaa), |
1170 | regmap_reg_range(0xab, 0xae), |
1171 | regmap_reg_range(0xaf, 0xba), |
1172 | regmap_reg_range(0xbb, 0xbc), |
1173 | regmap_reg_range(0xbd, 0xbd), |
1174 | regmap_reg_range(0xc0, 0xc0), |
1175 | regmap_reg_range(0xc2, 0xc2), |
1176 | regmap_reg_range(0xc3, 0xc3), |
1177 | regmap_reg_range(0xc4, 0xc4), |
1178 | regmap_reg_range(0xc6, 0xc6), |
1179 | }; |
1180 | |
1181 | static const struct regmap_access_table ksz8873_register_set = { |
1182 | .yes_ranges = ksz8873_valid_regs, |
1183 | .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), |
1184 | }; |
1185 | |
1186 | const struct ksz_chip_data ksz_switch_chips[] = { |
1187 | [KSZ8563] = { |
1188 | .chip_id = KSZ8563_CHIP_ID, |
1189 | .dev_name = "KSZ8563" , |
1190 | .num_vlans = 4096, |
1191 | .num_alus = 4096, |
1192 | .num_statics = 16, |
1193 | .cpu_ports = 0x07, /* can be configured as cpu port */ |
1194 | .port_cnt = 3, /* total port count */ |
1195 | .port_nirqs = 3, |
1196 | .num_tx_queues = 4, |
1197 | .tc_cbs_supported = true, |
1198 | .tc_ets_supported = true, |
1199 | .ops = &ksz9477_dev_ops, |
1200 | .mib_names = ksz9477_mib_names, |
1201 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1202 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1203 | .regs = ksz9477_regs, |
1204 | .masks = ksz9477_masks, |
1205 | .shifts = ksz9477_shifts, |
1206 | .xmii_ctrl0 = ksz9477_xmii_ctrl0, |
1207 | .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ |
1208 | .supports_mii = {false, false, true}, |
1209 | .supports_rmii = {false, false, true}, |
1210 | .supports_rgmii = {false, false, true}, |
1211 | .internal_phy = {true, true, false}, |
1212 | .gbit_capable = {false, false, true}, |
1213 | .wr_table = &ksz8563_register_set, |
1214 | .rd_table = &ksz8563_register_set, |
1215 | }, |
1216 | |
1217 | [KSZ8795] = { |
1218 | .chip_id = KSZ8795_CHIP_ID, |
1219 | .dev_name = "KSZ8795" , |
1220 | .num_vlans = 4096, |
1221 | .num_alus = 0, |
1222 | .num_statics = 8, |
1223 | .cpu_ports = 0x10, /* can be configured as cpu port */ |
1224 | .port_cnt = 5, /* total cpu and user ports */ |
1225 | .num_tx_queues = 4, |
1226 | .ops = &ksz8_dev_ops, |
1227 | .ksz87xx_eee_link_erratum = true, |
1228 | .mib_names = ksz9477_mib_names, |
1229 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1230 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1231 | .regs = ksz8795_regs, |
1232 | .masks = ksz8795_masks, |
1233 | .shifts = ksz8795_shifts, |
1234 | .xmii_ctrl0 = ksz8795_xmii_ctrl0, |
1235 | .xmii_ctrl1 = ksz8795_xmii_ctrl1, |
1236 | .supports_mii = {false, false, false, false, true}, |
1237 | .supports_rmii = {false, false, false, false, true}, |
1238 | .supports_rgmii = {false, false, false, false, true}, |
1239 | .internal_phy = {true, true, true, true, false}, |
1240 | }, |
1241 | |
1242 | [KSZ8794] = { |
1243 | /* WARNING |
1244 | * ======= |
1245 | * KSZ8794 is similar to KSZ8795, except the port map |
1246 | * contains a gap between external and CPU ports, the |
1247 | * port map is NOT continuous. The per-port register |
1248 | * map is shifted accordingly too, i.e. registers at |
1249 | * offset 0x40 are NOT used on KSZ8794 and they ARE |
1250 | * used on KSZ8795 for external port 3. |
1251 | * external cpu |
1252 | * KSZ8794 0,1,2 4 |
1253 | * KSZ8795 0,1,2,3 4 |
1254 | * KSZ8765 0,1,2,3 4 |
1255 | * port_cnt is configured as 5, even though it is 4 |
1256 | */ |
1257 | .chip_id = KSZ8794_CHIP_ID, |
1258 | .dev_name = "KSZ8794" , |
1259 | .num_vlans = 4096, |
1260 | .num_alus = 0, |
1261 | .num_statics = 8, |
1262 | .cpu_ports = 0x10, /* can be configured as cpu port */ |
1263 | .port_cnt = 5, /* total cpu and user ports */ |
1264 | .num_tx_queues = 4, |
1265 | .ops = &ksz8_dev_ops, |
1266 | .ksz87xx_eee_link_erratum = true, |
1267 | .mib_names = ksz9477_mib_names, |
1268 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1269 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1270 | .regs = ksz8795_regs, |
1271 | .masks = ksz8795_masks, |
1272 | .shifts = ksz8795_shifts, |
1273 | .xmii_ctrl0 = ksz8795_xmii_ctrl0, |
1274 | .xmii_ctrl1 = ksz8795_xmii_ctrl1, |
1275 | .supports_mii = {false, false, false, false, true}, |
1276 | .supports_rmii = {false, false, false, false, true}, |
1277 | .supports_rgmii = {false, false, false, false, true}, |
1278 | .internal_phy = {true, true, true, false, false}, |
1279 | }, |
1280 | |
1281 | [KSZ8765] = { |
1282 | .chip_id = KSZ8765_CHIP_ID, |
1283 | .dev_name = "KSZ8765" , |
1284 | .num_vlans = 4096, |
1285 | .num_alus = 0, |
1286 | .num_statics = 8, |
1287 | .cpu_ports = 0x10, /* can be configured as cpu port */ |
1288 | .port_cnt = 5, /* total cpu and user ports */ |
1289 | .num_tx_queues = 4, |
1290 | .ops = &ksz8_dev_ops, |
1291 | .ksz87xx_eee_link_erratum = true, |
1292 | .mib_names = ksz9477_mib_names, |
1293 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1294 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1295 | .regs = ksz8795_regs, |
1296 | .masks = ksz8795_masks, |
1297 | .shifts = ksz8795_shifts, |
1298 | .xmii_ctrl0 = ksz8795_xmii_ctrl0, |
1299 | .xmii_ctrl1 = ksz8795_xmii_ctrl1, |
1300 | .supports_mii = {false, false, false, false, true}, |
1301 | .supports_rmii = {false, false, false, false, true}, |
1302 | .supports_rgmii = {false, false, false, false, true}, |
1303 | .internal_phy = {true, true, true, true, false}, |
1304 | }, |
1305 | |
1306 | [KSZ8830] = { |
1307 | .chip_id = KSZ8830_CHIP_ID, |
1308 | .dev_name = "KSZ8863/KSZ8873" , |
1309 | .num_vlans = 16, |
1310 | .num_alus = 0, |
1311 | .num_statics = 8, |
1312 | .cpu_ports = 0x4, /* can be configured as cpu port */ |
1313 | .port_cnt = 3, |
1314 | .num_tx_queues = 4, |
1315 | .ops = &ksz8_dev_ops, |
1316 | .mib_names = ksz88xx_mib_names, |
1317 | .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), |
1318 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1319 | .regs = ksz8863_regs, |
1320 | .masks = ksz8863_masks, |
1321 | .shifts = ksz8863_shifts, |
1322 | .supports_mii = {false, false, true}, |
1323 | .supports_rmii = {false, false, true}, |
1324 | .internal_phy = {true, true, false}, |
1325 | .wr_table = &ksz8873_register_set, |
1326 | .rd_table = &ksz8873_register_set, |
1327 | }, |
1328 | |
1329 | [KSZ9477] = { |
1330 | .chip_id = KSZ9477_CHIP_ID, |
1331 | .dev_name = "KSZ9477" , |
1332 | .num_vlans = 4096, |
1333 | .num_alus = 4096, |
1334 | .num_statics = 16, |
1335 | .cpu_ports = 0x7F, /* can be configured as cpu port */ |
1336 | .port_cnt = 7, /* total physical port count */ |
1337 | .port_nirqs = 4, |
1338 | .num_tx_queues = 4, |
1339 | .tc_cbs_supported = true, |
1340 | .tc_ets_supported = true, |
1341 | .ops = &ksz9477_dev_ops, |
1342 | .mib_names = ksz9477_mib_names, |
1343 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1344 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1345 | .regs = ksz9477_regs, |
1346 | .masks = ksz9477_masks, |
1347 | .shifts = ksz9477_shifts, |
1348 | .xmii_ctrl0 = ksz9477_xmii_ctrl0, |
1349 | .xmii_ctrl1 = ksz9477_xmii_ctrl1, |
1350 | .supports_mii = {false, false, false, false, |
1351 | false, true, false}, |
1352 | .supports_rmii = {false, false, false, false, |
1353 | false, true, false}, |
1354 | .supports_rgmii = {false, false, false, false, |
1355 | false, true, false}, |
1356 | .internal_phy = {true, true, true, true, |
1357 | true, false, false}, |
1358 | .gbit_capable = {true, true, true, true, true, true, true}, |
1359 | .wr_table = &ksz9477_register_set, |
1360 | .rd_table = &ksz9477_register_set, |
1361 | }, |
1362 | |
1363 | [KSZ9896] = { |
1364 | .chip_id = KSZ9896_CHIP_ID, |
1365 | .dev_name = "KSZ9896" , |
1366 | .num_vlans = 4096, |
1367 | .num_alus = 4096, |
1368 | .num_statics = 16, |
1369 | .cpu_ports = 0x3F, /* can be configured as cpu port */ |
1370 | .port_cnt = 6, /* total physical port count */ |
1371 | .port_nirqs = 2, |
1372 | .num_tx_queues = 4, |
1373 | .ops = &ksz9477_dev_ops, |
1374 | .mib_names = ksz9477_mib_names, |
1375 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1376 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1377 | .regs = ksz9477_regs, |
1378 | .masks = ksz9477_masks, |
1379 | .shifts = ksz9477_shifts, |
1380 | .xmii_ctrl0 = ksz9477_xmii_ctrl0, |
1381 | .xmii_ctrl1 = ksz9477_xmii_ctrl1, |
1382 | .supports_mii = {false, false, false, false, |
1383 | false, true}, |
1384 | .supports_rmii = {false, false, false, false, |
1385 | false, true}, |
1386 | .supports_rgmii = {false, false, false, false, |
1387 | false, true}, |
1388 | .internal_phy = {true, true, true, true, |
1389 | true, false}, |
1390 | .gbit_capable = {true, true, true, true, true, true}, |
1391 | .wr_table = &ksz9896_register_set, |
1392 | .rd_table = &ksz9896_register_set, |
1393 | }, |
1394 | |
1395 | [KSZ9897] = { |
1396 | .chip_id = KSZ9897_CHIP_ID, |
1397 | .dev_name = "KSZ9897" , |
1398 | .num_vlans = 4096, |
1399 | .num_alus = 4096, |
1400 | .num_statics = 16, |
1401 | .cpu_ports = 0x7F, /* can be configured as cpu port */ |
1402 | .port_cnt = 7, /* total physical port count */ |
1403 | .port_nirqs = 2, |
1404 | .num_tx_queues = 4, |
1405 | .ops = &ksz9477_dev_ops, |
1406 | .mib_names = ksz9477_mib_names, |
1407 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1408 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1409 | .regs = ksz9477_regs, |
1410 | .masks = ksz9477_masks, |
1411 | .shifts = ksz9477_shifts, |
1412 | .xmii_ctrl0 = ksz9477_xmii_ctrl0, |
1413 | .xmii_ctrl1 = ksz9477_xmii_ctrl1, |
1414 | .supports_mii = {false, false, false, false, |
1415 | false, true, true}, |
1416 | .supports_rmii = {false, false, false, false, |
1417 | false, true, true}, |
1418 | .supports_rgmii = {false, false, false, false, |
1419 | false, true, true}, |
1420 | .internal_phy = {true, true, true, true, |
1421 | true, false, false}, |
1422 | .gbit_capable = {true, true, true, true, true, true, true}, |
1423 | }, |
1424 | |
1425 | [KSZ9893] = { |
1426 | .chip_id = KSZ9893_CHIP_ID, |
1427 | .dev_name = "KSZ9893" , |
1428 | .num_vlans = 4096, |
1429 | .num_alus = 4096, |
1430 | .num_statics = 16, |
1431 | .cpu_ports = 0x07, /* can be configured as cpu port */ |
1432 | .port_cnt = 3, /* total port count */ |
1433 | .port_nirqs = 2, |
1434 | .num_tx_queues = 4, |
1435 | .ops = &ksz9477_dev_ops, |
1436 | .mib_names = ksz9477_mib_names, |
1437 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1438 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1439 | .regs = ksz9477_regs, |
1440 | .masks = ksz9477_masks, |
1441 | .shifts = ksz9477_shifts, |
1442 | .xmii_ctrl0 = ksz9477_xmii_ctrl0, |
1443 | .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ |
1444 | .supports_mii = {false, false, true}, |
1445 | .supports_rmii = {false, false, true}, |
1446 | .supports_rgmii = {false, false, true}, |
1447 | .internal_phy = {true, true, false}, |
1448 | .gbit_capable = {true, true, true}, |
1449 | }, |
1450 | |
1451 | [KSZ9563] = { |
1452 | .chip_id = KSZ9563_CHIP_ID, |
1453 | .dev_name = "KSZ9563" , |
1454 | .num_vlans = 4096, |
1455 | .num_alus = 4096, |
1456 | .num_statics = 16, |
1457 | .cpu_ports = 0x07, /* can be configured as cpu port */ |
1458 | .port_cnt = 3, /* total port count */ |
1459 | .port_nirqs = 3, |
1460 | .num_tx_queues = 4, |
1461 | .tc_cbs_supported = true, |
1462 | .tc_ets_supported = true, |
1463 | .ops = &ksz9477_dev_ops, |
1464 | .mib_names = ksz9477_mib_names, |
1465 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1466 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1467 | .regs = ksz9477_regs, |
1468 | .masks = ksz9477_masks, |
1469 | .shifts = ksz9477_shifts, |
1470 | .xmii_ctrl0 = ksz9477_xmii_ctrl0, |
1471 | .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ |
1472 | .supports_mii = {false, false, true}, |
1473 | .supports_rmii = {false, false, true}, |
1474 | .supports_rgmii = {false, false, true}, |
1475 | .internal_phy = {true, true, false}, |
1476 | .gbit_capable = {true, true, true}, |
1477 | }, |
1478 | |
1479 | [KSZ8567] = { |
1480 | .chip_id = KSZ8567_CHIP_ID, |
1481 | .dev_name = "KSZ8567" , |
1482 | .num_vlans = 4096, |
1483 | .num_alus = 4096, |
1484 | .num_statics = 16, |
1485 | .cpu_ports = 0x7F, /* can be configured as cpu port */ |
1486 | .port_cnt = 7, /* total port count */ |
1487 | .port_nirqs = 3, |
1488 | .num_tx_queues = 4, |
1489 | .tc_cbs_supported = true, |
1490 | .tc_ets_supported = true, |
1491 | .ops = &ksz9477_dev_ops, |
1492 | .mib_names = ksz9477_mib_names, |
1493 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1494 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1495 | .regs = ksz9477_regs, |
1496 | .masks = ksz9477_masks, |
1497 | .shifts = ksz9477_shifts, |
1498 | .xmii_ctrl0 = ksz9477_xmii_ctrl0, |
1499 | .xmii_ctrl1 = ksz9477_xmii_ctrl1, |
1500 | .supports_mii = {false, false, false, false, |
1501 | false, true, true}, |
1502 | .supports_rmii = {false, false, false, false, |
1503 | false, true, true}, |
1504 | .supports_rgmii = {false, false, false, false, |
1505 | false, true, true}, |
1506 | .internal_phy = {true, true, true, true, |
1507 | true, false, false}, |
1508 | .gbit_capable = {false, false, false, false, false, |
1509 | true, true}, |
1510 | }, |
1511 | |
1512 | [KSZ9567] = { |
1513 | .chip_id = KSZ9567_CHIP_ID, |
1514 | .dev_name = "KSZ9567" , |
1515 | .num_vlans = 4096, |
1516 | .num_alus = 4096, |
1517 | .num_statics = 16, |
1518 | .cpu_ports = 0x7F, /* can be configured as cpu port */ |
1519 | .port_cnt = 7, /* total physical port count */ |
1520 | .port_nirqs = 3, |
1521 | .num_tx_queues = 4, |
1522 | .tc_cbs_supported = true, |
1523 | .tc_ets_supported = true, |
1524 | .ops = &ksz9477_dev_ops, |
1525 | .mib_names = ksz9477_mib_names, |
1526 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1527 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1528 | .regs = ksz9477_regs, |
1529 | .masks = ksz9477_masks, |
1530 | .shifts = ksz9477_shifts, |
1531 | .xmii_ctrl0 = ksz9477_xmii_ctrl0, |
1532 | .xmii_ctrl1 = ksz9477_xmii_ctrl1, |
1533 | .supports_mii = {false, false, false, false, |
1534 | false, true, true}, |
1535 | .supports_rmii = {false, false, false, false, |
1536 | false, true, true}, |
1537 | .supports_rgmii = {false, false, false, false, |
1538 | false, true, true}, |
1539 | .internal_phy = {true, true, true, true, |
1540 | true, false, false}, |
1541 | .gbit_capable = {true, true, true, true, true, true, true}, |
1542 | }, |
1543 | |
1544 | [LAN9370] = { |
1545 | .chip_id = LAN9370_CHIP_ID, |
1546 | .dev_name = "LAN9370" , |
1547 | .num_vlans = 4096, |
1548 | .num_alus = 1024, |
1549 | .num_statics = 256, |
1550 | .cpu_ports = 0x10, /* can be configured as cpu port */ |
1551 | .port_cnt = 5, /* total physical port count */ |
1552 | .port_nirqs = 6, |
1553 | .num_tx_queues = 8, |
1554 | .tc_cbs_supported = true, |
1555 | .tc_ets_supported = true, |
1556 | .ops = &lan937x_dev_ops, |
1557 | .mib_names = ksz9477_mib_names, |
1558 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1559 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1560 | .regs = ksz9477_regs, |
1561 | .masks = lan937x_masks, |
1562 | .shifts = lan937x_shifts, |
1563 | .xmii_ctrl0 = ksz9477_xmii_ctrl0, |
1564 | .xmii_ctrl1 = ksz9477_xmii_ctrl1, |
1565 | .supports_mii = {false, false, false, false, true}, |
1566 | .supports_rmii = {false, false, false, false, true}, |
1567 | .supports_rgmii = {false, false, false, false, true}, |
1568 | .internal_phy = {true, true, true, true, false}, |
1569 | }, |
1570 | |
1571 | [LAN9371] = { |
1572 | .chip_id = LAN9371_CHIP_ID, |
1573 | .dev_name = "LAN9371" , |
1574 | .num_vlans = 4096, |
1575 | .num_alus = 1024, |
1576 | .num_statics = 256, |
1577 | .cpu_ports = 0x30, /* can be configured as cpu port */ |
1578 | .port_cnt = 6, /* total physical port count */ |
1579 | .port_nirqs = 6, |
1580 | .num_tx_queues = 8, |
1581 | .tc_cbs_supported = true, |
1582 | .tc_ets_supported = true, |
1583 | .ops = &lan937x_dev_ops, |
1584 | .mib_names = ksz9477_mib_names, |
1585 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1586 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1587 | .regs = ksz9477_regs, |
1588 | .masks = lan937x_masks, |
1589 | .shifts = lan937x_shifts, |
1590 | .xmii_ctrl0 = ksz9477_xmii_ctrl0, |
1591 | .xmii_ctrl1 = ksz9477_xmii_ctrl1, |
1592 | .supports_mii = {false, false, false, false, true, true}, |
1593 | .supports_rmii = {false, false, false, false, true, true}, |
1594 | .supports_rgmii = {false, false, false, false, true, true}, |
1595 | .internal_phy = {true, true, true, true, false, false}, |
1596 | }, |
1597 | |
1598 | [LAN9372] = { |
1599 | .chip_id = LAN9372_CHIP_ID, |
1600 | .dev_name = "LAN9372" , |
1601 | .num_vlans = 4096, |
1602 | .num_alus = 1024, |
1603 | .num_statics = 256, |
1604 | .cpu_ports = 0x30, /* can be configured as cpu port */ |
1605 | .port_cnt = 8, /* total physical port count */ |
1606 | .port_nirqs = 6, |
1607 | .num_tx_queues = 8, |
1608 | .tc_cbs_supported = true, |
1609 | .tc_ets_supported = true, |
1610 | .ops = &lan937x_dev_ops, |
1611 | .mib_names = ksz9477_mib_names, |
1612 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1613 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1614 | .regs = ksz9477_regs, |
1615 | .masks = lan937x_masks, |
1616 | .shifts = lan937x_shifts, |
1617 | .xmii_ctrl0 = ksz9477_xmii_ctrl0, |
1618 | .xmii_ctrl1 = ksz9477_xmii_ctrl1, |
1619 | .supports_mii = {false, false, false, false, |
1620 | true, true, false, false}, |
1621 | .supports_rmii = {false, false, false, false, |
1622 | true, true, false, false}, |
1623 | .supports_rgmii = {false, false, false, false, |
1624 | true, true, false, false}, |
1625 | .internal_phy = {true, true, true, true, |
1626 | false, false, true, true}, |
1627 | }, |
1628 | |
1629 | [LAN9373] = { |
1630 | .chip_id = LAN9373_CHIP_ID, |
1631 | .dev_name = "LAN9373" , |
1632 | .num_vlans = 4096, |
1633 | .num_alus = 1024, |
1634 | .num_statics = 256, |
1635 | .cpu_ports = 0x38, /* can be configured as cpu port */ |
1636 | .port_cnt = 5, /* total physical port count */ |
1637 | .port_nirqs = 6, |
1638 | .num_tx_queues = 8, |
1639 | .tc_cbs_supported = true, |
1640 | .tc_ets_supported = true, |
1641 | .ops = &lan937x_dev_ops, |
1642 | .mib_names = ksz9477_mib_names, |
1643 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1644 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1645 | .regs = ksz9477_regs, |
1646 | .masks = lan937x_masks, |
1647 | .shifts = lan937x_shifts, |
1648 | .xmii_ctrl0 = ksz9477_xmii_ctrl0, |
1649 | .xmii_ctrl1 = ksz9477_xmii_ctrl1, |
1650 | .supports_mii = {false, false, false, false, |
1651 | true, true, false, false}, |
1652 | .supports_rmii = {false, false, false, false, |
1653 | true, true, false, false}, |
1654 | .supports_rgmii = {false, false, false, false, |
1655 | true, true, false, false}, |
1656 | .internal_phy = {true, true, true, false, |
1657 | false, false, true, true}, |
1658 | }, |
1659 | |
1660 | [LAN9374] = { |
1661 | .chip_id = LAN9374_CHIP_ID, |
1662 | .dev_name = "LAN9374" , |
1663 | .num_vlans = 4096, |
1664 | .num_alus = 1024, |
1665 | .num_statics = 256, |
1666 | .cpu_ports = 0x30, /* can be configured as cpu port */ |
1667 | .port_cnt = 8, /* total physical port count */ |
1668 | .port_nirqs = 6, |
1669 | .num_tx_queues = 8, |
1670 | .tc_cbs_supported = true, |
1671 | .tc_ets_supported = true, |
1672 | .ops = &lan937x_dev_ops, |
1673 | .mib_names = ksz9477_mib_names, |
1674 | .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), |
1675 | .reg_mib_cnt = MIB_COUNTER_NUM, |
1676 | .regs = ksz9477_regs, |
1677 | .masks = lan937x_masks, |
1678 | .shifts = lan937x_shifts, |
1679 | .xmii_ctrl0 = ksz9477_xmii_ctrl0, |
1680 | .xmii_ctrl1 = ksz9477_xmii_ctrl1, |
1681 | .supports_mii = {false, false, false, false, |
1682 | true, true, false, false}, |
1683 | .supports_rmii = {false, false, false, false, |
1684 | true, true, false, false}, |
1685 | .supports_rgmii = {false, false, false, false, |
1686 | true, true, false, false}, |
1687 | .internal_phy = {true, true, true, true, |
1688 | false, false, true, true}, |
1689 | }, |
1690 | }; |
1691 | EXPORT_SYMBOL_GPL(ksz_switch_chips); |
1692 | |
1693 | static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) |
1694 | { |
1695 | int i; |
1696 | |
1697 | for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { |
1698 | const struct ksz_chip_data *chip = &ksz_switch_chips[i]; |
1699 | |
1700 | if (chip->chip_id == prod_num) |
1701 | return chip; |
1702 | } |
1703 | |
1704 | return NULL; |
1705 | } |
1706 | |
1707 | static int ksz_check_device_id(struct ksz_device *dev) |
1708 | { |
1709 | const struct ksz_chip_data *expected_chip_data; |
1710 | u32 expected_chip_id; |
1711 | |
1712 | if (dev->pdata) { |
1713 | expected_chip_id = dev->pdata->chip_id; |
1714 | expected_chip_data = ksz_lookup_info(prod_num: expected_chip_id); |
1715 | if (WARN_ON(!expected_chip_data)) |
1716 | return -ENODEV; |
1717 | } else { |
1718 | expected_chip_data = of_device_get_match_data(dev: dev->dev); |
1719 | expected_chip_id = expected_chip_data->chip_id; |
1720 | } |
1721 | |
1722 | if (expected_chip_id != dev->chip_id) { |
1723 | dev_err(dev->dev, |
1724 | "Device tree specifies chip %s but found %s, please fix it!\n" , |
1725 | expected_chip_data->dev_name, dev->info->dev_name); |
1726 | return -ENODEV; |
1727 | } |
1728 | |
1729 | return 0; |
1730 | } |
1731 | |
1732 | static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, |
1733 | struct phylink_config *config) |
1734 | { |
1735 | struct ksz_device *dev = ds->priv; |
1736 | |
1737 | if (dev->info->supports_mii[port]) |
1738 | __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); |
1739 | |
1740 | if (dev->info->supports_rmii[port]) |
1741 | __set_bit(PHY_INTERFACE_MODE_RMII, |
1742 | config->supported_interfaces); |
1743 | |
1744 | if (dev->info->supports_rgmii[port]) |
1745 | phy_interface_set_rgmii(intf: config->supported_interfaces); |
1746 | |
1747 | if (dev->info->internal_phy[port]) { |
1748 | __set_bit(PHY_INTERFACE_MODE_INTERNAL, |
1749 | config->supported_interfaces); |
1750 | /* Compatibility for phylib's default interface type when the |
1751 | * phy-mode property is absent |
1752 | */ |
1753 | __set_bit(PHY_INTERFACE_MODE_GMII, |
1754 | config->supported_interfaces); |
1755 | } |
1756 | |
1757 | if (dev->dev_ops->get_caps) |
1758 | dev->dev_ops->get_caps(dev, port, config); |
1759 | } |
1760 | |
1761 | void ksz_r_mib_stats64(struct ksz_device *dev, int port) |
1762 | { |
1763 | struct ethtool_pause_stats *pstats; |
1764 | struct rtnl_link_stats64 *stats; |
1765 | struct ksz_stats_raw *raw; |
1766 | struct ksz_port_mib *mib; |
1767 | |
1768 | mib = &dev->ports[port].mib; |
1769 | stats = &mib->stats64; |
1770 | pstats = &mib->pause_stats; |
1771 | raw = (struct ksz_stats_raw *)mib->counters; |
1772 | |
1773 | spin_lock(lock: &mib->stats64_lock); |
1774 | |
1775 | stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + |
1776 | raw->rx_pause; |
1777 | stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + |
1778 | raw->tx_pause; |
1779 | |
1780 | /* HW counters are counting bytes + FCS which is not acceptable |
1781 | * for rtnl_link_stats64 interface |
1782 | */ |
1783 | stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; |
1784 | stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; |
1785 | |
1786 | stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + |
1787 | raw->rx_oversize; |
1788 | |
1789 | stats->rx_crc_errors = raw->rx_crc_err; |
1790 | stats->rx_frame_errors = raw->rx_align_err; |
1791 | stats->rx_dropped = raw->rx_discards; |
1792 | stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + |
1793 | stats->rx_frame_errors + stats->rx_dropped; |
1794 | |
1795 | stats->tx_window_errors = raw->tx_late_col; |
1796 | stats->tx_fifo_errors = raw->tx_discards; |
1797 | stats->tx_aborted_errors = raw->tx_exc_col; |
1798 | stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + |
1799 | stats->tx_aborted_errors; |
1800 | |
1801 | stats->multicast = raw->rx_mcast; |
1802 | stats->collisions = raw->tx_total_col; |
1803 | |
1804 | pstats->tx_pause_frames = raw->tx_pause; |
1805 | pstats->rx_pause_frames = raw->rx_pause; |
1806 | |
1807 | spin_unlock(lock: &mib->stats64_lock); |
1808 | } |
1809 | |
1810 | void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) |
1811 | { |
1812 | struct ethtool_pause_stats *pstats; |
1813 | struct rtnl_link_stats64 *stats; |
1814 | struct ksz88xx_stats_raw *raw; |
1815 | struct ksz_port_mib *mib; |
1816 | |
1817 | mib = &dev->ports[port].mib; |
1818 | stats = &mib->stats64; |
1819 | pstats = &mib->pause_stats; |
1820 | raw = (struct ksz88xx_stats_raw *)mib->counters; |
1821 | |
1822 | spin_lock(lock: &mib->stats64_lock); |
1823 | |
1824 | stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + |
1825 | raw->rx_pause; |
1826 | stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + |
1827 | raw->tx_pause; |
1828 | |
1829 | /* HW counters are counting bytes + FCS which is not acceptable |
1830 | * for rtnl_link_stats64 interface |
1831 | */ |
1832 | stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; |
1833 | stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; |
1834 | |
1835 | stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + |
1836 | raw->rx_oversize; |
1837 | |
1838 | stats->rx_crc_errors = raw->rx_crc_err; |
1839 | stats->rx_frame_errors = raw->rx_align_err; |
1840 | stats->rx_dropped = raw->rx_discards; |
1841 | stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + |
1842 | stats->rx_frame_errors + stats->rx_dropped; |
1843 | |
1844 | stats->tx_window_errors = raw->tx_late_col; |
1845 | stats->tx_fifo_errors = raw->tx_discards; |
1846 | stats->tx_aborted_errors = raw->tx_exc_col; |
1847 | stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + |
1848 | stats->tx_aborted_errors; |
1849 | |
1850 | stats->multicast = raw->rx_mcast; |
1851 | stats->collisions = raw->tx_total_col; |
1852 | |
1853 | pstats->tx_pause_frames = raw->tx_pause; |
1854 | pstats->rx_pause_frames = raw->rx_pause; |
1855 | |
1856 | spin_unlock(lock: &mib->stats64_lock); |
1857 | } |
1858 | |
1859 | static void ksz_get_stats64(struct dsa_switch *ds, int port, |
1860 | struct rtnl_link_stats64 *s) |
1861 | { |
1862 | struct ksz_device *dev = ds->priv; |
1863 | struct ksz_port_mib *mib; |
1864 | |
1865 | mib = &dev->ports[port].mib; |
1866 | |
1867 | spin_lock(lock: &mib->stats64_lock); |
1868 | memcpy(s, &mib->stats64, sizeof(*s)); |
1869 | spin_unlock(lock: &mib->stats64_lock); |
1870 | } |
1871 | |
1872 | static void ksz_get_pause_stats(struct dsa_switch *ds, int port, |
1873 | struct ethtool_pause_stats *pause_stats) |
1874 | { |
1875 | struct ksz_device *dev = ds->priv; |
1876 | struct ksz_port_mib *mib; |
1877 | |
1878 | mib = &dev->ports[port].mib; |
1879 | |
1880 | spin_lock(lock: &mib->stats64_lock); |
1881 | memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); |
1882 | spin_unlock(lock: &mib->stats64_lock); |
1883 | } |
1884 | |
1885 | static void ksz_get_strings(struct dsa_switch *ds, int port, |
1886 | u32 stringset, uint8_t *buf) |
1887 | { |
1888 | struct ksz_device *dev = ds->priv; |
1889 | int i; |
1890 | |
1891 | if (stringset != ETH_SS_STATS) |
1892 | return; |
1893 | |
1894 | for (i = 0; i < dev->info->mib_cnt; i++) { |
1895 | memcpy(buf + i * ETH_GSTRING_LEN, |
1896 | dev->info->mib_names[i].string, ETH_GSTRING_LEN); |
1897 | } |
1898 | } |
1899 | |
1900 | /** |
1901 | * ksz_update_port_member - Adjust port forwarding rules based on STP state and |
1902 | * isolation settings. |
1903 | * @dev: A pointer to the struct ksz_device representing the device. |
1904 | * @port: The port number to adjust. |
1905 | * |
1906 | * This function dynamically adjusts the port membership configuration for a |
1907 | * specified port and other device ports, based on Spanning Tree Protocol (STP) |
1908 | * states and port isolation settings. Each port, including the CPU port, has a |
1909 | * membership register, represented as a bitfield, where each bit corresponds |
1910 | * to a port number. A set bit indicates permission to forward frames to that |
1911 | * port. This function iterates over all ports, updating the membership register |
1912 | * to reflect current forwarding permissions: |
1913 | * |
1914 | * 1. Forwards frames only to ports that are part of the same bridge group and |
1915 | * in the BR_STATE_FORWARDING state. |
1916 | * 2. Takes into account the isolation status of ports; ports in the |
1917 | * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward |
1918 | * frames to each other, even if they are in the same bridge group. |
1919 | * 3. Ensures that the CPU port is included in the membership based on its |
1920 | * upstream port configuration, allowing for management and control traffic |
1921 | * to flow as required. |
1922 | */ |
1923 | static void ksz_update_port_member(struct ksz_device *dev, int port) |
1924 | { |
1925 | struct ksz_port *p = &dev->ports[port]; |
1926 | struct dsa_switch *ds = dev->ds; |
1927 | u8 port_member = 0, cpu_port; |
1928 | const struct dsa_port *dp; |
1929 | int i, j; |
1930 | |
1931 | if (!dsa_is_user_port(ds, p: port)) |
1932 | return; |
1933 | |
1934 | dp = dsa_to_port(ds, p: port); |
1935 | cpu_port = BIT(dsa_upstream_port(ds, port)); |
1936 | |
1937 | for (i = 0; i < ds->num_ports; i++) { |
1938 | const struct dsa_port *other_dp = dsa_to_port(ds, p: i); |
1939 | struct ksz_port *other_p = &dev->ports[i]; |
1940 | u8 val = 0; |
1941 | |
1942 | if (!dsa_is_user_port(ds, p: i)) |
1943 | continue; |
1944 | if (port == i) |
1945 | continue; |
1946 | if (!dsa_port_bridge_same(a: dp, b: other_dp)) |
1947 | continue; |
1948 | if (other_p->stp_state != BR_STATE_FORWARDING) |
1949 | continue; |
1950 | |
1951 | /* At this point we know that "port" and "other" port [i] are in |
1952 | * the same bridge group and that "other" port [i] is in |
1953 | * forwarding stp state. If "port" is also in forwarding stp |
1954 | * state, we can allow forwarding from port [port] to port [i]. |
1955 | * Except if both ports are isolated. |
1956 | */ |
1957 | if (p->stp_state == BR_STATE_FORWARDING && |
1958 | !(p->isolated && other_p->isolated)) { |
1959 | val |= BIT(port); |
1960 | port_member |= BIT(i); |
1961 | } |
1962 | |
1963 | /* Retain port [i]'s relationship to other ports than [port] */ |
1964 | for (j = 0; j < ds->num_ports; j++) { |
1965 | const struct dsa_port *third_dp; |
1966 | struct ksz_port *third_p; |
1967 | |
1968 | if (j == i) |
1969 | continue; |
1970 | if (j == port) |
1971 | continue; |
1972 | if (!dsa_is_user_port(ds, p: j)) |
1973 | continue; |
1974 | third_p = &dev->ports[j]; |
1975 | if (third_p->stp_state != BR_STATE_FORWARDING) |
1976 | continue; |
1977 | |
1978 | third_dp = dsa_to_port(ds, p: j); |
1979 | |
1980 | /* Now we updating relation of the "other" port [i] to |
1981 | * the "third" port [j]. We already know that "other" |
1982 | * port [i] is in forwarding stp state and that "third" |
1983 | * port [j] is in forwarding stp state too. |
1984 | * We need to check if "other" port [i] and "third" port |
1985 | * [j] are in the same bridge group and not isolated |
1986 | * before allowing forwarding from port [i] to port [j]. |
1987 | */ |
1988 | if (dsa_port_bridge_same(a: other_dp, b: third_dp) && |
1989 | !(other_p->isolated && third_p->isolated)) |
1990 | val |= BIT(j); |
1991 | } |
1992 | |
1993 | dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); |
1994 | } |
1995 | |
1996 | dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); |
1997 | } |
1998 | |
1999 | static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) |
2000 | { |
2001 | struct ksz_device *dev = bus->priv; |
2002 | u16 val; |
2003 | int ret; |
2004 | |
2005 | ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); |
2006 | if (ret < 0) |
2007 | return ret; |
2008 | |
2009 | return val; |
2010 | } |
2011 | |
2012 | static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, |
2013 | u16 val) |
2014 | { |
2015 | struct ksz_device *dev = bus->priv; |
2016 | |
2017 | return dev->dev_ops->w_phy(dev, addr, regnum, val); |
2018 | } |
2019 | |
2020 | static int ksz_irq_phy_setup(struct ksz_device *dev) |
2021 | { |
2022 | struct dsa_switch *ds = dev->ds; |
2023 | int phy; |
2024 | int irq; |
2025 | int ret; |
2026 | |
2027 | for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) { |
2028 | if (BIT(phy) & ds->phys_mii_mask) { |
2029 | irq = irq_find_mapping(domain: dev->ports[phy].pirq.domain, |
2030 | PORT_SRC_PHY_INT); |
2031 | if (irq < 0) { |
2032 | ret = irq; |
2033 | goto out; |
2034 | } |
2035 | ds->user_mii_bus->irq[phy] = irq; |
2036 | } |
2037 | } |
2038 | return 0; |
2039 | out: |
2040 | while (phy--) |
2041 | if (BIT(phy) & ds->phys_mii_mask) |
2042 | irq_dispose_mapping(virq: ds->user_mii_bus->irq[phy]); |
2043 | |
2044 | return ret; |
2045 | } |
2046 | |
2047 | static void ksz_irq_phy_free(struct ksz_device *dev) |
2048 | { |
2049 | struct dsa_switch *ds = dev->ds; |
2050 | int phy; |
2051 | |
2052 | for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) |
2053 | if (BIT(phy) & ds->phys_mii_mask) |
2054 | irq_dispose_mapping(virq: ds->user_mii_bus->irq[phy]); |
2055 | } |
2056 | |
2057 | static int ksz_mdio_register(struct ksz_device *dev) |
2058 | { |
2059 | struct dsa_switch *ds = dev->ds; |
2060 | struct device_node *mdio_np; |
2061 | struct mii_bus *bus; |
2062 | int ret; |
2063 | |
2064 | mdio_np = of_get_child_by_name(node: dev->dev->of_node, name: "mdio" ); |
2065 | if (!mdio_np) |
2066 | return 0; |
2067 | |
2068 | bus = devm_mdiobus_alloc(dev: ds->dev); |
2069 | if (!bus) { |
2070 | of_node_put(node: mdio_np); |
2071 | return -ENOMEM; |
2072 | } |
2073 | |
2074 | bus->priv = dev; |
2075 | bus->read = ksz_sw_mdio_read; |
2076 | bus->write = ksz_sw_mdio_write; |
2077 | bus->name = "ksz user smi" ; |
2078 | snprintf(buf: bus->id, MII_BUS_ID_SIZE, fmt: "SMI-%d" , ds->index); |
2079 | bus->parent = ds->dev; |
2080 | bus->phy_mask = ~ds->phys_mii_mask; |
2081 | |
2082 | ds->user_mii_bus = bus; |
2083 | |
2084 | if (dev->irq > 0) { |
2085 | ret = ksz_irq_phy_setup(dev); |
2086 | if (ret) { |
2087 | of_node_put(node: mdio_np); |
2088 | return ret; |
2089 | } |
2090 | } |
2091 | |
2092 | ret = devm_of_mdiobus_register(dev: ds->dev, mdio: bus, np: mdio_np); |
2093 | if (ret) { |
2094 | dev_err(ds->dev, "unable to register MDIO bus %s\n" , |
2095 | bus->id); |
2096 | if (dev->irq > 0) |
2097 | ksz_irq_phy_free(dev); |
2098 | } |
2099 | |
2100 | of_node_put(node: mdio_np); |
2101 | |
2102 | return ret; |
2103 | } |
2104 | |
2105 | static void ksz_irq_mask(struct irq_data *d) |
2106 | { |
2107 | struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); |
2108 | |
2109 | kirq->masked |= BIT(d->hwirq); |
2110 | } |
2111 | |
2112 | static void ksz_irq_unmask(struct irq_data *d) |
2113 | { |
2114 | struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); |
2115 | |
2116 | kirq->masked &= ~BIT(d->hwirq); |
2117 | } |
2118 | |
2119 | static void ksz_irq_bus_lock(struct irq_data *d) |
2120 | { |
2121 | struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); |
2122 | |
2123 | mutex_lock(&kirq->dev->lock_irq); |
2124 | } |
2125 | |
2126 | static void ksz_irq_bus_sync_unlock(struct irq_data *d) |
2127 | { |
2128 | struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); |
2129 | struct ksz_device *dev = kirq->dev; |
2130 | int ret; |
2131 | |
2132 | ret = ksz_write32(dev, reg: kirq->reg_mask, value: kirq->masked); |
2133 | if (ret) |
2134 | dev_err(dev->dev, "failed to change IRQ mask\n" ); |
2135 | |
2136 | mutex_unlock(lock: &dev->lock_irq); |
2137 | } |
2138 | |
2139 | static const struct irq_chip ksz_irq_chip = { |
2140 | .name = "ksz-irq" , |
2141 | .irq_mask = ksz_irq_mask, |
2142 | .irq_unmask = ksz_irq_unmask, |
2143 | .irq_bus_lock = ksz_irq_bus_lock, |
2144 | .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, |
2145 | }; |
2146 | |
2147 | static int ksz_irq_domain_map(struct irq_domain *d, |
2148 | unsigned int irq, irq_hw_number_t hwirq) |
2149 | { |
2150 | irq_set_chip_data(irq, data: d->host_data); |
2151 | irq_set_chip_and_handler(irq, chip: &ksz_irq_chip, handle: handle_level_irq); |
2152 | irq_set_noprobe(irq); |
2153 | |
2154 | return 0; |
2155 | } |
2156 | |
2157 | static const struct irq_domain_ops ksz_irq_domain_ops = { |
2158 | .map = ksz_irq_domain_map, |
2159 | .xlate = irq_domain_xlate_twocell, |
2160 | }; |
2161 | |
2162 | static void ksz_irq_free(struct ksz_irq *kirq) |
2163 | { |
2164 | int irq, virq; |
2165 | |
2166 | free_irq(kirq->irq_num, kirq); |
2167 | |
2168 | for (irq = 0; irq < kirq->nirqs; irq++) { |
2169 | virq = irq_find_mapping(domain: kirq->domain, hwirq: irq); |
2170 | irq_dispose_mapping(virq); |
2171 | } |
2172 | |
2173 | irq_domain_remove(host: kirq->domain); |
2174 | } |
2175 | |
2176 | static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) |
2177 | { |
2178 | struct ksz_irq *kirq = dev_id; |
2179 | unsigned int nhandled = 0; |
2180 | struct ksz_device *dev; |
2181 | unsigned int sub_irq; |
2182 | u8 data; |
2183 | int ret; |
2184 | u8 n; |
2185 | |
2186 | dev = kirq->dev; |
2187 | |
2188 | /* Read interrupt status register */ |
2189 | ret = ksz_read8(dev, reg: kirq->reg_status, val: &data); |
2190 | if (ret) |
2191 | goto out; |
2192 | |
2193 | for (n = 0; n < kirq->nirqs; ++n) { |
2194 | if (data & BIT(n)) { |
2195 | sub_irq = irq_find_mapping(domain: kirq->domain, hwirq: n); |
2196 | handle_nested_irq(irq: sub_irq); |
2197 | ++nhandled; |
2198 | } |
2199 | } |
2200 | out: |
2201 | return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); |
2202 | } |
2203 | |
2204 | static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) |
2205 | { |
2206 | int ret, n; |
2207 | |
2208 | kirq->dev = dev; |
2209 | kirq->masked = ~0; |
2210 | |
2211 | kirq->domain = irq_domain_add_simple(of_node: dev->dev->of_node, size: kirq->nirqs, first_irq: 0, |
2212 | ops: &ksz_irq_domain_ops, host_data: kirq); |
2213 | if (!kirq->domain) |
2214 | return -ENOMEM; |
2215 | |
2216 | for (n = 0; n < kirq->nirqs; n++) |
2217 | irq_create_mapping(host: kirq->domain, hwirq: n); |
2218 | |
2219 | ret = request_threaded_irq(irq: kirq->irq_num, NULL, thread_fn: ksz_irq_thread_fn, |
2220 | IRQF_ONESHOT, name: kirq->name, dev: kirq); |
2221 | if (ret) |
2222 | goto out; |
2223 | |
2224 | return 0; |
2225 | |
2226 | out: |
2227 | ksz_irq_free(kirq); |
2228 | |
2229 | return ret; |
2230 | } |
2231 | |
2232 | static int ksz_girq_setup(struct ksz_device *dev) |
2233 | { |
2234 | struct ksz_irq *girq = &dev->girq; |
2235 | |
2236 | girq->nirqs = dev->info->port_cnt; |
2237 | girq->reg_mask = REG_SW_PORT_INT_MASK__1; |
2238 | girq->reg_status = REG_SW_PORT_INT_STATUS__1; |
2239 | snprintf(buf: girq->name, size: sizeof(girq->name), fmt: "global_port_irq" ); |
2240 | |
2241 | girq->irq_num = dev->irq; |
2242 | |
2243 | return ksz_irq_common_setup(dev, kirq: girq); |
2244 | } |
2245 | |
2246 | static int ksz_pirq_setup(struct ksz_device *dev, u8 p) |
2247 | { |
2248 | struct ksz_irq *pirq = &dev->ports[p].pirq; |
2249 | |
2250 | pirq->nirqs = dev->info->port_nirqs; |
2251 | pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); |
2252 | pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); |
2253 | snprintf(buf: pirq->name, size: sizeof(pirq->name), fmt: "port_irq-%d" , p); |
2254 | |
2255 | pirq->irq_num = irq_find_mapping(domain: dev->girq.domain, hwirq: p); |
2256 | if (pirq->irq_num < 0) |
2257 | return pirq->irq_num; |
2258 | |
2259 | return ksz_irq_common_setup(dev, kirq: pirq); |
2260 | } |
2261 | |
2262 | static int ksz_parse_drive_strength(struct ksz_device *dev); |
2263 | |
2264 | static int ksz_setup(struct dsa_switch *ds) |
2265 | { |
2266 | struct ksz_device *dev = ds->priv; |
2267 | struct dsa_port *dp; |
2268 | struct ksz_port *p; |
2269 | const u16 *regs; |
2270 | int ret; |
2271 | |
2272 | regs = dev->info->regs; |
2273 | |
2274 | dev->vlan_cache = devm_kcalloc(dev: dev->dev, n: sizeof(struct vlan_table), |
2275 | size: dev->info->num_vlans, GFP_KERNEL); |
2276 | if (!dev->vlan_cache) |
2277 | return -ENOMEM; |
2278 | |
2279 | ret = dev->dev_ops->reset(dev); |
2280 | if (ret) { |
2281 | dev_err(ds->dev, "failed to reset switch\n" ); |
2282 | return ret; |
2283 | } |
2284 | |
2285 | ret = ksz_parse_drive_strength(dev); |
2286 | if (ret) |
2287 | return ret; |
2288 | |
2289 | /* set broadcast storm protection 10% rate */ |
2290 | regmap_update_bits(map: ksz_regmap_16(dev), reg: regs[S_BROADCAST_CTRL], |
2291 | BROADCAST_STORM_RATE, |
2292 | val: (BROADCAST_STORM_VALUE * |
2293 | BROADCAST_STORM_PROT_RATE) / 100); |
2294 | |
2295 | dev->dev_ops->config_cpu_port(ds); |
2296 | |
2297 | dev->dev_ops->enable_stp_addr(dev); |
2298 | |
2299 | ds->num_tx_queues = dev->info->num_tx_queues; |
2300 | |
2301 | regmap_update_bits(map: ksz_regmap_8(dev), reg: regs[S_MULTICAST_CTRL], |
2302 | MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); |
2303 | |
2304 | ksz_init_mib_timer(dev); |
2305 | |
2306 | ds->configure_vlan_while_not_filtering = false; |
2307 | |
2308 | if (dev->dev_ops->setup) { |
2309 | ret = dev->dev_ops->setup(ds); |
2310 | if (ret) |
2311 | return ret; |
2312 | } |
2313 | |
2314 | /* Start with learning disabled on standalone user ports, and enabled |
2315 | * on the CPU port. In lack of other finer mechanisms, learning on the |
2316 | * CPU port will avoid flooding bridge local addresses on the network |
2317 | * in some cases. |
2318 | */ |
2319 | p = &dev->ports[dev->cpu_port]; |
2320 | p->learning = true; |
2321 | |
2322 | if (dev->irq > 0) { |
2323 | ret = ksz_girq_setup(dev); |
2324 | if (ret) |
2325 | return ret; |
2326 | |
2327 | dsa_switch_for_each_user_port(dp, dev->ds) { |
2328 | ret = ksz_pirq_setup(dev, p: dp->index); |
2329 | if (ret) |
2330 | goto out_girq; |
2331 | |
2332 | ret = ksz_ptp_irq_setup(ds, p: dp->index); |
2333 | if (ret) |
2334 | goto out_pirq; |
2335 | } |
2336 | } |
2337 | |
2338 | ret = ksz_ptp_clock_register(ds); |
2339 | if (ret) { |
2340 | dev_err(dev->dev, "Failed to register PTP clock: %d\n" , ret); |
2341 | goto out_ptpirq; |
2342 | } |
2343 | |
2344 | ret = ksz_mdio_register(dev); |
2345 | if (ret < 0) { |
2346 | dev_err(dev->dev, "failed to register the mdio" ); |
2347 | goto out_ptp_clock_unregister; |
2348 | } |
2349 | |
2350 | /* start switch */ |
2351 | regmap_update_bits(map: ksz_regmap_8(dev), reg: regs[S_START_CTRL], |
2352 | SW_START, SW_START); |
2353 | |
2354 | return 0; |
2355 | |
2356 | out_ptp_clock_unregister: |
2357 | ksz_ptp_clock_unregister(ds); |
2358 | out_ptpirq: |
2359 | if (dev->irq > 0) |
2360 | dsa_switch_for_each_user_port(dp, dev->ds) |
2361 | ksz_ptp_irq_free(ds, p: dp->index); |
2362 | out_pirq: |
2363 | if (dev->irq > 0) |
2364 | dsa_switch_for_each_user_port(dp, dev->ds) |
2365 | ksz_irq_free(kirq: &dev->ports[dp->index].pirq); |
2366 | out_girq: |
2367 | if (dev->irq > 0) |
2368 | ksz_irq_free(kirq: &dev->girq); |
2369 | |
2370 | return ret; |
2371 | } |
2372 | |
2373 | static void ksz_teardown(struct dsa_switch *ds) |
2374 | { |
2375 | struct ksz_device *dev = ds->priv; |
2376 | struct dsa_port *dp; |
2377 | |
2378 | ksz_ptp_clock_unregister(ds); |
2379 | |
2380 | if (dev->irq > 0) { |
2381 | dsa_switch_for_each_user_port(dp, dev->ds) { |
2382 | ksz_ptp_irq_free(ds, p: dp->index); |
2383 | |
2384 | ksz_irq_free(kirq: &dev->ports[dp->index].pirq); |
2385 | } |
2386 | |
2387 | ksz_irq_free(kirq: &dev->girq); |
2388 | } |
2389 | |
2390 | if (dev->dev_ops->teardown) |
2391 | dev->dev_ops->teardown(ds); |
2392 | } |
2393 | |
2394 | static void port_r_cnt(struct ksz_device *dev, int port) |
2395 | { |
2396 | struct ksz_port_mib *mib = &dev->ports[port].mib; |
2397 | u64 *dropped; |
2398 | |
2399 | /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ |
2400 | while (mib->cnt_ptr < dev->info->reg_mib_cnt) { |
2401 | dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, |
2402 | &mib->counters[mib->cnt_ptr]); |
2403 | ++mib->cnt_ptr; |
2404 | } |
2405 | |
2406 | /* last one in storage */ |
2407 | dropped = &mib->counters[dev->info->mib_cnt]; |
2408 | |
2409 | /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ |
2410 | while (mib->cnt_ptr < dev->info->mib_cnt) { |
2411 | dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, |
2412 | dropped, &mib->counters[mib->cnt_ptr]); |
2413 | ++mib->cnt_ptr; |
2414 | } |
2415 | mib->cnt_ptr = 0; |
2416 | } |
2417 | |
2418 | static void ksz_mib_read_work(struct work_struct *work) |
2419 | { |
2420 | struct ksz_device *dev = container_of(work, struct ksz_device, |
2421 | mib_read.work); |
2422 | struct ksz_port_mib *mib; |
2423 | struct ksz_port *p; |
2424 | int i; |
2425 | |
2426 | for (i = 0; i < dev->info->port_cnt; i++) { |
2427 | if (dsa_is_unused_port(ds: dev->ds, p: i)) |
2428 | continue; |
2429 | |
2430 | p = &dev->ports[i]; |
2431 | mib = &p->mib; |
2432 | mutex_lock(&mib->cnt_mutex); |
2433 | |
2434 | /* Only read MIB counters when the port is told to do. |
2435 | * If not, read only dropped counters when link is not up. |
2436 | */ |
2437 | if (!p->read) { |
2438 | const struct dsa_port *dp = dsa_to_port(ds: dev->ds, p: i); |
2439 | |
2440 | if (!netif_carrier_ok(dev: dp->user)) |
2441 | mib->cnt_ptr = dev->info->reg_mib_cnt; |
2442 | } |
2443 | port_r_cnt(dev, port: i); |
2444 | p->read = false; |
2445 | |
2446 | if (dev->dev_ops->r_mib_stat64) |
2447 | dev->dev_ops->r_mib_stat64(dev, i); |
2448 | |
2449 | mutex_unlock(lock: &mib->cnt_mutex); |
2450 | } |
2451 | |
2452 | schedule_delayed_work(dwork: &dev->mib_read, delay: dev->mib_read_interval); |
2453 | } |
2454 | |
2455 | void ksz_init_mib_timer(struct ksz_device *dev) |
2456 | { |
2457 | int i; |
2458 | |
2459 | INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); |
2460 | |
2461 | for (i = 0; i < dev->info->port_cnt; i++) { |
2462 | struct ksz_port_mib *mib = &dev->ports[i].mib; |
2463 | |
2464 | dev->dev_ops->port_init_cnt(dev, i); |
2465 | |
2466 | mib->cnt_ptr = 0; |
2467 | memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); |
2468 | } |
2469 | } |
2470 | |
2471 | static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) |
2472 | { |
2473 | struct ksz_device *dev = ds->priv; |
2474 | u16 val = 0xffff; |
2475 | int ret; |
2476 | |
2477 | ret = dev->dev_ops->r_phy(dev, addr, reg, &val); |
2478 | if (ret) |
2479 | return ret; |
2480 | |
2481 | return val; |
2482 | } |
2483 | |
2484 | static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) |
2485 | { |
2486 | struct ksz_device *dev = ds->priv; |
2487 | int ret; |
2488 | |
2489 | ret = dev->dev_ops->w_phy(dev, addr, reg, val); |
2490 | if (ret) |
2491 | return ret; |
2492 | |
2493 | return 0; |
2494 | } |
2495 | |
2496 | static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) |
2497 | { |
2498 | struct ksz_device *dev = ds->priv; |
2499 | |
2500 | switch (dev->chip_id) { |
2501 | case KSZ8830_CHIP_ID: |
2502 | /* Silicon Errata Sheet (DS80000830A): |
2503 | * Port 1 does not work with LinkMD Cable-Testing. |
2504 | * Port 1 does not respond to received PAUSE control frames. |
2505 | */ |
2506 | if (!port) |
2507 | return MICREL_KSZ8_P1_ERRATA; |
2508 | break; |
2509 | case KSZ9477_CHIP_ID: |
2510 | /* KSZ9477 Errata DS80000754C |
2511 | * |
2512 | * Module 4: Energy Efficient Ethernet (EEE) feature select must |
2513 | * be manually disabled |
2514 | * The EEE feature is enabled by default, but it is not fully |
2515 | * operational. It must be manually disabled through register |
2516 | * controls. If not disabled, the PHY ports can auto-negotiate |
2517 | * to enable EEE, and this feature can cause link drops when |
2518 | * linked to another device supporting EEE. |
2519 | */ |
2520 | return MICREL_NO_EEE; |
2521 | } |
2522 | |
2523 | return 0; |
2524 | } |
2525 | |
2526 | static void ksz_mac_link_down(struct dsa_switch *ds, int port, |
2527 | unsigned int mode, phy_interface_t interface) |
2528 | { |
2529 | struct ksz_device *dev = ds->priv; |
2530 | struct ksz_port *p = &dev->ports[port]; |
2531 | |
2532 | /* Read all MIB counters when the link is going down. */ |
2533 | p->read = true; |
2534 | /* timer started */ |
2535 | if (dev->mib_read_interval) |
2536 | schedule_delayed_work(dwork: &dev->mib_read, delay: 0); |
2537 | } |
2538 | |
2539 | static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) |
2540 | { |
2541 | struct ksz_device *dev = ds->priv; |
2542 | |
2543 | if (sset != ETH_SS_STATS) |
2544 | return 0; |
2545 | |
2546 | return dev->info->mib_cnt; |
2547 | } |
2548 | |
2549 | static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, |
2550 | uint64_t *buf) |
2551 | { |
2552 | const struct dsa_port *dp = dsa_to_port(ds, p: port); |
2553 | struct ksz_device *dev = ds->priv; |
2554 | struct ksz_port_mib *mib; |
2555 | |
2556 | mib = &dev->ports[port].mib; |
2557 | mutex_lock(&mib->cnt_mutex); |
2558 | |
2559 | /* Only read dropped counters if no link. */ |
2560 | if (!netif_carrier_ok(dev: dp->user)) |
2561 | mib->cnt_ptr = dev->info->reg_mib_cnt; |
2562 | port_r_cnt(dev, port); |
2563 | memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); |
2564 | mutex_unlock(lock: &mib->cnt_mutex); |
2565 | } |
2566 | |
2567 | static int ksz_port_bridge_join(struct dsa_switch *ds, int port, |
2568 | struct dsa_bridge bridge, |
2569 | bool *tx_fwd_offload, |
2570 | struct netlink_ext_ack *extack) |
2571 | { |
2572 | /* port_stp_state_set() will be called after to put the port in |
2573 | * appropriate state so there is no need to do anything. |
2574 | */ |
2575 | |
2576 | return 0; |
2577 | } |
2578 | |
2579 | static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, |
2580 | struct dsa_bridge bridge) |
2581 | { |
2582 | /* port_stp_state_set() will be called after to put the port in |
2583 | * forwarding state so there is no need to do anything. |
2584 | */ |
2585 | } |
2586 | |
2587 | static void ksz_port_fast_age(struct dsa_switch *ds, int port) |
2588 | { |
2589 | struct ksz_device *dev = ds->priv; |
2590 | |
2591 | dev->dev_ops->flush_dyn_mac_table(dev, port); |
2592 | } |
2593 | |
2594 | static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) |
2595 | { |
2596 | struct ksz_device *dev = ds->priv; |
2597 | |
2598 | if (!dev->dev_ops->set_ageing_time) |
2599 | return -EOPNOTSUPP; |
2600 | |
2601 | return dev->dev_ops->set_ageing_time(dev, msecs); |
2602 | } |
2603 | |
2604 | static int ksz_port_fdb_add(struct dsa_switch *ds, int port, |
2605 | const unsigned char *addr, u16 vid, |
2606 | struct dsa_db db) |
2607 | { |
2608 | struct ksz_device *dev = ds->priv; |
2609 | |
2610 | if (!dev->dev_ops->fdb_add) |
2611 | return -EOPNOTSUPP; |
2612 | |
2613 | return dev->dev_ops->fdb_add(dev, port, addr, vid, db); |
2614 | } |
2615 | |
2616 | static int ksz_port_fdb_del(struct dsa_switch *ds, int port, |
2617 | const unsigned char *addr, |
2618 | u16 vid, struct dsa_db db) |
2619 | { |
2620 | struct ksz_device *dev = ds->priv; |
2621 | |
2622 | if (!dev->dev_ops->fdb_del) |
2623 | return -EOPNOTSUPP; |
2624 | |
2625 | return dev->dev_ops->fdb_del(dev, port, addr, vid, db); |
2626 | } |
2627 | |
2628 | static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, |
2629 | dsa_fdb_dump_cb_t *cb, void *data) |
2630 | { |
2631 | struct ksz_device *dev = ds->priv; |
2632 | |
2633 | if (!dev->dev_ops->fdb_dump) |
2634 | return -EOPNOTSUPP; |
2635 | |
2636 | return dev->dev_ops->fdb_dump(dev, port, cb, data); |
2637 | } |
2638 | |
2639 | static int ksz_port_mdb_add(struct dsa_switch *ds, int port, |
2640 | const struct switchdev_obj_port_mdb *mdb, |
2641 | struct dsa_db db) |
2642 | { |
2643 | struct ksz_device *dev = ds->priv; |
2644 | |
2645 | if (!dev->dev_ops->mdb_add) |
2646 | return -EOPNOTSUPP; |
2647 | |
2648 | return dev->dev_ops->mdb_add(dev, port, mdb, db); |
2649 | } |
2650 | |
2651 | static int ksz_port_mdb_del(struct dsa_switch *ds, int port, |
2652 | const struct switchdev_obj_port_mdb *mdb, |
2653 | struct dsa_db db) |
2654 | { |
2655 | struct ksz_device *dev = ds->priv; |
2656 | |
2657 | if (!dev->dev_ops->mdb_del) |
2658 | return -EOPNOTSUPP; |
2659 | |
2660 | return dev->dev_ops->mdb_del(dev, port, mdb, db); |
2661 | } |
2662 | |
2663 | static int ksz_port_setup(struct dsa_switch *ds, int port) |
2664 | { |
2665 | struct ksz_device *dev = ds->priv; |
2666 | |
2667 | if (!dsa_is_user_port(ds, p: port)) |
2668 | return 0; |
2669 | |
2670 | /* setup user port */ |
2671 | dev->dev_ops->port_setup(dev, port, false); |
2672 | |
2673 | /* port_stp_state_set() will be called after to enable the port so |
2674 | * there is no need to do anything. |
2675 | */ |
2676 | |
2677 | return 0; |
2678 | } |
2679 | |
2680 | void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) |
2681 | { |
2682 | struct ksz_device *dev = ds->priv; |
2683 | struct ksz_port *p; |
2684 | const u16 *regs; |
2685 | u8 data; |
2686 | |
2687 | regs = dev->info->regs; |
2688 | |
2689 | ksz_pread8(dev, port, offset: regs[P_STP_CTRL], data: &data); |
2690 | data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); |
2691 | |
2692 | p = &dev->ports[port]; |
2693 | |
2694 | switch (state) { |
2695 | case BR_STATE_DISABLED: |
2696 | data |= PORT_LEARN_DISABLE; |
2697 | break; |
2698 | case BR_STATE_LISTENING: |
2699 | data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); |
2700 | break; |
2701 | case BR_STATE_LEARNING: |
2702 | data |= PORT_RX_ENABLE; |
2703 | if (!p->learning) |
2704 | data |= PORT_LEARN_DISABLE; |
2705 | break; |
2706 | case BR_STATE_FORWARDING: |
2707 | data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); |
2708 | if (!p->learning) |
2709 | data |= PORT_LEARN_DISABLE; |
2710 | break; |
2711 | case BR_STATE_BLOCKING: |
2712 | data |= PORT_LEARN_DISABLE; |
2713 | break; |
2714 | default: |
2715 | dev_err(ds->dev, "invalid STP state: %d\n" , state); |
2716 | return; |
2717 | } |
2718 | |
2719 | ksz_pwrite8(dev, port, offset: regs[P_STP_CTRL], data); |
2720 | |
2721 | p->stp_state = state; |
2722 | |
2723 | ksz_update_port_member(dev, port); |
2724 | } |
2725 | |
2726 | static void ksz_port_teardown(struct dsa_switch *ds, int port) |
2727 | { |
2728 | struct ksz_device *dev = ds->priv; |
2729 | |
2730 | switch (dev->chip_id) { |
2731 | case KSZ8563_CHIP_ID: |
2732 | case KSZ8567_CHIP_ID: |
2733 | case KSZ9477_CHIP_ID: |
2734 | case KSZ9563_CHIP_ID: |
2735 | case KSZ9567_CHIP_ID: |
2736 | case KSZ9893_CHIP_ID: |
2737 | case KSZ9896_CHIP_ID: |
2738 | case KSZ9897_CHIP_ID: |
2739 | if (dsa_is_user_port(ds, p: port)) |
2740 | ksz9477_port_acl_free(dev, port); |
2741 | } |
2742 | } |
2743 | |
2744 | static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, |
2745 | struct switchdev_brport_flags flags, |
2746 | struct netlink_ext_ack *extack) |
2747 | { |
2748 | if (flags.mask & ~(BR_LEARNING | BR_ISOLATED)) |
2749 | return -EINVAL; |
2750 | |
2751 | return 0; |
2752 | } |
2753 | |
2754 | static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, |
2755 | struct switchdev_brport_flags flags, |
2756 | struct netlink_ext_ack *extack) |
2757 | { |
2758 | struct ksz_device *dev = ds->priv; |
2759 | struct ksz_port *p = &dev->ports[port]; |
2760 | |
2761 | if (flags.mask & (BR_LEARNING | BR_ISOLATED)) { |
2762 | if (flags.mask & BR_LEARNING) |
2763 | p->learning = !!(flags.val & BR_LEARNING); |
2764 | |
2765 | if (flags.mask & BR_ISOLATED) |
2766 | p->isolated = !!(flags.val & BR_ISOLATED); |
2767 | |
2768 | /* Make the change take effect immediately */ |
2769 | ksz_port_stp_state_set(ds, port, state: p->stp_state); |
2770 | } |
2771 | |
2772 | return 0; |
2773 | } |
2774 | |
2775 | static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, |
2776 | int port, |
2777 | enum dsa_tag_protocol mp) |
2778 | { |
2779 | struct ksz_device *dev = ds->priv; |
2780 | enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; |
2781 | |
2782 | if (dev->chip_id == KSZ8795_CHIP_ID || |
2783 | dev->chip_id == KSZ8794_CHIP_ID || |
2784 | dev->chip_id == KSZ8765_CHIP_ID) |
2785 | proto = DSA_TAG_PROTO_KSZ8795; |
2786 | |
2787 | if (dev->chip_id == KSZ8830_CHIP_ID || |
2788 | dev->chip_id == KSZ8563_CHIP_ID || |
2789 | dev->chip_id == KSZ9893_CHIP_ID || |
2790 | dev->chip_id == KSZ9563_CHIP_ID) |
2791 | proto = DSA_TAG_PROTO_KSZ9893; |
2792 | |
2793 | if (dev->chip_id == KSZ8567_CHIP_ID || |
2794 | dev->chip_id == KSZ9477_CHIP_ID || |
2795 | dev->chip_id == KSZ9896_CHIP_ID || |
2796 | dev->chip_id == KSZ9897_CHIP_ID || |
2797 | dev->chip_id == KSZ9567_CHIP_ID) |
2798 | proto = DSA_TAG_PROTO_KSZ9477; |
2799 | |
2800 | if (is_lan937x(dev)) |
2801 | proto = DSA_TAG_PROTO_LAN937X; |
2802 | |
2803 | return proto; |
2804 | } |
2805 | |
2806 | static int ksz_connect_tag_protocol(struct dsa_switch *ds, |
2807 | enum dsa_tag_protocol proto) |
2808 | { |
2809 | struct ksz_tagger_data *tagger_data; |
2810 | |
2811 | switch (proto) { |
2812 | case DSA_TAG_PROTO_KSZ8795: |
2813 | return 0; |
2814 | case DSA_TAG_PROTO_KSZ9893: |
2815 | case DSA_TAG_PROTO_KSZ9477: |
2816 | case DSA_TAG_PROTO_LAN937X: |
2817 | tagger_data = ksz_tagger_data(ds); |
2818 | tagger_data->xmit_work_fn = ksz_port_deferred_xmit; |
2819 | return 0; |
2820 | default: |
2821 | return -EPROTONOSUPPORT; |
2822 | } |
2823 | } |
2824 | |
2825 | static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, |
2826 | bool flag, struct netlink_ext_ack *extack) |
2827 | { |
2828 | struct ksz_device *dev = ds->priv; |
2829 | |
2830 | if (!dev->dev_ops->vlan_filtering) |
2831 | return -EOPNOTSUPP; |
2832 | |
2833 | return dev->dev_ops->vlan_filtering(dev, port, flag, extack); |
2834 | } |
2835 | |
2836 | static int ksz_port_vlan_add(struct dsa_switch *ds, int port, |
2837 | const struct switchdev_obj_port_vlan *vlan, |
2838 | struct netlink_ext_ack *extack) |
2839 | { |
2840 | struct ksz_device *dev = ds->priv; |
2841 | |
2842 | if (!dev->dev_ops->vlan_add) |
2843 | return -EOPNOTSUPP; |
2844 | |
2845 | return dev->dev_ops->vlan_add(dev, port, vlan, extack); |
2846 | } |
2847 | |
2848 | static int ksz_port_vlan_del(struct dsa_switch *ds, int port, |
2849 | const struct switchdev_obj_port_vlan *vlan) |
2850 | { |
2851 | struct ksz_device *dev = ds->priv; |
2852 | |
2853 | if (!dev->dev_ops->vlan_del) |
2854 | return -EOPNOTSUPP; |
2855 | |
2856 | return dev->dev_ops->vlan_del(dev, port, vlan); |
2857 | } |
2858 | |
2859 | static int ksz_port_mirror_add(struct dsa_switch *ds, int port, |
2860 | struct dsa_mall_mirror_tc_entry *mirror, |
2861 | bool ingress, struct netlink_ext_ack *extack) |
2862 | { |
2863 | struct ksz_device *dev = ds->priv; |
2864 | |
2865 | if (!dev->dev_ops->mirror_add) |
2866 | return -EOPNOTSUPP; |
2867 | |
2868 | return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); |
2869 | } |
2870 | |
2871 | static void ksz_port_mirror_del(struct dsa_switch *ds, int port, |
2872 | struct dsa_mall_mirror_tc_entry *mirror) |
2873 | { |
2874 | struct ksz_device *dev = ds->priv; |
2875 | |
2876 | if (dev->dev_ops->mirror_del) |
2877 | dev->dev_ops->mirror_del(dev, port, mirror); |
2878 | } |
2879 | |
2880 | static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) |
2881 | { |
2882 | struct ksz_device *dev = ds->priv; |
2883 | |
2884 | if (!dev->dev_ops->change_mtu) |
2885 | return -EOPNOTSUPP; |
2886 | |
2887 | return dev->dev_ops->change_mtu(dev, port, mtu); |
2888 | } |
2889 | |
2890 | static int ksz_max_mtu(struct dsa_switch *ds, int port) |
2891 | { |
2892 | struct ksz_device *dev = ds->priv; |
2893 | |
2894 | switch (dev->chip_id) { |
2895 | case KSZ8795_CHIP_ID: |
2896 | case KSZ8794_CHIP_ID: |
2897 | case KSZ8765_CHIP_ID: |
2898 | return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; |
2899 | case KSZ8830_CHIP_ID: |
2900 | return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; |
2901 | case KSZ8563_CHIP_ID: |
2902 | case KSZ8567_CHIP_ID: |
2903 | case KSZ9477_CHIP_ID: |
2904 | case KSZ9563_CHIP_ID: |
2905 | case KSZ9567_CHIP_ID: |
2906 | case KSZ9893_CHIP_ID: |
2907 | case KSZ9896_CHIP_ID: |
2908 | case KSZ9897_CHIP_ID: |
2909 | case LAN9370_CHIP_ID: |
2910 | case LAN9371_CHIP_ID: |
2911 | case LAN9372_CHIP_ID: |
2912 | case LAN9373_CHIP_ID: |
2913 | case LAN9374_CHIP_ID: |
2914 | return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; |
2915 | } |
2916 | |
2917 | return -EOPNOTSUPP; |
2918 | } |
2919 | |
2920 | static int ksz_validate_eee(struct dsa_switch *ds, int port) |
2921 | { |
2922 | struct ksz_device *dev = ds->priv; |
2923 | |
2924 | if (!dev->info->internal_phy[port]) |
2925 | return -EOPNOTSUPP; |
2926 | |
2927 | switch (dev->chip_id) { |
2928 | case KSZ8563_CHIP_ID: |
2929 | case KSZ8567_CHIP_ID: |
2930 | case KSZ9477_CHIP_ID: |
2931 | case KSZ9563_CHIP_ID: |
2932 | case KSZ9567_CHIP_ID: |
2933 | case KSZ9893_CHIP_ID: |
2934 | case KSZ9896_CHIP_ID: |
2935 | case KSZ9897_CHIP_ID: |
2936 | return 0; |
2937 | } |
2938 | |
2939 | return -EOPNOTSUPP; |
2940 | } |
2941 | |
2942 | static int ksz_get_mac_eee(struct dsa_switch *ds, int port, |
2943 | struct ethtool_keee *e) |
2944 | { |
2945 | int ret; |
2946 | |
2947 | ret = ksz_validate_eee(ds, port); |
2948 | if (ret) |
2949 | return ret; |
2950 | |
2951 | /* There is no documented control of Tx LPI configuration. */ |
2952 | e->tx_lpi_enabled = true; |
2953 | |
2954 | /* There is no documented control of Tx LPI timer. According to tests |
2955 | * Tx LPI timer seems to be set by default to minimal value. |
2956 | */ |
2957 | e->tx_lpi_timer = 0; |
2958 | |
2959 | return 0; |
2960 | } |
2961 | |
2962 | static int ksz_set_mac_eee(struct dsa_switch *ds, int port, |
2963 | struct ethtool_keee *e) |
2964 | { |
2965 | struct ksz_device *dev = ds->priv; |
2966 | int ret; |
2967 | |
2968 | ret = ksz_validate_eee(ds, port); |
2969 | if (ret) |
2970 | return ret; |
2971 | |
2972 | if (!e->tx_lpi_enabled) { |
2973 | dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n" ); |
2974 | return -EINVAL; |
2975 | } |
2976 | |
2977 | if (e->tx_lpi_timer) { |
2978 | dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n" ); |
2979 | return -EINVAL; |
2980 | } |
2981 | |
2982 | return 0; |
2983 | } |
2984 | |
2985 | static void ksz_set_xmii(struct ksz_device *dev, int port, |
2986 | phy_interface_t interface) |
2987 | { |
2988 | const u8 *bitval = dev->info->xmii_ctrl1; |
2989 | struct ksz_port *p = &dev->ports[port]; |
2990 | const u16 *regs = dev->info->regs; |
2991 | u8 data8; |
2992 | |
2993 | ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8); |
2994 | |
2995 | data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | |
2996 | P_RGMII_ID_EG_ENABLE); |
2997 | |
2998 | switch (interface) { |
2999 | case PHY_INTERFACE_MODE_MII: |
3000 | data8 |= bitval[P_MII_SEL]; |
3001 | break; |
3002 | case PHY_INTERFACE_MODE_RMII: |
3003 | data8 |= bitval[P_RMII_SEL]; |
3004 | break; |
3005 | case PHY_INTERFACE_MODE_GMII: |
3006 | data8 |= bitval[P_GMII_SEL]; |
3007 | break; |
3008 | case PHY_INTERFACE_MODE_RGMII: |
3009 | case PHY_INTERFACE_MODE_RGMII_ID: |
3010 | case PHY_INTERFACE_MODE_RGMII_TXID: |
3011 | case PHY_INTERFACE_MODE_RGMII_RXID: |
3012 | data8 |= bitval[P_RGMII_SEL]; |
3013 | /* On KSZ9893, disable RGMII in-band status support */ |
3014 | if (dev->chip_id == KSZ9893_CHIP_ID || |
3015 | dev->chip_id == KSZ8563_CHIP_ID || |
3016 | dev->chip_id == KSZ9563_CHIP_ID) |
3017 | data8 &= ~P_MII_MAC_MODE; |
3018 | break; |
3019 | default: |
3020 | dev_err(dev->dev, "Unsupported interface '%s' for port %d\n" , |
3021 | phy_modes(interface), port); |
3022 | return; |
3023 | } |
3024 | |
3025 | if (p->rgmii_tx_val) |
3026 | data8 |= P_RGMII_ID_EG_ENABLE; |
3027 | |
3028 | if (p->rgmii_rx_val) |
3029 | data8 |= P_RGMII_ID_IG_ENABLE; |
3030 | |
3031 | /* Write the updated value */ |
3032 | ksz_pwrite8(dev, port, offset: regs[P_XMII_CTRL_1], data: data8); |
3033 | } |
3034 | |
3035 | phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) |
3036 | { |
3037 | const u8 *bitval = dev->info->xmii_ctrl1; |
3038 | const u16 *regs = dev->info->regs; |
3039 | phy_interface_t interface; |
3040 | u8 data8; |
3041 | u8 val; |
3042 | |
3043 | ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8); |
3044 | |
3045 | val = FIELD_GET(P_MII_SEL_M, data8); |
3046 | |
3047 | if (val == bitval[P_MII_SEL]) { |
3048 | if (gbit) |
3049 | interface = PHY_INTERFACE_MODE_GMII; |
3050 | else |
3051 | interface = PHY_INTERFACE_MODE_MII; |
3052 | } else if (val == bitval[P_RMII_SEL]) { |
3053 | interface = PHY_INTERFACE_MODE_RGMII; |
3054 | } else { |
3055 | interface = PHY_INTERFACE_MODE_RGMII; |
3056 | if (data8 & P_RGMII_ID_EG_ENABLE) |
3057 | interface = PHY_INTERFACE_MODE_RGMII_TXID; |
3058 | if (data8 & P_RGMII_ID_IG_ENABLE) { |
3059 | interface = PHY_INTERFACE_MODE_RGMII_RXID; |
3060 | if (data8 & P_RGMII_ID_EG_ENABLE) |
3061 | interface = PHY_INTERFACE_MODE_RGMII_ID; |
3062 | } |
3063 | } |
3064 | |
3065 | return interface; |
3066 | } |
3067 | |
3068 | static void ksz_phylink_mac_config(struct dsa_switch *ds, int port, |
3069 | unsigned int mode, |
3070 | const struct phylink_link_state *state) |
3071 | { |
3072 | struct ksz_device *dev = ds->priv; |
3073 | |
3074 | if (ksz_is_ksz88x3(dev)) { |
3075 | dev->ports[port].manual_flow = !(state->pause & MLO_PAUSE_AN); |
3076 | return; |
3077 | } |
3078 | |
3079 | /* Internal PHYs */ |
3080 | if (dev->info->internal_phy[port]) |
3081 | return; |
3082 | |
3083 | if (phylink_autoneg_inband(mode)) { |
3084 | dev_err(dev->dev, "In-band AN not supported!\n" ); |
3085 | return; |
3086 | } |
3087 | |
3088 | ksz_set_xmii(dev, port, interface: state->interface); |
3089 | |
3090 | if (dev->dev_ops->phylink_mac_config) |
3091 | dev->dev_ops->phylink_mac_config(dev, port, mode, state); |
3092 | |
3093 | if (dev->dev_ops->setup_rgmii_delay) |
3094 | dev->dev_ops->setup_rgmii_delay(dev, port); |
3095 | } |
3096 | |
3097 | bool ksz_get_gbit(struct ksz_device *dev, int port) |
3098 | { |
3099 | const u8 *bitval = dev->info->xmii_ctrl1; |
3100 | const u16 *regs = dev->info->regs; |
3101 | bool gbit = false; |
3102 | u8 data8; |
3103 | bool val; |
3104 | |
3105 | ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8); |
3106 | |
3107 | val = FIELD_GET(P_GMII_1GBIT_M, data8); |
3108 | |
3109 | if (val == bitval[P_GMII_1GBIT]) |
3110 | gbit = true; |
3111 | |
3112 | return gbit; |
3113 | } |
3114 | |
3115 | static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) |
3116 | { |
3117 | const u8 *bitval = dev->info->xmii_ctrl1; |
3118 | const u16 *regs = dev->info->regs; |
3119 | u8 data8; |
3120 | |
3121 | ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_1], data: &data8); |
3122 | |
3123 | data8 &= ~P_GMII_1GBIT_M; |
3124 | |
3125 | if (gbit) |
3126 | data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); |
3127 | else |
3128 | data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); |
3129 | |
3130 | /* Write the updated value */ |
3131 | ksz_pwrite8(dev, port, offset: regs[P_XMII_CTRL_1], data: data8); |
3132 | } |
3133 | |
3134 | static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) |
3135 | { |
3136 | const u8 *bitval = dev->info->xmii_ctrl0; |
3137 | const u16 *regs = dev->info->regs; |
3138 | u8 data8; |
3139 | |
3140 | ksz_pread8(dev, port, offset: regs[P_XMII_CTRL_0], data: &data8); |
3141 | |
3142 | data8 &= ~P_MII_100MBIT_M; |
3143 | |
3144 | if (speed == SPEED_100) |
3145 | data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); |
3146 | else |
3147 | data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); |
3148 | |
3149 | /* Write the updated value */ |
3150 | ksz_pwrite8(dev, port, offset: regs[P_XMII_CTRL_0], data: data8); |
3151 | } |
3152 | |
3153 | static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) |
3154 | { |
3155 | if (speed == SPEED_1000) |
3156 | ksz_set_gbit(dev, port, gbit: true); |
3157 | else |
3158 | ksz_set_gbit(dev, port, gbit: false); |
3159 | |
3160 | if (speed == SPEED_100 || speed == SPEED_10) |
3161 | ksz_set_100_10mbit(dev, port, speed); |
3162 | } |
3163 | |
3164 | static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, |
3165 | bool tx_pause, bool rx_pause) |
3166 | { |
3167 | const u8 *bitval = dev->info->xmii_ctrl0; |
3168 | const u32 *masks = dev->info->masks; |
3169 | const u16 *regs = dev->info->regs; |
3170 | u8 mask; |
3171 | u8 val; |
3172 | |
3173 | mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | |
3174 | masks[P_MII_RX_FLOW_CTRL]; |
3175 | |
3176 | if (duplex == DUPLEX_FULL) |
3177 | val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); |
3178 | else |
3179 | val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); |
3180 | |
3181 | if (tx_pause) |
3182 | val |= masks[P_MII_TX_FLOW_CTRL]; |
3183 | |
3184 | if (rx_pause) |
3185 | val |= masks[P_MII_RX_FLOW_CTRL]; |
3186 | |
3187 | ksz_prmw8(dev, port, offset: regs[P_XMII_CTRL_0], mask, val); |
3188 | } |
3189 | |
3190 | static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port, |
3191 | unsigned int mode, |
3192 | phy_interface_t interface, |
3193 | struct phy_device *phydev, int speed, |
3194 | int duplex, bool tx_pause, |
3195 | bool rx_pause) |
3196 | { |
3197 | struct ksz_port *p; |
3198 | |
3199 | p = &dev->ports[port]; |
3200 | |
3201 | /* Internal PHYs */ |
3202 | if (dev->info->internal_phy[port]) |
3203 | return; |
3204 | |
3205 | p->phydev.speed = speed; |
3206 | |
3207 | ksz_port_set_xmii_speed(dev, port, speed); |
3208 | |
3209 | ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); |
3210 | } |
3211 | |
3212 | static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port, |
3213 | unsigned int mode, |
3214 | phy_interface_t interface, |
3215 | struct phy_device *phydev, int speed, |
3216 | int duplex, bool tx_pause, bool rx_pause) |
3217 | { |
3218 | struct ksz_device *dev = ds->priv; |
3219 | |
3220 | dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface, phydev, |
3221 | speed, duplex, tx_pause, rx_pause); |
3222 | } |
3223 | |
3224 | static int ksz_switch_detect(struct ksz_device *dev) |
3225 | { |
3226 | u8 id1, id2, id4; |
3227 | u16 id16; |
3228 | u32 id32; |
3229 | int ret; |
3230 | |
3231 | /* read chip id */ |
3232 | ret = ksz_read16(dev, REG_CHIP_ID0, val: &id16); |
3233 | if (ret) |
3234 | return ret; |
3235 | |
3236 | id1 = FIELD_GET(SW_FAMILY_ID_M, id16); |
3237 | id2 = FIELD_GET(SW_CHIP_ID_M, id16); |
3238 | |
3239 | switch (id1) { |
3240 | case KSZ87_FAMILY_ID: |
3241 | if (id2 == KSZ87_CHIP_ID_95) { |
3242 | u8 val; |
3243 | |
3244 | dev->chip_id = KSZ8795_CHIP_ID; |
3245 | |
3246 | ksz_read8(dev, KSZ8_PORT_STATUS_0, val: &val); |
3247 | if (val & KSZ8_PORT_FIBER_MODE) |
3248 | dev->chip_id = KSZ8765_CHIP_ID; |
3249 | } else if (id2 == KSZ87_CHIP_ID_94) { |
3250 | dev->chip_id = KSZ8794_CHIP_ID; |
3251 | } else { |
3252 | return -ENODEV; |
3253 | } |
3254 | break; |
3255 | case KSZ88_FAMILY_ID: |
3256 | if (id2 == KSZ88_CHIP_ID_63) |
3257 | dev->chip_id = KSZ8830_CHIP_ID; |
3258 | else |
3259 | return -ENODEV; |
3260 | break; |
3261 | default: |
3262 | ret = ksz_read32(dev, REG_CHIP_ID0, val: &id32); |
3263 | if (ret) |
3264 | return ret; |
3265 | |
3266 | dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); |
3267 | id32 &= ~0xFF; |
3268 | |
3269 | switch (id32) { |
3270 | case KSZ9477_CHIP_ID: |
3271 | case KSZ9896_CHIP_ID: |
3272 | case KSZ9897_CHIP_ID: |
3273 | case KSZ9567_CHIP_ID: |
3274 | case KSZ8567_CHIP_ID: |
3275 | case LAN9370_CHIP_ID: |
3276 | case LAN9371_CHIP_ID: |
3277 | case LAN9372_CHIP_ID: |
3278 | case LAN9373_CHIP_ID: |
3279 | case LAN9374_CHIP_ID: |
3280 | dev->chip_id = id32; |
3281 | break; |
3282 | case KSZ9893_CHIP_ID: |
3283 | ret = ksz_read8(dev, REG_CHIP_ID4, |
3284 | val: &id4); |
3285 | if (ret) |
3286 | return ret; |
3287 | |
3288 | if (id4 == SKU_ID_KSZ8563) |
3289 | dev->chip_id = KSZ8563_CHIP_ID; |
3290 | else if (id4 == SKU_ID_KSZ9563) |
3291 | dev->chip_id = KSZ9563_CHIP_ID; |
3292 | else |
3293 | dev->chip_id = KSZ9893_CHIP_ID; |
3294 | |
3295 | break; |
3296 | default: |
3297 | dev_err(dev->dev, |
3298 | "unsupported switch detected %x)\n" , id32); |
3299 | return -ENODEV; |
3300 | } |
3301 | } |
3302 | return 0; |
3303 | } |
3304 | |
3305 | static int ksz_cls_flower_add(struct dsa_switch *ds, int port, |
3306 | struct flow_cls_offload *cls, bool ingress) |
3307 | { |
3308 | struct ksz_device *dev = ds->priv; |
3309 | |
3310 | switch (dev->chip_id) { |
3311 | case KSZ8563_CHIP_ID: |
3312 | case KSZ8567_CHIP_ID: |
3313 | case KSZ9477_CHIP_ID: |
3314 | case KSZ9563_CHIP_ID: |
3315 | case KSZ9567_CHIP_ID: |
3316 | case KSZ9893_CHIP_ID: |
3317 | case KSZ9896_CHIP_ID: |
3318 | case KSZ9897_CHIP_ID: |
3319 | return ksz9477_cls_flower_add(ds, port, cls, ingress); |
3320 | } |
3321 | |
3322 | return -EOPNOTSUPP; |
3323 | } |
3324 | |
3325 | static int ksz_cls_flower_del(struct dsa_switch *ds, int port, |
3326 | struct flow_cls_offload *cls, bool ingress) |
3327 | { |
3328 | struct ksz_device *dev = ds->priv; |
3329 | |
3330 | switch (dev->chip_id) { |
3331 | case KSZ8563_CHIP_ID: |
3332 | case KSZ8567_CHIP_ID: |
3333 | case KSZ9477_CHIP_ID: |
3334 | case KSZ9563_CHIP_ID: |
3335 | case KSZ9567_CHIP_ID: |
3336 | case KSZ9893_CHIP_ID: |
3337 | case KSZ9896_CHIP_ID: |
3338 | case KSZ9897_CHIP_ID: |
3339 | return ksz9477_cls_flower_del(ds, port, cls, ingress); |
3340 | } |
3341 | |
3342 | return -EOPNOTSUPP; |
3343 | } |
3344 | |
3345 | /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth |
3346 | * is converted to Hex-decimal using the successive multiplication method. On |
3347 | * every step, integer part is taken and decimal part is carry forwarded. |
3348 | */ |
3349 | static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) |
3350 | { |
3351 | u32 cinc = 0; |
3352 | u32 txrate; |
3353 | u32 rate; |
3354 | u8 temp; |
3355 | u8 i; |
3356 | |
3357 | txrate = idle_slope - send_slope; |
3358 | |
3359 | if (!txrate) |
3360 | return -EINVAL; |
3361 | |
3362 | rate = idle_slope; |
3363 | |
3364 | /* 24 bit register */ |
3365 | for (i = 0; i < 6; i++) { |
3366 | rate = rate * 16; |
3367 | |
3368 | temp = rate / txrate; |
3369 | |
3370 | rate %= txrate; |
3371 | |
3372 | cinc = ((cinc << 4) | temp); |
3373 | } |
3374 | |
3375 | *bw = cinc; |
3376 | |
3377 | return 0; |
3378 | } |
3379 | |
3380 | static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, |
3381 | u8 shaper) |
3382 | { |
3383 | return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, |
3384 | FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | |
3385 | FIELD_PREP(MTI_SHAPING_M, shaper)); |
3386 | } |
3387 | |
3388 | static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, |
3389 | struct tc_cbs_qopt_offload *qopt) |
3390 | { |
3391 | struct ksz_device *dev = ds->priv; |
3392 | int ret; |
3393 | u32 bw; |
3394 | |
3395 | if (!dev->info->tc_cbs_supported) |
3396 | return -EOPNOTSUPP; |
3397 | |
3398 | if (qopt->queue > dev->info->num_tx_queues) |
3399 | return -EINVAL; |
3400 | |
3401 | /* Queue Selection */ |
3402 | ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, data: qopt->queue); |
3403 | if (ret) |
3404 | return ret; |
3405 | |
3406 | if (!qopt->enable) |
3407 | return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, |
3408 | MTI_SHAPING_OFF); |
3409 | |
3410 | /* High Credit */ |
3411 | ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, |
3412 | data: qopt->hicredit); |
3413 | if (ret) |
3414 | return ret; |
3415 | |
3416 | /* Low Credit */ |
3417 | ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, |
3418 | data: qopt->locredit); |
3419 | if (ret) |
3420 | return ret; |
3421 | |
3422 | /* Credit Increment Register */ |
3423 | ret = cinc_cal(idle_slope: qopt->idleslope, send_slope: qopt->sendslope, bw: &bw); |
3424 | if (ret) |
3425 | return ret; |
3426 | |
3427 | if (dev->dev_ops->tc_cbs_set_cinc) { |
3428 | ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); |
3429 | if (ret) |
3430 | return ret; |
3431 | } |
3432 | |
3433 | return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, |
3434 | MTI_SHAPING_SRP); |
3435 | } |
3436 | |
3437 | static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) |
3438 | { |
3439 | int queue, ret; |
3440 | |
3441 | /* Configuration will not take effect until the last Port Queue X |
3442 | * Egress Limit Control Register is written. |
3443 | */ |
3444 | for (queue = 0; queue < dev->info->num_tx_queues; queue++) { |
3445 | ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, |
3446 | KSZ9477_OUT_RATE_NO_LIMIT); |
3447 | if (ret) |
3448 | return ret; |
3449 | } |
3450 | |
3451 | return 0; |
3452 | } |
3453 | |
3454 | static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, |
3455 | int band) |
3456 | { |
3457 | /* Compared to queues, bands prioritize packets differently. In strict |
3458 | * priority mode, the lowest priority is assigned to Queue 0 while the |
3459 | * highest priority is given to Band 0. |
3460 | */ |
3461 | return p->bands - 1 - band; |
3462 | } |
3463 | |
3464 | static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) |
3465 | { |
3466 | int ret; |
3467 | |
3468 | ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, data: queue); |
3469 | if (ret) |
3470 | return ret; |
3471 | |
3472 | return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, |
3473 | MTI_SHAPING_OFF); |
3474 | } |
3475 | |
3476 | static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, |
3477 | int weight) |
3478 | { |
3479 | int ret; |
3480 | |
3481 | ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, data: queue); |
3482 | if (ret) |
3483 | return ret; |
3484 | |
3485 | ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, |
3486 | MTI_SHAPING_OFF); |
3487 | if (ret) |
3488 | return ret; |
3489 | |
3490 | return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, data: weight); |
3491 | } |
3492 | |
3493 | static int ksz_tc_ets_add(struct ksz_device *dev, int port, |
3494 | struct tc_ets_qopt_offload_replace_params *p) |
3495 | { |
3496 | int ret, band, tc_prio; |
3497 | u32 queue_map = 0; |
3498 | |
3499 | /* In order to ensure proper prioritization, it is necessary to set the |
3500 | * rate limit for the related queue to zero. Otherwise strict priority |
3501 | * or WRR mode will not work. This is a hardware limitation. |
3502 | */ |
3503 | ret = ksz_disable_egress_rate_limit(dev, port); |
3504 | if (ret) |
3505 | return ret; |
3506 | |
3507 | /* Configure queue scheduling mode for all bands. Currently only strict |
3508 | * prio mode is supported. |
3509 | */ |
3510 | for (band = 0; band < p->bands; band++) { |
3511 | int queue = ksz_ets_band_to_queue(p, band); |
3512 | |
3513 | ret = ksz_queue_set_strict(dev, port, queue); |
3514 | if (ret) |
3515 | return ret; |
3516 | } |
3517 | |
3518 | /* Configure the mapping between traffic classes and queues. Note: |
3519 | * priomap variable support 16 traffic classes, but the chip can handle |
3520 | * only 8 classes. |
3521 | */ |
3522 | for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { |
3523 | int queue; |
3524 | |
3525 | if (tc_prio > KSZ9477_MAX_TC_PRIO) |
3526 | break; |
3527 | |
3528 | queue = ksz_ets_band_to_queue(p, band: p->priomap[tc_prio]); |
3529 | queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); |
3530 | } |
3531 | |
3532 | return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, data: queue_map); |
3533 | } |
3534 | |
3535 | static int ksz_tc_ets_del(struct ksz_device *dev, int port) |
3536 | { |
3537 | int ret, queue, tc_prio, s; |
3538 | u32 queue_map = 0; |
3539 | |
3540 | /* To restore the default chip configuration, set all queues to use the |
3541 | * WRR scheduler with a weight of 1. |
3542 | */ |
3543 | for (queue = 0; queue < dev->info->num_tx_queues; queue++) { |
3544 | ret = ksz_queue_set_wrr(dev, port, queue, |
3545 | KSZ9477_DEFAULT_WRR_WEIGHT); |
3546 | if (ret) |
3547 | return ret; |
3548 | } |
3549 | |
3550 | switch (dev->info->num_tx_queues) { |
3551 | case 2: |
3552 | s = 2; |
3553 | break; |
3554 | case 4: |
3555 | s = 1; |
3556 | break; |
3557 | case 8: |
3558 | s = 0; |
3559 | break; |
3560 | default: |
3561 | return -EINVAL; |
3562 | } |
3563 | |
3564 | /* Revert the queue mapping for TC-priority to its default setting on |
3565 | * the chip. |
3566 | */ |
3567 | for (tc_prio = 0; tc_prio <= KSZ9477_MAX_TC_PRIO; tc_prio++) { |
3568 | int queue; |
3569 | |
3570 | queue = tc_prio >> s; |
3571 | queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); |
3572 | } |
3573 | |
3574 | return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, data: queue_map); |
3575 | } |
3576 | |
3577 | static int ksz_tc_ets_validate(struct ksz_device *dev, int port, |
3578 | struct tc_ets_qopt_offload_replace_params *p) |
3579 | { |
3580 | int band; |
3581 | |
3582 | /* Since it is not feasible to share one port among multiple qdisc, |
3583 | * the user must configure all available queues appropriately. |
3584 | */ |
3585 | if (p->bands != dev->info->num_tx_queues) { |
3586 | dev_err(dev->dev, "Not supported amount of bands. It should be %d\n" , |
3587 | dev->info->num_tx_queues); |
3588 | return -EOPNOTSUPP; |
3589 | } |
3590 | |
3591 | for (band = 0; band < p->bands; ++band) { |
3592 | /* The KSZ switches utilize a weighted round robin configuration |
3593 | * where a certain number of packets can be transmitted from a |
3594 | * queue before the next queue is serviced. For more information |
3595 | * on this, refer to section 5.2.8.4 of the KSZ8565R |
3596 | * documentation on the Port Transmit Queue Control 1 Register. |
3597 | * However, the current ETS Qdisc implementation (as of February |
3598 | * 2023) assigns a weight to each queue based on the number of |
3599 | * bytes or extrapolated bandwidth in percentages. Since this |
3600 | * differs from the KSZ switches' method and we don't want to |
3601 | * fake support by converting bytes to packets, it is better to |
3602 | * return an error instead. |
3603 | */ |
3604 | if (p->quanta[band]) { |
3605 | dev_err(dev->dev, "Quanta/weights configuration is not supported.\n" ); |
3606 | return -EOPNOTSUPP; |
3607 | } |
3608 | } |
3609 | |
3610 | return 0; |
3611 | } |
3612 | |
3613 | static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, |
3614 | struct tc_ets_qopt_offload *qopt) |
3615 | { |
3616 | struct ksz_device *dev = ds->priv; |
3617 | int ret; |
3618 | |
3619 | if (!dev->info->tc_ets_supported) |
3620 | return -EOPNOTSUPP; |
3621 | |
3622 | if (qopt->parent != TC_H_ROOT) { |
3623 | dev_err(dev->dev, "Parent should be \"root\"\n" ); |
3624 | return -EOPNOTSUPP; |
3625 | } |
3626 | |
3627 | switch (qopt->command) { |
3628 | case TC_ETS_REPLACE: |
3629 | ret = ksz_tc_ets_validate(dev, port, p: &qopt->replace_params); |
3630 | if (ret) |
3631 | return ret; |
3632 | |
3633 | return ksz_tc_ets_add(dev, port, p: &qopt->replace_params); |
3634 | case TC_ETS_DESTROY: |
3635 | return ksz_tc_ets_del(dev, port); |
3636 | case TC_ETS_STATS: |
3637 | case TC_ETS_GRAFT: |
3638 | return -EOPNOTSUPP; |
3639 | } |
3640 | |
3641 | return -EOPNOTSUPP; |
3642 | } |
3643 | |
3644 | static int ksz_setup_tc(struct dsa_switch *ds, int port, |
3645 | enum tc_setup_type type, void *type_data) |
3646 | { |
3647 | switch (type) { |
3648 | case TC_SETUP_QDISC_CBS: |
3649 | return ksz_setup_tc_cbs(ds, port, qopt: type_data); |
3650 | case TC_SETUP_QDISC_ETS: |
3651 | return ksz_tc_setup_qdisc_ets(ds, port, qopt: type_data); |
3652 | default: |
3653 | return -EOPNOTSUPP; |
3654 | } |
3655 | } |
3656 | |
3657 | static void ksz_get_wol(struct dsa_switch *ds, int port, |
3658 | struct ethtool_wolinfo *wol) |
3659 | { |
3660 | struct ksz_device *dev = ds->priv; |
3661 | |
3662 | if (dev->dev_ops->get_wol) |
3663 | dev->dev_ops->get_wol(dev, port, wol); |
3664 | } |
3665 | |
3666 | static int ksz_set_wol(struct dsa_switch *ds, int port, |
3667 | struct ethtool_wolinfo *wol) |
3668 | { |
3669 | struct ksz_device *dev = ds->priv; |
3670 | |
3671 | if (dev->dev_ops->set_wol) |
3672 | return dev->dev_ops->set_wol(dev, port, wol); |
3673 | |
3674 | return -EOPNOTSUPP; |
3675 | } |
3676 | |
3677 | static int ksz_port_set_mac_address(struct dsa_switch *ds, int port, |
3678 | const unsigned char *addr) |
3679 | { |
3680 | struct dsa_port *dp = dsa_to_port(ds, p: port); |
3681 | struct ethtool_wolinfo wol; |
3682 | |
3683 | if (dp->hsr_dev) { |
3684 | dev_err(ds->dev, |
3685 | "Cannot change MAC address on port %d with active HSR offload\n" , |
3686 | port); |
3687 | return -EBUSY; |
3688 | } |
3689 | |
3690 | ksz_get_wol(ds, port: dp->index, wol: &wol); |
3691 | if (wol.wolopts & WAKE_MAGIC) { |
3692 | dev_err(ds->dev, |
3693 | "Cannot change MAC address on port %d with active Wake on Magic Packet\n" , |
3694 | port); |
3695 | return -EBUSY; |
3696 | } |
3697 | |
3698 | return 0; |
3699 | } |
3700 | |
3701 | /** |
3702 | * ksz_is_port_mac_global_usable - Check if the MAC address on a given port |
3703 | * can be used as a global address. |
3704 | * @ds: Pointer to the DSA switch structure. |
3705 | * @port: The port number on which the MAC address is to be checked. |
3706 | * |
3707 | * This function examines the MAC address set on the specified port and |
3708 | * determines if it can be used as a global address for the switch. |
3709 | * |
3710 | * Return: true if the port's MAC address can be used as a global address, false |
3711 | * otherwise. |
3712 | */ |
3713 | bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port) |
3714 | { |
3715 | struct net_device *user = dsa_to_port(ds, p: port)->user; |
3716 | const unsigned char *addr = user->dev_addr; |
3717 | struct ksz_switch_macaddr *switch_macaddr; |
3718 | struct ksz_device *dev = ds->priv; |
3719 | |
3720 | ASSERT_RTNL(); |
3721 | |
3722 | switch_macaddr = dev->switch_macaddr; |
3723 | if (switch_macaddr && !ether_addr_equal(addr1: switch_macaddr->addr, addr2: addr)) |
3724 | return false; |
3725 | |
3726 | return true; |
3727 | } |
3728 | |
3729 | /** |
3730 | * ksz_switch_macaddr_get - Program the switch's MAC address register. |
3731 | * @ds: DSA switch instance. |
3732 | * @port: Port number. |
3733 | * @extack: Netlink extended acknowledgment. |
3734 | * |
3735 | * This function programs the switch's MAC address register with the MAC address |
3736 | * of the requesting user port. This single address is used by the switch for |
3737 | * multiple features like HSR self-address filtering and WoL. Other user ports |
3738 | * can share ownership of this address as long as their MAC address is the same. |
3739 | * The MAC addresses of user ports must not change while they have ownership of |
3740 | * the switch MAC address. |
3741 | * |
3742 | * Return: 0 on success, or other error codes on failure. |
3743 | */ |
3744 | int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, |
3745 | struct netlink_ext_ack *extack) |
3746 | { |
3747 | struct net_device *user = dsa_to_port(ds, p: port)->user; |
3748 | const unsigned char *addr = user->dev_addr; |
3749 | struct ksz_switch_macaddr *switch_macaddr; |
3750 | struct ksz_device *dev = ds->priv; |
3751 | const u16 *regs = dev->info->regs; |
3752 | int i, ret; |
3753 | |
3754 | /* Make sure concurrent MAC address changes are blocked */ |
3755 | ASSERT_RTNL(); |
3756 | |
3757 | switch_macaddr = dev->switch_macaddr; |
3758 | if (switch_macaddr) { |
3759 | if (!ether_addr_equal(addr1: switch_macaddr->addr, addr2: addr)) { |
3760 | NL_SET_ERR_MSG_FMT_MOD(extack, |
3761 | "Switch already configured for MAC address %pM" , |
3762 | switch_macaddr->addr); |
3763 | return -EBUSY; |
3764 | } |
3765 | |
3766 | refcount_inc(r: &switch_macaddr->refcount); |
3767 | return 0; |
3768 | } |
3769 | |
3770 | switch_macaddr = kzalloc(size: sizeof(*switch_macaddr), GFP_KERNEL); |
3771 | if (!switch_macaddr) |
3772 | return -ENOMEM; |
3773 | |
3774 | ether_addr_copy(dst: switch_macaddr->addr, src: addr); |
3775 | refcount_set(r: &switch_macaddr->refcount, n: 1); |
3776 | dev->switch_macaddr = switch_macaddr; |
3777 | |
3778 | /* Program the switch MAC address to hardware */ |
3779 | for (i = 0; i < ETH_ALEN; i++) { |
3780 | ret = ksz_write8(dev, reg: regs[REG_SW_MAC_ADDR] + i, value: addr[i]); |
3781 | if (ret) |
3782 | goto macaddr_drop; |
3783 | } |
3784 | |
3785 | return 0; |
3786 | |
3787 | macaddr_drop: |
3788 | dev->switch_macaddr = NULL; |
3789 | refcount_set(r: &switch_macaddr->refcount, n: 0); |
3790 | kfree(objp: switch_macaddr); |
3791 | |
3792 | return ret; |
3793 | } |
3794 | |
3795 | void ksz_switch_macaddr_put(struct dsa_switch *ds) |
3796 | { |
3797 | struct ksz_switch_macaddr *switch_macaddr; |
3798 | struct ksz_device *dev = ds->priv; |
3799 | const u16 *regs = dev->info->regs; |
3800 | int i; |
3801 | |
3802 | /* Make sure concurrent MAC address changes are blocked */ |
3803 | ASSERT_RTNL(); |
3804 | |
3805 | switch_macaddr = dev->switch_macaddr; |
3806 | if (!refcount_dec_and_test(r: &switch_macaddr->refcount)) |
3807 | return; |
3808 | |
3809 | for (i = 0; i < ETH_ALEN; i++) |
3810 | ksz_write8(dev, reg: regs[REG_SW_MAC_ADDR] + i, value: 0); |
3811 | |
3812 | dev->switch_macaddr = NULL; |
3813 | kfree(objp: switch_macaddr); |
3814 | } |
3815 | |
3816 | static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, |
3817 | struct netlink_ext_ack *extack) |
3818 | { |
3819 | struct ksz_device *dev = ds->priv; |
3820 | enum hsr_version ver; |
3821 | int ret; |
3822 | |
3823 | ret = hsr_get_version(dev: hsr, ver: &ver); |
3824 | if (ret) |
3825 | return ret; |
3826 | |
3827 | if (dev->chip_id != KSZ9477_CHIP_ID) { |
3828 | NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload" ); |
3829 | return -EOPNOTSUPP; |
3830 | } |
3831 | |
3832 | /* KSZ9477 can support HW offloading of only 1 HSR device */ |
3833 | if (dev->hsr_dev && hsr != dev->hsr_dev) { |
3834 | NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR" ); |
3835 | return -EOPNOTSUPP; |
3836 | } |
3837 | |
3838 | /* KSZ9477 only supports HSR v0 and v1 */ |
3839 | if (!(ver == HSR_V0 || ver == HSR_V1)) { |
3840 | NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported" ); |
3841 | return -EOPNOTSUPP; |
3842 | } |
3843 | |
3844 | /* Self MAC address filtering, to avoid frames traversing |
3845 | * the HSR ring more than once. |
3846 | */ |
3847 | ret = ksz_switch_macaddr_get(ds, port, extack); |
3848 | if (ret) |
3849 | return ret; |
3850 | |
3851 | ksz9477_hsr_join(ds, port, hsr); |
3852 | dev->hsr_dev = hsr; |
3853 | dev->hsr_ports |= BIT(port); |
3854 | |
3855 | return 0; |
3856 | } |
3857 | |
3858 | static int ksz_hsr_leave(struct dsa_switch *ds, int port, |
3859 | struct net_device *hsr) |
3860 | { |
3861 | struct ksz_device *dev = ds->priv; |
3862 | |
3863 | WARN_ON(dev->chip_id != KSZ9477_CHIP_ID); |
3864 | |
3865 | ksz9477_hsr_leave(ds, port, hsr); |
3866 | dev->hsr_ports &= ~BIT(port); |
3867 | if (!dev->hsr_ports) |
3868 | dev->hsr_dev = NULL; |
3869 | |
3870 | ksz_switch_macaddr_put(ds); |
3871 | |
3872 | return 0; |
3873 | } |
3874 | |
3875 | static const struct dsa_switch_ops ksz_switch_ops = { |
3876 | .get_tag_protocol = ksz_get_tag_protocol, |
3877 | .connect_tag_protocol = ksz_connect_tag_protocol, |
3878 | .get_phy_flags = ksz_get_phy_flags, |
3879 | .setup = ksz_setup, |
3880 | .teardown = ksz_teardown, |
3881 | .phy_read = ksz_phy_read16, |
3882 | .phy_write = ksz_phy_write16, |
3883 | .phylink_get_caps = ksz_phylink_get_caps, |
3884 | .phylink_mac_config = ksz_phylink_mac_config, |
3885 | .phylink_mac_link_up = ksz_phylink_mac_link_up, |
3886 | .phylink_mac_link_down = ksz_mac_link_down, |
3887 | .port_setup = ksz_port_setup, |
3888 | .set_ageing_time = ksz_set_ageing_time, |
3889 | .get_strings = ksz_get_strings, |
3890 | .get_ethtool_stats = ksz_get_ethtool_stats, |
3891 | .get_sset_count = ksz_sset_count, |
3892 | .port_bridge_join = ksz_port_bridge_join, |
3893 | .port_bridge_leave = ksz_port_bridge_leave, |
3894 | .port_hsr_join = ksz_hsr_join, |
3895 | .port_hsr_leave = ksz_hsr_leave, |
3896 | .port_set_mac_address = ksz_port_set_mac_address, |
3897 | .port_stp_state_set = ksz_port_stp_state_set, |
3898 | .port_teardown = ksz_port_teardown, |
3899 | .port_pre_bridge_flags = ksz_port_pre_bridge_flags, |
3900 | .port_bridge_flags = ksz_port_bridge_flags, |
3901 | .port_fast_age = ksz_port_fast_age, |
3902 | .port_vlan_filtering = ksz_port_vlan_filtering, |
3903 | .port_vlan_add = ksz_port_vlan_add, |
3904 | .port_vlan_del = ksz_port_vlan_del, |
3905 | .port_fdb_dump = ksz_port_fdb_dump, |
3906 | .port_fdb_add = ksz_port_fdb_add, |
3907 | .port_fdb_del = ksz_port_fdb_del, |
3908 | .port_mdb_add = ksz_port_mdb_add, |
3909 | .port_mdb_del = ksz_port_mdb_del, |
3910 | .port_mirror_add = ksz_port_mirror_add, |
3911 | .port_mirror_del = ksz_port_mirror_del, |
3912 | .get_stats64 = ksz_get_stats64, |
3913 | .get_pause_stats = ksz_get_pause_stats, |
3914 | .port_change_mtu = ksz_change_mtu, |
3915 | .port_max_mtu = ksz_max_mtu, |
3916 | .get_wol = ksz_get_wol, |
3917 | .set_wol = ksz_set_wol, |
3918 | .get_ts_info = ksz_get_ts_info, |
3919 | .port_hwtstamp_get = ksz_hwtstamp_get, |
3920 | .port_hwtstamp_set = ksz_hwtstamp_set, |
3921 | .port_txtstamp = ksz_port_txtstamp, |
3922 | .port_rxtstamp = ksz_port_rxtstamp, |
3923 | .cls_flower_add = ksz_cls_flower_add, |
3924 | .cls_flower_del = ksz_cls_flower_del, |
3925 | .port_setup_tc = ksz_setup_tc, |
3926 | .get_mac_eee = ksz_get_mac_eee, |
3927 | .set_mac_eee = ksz_set_mac_eee, |
3928 | }; |
3929 | |
3930 | struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) |
3931 | { |
3932 | struct dsa_switch *ds; |
3933 | struct ksz_device *swdev; |
3934 | |
3935 | ds = devm_kzalloc(dev: base, size: sizeof(*ds), GFP_KERNEL); |
3936 | if (!ds) |
3937 | return NULL; |
3938 | |
3939 | ds->dev = base; |
3940 | ds->num_ports = DSA_MAX_PORTS; |
3941 | ds->ops = &ksz_switch_ops; |
3942 | |
3943 | swdev = devm_kzalloc(dev: base, size: sizeof(*swdev), GFP_KERNEL); |
3944 | if (!swdev) |
3945 | return NULL; |
3946 | |
3947 | ds->priv = swdev; |
3948 | swdev->dev = base; |
3949 | |
3950 | swdev->ds = ds; |
3951 | swdev->priv = priv; |
3952 | |
3953 | return swdev; |
3954 | } |
3955 | EXPORT_SYMBOL(ksz_switch_alloc); |
3956 | |
3957 | /** |
3958 | * ksz_switch_shutdown - Shutdown routine for the switch device. |
3959 | * @dev: The switch device structure. |
3960 | * |
3961 | * This function is responsible for initiating a shutdown sequence for the |
3962 | * switch device. It invokes the reset operation defined in the device |
3963 | * operations, if available, to reset the switch. Subsequently, it calls the |
3964 | * DSA framework's shutdown function to ensure a proper shutdown of the DSA |
3965 | * switch. |
3966 | */ |
3967 | void ksz_switch_shutdown(struct ksz_device *dev) |
3968 | { |
3969 | bool wol_enabled = false; |
3970 | |
3971 | if (dev->dev_ops->wol_pre_shutdown) |
3972 | dev->dev_ops->wol_pre_shutdown(dev, &wol_enabled); |
3973 | |
3974 | if (dev->dev_ops->reset && !wol_enabled) |
3975 | dev->dev_ops->reset(dev); |
3976 | |
3977 | dsa_switch_shutdown(ds: dev->ds); |
3978 | } |
3979 | EXPORT_SYMBOL(ksz_switch_shutdown); |
3980 | |
3981 | static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, |
3982 | struct device_node *port_dn) |
3983 | { |
3984 | phy_interface_t phy_mode = dev->ports[port_num].interface; |
3985 | int rx_delay = -1, tx_delay = -1; |
3986 | |
3987 | if (!phy_interface_mode_is_rgmii(mode: phy_mode)) |
3988 | return; |
3989 | |
3990 | of_property_read_u32(np: port_dn, propname: "rx-internal-delay-ps" , out_value: &rx_delay); |
3991 | of_property_read_u32(np: port_dn, propname: "tx-internal-delay-ps" , out_value: &tx_delay); |
3992 | |
3993 | if (rx_delay == -1 && tx_delay == -1) { |
3994 | dev_warn(dev->dev, |
3995 | "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " |
3996 | "please update device tree to specify \"rx-internal-delay-ps\" and " |
3997 | "\"tx-internal-delay-ps\"" , |
3998 | port_num); |
3999 | |
4000 | if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || |
4001 | phy_mode == PHY_INTERFACE_MODE_RGMII_ID) |
4002 | rx_delay = 2000; |
4003 | |
4004 | if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || |
4005 | phy_mode == PHY_INTERFACE_MODE_RGMII_ID) |
4006 | tx_delay = 2000; |
4007 | } |
4008 | |
4009 | if (rx_delay < 0) |
4010 | rx_delay = 0; |
4011 | if (tx_delay < 0) |
4012 | tx_delay = 0; |
4013 | |
4014 | dev->ports[port_num].rgmii_rx_val = rx_delay; |
4015 | dev->ports[port_num].rgmii_tx_val = tx_delay; |
4016 | } |
4017 | |
4018 | /** |
4019 | * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding |
4020 | * register value. |
4021 | * @array: The array of drive strength values to search. |
4022 | * @array_size: The size of the array. |
4023 | * @microamp: The drive strength value in microamp to be converted. |
4024 | * |
4025 | * This function searches the array of drive strength values for the given |
4026 | * microamp value and returns the corresponding register value for that drive. |
4027 | * |
4028 | * Returns: If found, the corresponding register value for that drive strength |
4029 | * is returned. Otherwise, -EINVAL is returned indicating an invalid value. |
4030 | */ |
4031 | static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, |
4032 | size_t array_size, int microamp) |
4033 | { |
4034 | int i; |
4035 | |
4036 | for (i = 0; i < array_size; i++) { |
4037 | if (array[i].microamp == microamp) |
4038 | return array[i].reg_val; |
4039 | } |
4040 | |
4041 | return -EINVAL; |
4042 | } |
4043 | |
4044 | /** |
4045 | * ksz_drive_strength_error() - Report invalid drive strength value |
4046 | * @dev: ksz device |
4047 | * @array: The array of drive strength values to search. |
4048 | * @array_size: The size of the array. |
4049 | * @microamp: Invalid drive strength value in microamp |
4050 | * |
4051 | * This function logs an error message when an unsupported drive strength value |
4052 | * is detected. It lists out all the supported drive strength values for |
4053 | * reference in the error message. |
4054 | */ |
4055 | static void ksz_drive_strength_error(struct ksz_device *dev, |
4056 | const struct ksz_drive_strength *array, |
4057 | size_t array_size, int microamp) |
4058 | { |
4059 | char supported_values[100]; |
4060 | size_t remaining_size; |
4061 | int added_len; |
4062 | char *ptr; |
4063 | int i; |
4064 | |
4065 | remaining_size = sizeof(supported_values); |
4066 | ptr = supported_values; |
4067 | |
4068 | for (i = 0; i < array_size; i++) { |
4069 | added_len = snprintf(buf: ptr, size: remaining_size, |
4070 | fmt: i == 0 ? "%d" : ", %d" , array[i].microamp); |
4071 | |
4072 | if (added_len >= remaining_size) |
4073 | break; |
4074 | |
4075 | ptr += added_len; |
4076 | remaining_size -= added_len; |
4077 | } |
4078 | |
4079 | dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n" , |
4080 | microamp, supported_values); |
4081 | } |
4082 | |
4083 | /** |
4084 | * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 |
4085 | * chip variants. |
4086 | * @dev: ksz device |
4087 | * @props: Array of drive strength properties to be applied |
4088 | * @num_props: Number of properties in the array |
4089 | * |
4090 | * This function configures the drive strength for various KSZ9477 chip variants |
4091 | * based on the provided properties. It handles chip-specific nuances and |
4092 | * ensures only valid drive strengths are written to the respective chip. |
4093 | * |
4094 | * Return: 0 on successful configuration, a negative error code on failure. |
4095 | */ |
4096 | static int ksz9477_drive_strength_write(struct ksz_device *dev, |
4097 | struct ksz_driver_strength_prop *props, |
4098 | int num_props) |
4099 | { |
4100 | size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); |
4101 | int i, ret, reg; |
4102 | u8 mask = 0; |
4103 | u8 val = 0; |
4104 | |
4105 | if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) |
4106 | dev_warn(dev->dev, "%s is not supported by this chip variant\n" , |
4107 | props[KSZ_DRIVER_STRENGTH_IO].name); |
4108 | |
4109 | if (dev->chip_id == KSZ8795_CHIP_ID || |
4110 | dev->chip_id == KSZ8794_CHIP_ID || |
4111 | dev->chip_id == KSZ8765_CHIP_ID) |
4112 | reg = KSZ8795_REG_SW_CTRL_20; |
4113 | else |
4114 | reg = KSZ9477_REG_SW_IO_STRENGTH; |
4115 | |
4116 | for (i = 0; i < num_props; i++) { |
4117 | if (props[i].value == -1) |
4118 | continue; |
4119 | |
4120 | ret = ksz_drive_strength_to_reg(array: ksz9477_drive_strengths, |
4121 | array_size, microamp: props[i].value); |
4122 | if (ret < 0) { |
4123 | ksz_drive_strength_error(dev, array: ksz9477_drive_strengths, |
4124 | array_size, microamp: props[i].value); |
4125 | return ret; |
4126 | } |
4127 | |
4128 | mask |= SW_DRIVE_STRENGTH_M << props[i].offset; |
4129 | val |= ret << props[i].offset; |
4130 | } |
4131 | |
4132 | return ksz_rmw8(dev, offset: reg, mask, val); |
4133 | } |
4134 | |
4135 | /** |
4136 | * ksz8830_drive_strength_write() - Set the drive strength configuration for |
4137 | * KSZ8830 compatible chip variants. |
4138 | * @dev: ksz device |
4139 | * @props: Array of drive strength properties to be set |
4140 | * @num_props: Number of properties in the array |
4141 | * |
4142 | * This function applies the specified drive strength settings to KSZ8830 chip |
4143 | * variants (KSZ8873, KSZ8863). |
4144 | * It ensures the configurations align with what the chip variant supports and |
4145 | * warns or errors out on unsupported settings. |
4146 | * |
4147 | * Return: 0 on success, error code otherwise |
4148 | */ |
4149 | static int ksz8830_drive_strength_write(struct ksz_device *dev, |
4150 | struct ksz_driver_strength_prop *props, |
4151 | int num_props) |
4152 | { |
4153 | size_t array_size = ARRAY_SIZE(ksz8830_drive_strengths); |
4154 | int microamp; |
4155 | int i, ret; |
4156 | |
4157 | for (i = 0; i < num_props; i++) { |
4158 | if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) |
4159 | continue; |
4160 | |
4161 | dev_warn(dev->dev, "%s is not supported by this chip variant\n" , |
4162 | props[i].name); |
4163 | } |
4164 | |
4165 | microamp = props[KSZ_DRIVER_STRENGTH_IO].value; |
4166 | ret = ksz_drive_strength_to_reg(array: ksz8830_drive_strengths, array_size, |
4167 | microamp); |
4168 | if (ret < 0) { |
4169 | ksz_drive_strength_error(dev, array: ksz8830_drive_strengths, |
4170 | array_size, microamp); |
4171 | return ret; |
4172 | } |
4173 | |
4174 | return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, |
4175 | KSZ8873_DRIVE_STRENGTH_16MA, val: ret); |
4176 | } |
4177 | |
4178 | /** |
4179 | * ksz_parse_drive_strength() - Extract and apply drive strength configurations |
4180 | * from device tree properties. |
4181 | * @dev: ksz device |
4182 | * |
4183 | * This function reads the specified drive strength properties from the |
4184 | * device tree, validates against the supported chip variants, and sets |
4185 | * them accordingly. An error should be critical here, as the drive strength |
4186 | * settings are crucial for EMI compliance. |
4187 | * |
4188 | * Return: 0 on success, error code otherwise |
4189 | */ |
4190 | static int ksz_parse_drive_strength(struct ksz_device *dev) |
4191 | { |
4192 | struct ksz_driver_strength_prop of_props[] = { |
4193 | [KSZ_DRIVER_STRENGTH_HI] = { |
4194 | .name = "microchip,hi-drive-strength-microamp" , |
4195 | .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, |
4196 | .value = -1, |
4197 | }, |
4198 | [KSZ_DRIVER_STRENGTH_LO] = { |
4199 | .name = "microchip,lo-drive-strength-microamp" , |
4200 | .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, |
4201 | .value = -1, |
4202 | }, |
4203 | [KSZ_DRIVER_STRENGTH_IO] = { |
4204 | .name = "microchip,io-drive-strength-microamp" , |
4205 | .offset = 0, /* don't care */ |
4206 | .value = -1, |
4207 | }, |
4208 | }; |
4209 | struct device_node *np = dev->dev->of_node; |
4210 | bool have_any_prop = false; |
4211 | int i, ret; |
4212 | |
4213 | for (i = 0; i < ARRAY_SIZE(of_props); i++) { |
4214 | ret = of_property_read_u32(np, propname: of_props[i].name, |
4215 | out_value: &of_props[i].value); |
4216 | if (ret && ret != -EINVAL) |
4217 | dev_warn(dev->dev, "Failed to read %s\n" , |
4218 | of_props[i].name); |
4219 | if (ret) |
4220 | continue; |
4221 | |
4222 | have_any_prop = true; |
4223 | } |
4224 | |
4225 | if (!have_any_prop) |
4226 | return 0; |
4227 | |
4228 | switch (dev->chip_id) { |
4229 | case KSZ8830_CHIP_ID: |
4230 | return ksz8830_drive_strength_write(dev, props: of_props, |
4231 | ARRAY_SIZE(of_props)); |
4232 | case KSZ8795_CHIP_ID: |
4233 | case KSZ8794_CHIP_ID: |
4234 | case KSZ8765_CHIP_ID: |
4235 | case KSZ8563_CHIP_ID: |
4236 | case KSZ8567_CHIP_ID: |
4237 | case KSZ9477_CHIP_ID: |
4238 | case KSZ9563_CHIP_ID: |
4239 | case KSZ9567_CHIP_ID: |
4240 | case KSZ9893_CHIP_ID: |
4241 | case KSZ9896_CHIP_ID: |
4242 | case KSZ9897_CHIP_ID: |
4243 | return ksz9477_drive_strength_write(dev, props: of_props, |
4244 | ARRAY_SIZE(of_props)); |
4245 | default: |
4246 | for (i = 0; i < ARRAY_SIZE(of_props); i++) { |
4247 | if (of_props[i].value == -1) |
4248 | continue; |
4249 | |
4250 | dev_warn(dev->dev, "%s is not supported by this chip variant\n" , |
4251 | of_props[i].name); |
4252 | } |
4253 | } |
4254 | |
4255 | return 0; |
4256 | } |
4257 | |
4258 | int ksz_switch_register(struct ksz_device *dev) |
4259 | { |
4260 | const struct ksz_chip_data *info; |
4261 | struct device_node *port, *ports; |
4262 | phy_interface_t interface; |
4263 | unsigned int port_num; |
4264 | int ret; |
4265 | int i; |
4266 | |
4267 | dev->reset_gpio = devm_gpiod_get_optional(dev: dev->dev, con_id: "reset" , |
4268 | flags: GPIOD_OUT_LOW); |
4269 | if (IS_ERR(ptr: dev->reset_gpio)) |
4270 | return PTR_ERR(ptr: dev->reset_gpio); |
4271 | |
4272 | if (dev->reset_gpio) { |
4273 | gpiod_set_value_cansleep(desc: dev->reset_gpio, value: 1); |
4274 | usleep_range(min: 10000, max: 12000); |
4275 | gpiod_set_value_cansleep(desc: dev->reset_gpio, value: 0); |
4276 | msleep(msecs: 100); |
4277 | } |
4278 | |
4279 | mutex_init(&dev->dev_mutex); |
4280 | mutex_init(&dev->regmap_mutex); |
4281 | mutex_init(&dev->alu_mutex); |
4282 | mutex_init(&dev->vlan_mutex); |
4283 | |
4284 | ret = ksz_switch_detect(dev); |
4285 | if (ret) |
4286 | return ret; |
4287 | |
4288 | info = ksz_lookup_info(prod_num: dev->chip_id); |
4289 | if (!info) |
4290 | return -ENODEV; |
4291 | |
4292 | /* Update the compatible info with the probed one */ |
4293 | dev->info = info; |
4294 | |
4295 | dev_info(dev->dev, "found switch: %s, rev %i\n" , |
4296 | dev->info->dev_name, dev->chip_rev); |
4297 | |
4298 | ret = ksz_check_device_id(dev); |
4299 | if (ret) |
4300 | return ret; |
4301 | |
4302 | dev->dev_ops = dev->info->ops; |
4303 | |
4304 | ret = dev->dev_ops->init(dev); |
4305 | if (ret) |
4306 | return ret; |
4307 | |
4308 | dev->ports = devm_kzalloc(dev: dev->dev, |
4309 | size: dev->info->port_cnt * sizeof(struct ksz_port), |
4310 | GFP_KERNEL); |
4311 | if (!dev->ports) |
4312 | return -ENOMEM; |
4313 | |
4314 | for (i = 0; i < dev->info->port_cnt; i++) { |
4315 | spin_lock_init(&dev->ports[i].mib.stats64_lock); |
4316 | mutex_init(&dev->ports[i].mib.cnt_mutex); |
4317 | dev->ports[i].mib.counters = |
4318 | devm_kzalloc(dev: dev->dev, |
4319 | size: sizeof(u64) * (dev->info->mib_cnt + 1), |
4320 | GFP_KERNEL); |
4321 | if (!dev->ports[i].mib.counters) |
4322 | return -ENOMEM; |
4323 | |
4324 | dev->ports[i].ksz_dev = dev; |
4325 | dev->ports[i].num = i; |
4326 | } |
4327 | |
4328 | /* set the real number of ports */ |
4329 | dev->ds->num_ports = dev->info->port_cnt; |
4330 | |
4331 | /* Host port interface will be self detected, or specifically set in |
4332 | * device tree. |
4333 | */ |
4334 | for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) |
4335 | dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; |
4336 | if (dev->dev->of_node) { |
4337 | ret = of_get_phy_mode(np: dev->dev->of_node, interface: &interface); |
4338 | if (ret == 0) |
4339 | dev->compat_interface = interface; |
4340 | ports = of_get_child_by_name(node: dev->dev->of_node, name: "ethernet-ports" ); |
4341 | if (!ports) |
4342 | ports = of_get_child_by_name(node: dev->dev->of_node, name: "ports" ); |
4343 | if (ports) { |
4344 | for_each_available_child_of_node(ports, port) { |
4345 | if (of_property_read_u32(np: port, propname: "reg" , |
4346 | out_value: &port_num)) |
4347 | continue; |
4348 | if (!(dev->port_mask & BIT(port_num))) { |
4349 | of_node_put(node: port); |
4350 | of_node_put(node: ports); |
4351 | return -EINVAL; |
4352 | } |
4353 | of_get_phy_mode(np: port, |
4354 | interface: &dev->ports[port_num].interface); |
4355 | |
4356 | ksz_parse_rgmii_delay(dev, port_num, port_dn: port); |
4357 | } |
4358 | of_node_put(node: ports); |
4359 | } |
4360 | dev->synclko_125 = of_property_read_bool(np: dev->dev->of_node, |
4361 | propname: "microchip,synclko-125" ); |
4362 | dev->synclko_disable = of_property_read_bool(np: dev->dev->of_node, |
4363 | propname: "microchip,synclko-disable" ); |
4364 | if (dev->synclko_125 && dev->synclko_disable) { |
4365 | dev_err(dev->dev, "inconsistent synclko settings\n" ); |
4366 | return -EINVAL; |
4367 | } |
4368 | |
4369 | dev->wakeup_source = of_property_read_bool(np: dev->dev->of_node, |
4370 | propname: "wakeup-source" ); |
4371 | } |
4372 | |
4373 | ret = dsa_register_switch(ds: dev->ds); |
4374 | if (ret) { |
4375 | dev->dev_ops->exit(dev); |
4376 | return ret; |
4377 | } |
4378 | |
4379 | /* Read MIB counters every 30 seconds to avoid overflow. */ |
4380 | dev->mib_read_interval = msecs_to_jiffies(m: 5000); |
4381 | |
4382 | /* Start the MIB timer. */ |
4383 | schedule_delayed_work(dwork: &dev->mib_read, delay: 0); |
4384 | |
4385 | return ret; |
4386 | } |
4387 | EXPORT_SYMBOL(ksz_switch_register); |
4388 | |
4389 | void ksz_switch_remove(struct ksz_device *dev) |
4390 | { |
4391 | /* timer started */ |
4392 | if (dev->mib_read_interval) { |
4393 | dev->mib_read_interval = 0; |
4394 | cancel_delayed_work_sync(dwork: &dev->mib_read); |
4395 | } |
4396 | |
4397 | dev->dev_ops->exit(dev); |
4398 | dsa_unregister_switch(ds: dev->ds); |
4399 | |
4400 | if (dev->reset_gpio) |
4401 | gpiod_set_value_cansleep(desc: dev->reset_gpio, value: 1); |
4402 | |
4403 | } |
4404 | EXPORT_SYMBOL(ksz_switch_remove); |
4405 | |
4406 | MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>" ); |
4407 | MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver" ); |
4408 | MODULE_LICENSE("GPL" ); |
4409 | |