| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Marvell 88E6xxx Switch Global 2 Registers support |
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| 4 | * |
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| 5 | * Copyright (c) 2008 Marvell Semiconductor |
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| 6 | * |
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| 7 | * Copyright (c) 2016-2017 Savoir-faire Linux Inc. |
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| 8 | * Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
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| 9 | */ |
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| 10 | |
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| 11 | #ifndef _MV88E6XXX_GLOBAL2_H |
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| 12 | #define _MV88E6XXX_GLOBAL2_H |
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| 13 | |
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| 14 | #include "chip.h" |
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| 15 | |
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| 16 | /* Offset 0x00: Interrupt Source Register */ |
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| 17 | #define MV88E6XXX_G2_INT_SRC 0x00 |
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| 18 | #define MV88E6XXX_G2_INT_SRC_WDOG 0x8000 |
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| 19 | #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000 |
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| 20 | #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000 |
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| 21 | #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000 |
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| 22 | #define MV88E6352_G2_INT_SRC_SERDES 0x0800 |
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| 23 | #define MV88E6352_G2_INT_SRC_PHY 0x001f |
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| 24 | #define MV88E6390_G2_INT_SRC_PHY 0x07fe |
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| 25 | |
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| 26 | #define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15 |
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| 27 | |
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| 28 | /* Offset 0x01: Interrupt Mask Register */ |
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| 29 | #define MV88E6XXX_G2_INT_MASK 0x01 |
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| 30 | #define MV88E6XXX_G2_INT_MASK_WDOG 0x8000 |
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| 31 | #define MV88E6XXX_G2_INT_MASK_JAM_LIMIT 0x4000 |
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| 32 | #define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH 0x2000 |
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| 33 | #define MV88E6XXX_G2_INT_MASK_WAKE_EVENT 0x1000 |
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| 34 | #define MV88E6352_G2_INT_MASK_SERDES 0x0800 |
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| 35 | #define MV88E6352_G2_INT_MASK_PHY 0x001f |
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| 36 | #define MV88E6390_G2_INT_MASK_PHY 0x07fe |
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| 37 | |
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| 38 | /* Offset 0x02: MGMT Enable Register 2x */ |
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| 39 | #define MV88E6XXX_G2_MGMT_EN_2X 0x02 |
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| 40 | |
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| 41 | /* Offset 0x02: MAC LINK change IRQ Register for MV88E6393X */ |
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| 42 | #define MV88E6393X_G2_MACLINK_INT_SRC 0x02 |
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| 43 | |
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| 44 | /* Offset 0x03: MGMT Enable Register 0x */ |
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| 45 | #define MV88E6XXX_G2_MGMT_EN_0X 0x03 |
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| 46 | |
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| 47 | /* Offset 0x03: MAC LINK change IRQ Mask Register for MV88E6393X */ |
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| 48 | #define MV88E6393X_G2_MACLINK_INT_MASK 0x03 |
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| 49 | |
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| 50 | /* Offset 0x04: Flow Control Delay Register */ |
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| 51 | #define MV88E6XXX_G2_FLOW_CTL 0x04 |
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| 52 | |
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| 53 | /* Offset 0x05: Switch Management Register */ |
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| 54 | #define MV88E6XXX_G2_SWITCH_MGMT 0x05 |
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| 55 | #define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000 |
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| 56 | #define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000 |
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| 57 | #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000 |
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| 58 | #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080 |
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| 59 | #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008 |
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| 60 | |
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| 61 | #define MV88E6393X_G2_EGRESS_MONITOR_DEST 0x05 |
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| 62 | |
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| 63 | /* Offset 0x06: Device Mapping Table Register */ |
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| 64 | #define MV88E6XXX_G2_DEVICE_MAPPING 0x06 |
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| 65 | #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000 |
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| 66 | #define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f00 |
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| 67 | #define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK 0x000f |
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| 68 | #define MV88E6390_G2_DEVICE_MAPPING_PORT_MASK 0x001f |
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| 69 | |
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| 70 | /* Offset 0x07: Trunk Mask Table Register */ |
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| 71 | #define MV88E6XXX_G2_TRUNK_MASK 0x07 |
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| 72 | #define MV88E6XXX_G2_TRUNK_MASK_UPDATE 0x8000 |
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| 73 | #define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK 0x7000 |
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| 74 | #define MV88E6XXX_G2_TRUNK_MASK_HASH 0x0800 |
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| 75 | |
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| 76 | /* Offset 0x08: Trunk Mapping Table Register */ |
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| 77 | #define MV88E6XXX_G2_TRUNK_MAPPING 0x08 |
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| 78 | #define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x8000 |
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| 79 | #define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x7800 |
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| 80 | |
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| 81 | /* Offset 0x09: Ingress Rate Command Register */ |
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| 82 | #define MV88E6XXX_G2_IRL_CMD 0x09 |
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| 83 | #define MV88E6XXX_G2_IRL_CMD_BUSY 0x8000 |
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| 84 | #define MV88E6352_G2_IRL_CMD_OP_MASK 0x7000 |
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| 85 | #define MV88E6352_G2_IRL_CMD_OP_NOOP 0x0000 |
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| 86 | #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x1000 |
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| 87 | #define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x2000 |
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| 88 | #define MV88E6352_G2_IRL_CMD_OP_WRITE_REG 0x3000 |
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| 89 | #define MV88E6352_G2_IRL_CMD_OP_READ_REG 0x4000 |
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| 90 | #define MV88E6390_G2_IRL_CMD_OP_MASK 0x6000 |
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| 91 | #define MV88E6390_G2_IRL_CMD_OP_READ_REG 0x0000 |
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| 92 | #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x2000 |
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| 93 | #define MV88E6390_G2_IRL_CMD_OP_INIT_RES 0x4000 |
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| 94 | #define MV88E6390_G2_IRL_CMD_OP_WRITE_REG 0x6000 |
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| 95 | #define MV88E6352_G2_IRL_CMD_PORT_MASK 0x0f00 |
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| 96 | #define MV88E6390_G2_IRL_CMD_PORT_MASK 0x1f00 |
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| 97 | #define MV88E6XXX_G2_IRL_CMD_RES_MASK 0x00e0 |
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| 98 | #define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f |
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| 99 | |
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| 100 | /* Offset 0x0A: Ingress Rate Data Register */ |
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| 101 | #define MV88E6XXX_G2_IRL_DATA 0x0a |
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| 102 | #define MV88E6XXX_G2_IRL_DATA_MASK 0xffff |
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| 103 | |
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| 104 | /* Offset 0x0B: Cross-chip Port VLAN Register */ |
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| 105 | #define MV88E6XXX_G2_PVT_ADDR 0x0b |
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| 106 | #define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000 |
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| 107 | #define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000 |
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| 108 | #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000 |
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| 109 | #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000 |
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| 110 | #define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000 |
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| 111 | #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff |
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| 112 | #define MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK 0x1f |
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| 113 | |
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| 114 | /* Offset 0x0C: Cross-chip Port VLAN Data Register */ |
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| 115 | #define MV88E6XXX_G2_PVT_DATA 0x0c |
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| 116 | #define MV88E6XXX_G2_PVT_DATA_MASK 0x7f |
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| 117 | |
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| 118 | /* Offset 0x0D: Switch MAC/WoL/WoF Register */ |
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| 119 | #define MV88E6XXX_G2_SWITCH_MAC 0x0d |
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| 120 | #define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000 |
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| 121 | #define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00 |
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| 122 | #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff |
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| 123 | |
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| 124 | /* Offset 0x0E: ATU Stats Register */ |
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| 125 | #define MV88E6XXX_G2_ATU_STATS 0x0e |
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| 126 | #define MV88E6XXX_G2_ATU_STATS_BIN_0 (0x0 << 14) |
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| 127 | #define MV88E6XXX_G2_ATU_STATS_BIN_1 (0x1 << 14) |
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| 128 | #define MV88E6XXX_G2_ATU_STATS_BIN_2 (0x2 << 14) |
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| 129 | #define MV88E6XXX_G2_ATU_STATS_BIN_3 (0x3 << 14) |
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| 130 | #define MV88E6XXX_G2_ATU_STATS_MODE_ALL (0x0 << 12) |
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| 131 | #define MV88E6XXX_G2_ATU_STATS_MODE_ALL_DYNAMIC (0x1 << 12) |
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| 132 | #define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL (0x2 << 12) |
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| 133 | #define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL_DYNAMIC (0x3 << 12) |
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| 134 | #define MV88E6XXX_G2_ATU_STATS_MASK 0x0fff |
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| 135 | |
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| 136 | /* Offset 0x0F: Priority Override Table */ |
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| 137 | #define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f |
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| 138 | #define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000 |
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| 139 | #define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000 |
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| 140 | #define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00 |
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| 141 | #define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080 |
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| 142 | #define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030 |
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| 143 | #define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008 |
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| 144 | #define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007 |
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| 145 | |
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| 146 | /* Offset 0x14: EEPROM Command */ |
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| 147 | #define MV88E6XXX_G2_EEPROM_CMD 0x14 |
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| 148 | #define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000 |
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| 149 | #define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000 |
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| 150 | #define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000 |
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| 151 | #define MV88E6XXX_G2_EEPROM_CMD_OP_READ 0x4000 |
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| 152 | #define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD 0x6000 |
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| 153 | #define MV88E6XXX_G2_EEPROM_CMD_RUNNING 0x0800 |
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| 154 | #define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN 0x0400 |
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| 155 | #define MV88E6352_G2_EEPROM_CMD_ADDR_MASK 0x00ff |
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| 156 | #define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff |
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| 157 | |
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| 158 | /* Offset 0x15: EEPROM Data */ |
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| 159 | #define MV88E6352_G2_EEPROM_DATA 0x15 |
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| 160 | #define MV88E6352_G2_EEPROM_DATA_MASK 0xffff |
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| 161 | |
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| 162 | /* Offset 0x15: EEPROM Addr */ |
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| 163 | #define MV88E6390_G2_EEPROM_ADDR 0x15 |
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| 164 | #define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff |
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| 165 | |
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| 166 | /* Offset 0x16: AVB Command Register */ |
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| 167 | #define MV88E6352_G2_AVB_CMD 0x16 |
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| 168 | #define MV88E6352_G2_AVB_CMD_BUSY 0x8000 |
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| 169 | #define MV88E6352_G2_AVB_CMD_OP_READ 0x4000 |
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| 170 | #define MV88E6352_G2_AVB_CMD_OP_READ_INCR 0x6000 |
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| 171 | #define MV88E6352_G2_AVB_CMD_OP_WRITE 0x3000 |
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| 172 | #define MV88E6390_G2_AVB_CMD_OP_READ 0x0000 |
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| 173 | #define MV88E6390_G2_AVB_CMD_OP_READ_INCR 0x4000 |
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| 174 | #define MV88E6390_G2_AVB_CMD_OP_WRITE 0x6000 |
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| 175 | #define MV88E6352_G2_AVB_CMD_PORT_MASK 0x0f00 |
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| 176 | #define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL 0xe |
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| 177 | #define MV88E6165_G2_AVB_CMD_PORT_PTPGLOBAL 0xf |
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| 178 | #define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL 0xf |
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| 179 | #define MV88E6390_G2_AVB_CMD_PORT_MASK 0x1f00 |
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| 180 | #define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL 0x1e |
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| 181 | #define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL 0x1f |
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| 182 | #define MV88E6352_G2_AVB_CMD_BLOCK_PTP 0 |
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| 183 | #define MV88E6352_G2_AVB_CMD_BLOCK_AVB 1 |
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| 184 | #define MV88E6352_G2_AVB_CMD_BLOCK_QAV 2 |
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| 185 | #define MV88E6352_G2_AVB_CMD_BLOCK_QVB 3 |
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| 186 | #define MV88E6352_G2_AVB_CMD_BLOCK_MASK 0x00e0 |
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| 187 | #define MV88E6352_G2_AVB_CMD_ADDR_MASK 0x001f |
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| 188 | |
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| 189 | /* Offset 0x17: AVB Data Register */ |
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| 190 | #define MV88E6352_G2_AVB_DATA 0x17 |
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| 191 | |
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| 192 | /* Offset 0x18: SMI PHY Command Register */ |
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| 193 | #define MV88E6XXX_G2_SMI_PHY_CMD 0x18 |
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| 194 | #define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000 |
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| 195 | #define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000 |
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| 196 | #define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000 |
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| 197 | #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000 |
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| 198 | #define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP 0x4000 |
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| 199 | #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK 0x1000 |
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| 200 | #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 0x0000 |
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| 201 | #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 0x1000 |
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| 202 | #define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK 0x0c00 |
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| 203 | #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA 0x0400 |
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| 204 | #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA 0x0800 |
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| 205 | #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR 0x0000 |
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| 206 | #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA 0x0400 |
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| 207 | #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC 0x0800 |
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| 208 | #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA 0x0c00 |
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| 209 | #define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK 0x03e0 |
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| 210 | #define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK 0x001f |
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| 211 | #define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff |
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| 212 | |
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| 213 | /* Offset 0x19: SMI PHY Data Register */ |
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| 214 | #define MV88E6XXX_G2_SMI_PHY_DATA 0x19 |
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| 215 | |
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| 216 | /* Offset 0x1A: Scratch and Misc. Register */ |
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| 217 | #define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a |
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| 218 | #define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000 |
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| 219 | #define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00 |
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| 220 | #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff |
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| 221 | |
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| 222 | /* Offset 0x1B: Watch Dog Control Register */ |
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| 223 | #define MV88E6250_G2_WDOG_CTL 0x1b |
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| 224 | #define MV88E6250_G2_WDOG_CTL_QC_HISTORY 0x0100 |
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| 225 | #define MV88E6250_G2_WDOG_CTL_QC_EVENT 0x0080 |
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| 226 | #define MV88E6250_G2_WDOG_CTL_QC_ENABLE 0x0040 |
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| 227 | #define MV88E6250_G2_WDOG_CTL_EGRESS_HISTORY 0x0020 |
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| 228 | #define MV88E6250_G2_WDOG_CTL_EGRESS_EVENT 0x0010 |
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| 229 | #define MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE 0x0008 |
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| 230 | #define MV88E6250_G2_WDOG_CTL_FORCE_IRQ 0x0004 |
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| 231 | #define MV88E6250_G2_WDOG_CTL_HISTORY 0x0002 |
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| 232 | #define MV88E6250_G2_WDOG_CTL_SWRESET 0x0001 |
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| 233 | |
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| 234 | /* Offset 0x1B: Watch Dog Control Register */ |
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| 235 | #define MV88E6352_G2_WDOG_CTL 0x1b |
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| 236 | #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080 |
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| 237 | #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040 |
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| 238 | #define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020 |
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| 239 | #define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY 0x0010 |
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| 240 | #define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008 |
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| 241 | #define MV88E6352_G2_WDOG_CTL_FORCE_IRQ 0x0004 |
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| 242 | #define MV88E6352_G2_WDOG_CTL_HISTORY 0x0002 |
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| 243 | #define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001 |
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| 244 | |
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| 245 | /* Offset 0x1B: Watch Dog Control Register */ |
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| 246 | #define MV88E6390_G2_WDOG_CTL 0x1b |
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| 247 | #define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000 |
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| 248 | #define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00 |
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| 249 | #define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000 |
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| 250 | #define MV88E6390_G2_WDOG_CTL_PTR_INT_STS 0x1000 |
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| 251 | #define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE 0x1100 |
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| 252 | #define MV88E6390_G2_WDOG_CTL_PTR_EVENT 0x1200 |
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| 253 | #define MV88E6390_G2_WDOG_CTL_PTR_HISTORY 0x1300 |
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| 254 | #define MV88E6390_G2_WDOG_CTL_DATA_MASK 0x00ff |
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| 255 | #define MV88E6390_G2_WDOG_CTL_CUT_THROUGH 0x0008 |
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| 256 | #define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER 0x0004 |
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| 257 | #define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002 |
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| 258 | #define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001 |
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| 259 | |
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| 260 | /* Offset 0x1C: QoS Weights Register */ |
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| 261 | #define MV88E6XXX_G2_QOS_WEIGHTS 0x1c |
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| 262 | #define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000 |
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| 263 | #define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00 |
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| 264 | #define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00 |
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| 265 | #define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff |
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| 266 | |
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| 267 | /* Offset 0x1D: Misc Register */ |
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| 268 | #define MV88E6XXX_G2_MISC 0x1d |
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| 269 | #define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000 |
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| 270 | #define MV88E6352_G2_NOEGR_POLICY 0x2000 |
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| 271 | #define MV88E6390_G2_LAG_ID_4 0x2000 |
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| 272 | |
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| 273 | /* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */ |
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| 274 | /* Offset 0x02: Misc Configuration */ |
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| 275 | #define MV88E6352_G2_SCRATCH_MISC_CFG 0x02 |
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| 276 | #define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI 0x80 |
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| 277 | /* Offset 0x60-0x61: GPIO Configuration */ |
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| 278 | #define MV88E6352_G2_SCRATCH_GPIO_CFG0 0x60 |
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| 279 | #define MV88E6352_G2_SCRATCH_GPIO_CFG1 0x61 |
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| 280 | /* Offset 0x62-0x63: GPIO Direction */ |
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| 281 | #define MV88E6352_G2_SCRATCH_GPIO_DIR0 0x62 |
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| 282 | #define MV88E6352_G2_SCRATCH_GPIO_DIR1 0x63 |
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| 283 | #define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT 0 |
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| 284 | #define MV88E6352_G2_SCRATCH_GPIO_DIR_IN 1 |
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| 285 | /* Offset 0x64-0x65: GPIO Data */ |
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| 286 | #define MV88E6352_G2_SCRATCH_GPIO_DATA0 0x64 |
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| 287 | #define MV88E6352_G2_SCRATCH_GPIO_DATA1 0x65 |
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| 288 | /* Offset 0x68-0x6F: GPIO Pin Control */ |
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| 289 | #define MV88E6352_G2_SCRATCH_GPIO_PCTL0 0x68 |
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| 290 | #define MV88E6352_G2_SCRATCH_GPIO_PCTL1 0x69 |
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| 291 | #define MV88E6352_G2_SCRATCH_GPIO_PCTL2 0x6A |
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| 292 | #define MV88E6352_G2_SCRATCH_GPIO_PCTL3 0x6B |
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| 293 | #define MV88E6352_G2_SCRATCH_GPIO_PCTL4 0x6C |
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| 294 | #define MV88E6352_G2_SCRATCH_GPIO_PCTL5 0x6D |
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| 295 | #define MV88E6352_G2_SCRATCH_GPIO_PCTL6 0x6E |
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| 296 | #define MV88E6352_G2_SCRATCH_GPIO_PCTL7 0x6F |
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| 297 | #define MV88E6352_G2_SCRATCH_CONFIG_DATA0 0x70 |
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| 298 | #define MV88E6352_G2_SCRATCH_CONFIG_DATA1 0x71 |
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| 299 | #define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU BIT(2) |
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| 300 | #define MV88E6352_G2_SCRATCH_CONFIG_DATA2 0x72 |
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| 301 | #define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK 0xf |
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| 302 | #define MV88E6352_G2_SCRATCH_CONFIG_DATA3 0x73 |
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| 303 | #define MV88E6352_G2_SCRATCH_CONFIG_DATA3_S_SEL BIT(1) |
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| 304 | |
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| 305 | #define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO 0 |
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| 306 | #define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG 1 |
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| 307 | #define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ 2 |
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| 308 | |
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| 309 | int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); |
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| 310 | int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val); |
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| 311 | int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg, |
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| 312 | int bit, int val); |
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| 313 | |
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| 314 | int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); |
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| 315 | int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port); |
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| 316 | |
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| 317 | int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip, |
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| 318 | struct mii_bus *bus, |
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| 319 | int addr, int reg, u16 *val); |
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| 320 | int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip, |
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| 321 | struct mii_bus *bus, |
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| 322 | int addr, int reg, u16 val); |
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| 323 | int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip, |
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| 324 | struct mii_bus *bus, |
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| 325 | int addr, int devad, int reg, u16 *val); |
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| 326 | int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip, |
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| 327 | struct mii_bus *bus, |
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| 328 | int addr, int devad, int reg, u16 val); |
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| 329 | int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); |
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| 330 | |
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| 331 | int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip, |
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| 332 | struct ethtool_eeprom *eeprom, u8 *data); |
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| 333 | int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip, |
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| 334 | struct ethtool_eeprom *eeprom, u8 *data); |
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| 335 | |
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| 336 | int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip, |
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| 337 | struct ethtool_eeprom *eeprom, u8 *data); |
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| 338 | int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip, |
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| 339 | struct ethtool_eeprom *eeprom, u8 *data); |
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| 340 | |
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| 341 | int mv88e6xxx_g2_pvt_read(struct mv88e6xxx_chip *chip, int src_dev, |
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| 342 | int src_port, u16 *data); |
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| 343 | int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev, |
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| 344 | int src_port, u16 data); |
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| 345 | int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip); |
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| 346 | |
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| 347 | int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip); |
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| 348 | void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip); |
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| 349 | |
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| 350 | int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip, |
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| 351 | struct mii_bus *bus); |
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| 352 | void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip, |
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| 353 | struct mii_bus *bus); |
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| 354 | |
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| 355 | int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); |
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| 356 | int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); |
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| 357 | |
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| 358 | int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip); |
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| 359 | |
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| 360 | int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num, |
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| 361 | bool hash, u16 mask); |
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| 362 | int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id, |
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| 363 | u16 map); |
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| 364 | int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip); |
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| 365 | |
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| 366 | int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target, |
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| 367 | int port); |
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| 368 | int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip); |
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| 369 | |
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| 370 | extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops; |
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| 371 | extern const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops; |
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| 372 | extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops; |
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| 373 | extern const struct mv88e6xxx_irq_ops mv88e6393x_watchdog_ops; |
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| 374 | |
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| 375 | extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops; |
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| 376 | extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops; |
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| 377 | extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops; |
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| 378 | |
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| 379 | extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops; |
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| 380 | |
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| 381 | int mv88e6390_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, |
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| 382 | bool external); |
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| 383 | int mv88e6393x_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip, |
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| 384 | bool external); |
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| 385 | int mv88e6352_g2_scratch_port_has_serdes(struct mv88e6xxx_chip *chip, int port); |
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| 386 | int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin); |
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| 387 | int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats); |
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| 388 | |
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| 389 | #endif /* _MV88E6XXX_GLOBAL2_H */ |
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| 390 | |
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