1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Marvell 88e6xxx Ethernet switch single-chip support |
4 | * |
5 | * Copyright (c) 2008 Marvell Semiconductor |
6 | * |
7 | * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> |
8 | * |
9 | * Copyright (c) 2016-2017 Savoir-faire Linux Inc. |
10 | * Vivien Didelot <vivien.didelot@savoirfairelinux.com> |
11 | */ |
12 | |
13 | #include <linux/bitfield.h> |
14 | #include <linux/delay.h> |
15 | #include <linux/dsa/mv88e6xxx.h> |
16 | #include <linux/etherdevice.h> |
17 | #include <linux/ethtool.h> |
18 | #include <linux/if_bridge.h> |
19 | #include <linux/interrupt.h> |
20 | #include <linux/irq.h> |
21 | #include <linux/irqdomain.h> |
22 | #include <linux/jiffies.h> |
23 | #include <linux/list.h> |
24 | #include <linux/mdio.h> |
25 | #include <linux/module.h> |
26 | #include <linux/of.h> |
27 | #include <linux/of_irq.h> |
28 | #include <linux/of_mdio.h> |
29 | #include <linux/platform_data/mv88e6xxx.h> |
30 | #include <linux/netdevice.h> |
31 | #include <linux/gpio/consumer.h> |
32 | #include <linux/phylink.h> |
33 | #include <net/dsa.h> |
34 | |
35 | #include "chip.h" |
36 | #include "devlink.h" |
37 | #include "global1.h" |
38 | #include "global2.h" |
39 | #include "hwtstamp.h" |
40 | #include "phy.h" |
41 | #include "port.h" |
42 | #include "ptp.h" |
43 | #include "serdes.h" |
44 | #include "smi.h" |
45 | |
46 | static void assert_reg_lock(struct mv88e6xxx_chip *chip) |
47 | { |
48 | if (unlikely(!mutex_is_locked(&chip->reg_lock))) { |
49 | dev_err(chip->dev, "Switch registers lock not held!\n" ); |
50 | dump_stack(); |
51 | } |
52 | } |
53 | |
54 | int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) |
55 | { |
56 | int err; |
57 | |
58 | assert_reg_lock(chip); |
59 | |
60 | err = mv88e6xxx_smi_read(chip, dev: addr, reg, data: val); |
61 | if (err) |
62 | return err; |
63 | |
64 | dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n" , |
65 | addr, reg, *val); |
66 | |
67 | return 0; |
68 | } |
69 | |
70 | int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) |
71 | { |
72 | int err; |
73 | |
74 | assert_reg_lock(chip); |
75 | |
76 | err = mv88e6xxx_smi_write(chip, dev: addr, reg, data: val); |
77 | if (err) |
78 | return err; |
79 | |
80 | dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n" , |
81 | addr, reg, val); |
82 | |
83 | return 0; |
84 | } |
85 | |
86 | int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, |
87 | u16 mask, u16 val) |
88 | { |
89 | const unsigned long timeout = jiffies + msecs_to_jiffies(m: 50); |
90 | u16 data; |
91 | int err; |
92 | int i; |
93 | |
94 | /* There's no bus specific operation to wait for a mask. Even |
95 | * if the initial poll takes longer than 50ms, always do at |
96 | * least one more attempt. |
97 | */ |
98 | for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { |
99 | err = mv88e6xxx_read(chip, addr, reg, val: &data); |
100 | if (err) |
101 | return err; |
102 | |
103 | if ((data & mask) == val) |
104 | return 0; |
105 | |
106 | if (i < 2) |
107 | cpu_relax(); |
108 | else |
109 | usleep_range(min: 1000, max: 2000); |
110 | } |
111 | |
112 | err = mv88e6xxx_read(chip, addr, reg, val: &data); |
113 | if (err) |
114 | return err; |
115 | |
116 | if ((data & mask) == val) |
117 | return 0; |
118 | |
119 | dev_err(chip->dev, "Timeout while waiting for switch\n" ); |
120 | return -ETIMEDOUT; |
121 | } |
122 | |
123 | int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, |
124 | int bit, int val) |
125 | { |
126 | return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), |
127 | val: val ? BIT(bit) : 0x0000); |
128 | } |
129 | |
130 | struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) |
131 | { |
132 | struct mv88e6xxx_mdio_bus *mdio_bus; |
133 | |
134 | mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, |
135 | list); |
136 | if (!mdio_bus) |
137 | return NULL; |
138 | |
139 | return mdio_bus->bus; |
140 | } |
141 | |
142 | static void mv88e6xxx_g1_irq_mask(struct irq_data *d) |
143 | { |
144 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); |
145 | unsigned int n = d->hwirq; |
146 | |
147 | chip->g1_irq.masked |= (1 << n); |
148 | } |
149 | |
150 | static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) |
151 | { |
152 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); |
153 | unsigned int n = d->hwirq; |
154 | |
155 | chip->g1_irq.masked &= ~(1 << n); |
156 | } |
157 | |
158 | static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) |
159 | { |
160 | unsigned int nhandled = 0; |
161 | unsigned int sub_irq; |
162 | unsigned int n; |
163 | u16 reg; |
164 | u16 ctl1; |
165 | int err; |
166 | |
167 | mv88e6xxx_reg_lock(chip); |
168 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, val: ®); |
169 | mv88e6xxx_reg_unlock(chip); |
170 | |
171 | if (err) |
172 | goto out; |
173 | |
174 | do { |
175 | for (n = 0; n < chip->g1_irq.nirqs; ++n) { |
176 | if (reg & (1 << n)) { |
177 | sub_irq = irq_find_mapping(domain: chip->g1_irq.domain, |
178 | hwirq: n); |
179 | handle_nested_irq(irq: sub_irq); |
180 | ++nhandled; |
181 | } |
182 | } |
183 | |
184 | mv88e6xxx_reg_lock(chip); |
185 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, val: &ctl1); |
186 | if (err) |
187 | goto unlock; |
188 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, val: ®); |
189 | unlock: |
190 | mv88e6xxx_reg_unlock(chip); |
191 | if (err) |
192 | goto out; |
193 | ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); |
194 | } while (reg & ctl1); |
195 | |
196 | out: |
197 | return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); |
198 | } |
199 | |
200 | static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) |
201 | { |
202 | struct mv88e6xxx_chip *chip = dev_id; |
203 | |
204 | return mv88e6xxx_g1_irq_thread_work(chip); |
205 | } |
206 | |
207 | static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) |
208 | { |
209 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); |
210 | |
211 | mv88e6xxx_reg_lock(chip); |
212 | } |
213 | |
214 | static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) |
215 | { |
216 | struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); |
217 | u16 mask = GENMASK(chip->g1_irq.nirqs, 0); |
218 | u16 reg; |
219 | int err; |
220 | |
221 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, val: ®); |
222 | if (err) |
223 | goto out; |
224 | |
225 | reg &= ~mask; |
226 | reg |= (~chip->g1_irq.masked & mask); |
227 | |
228 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val: reg); |
229 | if (err) |
230 | goto out; |
231 | |
232 | out: |
233 | mv88e6xxx_reg_unlock(chip); |
234 | } |
235 | |
236 | static const struct irq_chip mv88e6xxx_g1_irq_chip = { |
237 | .name = "mv88e6xxx-g1" , |
238 | .irq_mask = mv88e6xxx_g1_irq_mask, |
239 | .irq_unmask = mv88e6xxx_g1_irq_unmask, |
240 | .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, |
241 | .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, |
242 | }; |
243 | |
244 | static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, |
245 | unsigned int irq, |
246 | irq_hw_number_t hwirq) |
247 | { |
248 | struct mv88e6xxx_chip *chip = d->host_data; |
249 | |
250 | irq_set_chip_data(irq, data: d->host_data); |
251 | irq_set_chip_and_handler(irq, chip: &chip->g1_irq.chip, handle: handle_level_irq); |
252 | irq_set_noprobe(irq); |
253 | |
254 | return 0; |
255 | } |
256 | |
257 | static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { |
258 | .map = mv88e6xxx_g1_irq_domain_map, |
259 | .xlate = irq_domain_xlate_twocell, |
260 | }; |
261 | |
262 | /* To be called with reg_lock held */ |
263 | static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) |
264 | { |
265 | int irq, virq; |
266 | u16 mask; |
267 | |
268 | mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, val: &mask); |
269 | mask &= ~GENMASK(chip->g1_irq.nirqs, 0); |
270 | mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val: mask); |
271 | |
272 | for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { |
273 | virq = irq_find_mapping(domain: chip->g1_irq.domain, hwirq: irq); |
274 | irq_dispose_mapping(virq); |
275 | } |
276 | |
277 | irq_domain_remove(host: chip->g1_irq.domain); |
278 | } |
279 | |
280 | static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) |
281 | { |
282 | /* |
283 | * free_irq must be called without reg_lock taken because the irq |
284 | * handler takes this lock, too. |
285 | */ |
286 | free_irq(chip->irq, chip); |
287 | |
288 | mv88e6xxx_reg_lock(chip); |
289 | mv88e6xxx_g1_irq_free_common(chip); |
290 | mv88e6xxx_reg_unlock(chip); |
291 | } |
292 | |
293 | static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) |
294 | { |
295 | int err, irq, virq; |
296 | u16 reg, mask; |
297 | |
298 | chip->g1_irq.nirqs = chip->info->g1_irqs; |
299 | chip->g1_irq.domain = irq_domain_add_simple( |
300 | NULL, size: chip->g1_irq.nirqs, first_irq: 0, |
301 | ops: &mv88e6xxx_g1_irq_domain_ops, host_data: chip); |
302 | if (!chip->g1_irq.domain) |
303 | return -ENOMEM; |
304 | |
305 | for (irq = 0; irq < chip->g1_irq.nirqs; irq++) |
306 | irq_create_mapping(host: chip->g1_irq.domain, hwirq: irq); |
307 | |
308 | chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; |
309 | chip->g1_irq.masked = ~0; |
310 | |
311 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, val: &mask); |
312 | if (err) |
313 | goto out_mapping; |
314 | |
315 | mask &= ~GENMASK(chip->g1_irq.nirqs, 0); |
316 | |
317 | err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val: mask); |
318 | if (err) |
319 | goto out_disable; |
320 | |
321 | /* Reading the interrupt status clears (most of) them */ |
322 | err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, val: ®); |
323 | if (err) |
324 | goto out_disable; |
325 | |
326 | return 0; |
327 | |
328 | out_disable: |
329 | mask &= ~GENMASK(chip->g1_irq.nirqs, 0); |
330 | mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val: mask); |
331 | |
332 | out_mapping: |
333 | for (irq = 0; irq < 16; irq++) { |
334 | virq = irq_find_mapping(domain: chip->g1_irq.domain, hwirq: irq); |
335 | irq_dispose_mapping(virq); |
336 | } |
337 | |
338 | irq_domain_remove(host: chip->g1_irq.domain); |
339 | |
340 | return err; |
341 | } |
342 | |
343 | static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) |
344 | { |
345 | static struct lock_class_key lock_key; |
346 | static struct lock_class_key request_key; |
347 | int err; |
348 | |
349 | err = mv88e6xxx_g1_irq_setup_common(chip); |
350 | if (err) |
351 | return err; |
352 | |
353 | /* These lock classes tells lockdep that global 1 irqs are in |
354 | * a different category than their parent GPIO, so it won't |
355 | * report false recursion. |
356 | */ |
357 | irq_set_lockdep_class(irq: chip->irq, lock_class: &lock_key, request_class: &request_key); |
358 | |
359 | snprintf(buf: chip->irq_name, size: sizeof(chip->irq_name), |
360 | fmt: "mv88e6xxx-%s" , dev_name(dev: chip->dev)); |
361 | |
362 | mv88e6xxx_reg_unlock(chip); |
363 | err = request_threaded_irq(irq: chip->irq, NULL, |
364 | thread_fn: mv88e6xxx_g1_irq_thread_fn, |
365 | IRQF_ONESHOT | IRQF_SHARED, |
366 | name: chip->irq_name, dev: chip); |
367 | mv88e6xxx_reg_lock(chip); |
368 | if (err) |
369 | mv88e6xxx_g1_irq_free_common(chip); |
370 | |
371 | return err; |
372 | } |
373 | |
374 | static void mv88e6xxx_irq_poll(struct kthread_work *work) |
375 | { |
376 | struct mv88e6xxx_chip *chip = container_of(work, |
377 | struct mv88e6xxx_chip, |
378 | irq_poll_work.work); |
379 | mv88e6xxx_g1_irq_thread_work(chip); |
380 | |
381 | kthread_queue_delayed_work(worker: chip->kworker, dwork: &chip->irq_poll_work, |
382 | delay: msecs_to_jiffies(m: 100)); |
383 | } |
384 | |
385 | static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) |
386 | { |
387 | int err; |
388 | |
389 | err = mv88e6xxx_g1_irq_setup_common(chip); |
390 | if (err) |
391 | return err; |
392 | |
393 | kthread_init_delayed_work(&chip->irq_poll_work, |
394 | mv88e6xxx_irq_poll); |
395 | |
396 | chip->kworker = kthread_create_worker(flags: 0, namefmt: "%s" , dev_name(dev: chip->dev)); |
397 | if (IS_ERR(ptr: chip->kworker)) |
398 | return PTR_ERR(ptr: chip->kworker); |
399 | |
400 | kthread_queue_delayed_work(worker: chip->kworker, dwork: &chip->irq_poll_work, |
401 | delay: msecs_to_jiffies(m: 100)); |
402 | |
403 | return 0; |
404 | } |
405 | |
406 | static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) |
407 | { |
408 | kthread_cancel_delayed_work_sync(work: &chip->irq_poll_work); |
409 | kthread_destroy_worker(worker: chip->kworker); |
410 | |
411 | mv88e6xxx_reg_lock(chip); |
412 | mv88e6xxx_g1_irq_free_common(chip); |
413 | mv88e6xxx_reg_unlock(chip); |
414 | } |
415 | |
416 | static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, |
417 | int port, phy_interface_t interface) |
418 | { |
419 | int err; |
420 | |
421 | if (chip->info->ops->port_set_rgmii_delay) { |
422 | err = chip->info->ops->port_set_rgmii_delay(chip, port, |
423 | interface); |
424 | if (err && err != -EOPNOTSUPP) |
425 | return err; |
426 | } |
427 | |
428 | if (chip->info->ops->port_set_cmode) { |
429 | err = chip->info->ops->port_set_cmode(chip, port, |
430 | interface); |
431 | if (err && err != -EOPNOTSUPP) |
432 | return err; |
433 | } |
434 | |
435 | return 0; |
436 | } |
437 | |
438 | static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, |
439 | int link, int speed, int duplex, int pause, |
440 | phy_interface_t mode) |
441 | { |
442 | int err; |
443 | |
444 | if (!chip->info->ops->port_set_link) |
445 | return 0; |
446 | |
447 | /* Port's MAC control must not be changed unless the link is down */ |
448 | err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); |
449 | if (err) |
450 | return err; |
451 | |
452 | if (chip->info->ops->port_set_speed_duplex) { |
453 | err = chip->info->ops->port_set_speed_duplex(chip, port, |
454 | speed, duplex); |
455 | if (err && err != -EOPNOTSUPP) |
456 | goto restore_link; |
457 | } |
458 | |
459 | if (chip->info->ops->port_set_pause) { |
460 | err = chip->info->ops->port_set_pause(chip, port, pause); |
461 | if (err) |
462 | goto restore_link; |
463 | } |
464 | |
465 | err = mv88e6xxx_port_config_interface(chip, port, interface: mode); |
466 | restore_link: |
467 | if (chip->info->ops->port_set_link(chip, port, link)) |
468 | dev_err(chip->dev, "p%d: failed to restore MAC's link\n" , port); |
469 | |
470 | return err; |
471 | } |
472 | |
473 | static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) |
474 | { |
475 | return port >= chip->info->internal_phys_offset && |
476 | port < chip->info->num_internal_phys + |
477 | chip->info->internal_phys_offset; |
478 | } |
479 | |
480 | static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) |
481 | { |
482 | u16 reg; |
483 | int err; |
484 | |
485 | /* The 88e6250 family does not have the PHY detect bit. Instead, |
486 | * report whether the port is internal. |
487 | */ |
488 | if (chip->info->family == MV88E6XXX_FAMILY_6250) |
489 | return mv88e6xxx_phy_is_internal(chip, port); |
490 | |
491 | err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, val: ®); |
492 | if (err) { |
493 | dev_err(chip->dev, |
494 | "p%d: %s: failed to read port status\n" , |
495 | port, __func__); |
496 | return err; |
497 | } |
498 | |
499 | return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); |
500 | } |
501 | |
502 | static const u8 mv88e6185_phy_interface_modes[] = { |
503 | [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, |
504 | [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, |
505 | [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, |
506 | [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, |
507 | [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, |
508 | [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, |
509 | [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, |
510 | }; |
511 | |
512 | static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, |
513 | struct phylink_config *config) |
514 | { |
515 | u8 cmode = chip->ports[port].cmode; |
516 | |
517 | config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; |
518 | |
519 | if (mv88e6xxx_phy_is_internal(chip, port)) { |
520 | __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); |
521 | } else { |
522 | if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && |
523 | mv88e6185_phy_interface_modes[cmode]) |
524 | __set_bit(mv88e6185_phy_interface_modes[cmode], |
525 | config->supported_interfaces); |
526 | |
527 | config->mac_capabilities |= MAC_1000FD; |
528 | } |
529 | } |
530 | |
531 | static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, |
532 | struct phylink_config *config) |
533 | { |
534 | u8 cmode = chip->ports[port].cmode; |
535 | |
536 | if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && |
537 | mv88e6185_phy_interface_modes[cmode]) |
538 | __set_bit(mv88e6185_phy_interface_modes[cmode], |
539 | config->supported_interfaces); |
540 | |
541 | config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | |
542 | MAC_1000FD; |
543 | } |
544 | |
545 | static const u8 mv88e6xxx_phy_interface_modes[] = { |
546 | [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, |
547 | [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, |
548 | [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, |
549 | [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, |
550 | [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, |
551 | [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, |
552 | [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, |
553 | [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, |
554 | /* higher interface modes are not needed here, since ports supporting |
555 | * them are writable, and so the supported interfaces are filled in the |
556 | * corresponding .phylink_set_interfaces() implementation below |
557 | */ |
558 | }; |
559 | |
560 | static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) |
561 | { |
562 | if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && |
563 | mv88e6xxx_phy_interface_modes[cmode]) |
564 | __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); |
565 | else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) |
566 | phy_interface_set_rgmii(intf: supported); |
567 | } |
568 | |
569 | static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, |
570 | struct phylink_config *config) |
571 | { |
572 | unsigned long *supported = config->supported_interfaces; |
573 | |
574 | /* Translate the default cmode */ |
575 | mv88e6xxx_translate_cmode(cmode: chip->ports[port].cmode, supported); |
576 | |
577 | config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; |
578 | } |
579 | |
580 | static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, |
581 | struct phylink_config *config) |
582 | { |
583 | unsigned long *supported = config->supported_interfaces; |
584 | |
585 | /* Translate the default cmode */ |
586 | mv88e6xxx_translate_cmode(cmode: chip->ports[port].cmode, supported); |
587 | |
588 | config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | |
589 | MAC_1000FD; |
590 | } |
591 | |
592 | static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) |
593 | { |
594 | u16 reg, val; |
595 | int err; |
596 | |
597 | err = mv88e6xxx_port_read(chip, port: 4, MV88E6XXX_PORT_STS, val: ®); |
598 | if (err) |
599 | return err; |
600 | |
601 | /* If PHY_DETECT is zero, then we are not in auto-media mode */ |
602 | if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) |
603 | return 0xf; |
604 | |
605 | val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; |
606 | err = mv88e6xxx_port_write(chip, port: 4, MV88E6XXX_PORT_STS, val); |
607 | if (err) |
608 | return err; |
609 | |
610 | err = mv88e6xxx_port_read(chip, port: 4, MV88E6XXX_PORT_STS, val: &val); |
611 | if (err) |
612 | return err; |
613 | |
614 | /* Restore PHY_DETECT value */ |
615 | err = mv88e6xxx_port_write(chip, port: 4, MV88E6XXX_PORT_STS, val: reg); |
616 | if (err) |
617 | return err; |
618 | |
619 | return val & MV88E6XXX_PORT_STS_CMODE_MASK; |
620 | } |
621 | |
622 | static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, |
623 | struct phylink_config *config) |
624 | { |
625 | unsigned long *supported = config->supported_interfaces; |
626 | int err, cmode; |
627 | |
628 | /* Translate the default cmode */ |
629 | mv88e6xxx_translate_cmode(cmode: chip->ports[port].cmode, supported); |
630 | |
631 | config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | |
632 | MAC_1000FD; |
633 | |
634 | /* Port 4 supports automedia if the serdes is associated with it. */ |
635 | if (port == 4) { |
636 | err = mv88e6352_g2_scratch_port_has_serdes(chip, port); |
637 | if (err < 0) |
638 | dev_err(chip->dev, "p%d: failed to read scratch\n" , |
639 | port); |
640 | if (err <= 0) |
641 | return; |
642 | |
643 | cmode = mv88e6352_get_port4_serdes_cmode(chip); |
644 | if (cmode < 0) |
645 | dev_err(chip->dev, "p%d: failed to read serdes cmode\n" , |
646 | port); |
647 | else |
648 | mv88e6xxx_translate_cmode(cmode, supported); |
649 | } |
650 | } |
651 | |
652 | static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, |
653 | struct phylink_config *config) |
654 | { |
655 | unsigned long *supported = config->supported_interfaces; |
656 | |
657 | /* Translate the default cmode */ |
658 | mv88e6xxx_translate_cmode(cmode: chip->ports[port].cmode, supported); |
659 | |
660 | /* No ethtool bits for 200Mbps */ |
661 | config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | |
662 | MAC_1000FD; |
663 | |
664 | /* The C_Mode field is programmable on port 5 */ |
665 | if (port == 5) { |
666 | __set_bit(PHY_INTERFACE_MODE_SGMII, supported); |
667 | __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); |
668 | __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); |
669 | |
670 | config->mac_capabilities |= MAC_2500FD; |
671 | } |
672 | } |
673 | |
674 | static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, |
675 | struct phylink_config *config) |
676 | { |
677 | unsigned long *supported = config->supported_interfaces; |
678 | |
679 | /* Translate the default cmode */ |
680 | mv88e6xxx_translate_cmode(cmode: chip->ports[port].cmode, supported); |
681 | |
682 | /* No ethtool bits for 200Mbps */ |
683 | config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | |
684 | MAC_1000FD; |
685 | |
686 | /* The C_Mode field is programmable on ports 9 and 10 */ |
687 | if (port == 9 || port == 10) { |
688 | __set_bit(PHY_INTERFACE_MODE_SGMII, supported); |
689 | __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); |
690 | __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); |
691 | |
692 | config->mac_capabilities |= MAC_2500FD; |
693 | } |
694 | } |
695 | |
696 | static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, |
697 | struct phylink_config *config) |
698 | { |
699 | unsigned long *supported = config->supported_interfaces; |
700 | |
701 | mv88e6390_phylink_get_caps(chip, port, config); |
702 | |
703 | /* For the 6x90X, ports 2-7 can be in automedia mode. |
704 | * (Note that 6x90 doesn't support RXAUI nor XAUI). |
705 | * |
706 | * Port 2 can also support 1000BASE-X in automedia mode if port 9 is |
707 | * configured for 1000BASE-X, SGMII or 2500BASE-X. |
708 | * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is |
709 | * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. |
710 | * |
711 | * Port 5 can also support 1000BASE-X in automedia mode if port 10 is |
712 | * configured for 1000BASE-X, SGMII or 2500BASE-X. |
713 | * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is |
714 | * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. |
715 | * |
716 | * For now, be permissive (as the old code was) and allow 1000BASE-X |
717 | * on ports 2..7. |
718 | */ |
719 | if (port >= 2 && port <= 7) |
720 | __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); |
721 | |
722 | /* The C_Mode field can also be programmed for 10G speeds */ |
723 | if (port == 9 || port == 10) { |
724 | __set_bit(PHY_INTERFACE_MODE_XAUI, supported); |
725 | __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); |
726 | |
727 | config->mac_capabilities |= MAC_10000FD; |
728 | } |
729 | } |
730 | |
731 | static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, |
732 | struct phylink_config *config) |
733 | { |
734 | unsigned long *supported = config->supported_interfaces; |
735 | bool is_6191x = |
736 | chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; |
737 | bool is_6361 = |
738 | chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; |
739 | |
740 | mv88e6xxx_translate_cmode(cmode: chip->ports[port].cmode, supported); |
741 | |
742 | config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | |
743 | MAC_1000FD; |
744 | |
745 | /* The C_Mode field can be programmed for ports 0, 9 and 10 */ |
746 | if (port == 0 || port == 9 || port == 10) { |
747 | __set_bit(PHY_INTERFACE_MODE_SGMII, supported); |
748 | __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); |
749 | |
750 | /* 6191X supports >1G modes only on port 10 */ |
751 | if (!is_6191x || port == 10) { |
752 | __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); |
753 | config->mac_capabilities |= MAC_2500FD; |
754 | |
755 | /* 6361 only supports up to 2500BaseX */ |
756 | if (!is_6361) { |
757 | __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); |
758 | __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); |
759 | __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); |
760 | config->mac_capabilities |= MAC_5000FD | |
761 | MAC_10000FD; |
762 | } |
763 | } |
764 | } |
765 | |
766 | if (port == 0) { |
767 | __set_bit(PHY_INTERFACE_MODE_RMII, supported); |
768 | __set_bit(PHY_INTERFACE_MODE_RGMII, supported); |
769 | __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); |
770 | __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); |
771 | __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); |
772 | } |
773 | } |
774 | |
775 | static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, |
776 | struct phylink_config *config) |
777 | { |
778 | struct mv88e6xxx_chip *chip = ds->priv; |
779 | |
780 | mv88e6xxx_reg_lock(chip); |
781 | chip->info->ops->phylink_get_caps(chip, port, config); |
782 | mv88e6xxx_reg_unlock(chip); |
783 | |
784 | if (mv88e6xxx_phy_is_internal(chip, port)) { |
785 | __set_bit(PHY_INTERFACE_MODE_INTERNAL, |
786 | config->supported_interfaces); |
787 | /* Internal ports with no phy-mode need GMII for PHYLIB */ |
788 | __set_bit(PHY_INTERFACE_MODE_GMII, |
789 | config->supported_interfaces); |
790 | } |
791 | } |
792 | |
793 | static struct phylink_pcs *mv88e6xxx_mac_select_pcs(struct dsa_switch *ds, |
794 | int port, |
795 | phy_interface_t interface) |
796 | { |
797 | struct mv88e6xxx_chip *chip = ds->priv; |
798 | struct phylink_pcs *pcs = ERR_PTR(error: -EOPNOTSUPP); |
799 | |
800 | if (chip->info->ops->pcs_ops) |
801 | pcs = chip->info->ops->pcs_ops->pcs_select(chip, port, |
802 | interface); |
803 | |
804 | return pcs; |
805 | } |
806 | |
807 | static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port, |
808 | unsigned int mode, phy_interface_t interface) |
809 | { |
810 | struct mv88e6xxx_chip *chip = ds->priv; |
811 | int err = 0; |
812 | |
813 | /* In inband mode, the link may come up at any time while the link |
814 | * is not forced down. Force the link down while we reconfigure the |
815 | * interface mode. |
816 | */ |
817 | if (mode == MLO_AN_INBAND && |
818 | chip->ports[port].interface != interface && |
819 | chip->info->ops->port_set_link) { |
820 | mv88e6xxx_reg_lock(chip); |
821 | err = chip->info->ops->port_set_link(chip, port, |
822 | LINK_FORCED_DOWN); |
823 | mv88e6xxx_reg_unlock(chip); |
824 | } |
825 | |
826 | return err; |
827 | } |
828 | |
829 | static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, |
830 | unsigned int mode, |
831 | const struct phylink_link_state *state) |
832 | { |
833 | struct mv88e6xxx_chip *chip = ds->priv; |
834 | int err = 0; |
835 | |
836 | mv88e6xxx_reg_lock(chip); |
837 | |
838 | if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { |
839 | err = mv88e6xxx_port_config_interface(chip, port, |
840 | interface: state->interface); |
841 | if (err && err != -EOPNOTSUPP) |
842 | goto err_unlock; |
843 | } |
844 | |
845 | err_unlock: |
846 | mv88e6xxx_reg_unlock(chip); |
847 | |
848 | if (err && err != -EOPNOTSUPP) |
849 | dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n" , port); |
850 | } |
851 | |
852 | static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port, |
853 | unsigned int mode, phy_interface_t interface) |
854 | { |
855 | struct mv88e6xxx_chip *chip = ds->priv; |
856 | int err = 0; |
857 | |
858 | /* Undo the forced down state above after completing configuration |
859 | * irrespective of its state on entry, which allows the link to come |
860 | * up in the in-band case where there is no separate SERDES. Also |
861 | * ensure that the link can come up if the PPU is in use and we are |
862 | * in PHY mode (we treat the PPU as an effective in-band mechanism.) |
863 | */ |
864 | mv88e6xxx_reg_lock(chip); |
865 | |
866 | if (chip->info->ops->port_set_link && |
867 | ((mode == MLO_AN_INBAND && |
868 | chip->ports[port].interface != interface) || |
869 | (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) |
870 | err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); |
871 | |
872 | mv88e6xxx_reg_unlock(chip); |
873 | |
874 | chip->ports[port].interface = interface; |
875 | |
876 | return err; |
877 | } |
878 | |
879 | static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, |
880 | unsigned int mode, |
881 | phy_interface_t interface) |
882 | { |
883 | struct mv88e6xxx_chip *chip = ds->priv; |
884 | const struct mv88e6xxx_ops *ops; |
885 | int err = 0; |
886 | |
887 | ops = chip->info->ops; |
888 | |
889 | mv88e6xxx_reg_lock(chip); |
890 | /* Force the link down if we know the port may not be automatically |
891 | * updated by the switch or if we are using fixed-link mode. |
892 | */ |
893 | if ((!mv88e6xxx_port_ppu_updates(chip, port) || |
894 | mode == MLO_AN_FIXED) && ops->port_sync_link) |
895 | err = ops->port_sync_link(chip, port, mode, false); |
896 | |
897 | if (!err && ops->port_set_speed_duplex) |
898 | err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, |
899 | DUPLEX_UNFORCED); |
900 | mv88e6xxx_reg_unlock(chip); |
901 | |
902 | if (err) |
903 | dev_err(chip->dev, |
904 | "p%d: failed to force MAC link down\n" , port); |
905 | } |
906 | |
907 | static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, |
908 | unsigned int mode, phy_interface_t interface, |
909 | struct phy_device *phydev, |
910 | int speed, int duplex, |
911 | bool tx_pause, bool rx_pause) |
912 | { |
913 | struct mv88e6xxx_chip *chip = ds->priv; |
914 | const struct mv88e6xxx_ops *ops; |
915 | int err = 0; |
916 | |
917 | ops = chip->info->ops; |
918 | |
919 | mv88e6xxx_reg_lock(chip); |
920 | /* Configure and force the link up if we know that the port may not |
921 | * automatically updated by the switch or if we are using fixed-link |
922 | * mode. |
923 | */ |
924 | if (!mv88e6xxx_port_ppu_updates(chip, port) || |
925 | mode == MLO_AN_FIXED) { |
926 | if (ops->port_set_speed_duplex) { |
927 | err = ops->port_set_speed_duplex(chip, port, |
928 | speed, duplex); |
929 | if (err && err != -EOPNOTSUPP) |
930 | goto error; |
931 | } |
932 | |
933 | if (ops->port_sync_link) |
934 | err = ops->port_sync_link(chip, port, mode, true); |
935 | } |
936 | error: |
937 | mv88e6xxx_reg_unlock(chip); |
938 | |
939 | if (err && err != -EOPNOTSUPP) |
940 | dev_err(ds->dev, |
941 | "p%d: failed to configure MAC link up\n" , port); |
942 | } |
943 | |
944 | static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) |
945 | { |
946 | int err; |
947 | |
948 | if (!chip->info->ops->stats_snapshot) |
949 | return -EOPNOTSUPP; |
950 | |
951 | mv88e6xxx_reg_lock(chip); |
952 | err = chip->info->ops->stats_snapshot(chip, port); |
953 | mv88e6xxx_reg_unlock(chip); |
954 | |
955 | return err; |
956 | } |
957 | |
958 | #define MV88E6XXX_HW_STAT_MAPPER(_fn) \ |
959 | _fn(in_good_octets, 8, 0x00, STATS_TYPE_BANK0), \ |
960 | _fn(in_bad_octets, 4, 0x02, STATS_TYPE_BANK0), \ |
961 | _fn(in_unicast, 4, 0x04, STATS_TYPE_BANK0), \ |
962 | _fn(in_broadcasts, 4, 0x06, STATS_TYPE_BANK0), \ |
963 | _fn(in_multicasts, 4, 0x07, STATS_TYPE_BANK0), \ |
964 | _fn(in_pause, 4, 0x16, STATS_TYPE_BANK0), \ |
965 | _fn(in_undersize, 4, 0x18, STATS_TYPE_BANK0), \ |
966 | _fn(in_fragments, 4, 0x19, STATS_TYPE_BANK0), \ |
967 | _fn(in_oversize, 4, 0x1a, STATS_TYPE_BANK0), \ |
968 | _fn(in_jabber, 4, 0x1b, STATS_TYPE_BANK0), \ |
969 | _fn(in_rx_error, 4, 0x1c, STATS_TYPE_BANK0), \ |
970 | _fn(in_fcs_error, 4, 0x1d, STATS_TYPE_BANK0), \ |
971 | _fn(out_octets, 8, 0x0e, STATS_TYPE_BANK0), \ |
972 | _fn(out_unicast, 4, 0x10, STATS_TYPE_BANK0), \ |
973 | _fn(out_broadcasts, 4, 0x13, STATS_TYPE_BANK0), \ |
974 | _fn(out_multicasts, 4, 0x12, STATS_TYPE_BANK0), \ |
975 | _fn(out_pause, 4, 0x15, STATS_TYPE_BANK0), \ |
976 | _fn(excessive, 4, 0x11, STATS_TYPE_BANK0), \ |
977 | _fn(collisions, 4, 0x1e, STATS_TYPE_BANK0), \ |
978 | _fn(deferred, 4, 0x05, STATS_TYPE_BANK0), \ |
979 | _fn(single, 4, 0x14, STATS_TYPE_BANK0), \ |
980 | _fn(multiple, 4, 0x17, STATS_TYPE_BANK0), \ |
981 | _fn(out_fcs_error, 4, 0x03, STATS_TYPE_BANK0), \ |
982 | _fn(late, 4, 0x1f, STATS_TYPE_BANK0), \ |
983 | _fn(hist_64bytes, 4, 0x08, STATS_TYPE_BANK0), \ |
984 | _fn(hist_65_127bytes, 4, 0x09, STATS_TYPE_BANK0), \ |
985 | _fn(hist_128_255bytes, 4, 0x0a, STATS_TYPE_BANK0), \ |
986 | _fn(hist_256_511bytes, 4, 0x0b, STATS_TYPE_BANK0), \ |
987 | _fn(hist_512_1023bytes, 4, 0x0c, STATS_TYPE_BANK0), \ |
988 | _fn(hist_1024_max_bytes, 4, 0x0d, STATS_TYPE_BANK0), \ |
989 | _fn(sw_in_discards, 4, 0x10, STATS_TYPE_PORT), \ |
990 | _fn(sw_in_filtered, 2, 0x12, STATS_TYPE_PORT), \ |
991 | _fn(sw_out_filtered, 2, 0x13, STATS_TYPE_PORT), \ |
992 | _fn(in_discards, 4, 0x00, STATS_TYPE_BANK1), \ |
993 | _fn(in_filtered, 4, 0x01, STATS_TYPE_BANK1), \ |
994 | _fn(in_accepted, 4, 0x02, STATS_TYPE_BANK1), \ |
995 | _fn(in_bad_accepted, 4, 0x03, STATS_TYPE_BANK1), \ |
996 | _fn(in_good_avb_class_a, 4, 0x04, STATS_TYPE_BANK1), \ |
997 | _fn(in_good_avb_class_b, 4, 0x05, STATS_TYPE_BANK1), \ |
998 | _fn(in_bad_avb_class_a, 4, 0x06, STATS_TYPE_BANK1), \ |
999 | _fn(in_bad_avb_class_b, 4, 0x07, STATS_TYPE_BANK1), \ |
1000 | _fn(tcam_counter_0, 4, 0x08, STATS_TYPE_BANK1), \ |
1001 | _fn(tcam_counter_1, 4, 0x09, STATS_TYPE_BANK1), \ |
1002 | _fn(tcam_counter_2, 4, 0x0a, STATS_TYPE_BANK1), \ |
1003 | _fn(tcam_counter_3, 4, 0x0b, STATS_TYPE_BANK1), \ |
1004 | _fn(in_da_unknown, 4, 0x0e, STATS_TYPE_BANK1), \ |
1005 | _fn(in_management, 4, 0x0f, STATS_TYPE_BANK1), \ |
1006 | _fn(out_queue_0, 4, 0x10, STATS_TYPE_BANK1), \ |
1007 | _fn(out_queue_1, 4, 0x11, STATS_TYPE_BANK1), \ |
1008 | _fn(out_queue_2, 4, 0x12, STATS_TYPE_BANK1), \ |
1009 | _fn(out_queue_3, 4, 0x13, STATS_TYPE_BANK1), \ |
1010 | _fn(out_queue_4, 4, 0x14, STATS_TYPE_BANK1), \ |
1011 | _fn(out_queue_5, 4, 0x15, STATS_TYPE_BANK1), \ |
1012 | _fn(out_queue_6, 4, 0x16, STATS_TYPE_BANK1), \ |
1013 | _fn(out_queue_7, 4, 0x17, STATS_TYPE_BANK1), \ |
1014 | _fn(out_cut_through, 4, 0x18, STATS_TYPE_BANK1), \ |
1015 | _fn(out_octets_a, 4, 0x1a, STATS_TYPE_BANK1), \ |
1016 | _fn(out_octets_b, 4, 0x1b, STATS_TYPE_BANK1), \ |
1017 | _fn(out_management, 4, 0x1f, STATS_TYPE_BANK1), \ |
1018 | /* */ |
1019 | |
1020 | #define MV88E6XXX_HW_STAT_ENTRY(_string, _size, _reg, _type) \ |
1021 | { #_string, _size, _reg, _type } |
1022 | static const struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
1023 | MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENTRY) |
1024 | }; |
1025 | |
1026 | #define MV88E6XXX_HW_STAT_ENUM(_string, _size, _reg, _type) \ |
1027 | MV88E6XXX_HW_STAT_ID_ ## _string |
1028 | enum mv88e6xxx_hw_stat_id { |
1029 | MV88E6XXX_HW_STAT_MAPPER(MV88E6XXX_HW_STAT_ENUM) |
1030 | }; |
1031 | |
1032 | static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, |
1033 | const struct mv88e6xxx_hw_stat *s, |
1034 | int port, u16 bank1_select, |
1035 | u16 histogram) |
1036 | { |
1037 | u32 low; |
1038 | u32 high = 0; |
1039 | u16 reg = 0; |
1040 | int err; |
1041 | u64 value; |
1042 | |
1043 | switch (s->type) { |
1044 | case STATS_TYPE_PORT: |
1045 | err = mv88e6xxx_port_read(chip, port, reg: s->reg, val: ®); |
1046 | if (err) |
1047 | return U64_MAX; |
1048 | |
1049 | low = reg; |
1050 | if (s->size == 4) { |
1051 | err = mv88e6xxx_port_read(chip, port, reg: s->reg + 1, val: ®); |
1052 | if (err) |
1053 | return U64_MAX; |
1054 | low |= ((u32)reg) << 16; |
1055 | } |
1056 | break; |
1057 | case STATS_TYPE_BANK1: |
1058 | reg = bank1_select; |
1059 | fallthrough; |
1060 | case STATS_TYPE_BANK0: |
1061 | reg |= s->reg | histogram; |
1062 | mv88e6xxx_g1_stats_read(chip, stat: reg, val: &low); |
1063 | if (s->size == 8) |
1064 | mv88e6xxx_g1_stats_read(chip, stat: reg + 1, val: &high); |
1065 | break; |
1066 | default: |
1067 | return U64_MAX; |
1068 | } |
1069 | value = (((u64)high) << 32) | low; |
1070 | return value; |
1071 | } |
1072 | |
1073 | static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, |
1074 | uint8_t *data, int types) |
1075 | { |
1076 | const struct mv88e6xxx_hw_stat *stat; |
1077 | int i, j; |
1078 | |
1079 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
1080 | stat = &mv88e6xxx_hw_stats[i]; |
1081 | if (stat->type & types) { |
1082 | memcpy(data + j * ETH_GSTRING_LEN, stat->string, |
1083 | ETH_GSTRING_LEN); |
1084 | j++; |
1085 | } |
1086 | } |
1087 | |
1088 | return j; |
1089 | } |
1090 | |
1091 | static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, |
1092 | uint8_t *data) |
1093 | { |
1094 | return mv88e6xxx_stats_get_strings(chip, data, |
1095 | STATS_TYPE_BANK0 | STATS_TYPE_PORT); |
1096 | } |
1097 | |
1098 | static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, |
1099 | uint8_t *data) |
1100 | { |
1101 | return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); |
1102 | } |
1103 | |
1104 | static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, |
1105 | uint8_t *data) |
1106 | { |
1107 | return mv88e6xxx_stats_get_strings(chip, data, |
1108 | STATS_TYPE_BANK0 | STATS_TYPE_BANK1); |
1109 | } |
1110 | |
1111 | static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { |
1112 | "atu_member_violation" , |
1113 | "atu_miss_violation" , |
1114 | "atu_full_violation" , |
1115 | "vtu_member_violation" , |
1116 | "vtu_miss_violation" , |
1117 | }; |
1118 | |
1119 | static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) |
1120 | { |
1121 | unsigned int i; |
1122 | |
1123 | for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) |
1124 | strscpy(data + i * ETH_GSTRING_LEN, |
1125 | mv88e6xxx_atu_vtu_stats_strings[i], |
1126 | ETH_GSTRING_LEN); |
1127 | } |
1128 | |
1129 | static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, |
1130 | u32 stringset, uint8_t *data) |
1131 | { |
1132 | struct mv88e6xxx_chip *chip = ds->priv; |
1133 | int count = 0; |
1134 | |
1135 | if (stringset != ETH_SS_STATS) |
1136 | return; |
1137 | |
1138 | mv88e6xxx_reg_lock(chip); |
1139 | |
1140 | if (chip->info->ops->stats_get_strings) |
1141 | count = chip->info->ops->stats_get_strings(chip, data); |
1142 | |
1143 | if (chip->info->ops->serdes_get_strings) { |
1144 | data += count * ETH_GSTRING_LEN; |
1145 | count = chip->info->ops->serdes_get_strings(chip, port, data); |
1146 | } |
1147 | |
1148 | data += count * ETH_GSTRING_LEN; |
1149 | mv88e6xxx_atu_vtu_get_strings(data); |
1150 | |
1151 | mv88e6xxx_reg_unlock(chip); |
1152 | } |
1153 | |
1154 | static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, |
1155 | int types) |
1156 | { |
1157 | const struct mv88e6xxx_hw_stat *stat; |
1158 | int i, j; |
1159 | |
1160 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
1161 | stat = &mv88e6xxx_hw_stats[i]; |
1162 | if (stat->type & types) |
1163 | j++; |
1164 | } |
1165 | return j; |
1166 | } |
1167 | |
1168 | static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) |
1169 | { |
1170 | return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | |
1171 | STATS_TYPE_PORT); |
1172 | } |
1173 | |
1174 | static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) |
1175 | { |
1176 | return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); |
1177 | } |
1178 | |
1179 | static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) |
1180 | { |
1181 | return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | |
1182 | STATS_TYPE_BANK1); |
1183 | } |
1184 | |
1185 | static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) |
1186 | { |
1187 | struct mv88e6xxx_chip *chip = ds->priv; |
1188 | int serdes_count = 0; |
1189 | int count = 0; |
1190 | |
1191 | if (sset != ETH_SS_STATS) |
1192 | return 0; |
1193 | |
1194 | mv88e6xxx_reg_lock(chip); |
1195 | if (chip->info->ops->stats_get_sset_count) |
1196 | count = chip->info->ops->stats_get_sset_count(chip); |
1197 | if (count < 0) |
1198 | goto out; |
1199 | |
1200 | if (chip->info->ops->serdes_get_sset_count) |
1201 | serdes_count = chip->info->ops->serdes_get_sset_count(chip, |
1202 | port); |
1203 | if (serdes_count < 0) { |
1204 | count = serdes_count; |
1205 | goto out; |
1206 | } |
1207 | count += serdes_count; |
1208 | count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); |
1209 | |
1210 | out: |
1211 | mv88e6xxx_reg_unlock(chip); |
1212 | |
1213 | return count; |
1214 | } |
1215 | |
1216 | static size_t mv88e6095_stats_get_stat(struct mv88e6xxx_chip *chip, int port, |
1217 | const struct mv88e6xxx_hw_stat *stat, |
1218 | uint64_t *data) |
1219 | { |
1220 | if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_PORT))) |
1221 | return 0; |
1222 | |
1223 | *data = _mv88e6xxx_get_ethtool_stat(chip, s: stat, port, bank1_select: 0, |
1224 | MV88E6XXX_G1_STATS_OP_HIST_RX); |
1225 | return 1; |
1226 | } |
1227 | |
1228 | static size_t mv88e6250_stats_get_stat(struct mv88e6xxx_chip *chip, int port, |
1229 | const struct mv88e6xxx_hw_stat *stat, |
1230 | uint64_t *data) |
1231 | { |
1232 | if (!(stat->type & STATS_TYPE_BANK0)) |
1233 | return 0; |
1234 | |
1235 | *data = _mv88e6xxx_get_ethtool_stat(chip, s: stat, port, bank1_select: 0, |
1236 | MV88E6XXX_G1_STATS_OP_HIST_RX); |
1237 | return 1; |
1238 | } |
1239 | |
1240 | static size_t mv88e6320_stats_get_stat(struct mv88e6xxx_chip *chip, int port, |
1241 | const struct mv88e6xxx_hw_stat *stat, |
1242 | uint64_t *data) |
1243 | { |
1244 | if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1))) |
1245 | return 0; |
1246 | |
1247 | *data = _mv88e6xxx_get_ethtool_stat(chip, s: stat, port, |
1248 | MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, |
1249 | MV88E6XXX_G1_STATS_OP_HIST_RX); |
1250 | return 1; |
1251 | } |
1252 | |
1253 | static size_t mv88e6390_stats_get_stat(struct mv88e6xxx_chip *chip, int port, |
1254 | const struct mv88e6xxx_hw_stat *stat, |
1255 | uint64_t *data) |
1256 | { |
1257 | if (!(stat->type & (STATS_TYPE_BANK0 | STATS_TYPE_BANK1))) |
1258 | return 0; |
1259 | |
1260 | *data = _mv88e6xxx_get_ethtool_stat(chip, s: stat, port, |
1261 | MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, |
1262 | histogram: 0); |
1263 | return 1; |
1264 | } |
1265 | |
1266 | static size_t mv88e6xxx_stats_get_stat(struct mv88e6xxx_chip *chip, int port, |
1267 | const struct mv88e6xxx_hw_stat *stat, |
1268 | uint64_t *data) |
1269 | { |
1270 | int ret = 0; |
1271 | |
1272 | if (chip->info->ops->stats_get_stat) { |
1273 | mv88e6xxx_reg_lock(chip); |
1274 | ret = chip->info->ops->stats_get_stat(chip, port, stat, data); |
1275 | mv88e6xxx_reg_unlock(chip); |
1276 | } |
1277 | |
1278 | return ret; |
1279 | } |
1280 | |
1281 | static size_t mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, |
1282 | uint64_t *data) |
1283 | { |
1284 | const struct mv88e6xxx_hw_stat *stat; |
1285 | size_t i, j; |
1286 | |
1287 | for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { |
1288 | stat = &mv88e6xxx_hw_stats[i]; |
1289 | j += mv88e6xxx_stats_get_stat(chip, port, stat, data: &data[j]); |
1290 | } |
1291 | return j; |
1292 | } |
1293 | |
1294 | static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, |
1295 | uint64_t *data) |
1296 | { |
1297 | *data++ = chip->ports[port].atu_member_violation; |
1298 | *data++ = chip->ports[port].atu_miss_violation; |
1299 | *data++ = chip->ports[port].atu_full_violation; |
1300 | *data++ = chip->ports[port].vtu_member_violation; |
1301 | *data++ = chip->ports[port].vtu_miss_violation; |
1302 | } |
1303 | |
1304 | static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, |
1305 | uint64_t *data) |
1306 | { |
1307 | size_t count; |
1308 | |
1309 | count = mv88e6xxx_stats_get_stats(chip, port, data); |
1310 | |
1311 | mv88e6xxx_reg_lock(chip); |
1312 | if (chip->info->ops->serdes_get_stats) { |
1313 | data += count; |
1314 | count = chip->info->ops->serdes_get_stats(chip, port, data); |
1315 | } |
1316 | data += count; |
1317 | mv88e6xxx_atu_vtu_get_stats(chip, port, data); |
1318 | mv88e6xxx_reg_unlock(chip); |
1319 | } |
1320 | |
1321 | static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, |
1322 | uint64_t *data) |
1323 | { |
1324 | struct mv88e6xxx_chip *chip = ds->priv; |
1325 | int ret; |
1326 | |
1327 | ret = mv88e6xxx_stats_snapshot(chip, port); |
1328 | if (ret < 0) |
1329 | return; |
1330 | |
1331 | mv88e6xxx_get_stats(chip, port, data); |
1332 | } |
1333 | |
1334 | static void mv88e6xxx_get_eth_mac_stats(struct dsa_switch *ds, int port, |
1335 | struct ethtool_eth_mac_stats *mac_stats) |
1336 | { |
1337 | struct mv88e6xxx_chip *chip = ds->priv; |
1338 | int ret; |
1339 | |
1340 | ret = mv88e6xxx_stats_snapshot(chip, port); |
1341 | if (ret < 0) |
1342 | return; |
1343 | |
1344 | #define MV88E6XXX_ETH_MAC_STAT_MAP(_id, _member) \ |
1345 | mv88e6xxx_stats_get_stat(chip, port, \ |
1346 | &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ |
1347 | &mac_stats->stats._member) |
1348 | |
1349 | MV88E6XXX_ETH_MAC_STAT_MAP(out_unicast, FramesTransmittedOK); |
1350 | MV88E6XXX_ETH_MAC_STAT_MAP(single, SingleCollisionFrames); |
1351 | MV88E6XXX_ETH_MAC_STAT_MAP(multiple, MultipleCollisionFrames); |
1352 | MV88E6XXX_ETH_MAC_STAT_MAP(in_unicast, FramesReceivedOK); |
1353 | MV88E6XXX_ETH_MAC_STAT_MAP(in_fcs_error, FrameCheckSequenceErrors); |
1354 | MV88E6XXX_ETH_MAC_STAT_MAP(out_octets, OctetsTransmittedOK); |
1355 | MV88E6XXX_ETH_MAC_STAT_MAP(deferred, FramesWithDeferredXmissions); |
1356 | MV88E6XXX_ETH_MAC_STAT_MAP(late, LateCollisions); |
1357 | MV88E6XXX_ETH_MAC_STAT_MAP(in_good_octets, OctetsReceivedOK); |
1358 | MV88E6XXX_ETH_MAC_STAT_MAP(out_multicasts, MulticastFramesXmittedOK); |
1359 | MV88E6XXX_ETH_MAC_STAT_MAP(out_broadcasts, BroadcastFramesXmittedOK); |
1360 | MV88E6XXX_ETH_MAC_STAT_MAP(excessive, FramesWithExcessiveDeferral); |
1361 | MV88E6XXX_ETH_MAC_STAT_MAP(in_multicasts, MulticastFramesReceivedOK); |
1362 | MV88E6XXX_ETH_MAC_STAT_MAP(in_broadcasts, BroadcastFramesReceivedOK); |
1363 | |
1364 | #undef MV88E6XXX_ETH_MAC_STAT_MAP |
1365 | |
1366 | mac_stats->stats.FramesTransmittedOK += mac_stats->stats.MulticastFramesXmittedOK; |
1367 | mac_stats->stats.FramesTransmittedOK += mac_stats->stats.BroadcastFramesXmittedOK; |
1368 | mac_stats->stats.FramesReceivedOK += mac_stats->stats.MulticastFramesReceivedOK; |
1369 | mac_stats->stats.FramesReceivedOK += mac_stats->stats.BroadcastFramesReceivedOK; |
1370 | } |
1371 | |
1372 | static void mv88e6xxx_get_rmon_stats(struct dsa_switch *ds, int port, |
1373 | struct ethtool_rmon_stats *rmon_stats, |
1374 | const struct ethtool_rmon_hist_range **ranges) |
1375 | { |
1376 | static const struct ethtool_rmon_hist_range rmon_ranges[] = { |
1377 | { 64, 64 }, |
1378 | { 65, 127 }, |
1379 | { 128, 255 }, |
1380 | { 256, 511 }, |
1381 | { 512, 1023 }, |
1382 | { 1024, 65535 }, |
1383 | {} |
1384 | }; |
1385 | struct mv88e6xxx_chip *chip = ds->priv; |
1386 | int ret; |
1387 | |
1388 | ret = mv88e6xxx_stats_snapshot(chip, port); |
1389 | if (ret < 0) |
1390 | return; |
1391 | |
1392 | #define MV88E6XXX_RMON_STAT_MAP(_id, _member) \ |
1393 | mv88e6xxx_stats_get_stat(chip, port, \ |
1394 | &mv88e6xxx_hw_stats[MV88E6XXX_HW_STAT_ID_ ## _id], \ |
1395 | &rmon_stats->stats._member) |
1396 | |
1397 | MV88E6XXX_RMON_STAT_MAP(in_undersize, undersize_pkts); |
1398 | MV88E6XXX_RMON_STAT_MAP(in_oversize, oversize_pkts); |
1399 | MV88E6XXX_RMON_STAT_MAP(in_fragments, fragments); |
1400 | MV88E6XXX_RMON_STAT_MAP(in_jabber, jabbers); |
1401 | MV88E6XXX_RMON_STAT_MAP(hist_64bytes, hist[0]); |
1402 | MV88E6XXX_RMON_STAT_MAP(hist_65_127bytes, hist[1]); |
1403 | MV88E6XXX_RMON_STAT_MAP(hist_128_255bytes, hist[2]); |
1404 | MV88E6XXX_RMON_STAT_MAP(hist_256_511bytes, hist[3]); |
1405 | MV88E6XXX_RMON_STAT_MAP(hist_512_1023bytes, hist[4]); |
1406 | MV88E6XXX_RMON_STAT_MAP(hist_1024_max_bytes, hist[5]); |
1407 | |
1408 | #undef MV88E6XXX_RMON_STAT_MAP |
1409 | |
1410 | *ranges = rmon_ranges; |
1411 | } |
1412 | |
1413 | static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
1414 | { |
1415 | struct mv88e6xxx_chip *chip = ds->priv; |
1416 | int len; |
1417 | |
1418 | len = 32 * sizeof(u16); |
1419 | if (chip->info->ops->serdes_get_regs_len) |
1420 | len += chip->info->ops->serdes_get_regs_len(chip, port); |
1421 | |
1422 | return len; |
1423 | } |
1424 | |
1425 | static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, |
1426 | struct ethtool_regs *regs, void *_p) |
1427 | { |
1428 | struct mv88e6xxx_chip *chip = ds->priv; |
1429 | int err; |
1430 | u16 reg; |
1431 | u16 *p = _p; |
1432 | int i; |
1433 | |
1434 | regs->version = chip->info->prod_num; |
1435 | |
1436 | memset(p, 0xff, 32 * sizeof(u16)); |
1437 | |
1438 | mv88e6xxx_reg_lock(chip); |
1439 | |
1440 | for (i = 0; i < 32; i++) { |
1441 | |
1442 | err = mv88e6xxx_port_read(chip, port, reg: i, val: ®); |
1443 | if (!err) |
1444 | p[i] = reg; |
1445 | } |
1446 | |
1447 | if (chip->info->ops->serdes_get_regs) |
1448 | chip->info->ops->serdes_get_regs(chip, port, &p[i]); |
1449 | |
1450 | mv88e6xxx_reg_unlock(chip); |
1451 | } |
1452 | |
1453 | static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, |
1454 | struct ethtool_keee *e) |
1455 | { |
1456 | /* Nothing to do on the port's MAC */ |
1457 | return 0; |
1458 | } |
1459 | |
1460 | static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, |
1461 | struct ethtool_keee *e) |
1462 | { |
1463 | /* Nothing to do on the port's MAC */ |
1464 | return 0; |
1465 | } |
1466 | |
1467 | /* Mask of the local ports allowed to receive frames from a given fabric port */ |
1468 | static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) |
1469 | { |
1470 | struct dsa_switch *ds = chip->ds; |
1471 | struct dsa_switch_tree *dst = ds->dst; |
1472 | struct dsa_port *dp, *other_dp; |
1473 | bool found = false; |
1474 | u16 pvlan; |
1475 | |
1476 | /* dev is a physical switch */ |
1477 | if (dev <= dst->last_switch) { |
1478 | list_for_each_entry(dp, &dst->ports, list) { |
1479 | if (dp->ds->index == dev && dp->index == port) { |
1480 | /* dp might be a DSA link or a user port, so it |
1481 | * might or might not have a bridge. |
1482 | * Use the "found" variable for both cases. |
1483 | */ |
1484 | found = true; |
1485 | break; |
1486 | } |
1487 | } |
1488 | /* dev is a virtual bridge */ |
1489 | } else { |
1490 | list_for_each_entry(dp, &dst->ports, list) { |
1491 | unsigned int bridge_num = dsa_port_bridge_num_get(dp); |
1492 | |
1493 | if (!bridge_num) |
1494 | continue; |
1495 | |
1496 | if (bridge_num + dst->last_switch != dev) |
1497 | continue; |
1498 | |
1499 | found = true; |
1500 | break; |
1501 | } |
1502 | } |
1503 | |
1504 | /* Prevent frames from unknown switch or virtual bridge */ |
1505 | if (!found) |
1506 | return 0; |
1507 | |
1508 | /* Frames from DSA links and CPU ports can egress any local port */ |
1509 | if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) |
1510 | return mv88e6xxx_port_mask(chip); |
1511 | |
1512 | pvlan = 0; |
1513 | |
1514 | /* Frames from standalone user ports can only egress on the |
1515 | * upstream port. |
1516 | */ |
1517 | if (!dsa_port_bridge_dev_get(dp)) |
1518 | return BIT(dsa_switch_upstream_port(ds)); |
1519 | |
1520 | /* Frames from bridged user ports can egress any local DSA |
1521 | * links and CPU ports, as well as any local member of their |
1522 | * bridge group. |
1523 | */ |
1524 | dsa_switch_for_each_port(other_dp, ds) |
1525 | if (other_dp->type == DSA_PORT_TYPE_CPU || |
1526 | other_dp->type == DSA_PORT_TYPE_DSA || |
1527 | dsa_port_bridge_same(a: dp, b: other_dp)) |
1528 | pvlan |= BIT(other_dp->index); |
1529 | |
1530 | return pvlan; |
1531 | } |
1532 | |
1533 | static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) |
1534 | { |
1535 | u16 output_ports = mv88e6xxx_port_vlan(chip, dev: chip->ds->index, port); |
1536 | |
1537 | /* prevent frames from going back out of the port they came in on */ |
1538 | output_ports &= ~BIT(port); |
1539 | |
1540 | return mv88e6xxx_port_set_vlan_map(chip, port, map: output_ports); |
1541 | } |
1542 | |
1543 | static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, |
1544 | u8 state) |
1545 | { |
1546 | struct mv88e6xxx_chip *chip = ds->priv; |
1547 | int err; |
1548 | |
1549 | mv88e6xxx_reg_lock(chip); |
1550 | err = mv88e6xxx_port_set_state(chip, port, state); |
1551 | mv88e6xxx_reg_unlock(chip); |
1552 | |
1553 | if (err) |
1554 | dev_err(ds->dev, "p%d: failed to update state\n" , port); |
1555 | } |
1556 | |
1557 | static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) |
1558 | { |
1559 | int err; |
1560 | |
1561 | if (chip->info->ops->ieee_pri_map) { |
1562 | err = chip->info->ops->ieee_pri_map(chip); |
1563 | if (err) |
1564 | return err; |
1565 | } |
1566 | |
1567 | if (chip->info->ops->ip_pri_map) { |
1568 | err = chip->info->ops->ip_pri_map(chip); |
1569 | if (err) |
1570 | return err; |
1571 | } |
1572 | |
1573 | return 0; |
1574 | } |
1575 | |
1576 | static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) |
1577 | { |
1578 | struct dsa_switch *ds = chip->ds; |
1579 | int target, port; |
1580 | int err; |
1581 | |
1582 | if (!chip->info->global2_addr) |
1583 | return 0; |
1584 | |
1585 | /* Initialize the routing port to the 32 possible target devices */ |
1586 | for (target = 0; target < 32; target++) { |
1587 | port = dsa_routing_port(ds, device: target); |
1588 | if (port == ds->num_ports) |
1589 | port = 0x1f; |
1590 | |
1591 | err = mv88e6xxx_g2_device_mapping_write(chip, target, port); |
1592 | if (err) |
1593 | return err; |
1594 | } |
1595 | |
1596 | if (chip->info->ops->set_cascade_port) { |
1597 | port = MV88E6XXX_CASCADE_PORT_MULTIPLE; |
1598 | err = chip->info->ops->set_cascade_port(chip, port); |
1599 | if (err) |
1600 | return err; |
1601 | } |
1602 | |
1603 | err = mv88e6xxx_g1_set_device_number(chip, index: chip->ds->index); |
1604 | if (err) |
1605 | return err; |
1606 | |
1607 | return 0; |
1608 | } |
1609 | |
1610 | static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) |
1611 | { |
1612 | /* Clear all trunk masks and mapping */ |
1613 | if (chip->info->global2_addr) |
1614 | return mv88e6xxx_g2_trunk_clear(chip); |
1615 | |
1616 | return 0; |
1617 | } |
1618 | |
1619 | static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) |
1620 | { |
1621 | if (chip->info->ops->rmu_disable) |
1622 | return chip->info->ops->rmu_disable(chip); |
1623 | |
1624 | return 0; |
1625 | } |
1626 | |
1627 | static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) |
1628 | { |
1629 | if (chip->info->ops->pot_clear) |
1630 | return chip->info->ops->pot_clear(chip); |
1631 | |
1632 | return 0; |
1633 | } |
1634 | |
1635 | static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) |
1636 | { |
1637 | if (chip->info->ops->mgmt_rsvd2cpu) |
1638 | return chip->info->ops->mgmt_rsvd2cpu(chip); |
1639 | |
1640 | return 0; |
1641 | } |
1642 | |
1643 | static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) |
1644 | { |
1645 | int err; |
1646 | |
1647 | err = mv88e6xxx_g1_atu_flush(chip, fid: 0, all: true); |
1648 | if (err) |
1649 | return err; |
1650 | |
1651 | /* The chips that have a "learn2all" bit in Global1, ATU |
1652 | * Control are precisely those whose port registers have a |
1653 | * Message Port bit in Port Control 1 and hence implement |
1654 | * ->port_setup_message_port. |
1655 | */ |
1656 | if (chip->info->ops->port_setup_message_port) { |
1657 | err = mv88e6xxx_g1_atu_set_learn2all(chip, learn2all: true); |
1658 | if (err) |
1659 | return err; |
1660 | } |
1661 | |
1662 | return mv88e6xxx_g1_atu_set_age_time(chip, msecs: 300000); |
1663 | } |
1664 | |
1665 | static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) |
1666 | { |
1667 | int port; |
1668 | int err; |
1669 | |
1670 | if (!chip->info->ops->irl_init_all) |
1671 | return 0; |
1672 | |
1673 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { |
1674 | /* Disable ingress rate limiting by resetting all per port |
1675 | * ingress rate limit resources to their initial state. |
1676 | */ |
1677 | err = chip->info->ops->irl_init_all(chip, port); |
1678 | if (err) |
1679 | return err; |
1680 | } |
1681 | |
1682 | return 0; |
1683 | } |
1684 | |
1685 | static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) |
1686 | { |
1687 | if (chip->info->ops->set_switch_mac) { |
1688 | u8 addr[ETH_ALEN]; |
1689 | |
1690 | eth_random_addr(addr); |
1691 | |
1692 | return chip->info->ops->set_switch_mac(chip, addr); |
1693 | } |
1694 | |
1695 | return 0; |
1696 | } |
1697 | |
1698 | static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) |
1699 | { |
1700 | struct dsa_switch_tree *dst = chip->ds->dst; |
1701 | struct dsa_switch *ds; |
1702 | struct dsa_port *dp; |
1703 | u16 pvlan = 0; |
1704 | |
1705 | if (!mv88e6xxx_has_pvt(chip)) |
1706 | return 0; |
1707 | |
1708 | /* Skip the local source device, which uses in-chip port VLAN */ |
1709 | if (dev != chip->ds->index) { |
1710 | pvlan = mv88e6xxx_port_vlan(chip, dev, port); |
1711 | |
1712 | ds = dsa_switch_find(tree_index: dst->index, sw_index: dev); |
1713 | dp = ds ? dsa_to_port(ds, p: port) : NULL; |
1714 | if (dp && dp->lag) { |
1715 | /* As the PVT is used to limit flooding of |
1716 | * FORWARD frames, which use the LAG ID as the |
1717 | * source port, we must translate dev/port to |
1718 | * the special "LAG device" in the PVT, using |
1719 | * the LAG ID (one-based) as the port number |
1720 | * (zero-based). |
1721 | */ |
1722 | dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; |
1723 | port = dsa_port_lag_id_get(dp) - 1; |
1724 | } |
1725 | } |
1726 | |
1727 | return mv88e6xxx_g2_pvt_write(chip, src_dev: dev, src_port: port, data: pvlan); |
1728 | } |
1729 | |
1730 | static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) |
1731 | { |
1732 | int dev, port; |
1733 | int err; |
1734 | |
1735 | if (!mv88e6xxx_has_pvt(chip)) |
1736 | return 0; |
1737 | |
1738 | /* Clear 5 Bit Port for usage with Marvell Link Street devices: |
1739 | * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. |
1740 | */ |
1741 | err = mv88e6xxx_g2_misc_4_bit_port(chip); |
1742 | if (err) |
1743 | return err; |
1744 | |
1745 | for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { |
1746 | for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { |
1747 | err = mv88e6xxx_pvt_map(chip, dev, port); |
1748 | if (err) |
1749 | return err; |
1750 | } |
1751 | } |
1752 | |
1753 | return 0; |
1754 | } |
1755 | |
1756 | static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, |
1757 | u16 fid) |
1758 | { |
1759 | if (dsa_to_port(ds: chip->ds, p: port)->lag) |
1760 | /* Hardware is incapable of fast-aging a LAG through a |
1761 | * regular ATU move operation. Until we have something |
1762 | * more fancy in place this is a no-op. |
1763 | */ |
1764 | return -EOPNOTSUPP; |
1765 | |
1766 | return mv88e6xxx_g1_atu_remove(chip, fid, port, all: false); |
1767 | } |
1768 | |
1769 | static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) |
1770 | { |
1771 | struct mv88e6xxx_chip *chip = ds->priv; |
1772 | int err; |
1773 | |
1774 | mv88e6xxx_reg_lock(chip); |
1775 | err = mv88e6xxx_port_fast_age_fid(chip, port, fid: 0); |
1776 | mv88e6xxx_reg_unlock(chip); |
1777 | |
1778 | if (err) |
1779 | dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n" , |
1780 | port, err); |
1781 | } |
1782 | |
1783 | static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) |
1784 | { |
1785 | if (!mv88e6xxx_max_vid(chip)) |
1786 | return 0; |
1787 | |
1788 | return mv88e6xxx_g1_vtu_flush(chip); |
1789 | } |
1790 | |
1791 | static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, |
1792 | struct mv88e6xxx_vtu_entry *entry) |
1793 | { |
1794 | int err; |
1795 | |
1796 | if (!chip->info->ops->vtu_getnext) |
1797 | return -EOPNOTSUPP; |
1798 | |
1799 | entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); |
1800 | entry->valid = false; |
1801 | |
1802 | err = chip->info->ops->vtu_getnext(chip, entry); |
1803 | |
1804 | if (entry->vid != vid) |
1805 | entry->valid = false; |
1806 | |
1807 | return err; |
1808 | } |
1809 | |
1810 | int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, |
1811 | int (*cb)(struct mv88e6xxx_chip *chip, |
1812 | const struct mv88e6xxx_vtu_entry *entry, |
1813 | void *priv), |
1814 | void *priv) |
1815 | { |
1816 | struct mv88e6xxx_vtu_entry entry = { |
1817 | .vid = mv88e6xxx_max_vid(chip), |
1818 | .valid = false, |
1819 | }; |
1820 | int err; |
1821 | |
1822 | if (!chip->info->ops->vtu_getnext) |
1823 | return -EOPNOTSUPP; |
1824 | |
1825 | do { |
1826 | err = chip->info->ops->vtu_getnext(chip, &entry); |
1827 | if (err) |
1828 | return err; |
1829 | |
1830 | if (!entry.valid) |
1831 | break; |
1832 | |
1833 | err = cb(chip, &entry, priv); |
1834 | if (err) |
1835 | return err; |
1836 | } while (entry.vid < mv88e6xxx_max_vid(chip)); |
1837 | |
1838 | return 0; |
1839 | } |
1840 | |
1841 | static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, |
1842 | struct mv88e6xxx_vtu_entry *entry) |
1843 | { |
1844 | if (!chip->info->ops->vtu_loadpurge) |
1845 | return -EOPNOTSUPP; |
1846 | |
1847 | return chip->info->ops->vtu_loadpurge(chip, entry); |
1848 | } |
1849 | |
1850 | static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, |
1851 | const struct mv88e6xxx_vtu_entry *entry, |
1852 | void *_fid_bitmap) |
1853 | { |
1854 | unsigned long *fid_bitmap = _fid_bitmap; |
1855 | |
1856 | set_bit(nr: entry->fid, addr: fid_bitmap); |
1857 | return 0; |
1858 | } |
1859 | |
1860 | int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) |
1861 | { |
1862 | bitmap_zero(dst: fid_bitmap, MV88E6XXX_N_FID); |
1863 | |
1864 | /* Every FID has an associated VID, so walking the VTU |
1865 | * will discover the full set of FIDs in use. |
1866 | */ |
1867 | return mv88e6xxx_vtu_walk(chip, cb: mv88e6xxx_fid_map_vlan, priv: fid_bitmap); |
1868 | } |
1869 | |
1870 | static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) |
1871 | { |
1872 | DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); |
1873 | int err; |
1874 | |
1875 | err = mv88e6xxx_fid_map(chip, fid_bitmap); |
1876 | if (err) |
1877 | return err; |
1878 | |
1879 | *fid = find_first_zero_bit(addr: fid_bitmap, MV88E6XXX_N_FID); |
1880 | if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) |
1881 | return -ENOSPC; |
1882 | |
1883 | /* Clear the database */ |
1884 | return mv88e6xxx_g1_atu_flush(chip, fid: *fid, all: true); |
1885 | } |
1886 | |
1887 | static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, |
1888 | struct mv88e6xxx_stu_entry *entry) |
1889 | { |
1890 | if (!chip->info->ops->stu_loadpurge) |
1891 | return -EOPNOTSUPP; |
1892 | |
1893 | return chip->info->ops->stu_loadpurge(chip, entry); |
1894 | } |
1895 | |
1896 | static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) |
1897 | { |
1898 | struct mv88e6xxx_stu_entry stu = { |
1899 | .valid = true, |
1900 | .sid = 0 |
1901 | }; |
1902 | |
1903 | if (!mv88e6xxx_has_stu(chip)) |
1904 | return 0; |
1905 | |
1906 | /* Make sure that SID 0 is always valid. This is used by VTU |
1907 | * entries that do not make use of the STU, e.g. when creating |
1908 | * a VLAN upper on a port that is also part of a VLAN |
1909 | * filtering bridge. |
1910 | */ |
1911 | return mv88e6xxx_stu_loadpurge(chip, entry: &stu); |
1912 | } |
1913 | |
1914 | static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) |
1915 | { |
1916 | DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; |
1917 | struct mv88e6xxx_mst *mst; |
1918 | |
1919 | __set_bit(0, busy); |
1920 | |
1921 | list_for_each_entry(mst, &chip->msts, node) |
1922 | __set_bit(mst->stu.sid, busy); |
1923 | |
1924 | *sid = find_first_zero_bit(addr: busy, MV88E6XXX_N_SID); |
1925 | |
1926 | return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; |
1927 | } |
1928 | |
1929 | static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) |
1930 | { |
1931 | struct mv88e6xxx_mst *mst, *tmp; |
1932 | int err; |
1933 | |
1934 | if (!sid) |
1935 | return 0; |
1936 | |
1937 | list_for_each_entry_safe(mst, tmp, &chip->msts, node) { |
1938 | if (mst->stu.sid != sid) |
1939 | continue; |
1940 | |
1941 | if (!refcount_dec_and_test(r: &mst->refcnt)) |
1942 | return 0; |
1943 | |
1944 | mst->stu.valid = false; |
1945 | err = mv88e6xxx_stu_loadpurge(chip, entry: &mst->stu); |
1946 | if (err) { |
1947 | refcount_set(r: &mst->refcnt, n: 1); |
1948 | return err; |
1949 | } |
1950 | |
1951 | list_del(entry: &mst->node); |
1952 | kfree(objp: mst); |
1953 | return 0; |
1954 | } |
1955 | |
1956 | return -ENOENT; |
1957 | } |
1958 | |
1959 | static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, |
1960 | u16 msti, u8 *sid) |
1961 | { |
1962 | struct mv88e6xxx_mst *mst; |
1963 | int err, i; |
1964 | |
1965 | if (!mv88e6xxx_has_stu(chip)) { |
1966 | err = -EOPNOTSUPP; |
1967 | goto err; |
1968 | } |
1969 | |
1970 | if (!msti) { |
1971 | *sid = 0; |
1972 | return 0; |
1973 | } |
1974 | |
1975 | list_for_each_entry(mst, &chip->msts, node) { |
1976 | if (mst->br == br && mst->msti == msti) { |
1977 | refcount_inc(r: &mst->refcnt); |
1978 | *sid = mst->stu.sid; |
1979 | return 0; |
1980 | } |
1981 | } |
1982 | |
1983 | err = mv88e6xxx_sid_get(chip, sid); |
1984 | if (err) |
1985 | goto err; |
1986 | |
1987 | mst = kzalloc(size: sizeof(*mst), GFP_KERNEL); |
1988 | if (!mst) { |
1989 | err = -ENOMEM; |
1990 | goto err; |
1991 | } |
1992 | |
1993 | INIT_LIST_HEAD(list: &mst->node); |
1994 | refcount_set(r: &mst->refcnt, n: 1); |
1995 | mst->br = br; |
1996 | mst->msti = msti; |
1997 | mst->stu.valid = true; |
1998 | mst->stu.sid = *sid; |
1999 | |
2000 | /* The bridge starts out all ports in the disabled state. But |
2001 | * a STU state of disabled means to go by the port-global |
2002 | * state. So we set all user port's initial state to blocking, |
2003 | * to match the bridge's behavior. |
2004 | */ |
2005 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) |
2006 | mst->stu.state[i] = dsa_is_user_port(ds: chip->ds, p: i) ? |
2007 | MV88E6XXX_PORT_CTL0_STATE_BLOCKING : |
2008 | MV88E6XXX_PORT_CTL0_STATE_DISABLED; |
2009 | |
2010 | err = mv88e6xxx_stu_loadpurge(chip, entry: &mst->stu); |
2011 | if (err) |
2012 | goto err_free; |
2013 | |
2014 | list_add_tail(new: &mst->node, head: &chip->msts); |
2015 | return 0; |
2016 | |
2017 | err_free: |
2018 | kfree(objp: mst); |
2019 | err: |
2020 | return err; |
2021 | } |
2022 | |
2023 | static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, |
2024 | const struct switchdev_mst_state *st) |
2025 | { |
2026 | struct dsa_port *dp = dsa_to_port(ds, p: port); |
2027 | struct mv88e6xxx_chip *chip = ds->priv; |
2028 | struct mv88e6xxx_mst *mst; |
2029 | u8 state; |
2030 | int err; |
2031 | |
2032 | if (!mv88e6xxx_has_stu(chip)) |
2033 | return -EOPNOTSUPP; |
2034 | |
2035 | switch (st->state) { |
2036 | case BR_STATE_DISABLED: |
2037 | case BR_STATE_BLOCKING: |
2038 | case BR_STATE_LISTENING: |
2039 | state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; |
2040 | break; |
2041 | case BR_STATE_LEARNING: |
2042 | state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; |
2043 | break; |
2044 | case BR_STATE_FORWARDING: |
2045 | state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; |
2046 | break; |
2047 | default: |
2048 | return -EINVAL; |
2049 | } |
2050 | |
2051 | list_for_each_entry(mst, &chip->msts, node) { |
2052 | if (mst->br == dsa_port_bridge_dev_get(dp) && |
2053 | mst->msti == st->msti) { |
2054 | if (mst->stu.state[port] == state) |
2055 | return 0; |
2056 | |
2057 | mst->stu.state[port] = state; |
2058 | mv88e6xxx_reg_lock(chip); |
2059 | err = mv88e6xxx_stu_loadpurge(chip, entry: &mst->stu); |
2060 | mv88e6xxx_reg_unlock(chip); |
2061 | return err; |
2062 | } |
2063 | } |
2064 | |
2065 | return -ENOENT; |
2066 | } |
2067 | |
2068 | static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, |
2069 | u16 vid) |
2070 | { |
2071 | struct dsa_port *dp = dsa_to_port(ds, p: port), *other_dp; |
2072 | struct mv88e6xxx_chip *chip = ds->priv; |
2073 | struct mv88e6xxx_vtu_entry vlan; |
2074 | int err; |
2075 | |
2076 | /* DSA and CPU ports have to be members of multiple vlans */ |
2077 | if (dsa_port_is_dsa(port: dp) || dsa_port_is_cpu(port: dp)) |
2078 | return 0; |
2079 | |
2080 | err = mv88e6xxx_vtu_get(chip, vid, entry: &vlan); |
2081 | if (err) |
2082 | return err; |
2083 | |
2084 | if (!vlan.valid) |
2085 | return 0; |
2086 | |
2087 | dsa_switch_for_each_user_port(other_dp, ds) { |
2088 | struct net_device *other_br; |
2089 | |
2090 | if (vlan.member[other_dp->index] == |
2091 | MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
2092 | continue; |
2093 | |
2094 | if (dsa_port_bridge_same(a: dp, b: other_dp)) |
2095 | break; /* same bridge, check next VLAN */ |
2096 | |
2097 | other_br = dsa_port_bridge_dev_get(dp: other_dp); |
2098 | if (!other_br) |
2099 | continue; |
2100 | |
2101 | dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n" , |
2102 | port, vlan.vid, other_dp->index, netdev_name(other_br)); |
2103 | return -EOPNOTSUPP; |
2104 | } |
2105 | |
2106 | return 0; |
2107 | } |
2108 | |
2109 | static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) |
2110 | { |
2111 | struct dsa_port *dp = dsa_to_port(ds: chip->ds, p: port); |
2112 | struct net_device *br = dsa_port_bridge_dev_get(dp); |
2113 | struct mv88e6xxx_port *p = &chip->ports[port]; |
2114 | u16 pvid = MV88E6XXX_VID_STANDALONE; |
2115 | bool drop_untagged = false; |
2116 | int err; |
2117 | |
2118 | if (br) { |
2119 | if (br_vlan_enabled(dev: br)) { |
2120 | pvid = p->bridge_pvid.vid; |
2121 | drop_untagged = !p->bridge_pvid.valid; |
2122 | } else { |
2123 | pvid = MV88E6XXX_VID_BRIDGED; |
2124 | } |
2125 | } |
2126 | |
2127 | err = mv88e6xxx_port_set_pvid(chip, port, pvid); |
2128 | if (err) |
2129 | return err; |
2130 | |
2131 | return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); |
2132 | } |
2133 | |
2134 | static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, |
2135 | bool vlan_filtering, |
2136 | struct netlink_ext_ack *extack) |
2137 | { |
2138 | struct mv88e6xxx_chip *chip = ds->priv; |
2139 | u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : |
2140 | MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; |
2141 | int err; |
2142 | |
2143 | if (!mv88e6xxx_max_vid(chip)) |
2144 | return -EOPNOTSUPP; |
2145 | |
2146 | mv88e6xxx_reg_lock(chip); |
2147 | |
2148 | err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); |
2149 | if (err) |
2150 | goto unlock; |
2151 | |
2152 | err = mv88e6xxx_port_commit_pvid(chip, port); |
2153 | if (err) |
2154 | goto unlock; |
2155 | |
2156 | unlock: |
2157 | mv88e6xxx_reg_unlock(chip); |
2158 | |
2159 | return err; |
2160 | } |
2161 | |
2162 | static int |
2163 | mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, |
2164 | const struct switchdev_obj_port_vlan *vlan) |
2165 | { |
2166 | struct mv88e6xxx_chip *chip = ds->priv; |
2167 | int err; |
2168 | |
2169 | if (!mv88e6xxx_max_vid(chip)) |
2170 | return -EOPNOTSUPP; |
2171 | |
2172 | /* If the requested port doesn't belong to the same bridge as the VLAN |
2173 | * members, do not support it (yet) and fallback to software VLAN. |
2174 | */ |
2175 | mv88e6xxx_reg_lock(chip); |
2176 | err = mv88e6xxx_port_check_hw_vlan(ds, port, vid: vlan->vid); |
2177 | mv88e6xxx_reg_unlock(chip); |
2178 | |
2179 | return err; |
2180 | } |
2181 | |
2182 | static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, |
2183 | const unsigned char *addr, u16 vid, |
2184 | u8 state) |
2185 | { |
2186 | struct mv88e6xxx_atu_entry entry; |
2187 | struct mv88e6xxx_vtu_entry vlan; |
2188 | u16 fid; |
2189 | int err; |
2190 | |
2191 | /* Ports have two private address databases: one for when the port is |
2192 | * standalone and one for when the port is under a bridge and the |
2193 | * 802.1Q mode is disabled. When the port is standalone, DSA wants its |
2194 | * address database to remain 100% empty, so we never load an ATU entry |
2195 | * into a standalone port's database. Therefore, translate the null |
2196 | * VLAN ID into the port's database used for VLAN-unaware bridging. |
2197 | */ |
2198 | if (vid == 0) { |
2199 | fid = MV88E6XXX_FID_BRIDGED; |
2200 | } else { |
2201 | err = mv88e6xxx_vtu_get(chip, vid, entry: &vlan); |
2202 | if (err) |
2203 | return err; |
2204 | |
2205 | /* switchdev expects -EOPNOTSUPP to honor software VLANs */ |
2206 | if (!vlan.valid) |
2207 | return -EOPNOTSUPP; |
2208 | |
2209 | fid = vlan.fid; |
2210 | } |
2211 | |
2212 | entry.state = 0; |
2213 | ether_addr_copy(dst: entry.mac, src: addr); |
2214 | eth_addr_dec(addr: entry.mac); |
2215 | |
2216 | err = mv88e6xxx_g1_atu_getnext(chip, fid, entry: &entry); |
2217 | if (err) |
2218 | return err; |
2219 | |
2220 | /* Initialize a fresh ATU entry if it isn't found */ |
2221 | if (!entry.state || !ether_addr_equal(addr1: entry.mac, addr2: addr)) { |
2222 | memset(&entry, 0, sizeof(entry)); |
2223 | ether_addr_copy(dst: entry.mac, src: addr); |
2224 | } |
2225 | |
2226 | /* Purge the ATU entry only if no port is using it anymore */ |
2227 | if (!state) { |
2228 | entry.portvec &= ~BIT(port); |
2229 | if (!entry.portvec) |
2230 | entry.state = 0; |
2231 | } else { |
2232 | if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) |
2233 | entry.portvec = BIT(port); |
2234 | else |
2235 | entry.portvec |= BIT(port); |
2236 | |
2237 | entry.state = state; |
2238 | } |
2239 | |
2240 | return mv88e6xxx_g1_atu_loadpurge(chip, fid, entry: &entry); |
2241 | } |
2242 | |
2243 | static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, |
2244 | const struct mv88e6xxx_policy *policy) |
2245 | { |
2246 | enum mv88e6xxx_policy_mapping mapping = policy->mapping; |
2247 | enum mv88e6xxx_policy_action action = policy->action; |
2248 | const u8 *addr = policy->addr; |
2249 | u16 vid = policy->vid; |
2250 | u8 state; |
2251 | int err; |
2252 | int id; |
2253 | |
2254 | if (!chip->info->ops->port_set_policy) |
2255 | return -EOPNOTSUPP; |
2256 | |
2257 | switch (mapping) { |
2258 | case MV88E6XXX_POLICY_MAPPING_DA: |
2259 | case MV88E6XXX_POLICY_MAPPING_SA: |
2260 | if (action == MV88E6XXX_POLICY_ACTION_NORMAL) |
2261 | state = 0; /* Dissociate the port and address */ |
2262 | else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && |
2263 | is_multicast_ether_addr(addr)) |
2264 | state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; |
2265 | else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && |
2266 | is_unicast_ether_addr(addr)) |
2267 | state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; |
2268 | else |
2269 | return -EOPNOTSUPP; |
2270 | |
2271 | err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, |
2272 | state); |
2273 | if (err) |
2274 | return err; |
2275 | break; |
2276 | default: |
2277 | return -EOPNOTSUPP; |
2278 | } |
2279 | |
2280 | /* Skip the port's policy clearing if the mapping is still in use */ |
2281 | if (action == MV88E6XXX_POLICY_ACTION_NORMAL) |
2282 | idr_for_each_entry(&chip->policies, policy, id) |
2283 | if (policy->port == port && |
2284 | policy->mapping == mapping && |
2285 | policy->action != action) |
2286 | return 0; |
2287 | |
2288 | return chip->info->ops->port_set_policy(chip, port, mapping, action); |
2289 | } |
2290 | |
2291 | static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, |
2292 | struct ethtool_rx_flow_spec *fs) |
2293 | { |
2294 | struct ethhdr *mac_entry = &fs->h_u.ether_spec; |
2295 | struct ethhdr *mac_mask = &fs->m_u.ether_spec; |
2296 | enum mv88e6xxx_policy_mapping mapping; |
2297 | enum mv88e6xxx_policy_action action; |
2298 | struct mv88e6xxx_policy *policy; |
2299 | u16 vid = 0; |
2300 | u8 *addr; |
2301 | int err; |
2302 | int id; |
2303 | |
2304 | if (fs->location != RX_CLS_LOC_ANY) |
2305 | return -EINVAL; |
2306 | |
2307 | if (fs->ring_cookie == RX_CLS_FLOW_DISC) |
2308 | action = MV88E6XXX_POLICY_ACTION_DISCARD; |
2309 | else |
2310 | return -EOPNOTSUPP; |
2311 | |
2312 | switch (fs->flow_type & ~FLOW_EXT) { |
2313 | case ETHER_FLOW: |
2314 | if (!is_zero_ether_addr(addr: mac_mask->h_dest) && |
2315 | is_zero_ether_addr(addr: mac_mask->h_source)) { |
2316 | mapping = MV88E6XXX_POLICY_MAPPING_DA; |
2317 | addr = mac_entry->h_dest; |
2318 | } else if (is_zero_ether_addr(addr: mac_mask->h_dest) && |
2319 | !is_zero_ether_addr(addr: mac_mask->h_source)) { |
2320 | mapping = MV88E6XXX_POLICY_MAPPING_SA; |
2321 | addr = mac_entry->h_source; |
2322 | } else { |
2323 | /* Cannot support DA and SA mapping in the same rule */ |
2324 | return -EOPNOTSUPP; |
2325 | } |
2326 | break; |
2327 | default: |
2328 | return -EOPNOTSUPP; |
2329 | } |
2330 | |
2331 | if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { |
2332 | if (fs->m_ext.vlan_tci != htons(0xffff)) |
2333 | return -EOPNOTSUPP; |
2334 | vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; |
2335 | } |
2336 | |
2337 | idr_for_each_entry(&chip->policies, policy, id) { |
2338 | if (policy->port == port && policy->mapping == mapping && |
2339 | policy->action == action && policy->vid == vid && |
2340 | ether_addr_equal(addr1: policy->addr, addr2: addr)) |
2341 | return -EEXIST; |
2342 | } |
2343 | |
2344 | policy = devm_kzalloc(dev: chip->dev, size: sizeof(*policy), GFP_KERNEL); |
2345 | if (!policy) |
2346 | return -ENOMEM; |
2347 | |
2348 | fs->location = 0; |
2349 | err = idr_alloc_u32(&chip->policies, ptr: policy, id: &fs->location, max: 0xffffffff, |
2350 | GFP_KERNEL); |
2351 | if (err) { |
2352 | devm_kfree(dev: chip->dev, p: policy); |
2353 | return err; |
2354 | } |
2355 | |
2356 | memcpy(&policy->fs, fs, sizeof(*fs)); |
2357 | ether_addr_copy(dst: policy->addr, src: addr); |
2358 | policy->mapping = mapping; |
2359 | policy->action = action; |
2360 | policy->port = port; |
2361 | policy->vid = vid; |
2362 | |
2363 | err = mv88e6xxx_policy_apply(chip, port, policy); |
2364 | if (err) { |
2365 | idr_remove(&chip->policies, id: fs->location); |
2366 | devm_kfree(dev: chip->dev, p: policy); |
2367 | return err; |
2368 | } |
2369 | |
2370 | return 0; |
2371 | } |
2372 | |
2373 | static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, |
2374 | struct ethtool_rxnfc *rxnfc, u32 *rule_locs) |
2375 | { |
2376 | struct ethtool_rx_flow_spec *fs = &rxnfc->fs; |
2377 | struct mv88e6xxx_chip *chip = ds->priv; |
2378 | struct mv88e6xxx_policy *policy; |
2379 | int err; |
2380 | int id; |
2381 | |
2382 | mv88e6xxx_reg_lock(chip); |
2383 | |
2384 | switch (rxnfc->cmd) { |
2385 | case ETHTOOL_GRXCLSRLCNT: |
2386 | rxnfc->data = 0; |
2387 | rxnfc->data |= RX_CLS_LOC_SPECIAL; |
2388 | rxnfc->rule_cnt = 0; |
2389 | idr_for_each_entry(&chip->policies, policy, id) |
2390 | if (policy->port == port) |
2391 | rxnfc->rule_cnt++; |
2392 | err = 0; |
2393 | break; |
2394 | case ETHTOOL_GRXCLSRULE: |
2395 | err = -ENOENT; |
2396 | policy = idr_find(&chip->policies, id: fs->location); |
2397 | if (policy) { |
2398 | memcpy(fs, &policy->fs, sizeof(*fs)); |
2399 | err = 0; |
2400 | } |
2401 | break; |
2402 | case ETHTOOL_GRXCLSRLALL: |
2403 | rxnfc->data = 0; |
2404 | rxnfc->rule_cnt = 0; |
2405 | idr_for_each_entry(&chip->policies, policy, id) |
2406 | if (policy->port == port) |
2407 | rule_locs[rxnfc->rule_cnt++] = id; |
2408 | err = 0; |
2409 | break; |
2410 | default: |
2411 | err = -EOPNOTSUPP; |
2412 | break; |
2413 | } |
2414 | |
2415 | mv88e6xxx_reg_unlock(chip); |
2416 | |
2417 | return err; |
2418 | } |
2419 | |
2420 | static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, |
2421 | struct ethtool_rxnfc *rxnfc) |
2422 | { |
2423 | struct ethtool_rx_flow_spec *fs = &rxnfc->fs; |
2424 | struct mv88e6xxx_chip *chip = ds->priv; |
2425 | struct mv88e6xxx_policy *policy; |
2426 | int err; |
2427 | |
2428 | mv88e6xxx_reg_lock(chip); |
2429 | |
2430 | switch (rxnfc->cmd) { |
2431 | case ETHTOOL_SRXCLSRLINS: |
2432 | err = mv88e6xxx_policy_insert(chip, port, fs); |
2433 | break; |
2434 | case ETHTOOL_SRXCLSRLDEL: |
2435 | err = -ENOENT; |
2436 | policy = idr_remove(&chip->policies, id: fs->location); |
2437 | if (policy) { |
2438 | policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; |
2439 | err = mv88e6xxx_policy_apply(chip, port, policy); |
2440 | devm_kfree(dev: chip->dev, p: policy); |
2441 | } |
2442 | break; |
2443 | default: |
2444 | err = -EOPNOTSUPP; |
2445 | break; |
2446 | } |
2447 | |
2448 | mv88e6xxx_reg_unlock(chip); |
2449 | |
2450 | return err; |
2451 | } |
2452 | |
2453 | static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, |
2454 | u16 vid) |
2455 | { |
2456 | u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; |
2457 | u8 broadcast[ETH_ALEN]; |
2458 | |
2459 | eth_broadcast_addr(addr: broadcast); |
2460 | |
2461 | return mv88e6xxx_port_db_load_purge(chip, port, addr: broadcast, vid, state); |
2462 | } |
2463 | |
2464 | static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) |
2465 | { |
2466 | int port; |
2467 | int err; |
2468 | |
2469 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { |
2470 | struct dsa_port *dp = dsa_to_port(ds: chip->ds, p: port); |
2471 | struct net_device *brport; |
2472 | |
2473 | if (dsa_is_unused_port(ds: chip->ds, p: port)) |
2474 | continue; |
2475 | |
2476 | brport = dsa_port_to_bridge_port(dp); |
2477 | if (brport && !br_port_flag_is_set(dev: brport, BR_BCAST_FLOOD)) |
2478 | /* Skip bridged user ports where broadcast |
2479 | * flooding is disabled. |
2480 | */ |
2481 | continue; |
2482 | |
2483 | err = mv88e6xxx_port_add_broadcast(chip, port, vid); |
2484 | if (err) |
2485 | return err; |
2486 | } |
2487 | |
2488 | return 0; |
2489 | } |
2490 | |
2491 | struct mv88e6xxx_port_broadcast_sync_ctx { |
2492 | int port; |
2493 | bool flood; |
2494 | }; |
2495 | |
2496 | static int |
2497 | mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, |
2498 | const struct mv88e6xxx_vtu_entry *vlan, |
2499 | void *_ctx) |
2500 | { |
2501 | struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; |
2502 | u8 broadcast[ETH_ALEN]; |
2503 | u8 state; |
2504 | |
2505 | if (ctx->flood) |
2506 | state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; |
2507 | else |
2508 | state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; |
2509 | |
2510 | eth_broadcast_addr(addr: broadcast); |
2511 | |
2512 | return mv88e6xxx_port_db_load_purge(chip, port: ctx->port, addr: broadcast, |
2513 | vid: vlan->vid, state); |
2514 | } |
2515 | |
2516 | static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, |
2517 | bool flood) |
2518 | { |
2519 | struct mv88e6xxx_port_broadcast_sync_ctx ctx = { |
2520 | .port = port, |
2521 | .flood = flood, |
2522 | }; |
2523 | struct mv88e6xxx_vtu_entry vid0 = { |
2524 | .vid = 0, |
2525 | }; |
2526 | int err; |
2527 | |
2528 | /* Update the port's private database... */ |
2529 | err = mv88e6xxx_port_broadcast_sync_vlan(chip, vlan: &vid0, ctx: &ctx); |
2530 | if (err) |
2531 | return err; |
2532 | |
2533 | /* ...and the database for all VLANs. */ |
2534 | return mv88e6xxx_vtu_walk(chip, cb: mv88e6xxx_port_broadcast_sync_vlan, |
2535 | priv: &ctx); |
2536 | } |
2537 | |
2538 | static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, |
2539 | u16 vid, u8 member, bool warn) |
2540 | { |
2541 | const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; |
2542 | struct mv88e6xxx_vtu_entry vlan; |
2543 | int i, err; |
2544 | |
2545 | err = mv88e6xxx_vtu_get(chip, vid, entry: &vlan); |
2546 | if (err) |
2547 | return err; |
2548 | |
2549 | if (!vlan.valid) { |
2550 | memset(&vlan, 0, sizeof(vlan)); |
2551 | |
2552 | if (vid == MV88E6XXX_VID_STANDALONE) |
2553 | vlan.policy = true; |
2554 | |
2555 | err = mv88e6xxx_atu_new(chip, fid: &vlan.fid); |
2556 | if (err) |
2557 | return err; |
2558 | |
2559 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) |
2560 | if (i == port) |
2561 | vlan.member[i] = member; |
2562 | else |
2563 | vlan.member[i] = non_member; |
2564 | |
2565 | vlan.vid = vid; |
2566 | vlan.valid = true; |
2567 | |
2568 | err = mv88e6xxx_vtu_loadpurge(chip, entry: &vlan); |
2569 | if (err) |
2570 | return err; |
2571 | |
2572 | err = mv88e6xxx_broadcast_setup(chip, vid: vlan.vid); |
2573 | if (err) |
2574 | return err; |
2575 | } else if (vlan.member[port] != member) { |
2576 | vlan.member[port] = member; |
2577 | |
2578 | err = mv88e6xxx_vtu_loadpurge(chip, entry: &vlan); |
2579 | if (err) |
2580 | return err; |
2581 | } else if (warn) { |
2582 | dev_info(chip->dev, "p%d: already a member of VLAN %d\n" , |
2583 | port, vid); |
2584 | } |
2585 | |
2586 | return 0; |
2587 | } |
2588 | |
2589 | static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, |
2590 | const struct switchdev_obj_port_vlan *vlan, |
2591 | struct netlink_ext_ack *extack) |
2592 | { |
2593 | struct mv88e6xxx_chip *chip = ds->priv; |
2594 | bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; |
2595 | bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; |
2596 | struct mv88e6xxx_port *p = &chip->ports[port]; |
2597 | bool warn; |
2598 | u8 member; |
2599 | int err; |
2600 | |
2601 | if (!vlan->vid) |
2602 | return 0; |
2603 | |
2604 | err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); |
2605 | if (err) |
2606 | return err; |
2607 | |
2608 | if (dsa_is_dsa_port(ds, p: port) || dsa_is_cpu_port(ds, p: port)) |
2609 | member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; |
2610 | else if (untagged) |
2611 | member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; |
2612 | else |
2613 | member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; |
2614 | |
2615 | /* net/dsa/user.c will call dsa_port_vlan_add() for the affected port |
2616 | * and then the CPU port. Do not warn for duplicates for the CPU port. |
2617 | */ |
2618 | warn = !dsa_is_cpu_port(ds, p: port) && !dsa_is_dsa_port(ds, p: port); |
2619 | |
2620 | mv88e6xxx_reg_lock(chip); |
2621 | |
2622 | err = mv88e6xxx_port_vlan_join(chip, port, vid: vlan->vid, member, warn); |
2623 | if (err) { |
2624 | dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n" , port, |
2625 | vlan->vid, untagged ? 'u' : 't'); |
2626 | goto out; |
2627 | } |
2628 | |
2629 | if (pvid) { |
2630 | p->bridge_pvid.vid = vlan->vid; |
2631 | p->bridge_pvid.valid = true; |
2632 | |
2633 | err = mv88e6xxx_port_commit_pvid(chip, port); |
2634 | if (err) |
2635 | goto out; |
2636 | } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { |
2637 | /* The old pvid was reinstalled as a non-pvid VLAN */ |
2638 | p->bridge_pvid.valid = false; |
2639 | |
2640 | err = mv88e6xxx_port_commit_pvid(chip, port); |
2641 | if (err) |
2642 | goto out; |
2643 | } |
2644 | |
2645 | out: |
2646 | mv88e6xxx_reg_unlock(chip); |
2647 | |
2648 | return err; |
2649 | } |
2650 | |
2651 | static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, |
2652 | int port, u16 vid) |
2653 | { |
2654 | struct mv88e6xxx_vtu_entry vlan; |
2655 | int i, err; |
2656 | |
2657 | if (!vid) |
2658 | return 0; |
2659 | |
2660 | err = mv88e6xxx_vtu_get(chip, vid, entry: &vlan); |
2661 | if (err) |
2662 | return err; |
2663 | |
2664 | /* If the VLAN doesn't exist in hardware or the port isn't a member, |
2665 | * tell switchdev that this VLAN is likely handled in software. |
2666 | */ |
2667 | if (!vlan.valid || |
2668 | vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) |
2669 | return -EOPNOTSUPP; |
2670 | |
2671 | vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; |
2672 | |
2673 | /* keep the VLAN unless all ports are excluded */ |
2674 | vlan.valid = false; |
2675 | for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { |
2676 | if (vlan.member[i] != |
2677 | MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { |
2678 | vlan.valid = true; |
2679 | break; |
2680 | } |
2681 | } |
2682 | |
2683 | err = mv88e6xxx_vtu_loadpurge(chip, entry: &vlan); |
2684 | if (err) |
2685 | return err; |
2686 | |
2687 | if (!vlan.valid) { |
2688 | err = mv88e6xxx_mst_put(chip, sid: vlan.sid); |
2689 | if (err) |
2690 | return err; |
2691 | } |
2692 | |
2693 | return mv88e6xxx_g1_atu_remove(chip, fid: vlan.fid, port, all: false); |
2694 | } |
2695 | |
2696 | static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, |
2697 | const struct switchdev_obj_port_vlan *vlan) |
2698 | { |
2699 | struct mv88e6xxx_chip *chip = ds->priv; |
2700 | struct mv88e6xxx_port *p = &chip->ports[port]; |
2701 | int err = 0; |
2702 | u16 pvid; |
2703 | |
2704 | if (!mv88e6xxx_max_vid(chip)) |
2705 | return -EOPNOTSUPP; |
2706 | |
2707 | /* The ATU removal procedure needs the FID to be mapped in the VTU, |
2708 | * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA |
2709 | * switchdev workqueue to ensure that all FDB entries are deleted |
2710 | * before we remove the VLAN. |
2711 | */ |
2712 | dsa_flush_workqueue(); |
2713 | |
2714 | mv88e6xxx_reg_lock(chip); |
2715 | |
2716 | err = mv88e6xxx_port_get_pvid(chip, port, pvid: &pvid); |
2717 | if (err) |
2718 | goto unlock; |
2719 | |
2720 | err = mv88e6xxx_port_vlan_leave(chip, port, vid: vlan->vid); |
2721 | if (err) |
2722 | goto unlock; |
2723 | |
2724 | if (vlan->vid == pvid) { |
2725 | p->bridge_pvid.valid = false; |
2726 | |
2727 | err = mv88e6xxx_port_commit_pvid(chip, port); |
2728 | if (err) |
2729 | goto unlock; |
2730 | } |
2731 | |
2732 | unlock: |
2733 | mv88e6xxx_reg_unlock(chip); |
2734 | |
2735 | return err; |
2736 | } |
2737 | |
2738 | static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) |
2739 | { |
2740 | struct mv88e6xxx_chip *chip = ds->priv; |
2741 | struct mv88e6xxx_vtu_entry vlan; |
2742 | int err; |
2743 | |
2744 | mv88e6xxx_reg_lock(chip); |
2745 | |
2746 | err = mv88e6xxx_vtu_get(chip, vid, entry: &vlan); |
2747 | if (err) |
2748 | goto unlock; |
2749 | |
2750 | err = mv88e6xxx_port_fast_age_fid(chip, port, fid: vlan.fid); |
2751 | |
2752 | unlock: |
2753 | mv88e6xxx_reg_unlock(chip); |
2754 | |
2755 | return err; |
2756 | } |
2757 | |
2758 | static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, |
2759 | struct dsa_bridge bridge, |
2760 | const struct switchdev_vlan_msti *msti) |
2761 | { |
2762 | struct mv88e6xxx_chip *chip = ds->priv; |
2763 | struct mv88e6xxx_vtu_entry vlan; |
2764 | u8 old_sid, new_sid; |
2765 | int err; |
2766 | |
2767 | if (!mv88e6xxx_has_stu(chip)) |
2768 | return -EOPNOTSUPP; |
2769 | |
2770 | mv88e6xxx_reg_lock(chip); |
2771 | |
2772 | err = mv88e6xxx_vtu_get(chip, vid: msti->vid, entry: &vlan); |
2773 | if (err) |
2774 | goto unlock; |
2775 | |
2776 | if (!vlan.valid) { |
2777 | err = -EINVAL; |
2778 | goto unlock; |
2779 | } |
2780 | |
2781 | old_sid = vlan.sid; |
2782 | |
2783 | err = mv88e6xxx_mst_get(chip, br: bridge.dev, msti: msti->msti, sid: &new_sid); |
2784 | if (err) |
2785 | goto unlock; |
2786 | |
2787 | if (new_sid != old_sid) { |
2788 | vlan.sid = new_sid; |
2789 | |
2790 | err = mv88e6xxx_vtu_loadpurge(chip, entry: &vlan); |
2791 | if (err) { |
2792 | mv88e6xxx_mst_put(chip, sid: new_sid); |
2793 | goto unlock; |
2794 | } |
2795 | } |
2796 | |
2797 | err = mv88e6xxx_mst_put(chip, sid: old_sid); |
2798 | |
2799 | unlock: |
2800 | mv88e6xxx_reg_unlock(chip); |
2801 | return err; |
2802 | } |
2803 | |
2804 | static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
2805 | const unsigned char *addr, u16 vid, |
2806 | struct dsa_db db) |
2807 | { |
2808 | struct mv88e6xxx_chip *chip = ds->priv; |
2809 | int err; |
2810 | |
2811 | mv88e6xxx_reg_lock(chip); |
2812 | err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, |
2813 | MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); |
2814 | mv88e6xxx_reg_unlock(chip); |
2815 | |
2816 | return err; |
2817 | } |
2818 | |
2819 | static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
2820 | const unsigned char *addr, u16 vid, |
2821 | struct dsa_db db) |
2822 | { |
2823 | struct mv88e6xxx_chip *chip = ds->priv; |
2824 | int err; |
2825 | |
2826 | mv88e6xxx_reg_lock(chip); |
2827 | err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, state: 0); |
2828 | mv88e6xxx_reg_unlock(chip); |
2829 | |
2830 | return err; |
2831 | } |
2832 | |
2833 | static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, |
2834 | u16 fid, u16 vid, int port, |
2835 | dsa_fdb_dump_cb_t *cb, void *data) |
2836 | { |
2837 | struct mv88e6xxx_atu_entry addr; |
2838 | bool is_static; |
2839 | int err; |
2840 | |
2841 | addr.state = 0; |
2842 | eth_broadcast_addr(addr: addr.mac); |
2843 | |
2844 | do { |
2845 | err = mv88e6xxx_g1_atu_getnext(chip, fid, entry: &addr); |
2846 | if (err) |
2847 | return err; |
2848 | |
2849 | if (!addr.state) |
2850 | break; |
2851 | |
2852 | if (addr.trunk || (addr.portvec & BIT(port)) == 0) |
2853 | continue; |
2854 | |
2855 | if (!is_unicast_ether_addr(addr: addr.mac)) |
2856 | continue; |
2857 | |
2858 | is_static = (addr.state == |
2859 | MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); |
2860 | err = cb(addr.mac, vid, is_static, data); |
2861 | if (err) |
2862 | return err; |
2863 | } while (!is_broadcast_ether_addr(addr: addr.mac)); |
2864 | |
2865 | return err; |
2866 | } |
2867 | |
2868 | struct mv88e6xxx_port_db_dump_vlan_ctx { |
2869 | int port; |
2870 | dsa_fdb_dump_cb_t *cb; |
2871 | void *data; |
2872 | }; |
2873 | |
2874 | static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, |
2875 | const struct mv88e6xxx_vtu_entry *entry, |
2876 | void *_data) |
2877 | { |
2878 | struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; |
2879 | |
2880 | return mv88e6xxx_port_db_dump_fid(chip, fid: entry->fid, vid: entry->vid, |
2881 | port: ctx->port, cb: ctx->cb, data: ctx->data); |
2882 | } |
2883 | |
2884 | static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, |
2885 | dsa_fdb_dump_cb_t *cb, void *data) |
2886 | { |
2887 | struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { |
2888 | .port = port, |
2889 | .cb = cb, |
2890 | .data = data, |
2891 | }; |
2892 | u16 fid; |
2893 | int err; |
2894 | |
2895 | /* Dump port's default Filtering Information Database (VLAN ID 0) */ |
2896 | err = mv88e6xxx_port_get_fid(chip, port, fid: &fid); |
2897 | if (err) |
2898 | return err; |
2899 | |
2900 | err = mv88e6xxx_port_db_dump_fid(chip, fid, vid: 0, port, cb, data); |
2901 | if (err) |
2902 | return err; |
2903 | |
2904 | return mv88e6xxx_vtu_walk(chip, cb: mv88e6xxx_port_db_dump_vlan, priv: &ctx); |
2905 | } |
2906 | |
2907 | static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, |
2908 | dsa_fdb_dump_cb_t *cb, void *data) |
2909 | { |
2910 | struct mv88e6xxx_chip *chip = ds->priv; |
2911 | int err; |
2912 | |
2913 | mv88e6xxx_reg_lock(chip); |
2914 | err = mv88e6xxx_port_db_dump(chip, port, cb, data); |
2915 | mv88e6xxx_reg_unlock(chip); |
2916 | |
2917 | return err; |
2918 | } |
2919 | |
2920 | static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, |
2921 | struct dsa_bridge bridge) |
2922 | { |
2923 | struct dsa_switch *ds = chip->ds; |
2924 | struct dsa_switch_tree *dst = ds->dst; |
2925 | struct dsa_port *dp; |
2926 | int err; |
2927 | |
2928 | list_for_each_entry(dp, &dst->ports, list) { |
2929 | if (dsa_port_offloads_bridge(dp, bridge: &bridge)) { |
2930 | if (dp->ds == ds) { |
2931 | /* This is a local bridge group member, |
2932 | * remap its Port VLAN Map. |
2933 | */ |
2934 | err = mv88e6xxx_port_vlan_map(chip, port: dp->index); |
2935 | if (err) |
2936 | return err; |
2937 | } else { |
2938 | /* This is an external bridge group member, |
2939 | * remap its cross-chip Port VLAN Table entry. |
2940 | */ |
2941 | err = mv88e6xxx_pvt_map(chip, dev: dp->ds->index, |
2942 | port: dp->index); |
2943 | if (err) |
2944 | return err; |
2945 | } |
2946 | } |
2947 | } |
2948 | |
2949 | return 0; |
2950 | } |
2951 | |
2952 | /* Treat the software bridge as a virtual single-port switch behind the |
2953 | * CPU and map in the PVT. First dst->last_switch elements are taken by |
2954 | * physical switches, so start from beyond that range. |
2955 | */ |
2956 | static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, |
2957 | unsigned int bridge_num) |
2958 | { |
2959 | u8 dev = bridge_num + ds->dst->last_switch; |
2960 | struct mv88e6xxx_chip *chip = ds->priv; |
2961 | |
2962 | return mv88e6xxx_pvt_map(chip, dev, port: 0); |
2963 | } |
2964 | |
2965 | static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, |
2966 | struct dsa_bridge bridge, |
2967 | bool *tx_fwd_offload, |
2968 | struct netlink_ext_ack *extack) |
2969 | { |
2970 | struct mv88e6xxx_chip *chip = ds->priv; |
2971 | int err; |
2972 | |
2973 | mv88e6xxx_reg_lock(chip); |
2974 | |
2975 | err = mv88e6xxx_bridge_map(chip, bridge); |
2976 | if (err) |
2977 | goto unlock; |
2978 | |
2979 | err = mv88e6xxx_port_set_map_da(chip, port, map: true); |
2980 | if (err) |
2981 | goto unlock; |
2982 | |
2983 | err = mv88e6xxx_port_commit_pvid(chip, port); |
2984 | if (err) |
2985 | goto unlock; |
2986 | |
2987 | if (mv88e6xxx_has_pvt(chip)) { |
2988 | err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num: bridge.num); |
2989 | if (err) |
2990 | goto unlock; |
2991 | |
2992 | *tx_fwd_offload = true; |
2993 | } |
2994 | |
2995 | unlock: |
2996 | mv88e6xxx_reg_unlock(chip); |
2997 | |
2998 | return err; |
2999 | } |
3000 | |
3001 | static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, |
3002 | struct dsa_bridge bridge) |
3003 | { |
3004 | struct mv88e6xxx_chip *chip = ds->priv; |
3005 | int err; |
3006 | |
3007 | mv88e6xxx_reg_lock(chip); |
3008 | |
3009 | if (bridge.tx_fwd_offload && |
3010 | mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num: bridge.num)) |
3011 | dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n" ); |
3012 | |
3013 | if (mv88e6xxx_bridge_map(chip, bridge) || |
3014 | mv88e6xxx_port_vlan_map(chip, port)) |
3015 | dev_err(ds->dev, "failed to remap in-chip Port VLAN\n" ); |
3016 | |
3017 | err = mv88e6xxx_port_set_map_da(chip, port, map: false); |
3018 | if (err) |
3019 | dev_err(ds->dev, |
3020 | "port %d failed to restore map-DA: %pe\n" , |
3021 | port, ERR_PTR(err)); |
3022 | |
3023 | err = mv88e6xxx_port_commit_pvid(chip, port); |
3024 | if (err) |
3025 | dev_err(ds->dev, |
3026 | "port %d failed to restore standalone pvid: %pe\n" , |
3027 | port, ERR_PTR(err)); |
3028 | |
3029 | mv88e6xxx_reg_unlock(chip); |
3030 | } |
3031 | |
3032 | static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, |
3033 | int tree_index, int sw_index, |
3034 | int port, struct dsa_bridge bridge, |
3035 | struct netlink_ext_ack *extack) |
3036 | { |
3037 | struct mv88e6xxx_chip *chip = ds->priv; |
3038 | int err; |
3039 | |
3040 | if (tree_index != ds->dst->index) |
3041 | return 0; |
3042 | |
3043 | mv88e6xxx_reg_lock(chip); |
3044 | err = mv88e6xxx_pvt_map(chip, dev: sw_index, port); |
3045 | err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num: bridge.num); |
3046 | mv88e6xxx_reg_unlock(chip); |
3047 | |
3048 | return err; |
3049 | } |
3050 | |
3051 | static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, |
3052 | int tree_index, int sw_index, |
3053 | int port, struct dsa_bridge bridge) |
3054 | { |
3055 | struct mv88e6xxx_chip *chip = ds->priv; |
3056 | |
3057 | if (tree_index != ds->dst->index) |
3058 | return; |
3059 | |
3060 | mv88e6xxx_reg_lock(chip); |
3061 | if (mv88e6xxx_pvt_map(chip, dev: sw_index, port) || |
3062 | mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num: bridge.num)) |
3063 | dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n" ); |
3064 | mv88e6xxx_reg_unlock(chip); |
3065 | } |
3066 | |
3067 | static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) |
3068 | { |
3069 | if (chip->info->ops->reset) |
3070 | return chip->info->ops->reset(chip); |
3071 | |
3072 | return 0; |
3073 | } |
3074 | |
3075 | static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) |
3076 | { |
3077 | struct gpio_desc *gpiod = chip->reset; |
3078 | |
3079 | /* If there is a GPIO connected to the reset pin, toggle it */ |
3080 | if (gpiod) { |
3081 | /* If the switch has just been reset and not yet completed |
3082 | * loading EEPROM, the reset may interrupt the I2C transaction |
3083 | * mid-byte, causing the first EEPROM read after the reset |
3084 | * from the wrong location resulting in the switch booting |
3085 | * to wrong mode and inoperable. |
3086 | */ |
3087 | if (chip->info->ops->get_eeprom) |
3088 | mv88e6xxx_g2_eeprom_wait(chip); |
3089 | |
3090 | gpiod_set_value_cansleep(desc: gpiod, value: 1); |
3091 | usleep_range(min: 10000, max: 20000); |
3092 | gpiod_set_value_cansleep(desc: gpiod, value: 0); |
3093 | usleep_range(min: 10000, max: 20000); |
3094 | |
3095 | if (chip->info->ops->get_eeprom) |
3096 | mv88e6xxx_g2_eeprom_wait(chip); |
3097 | } |
3098 | } |
3099 | |
3100 | static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) |
3101 | { |
3102 | int i, err; |
3103 | |
3104 | /* Set all ports to the Disabled state */ |
3105 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
3106 | err = mv88e6xxx_port_set_state(chip, port: i, BR_STATE_DISABLED); |
3107 | if (err) |
3108 | return err; |
3109 | } |
3110 | |
3111 | /* Wait for transmit queues to drain, |
3112 | * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. |
3113 | */ |
3114 | usleep_range(min: 2000, max: 4000); |
3115 | |
3116 | return 0; |
3117 | } |
3118 | |
3119 | static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) |
3120 | { |
3121 | int err; |
3122 | |
3123 | err = mv88e6xxx_disable_ports(chip); |
3124 | if (err) |
3125 | return err; |
3126 | |
3127 | mv88e6xxx_hardware_reset(chip); |
3128 | |
3129 | return mv88e6xxx_software_reset(chip); |
3130 | } |
3131 | |
3132 | static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, |
3133 | enum mv88e6xxx_frame_mode frame, |
3134 | enum mv88e6xxx_egress_mode egress, u16 etype) |
3135 | { |
3136 | int err; |
3137 | |
3138 | if (!chip->info->ops->port_set_frame_mode) |
3139 | return -EOPNOTSUPP; |
3140 | |
3141 | err = mv88e6xxx_port_set_egress_mode(chip, port, mode: egress); |
3142 | if (err) |
3143 | return err; |
3144 | |
3145 | err = chip->info->ops->port_set_frame_mode(chip, port, frame); |
3146 | if (err) |
3147 | return err; |
3148 | |
3149 | if (chip->info->ops->port_set_ether_type) |
3150 | return chip->info->ops->port_set_ether_type(chip, port, etype); |
3151 | |
3152 | return 0; |
3153 | } |
3154 | |
3155 | static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) |
3156 | { |
3157 | return mv88e6xxx_set_port_mode(chip, port, frame: MV88E6XXX_FRAME_MODE_NORMAL, |
3158 | egress: MV88E6XXX_EGRESS_MODE_UNMODIFIED, |
3159 | MV88E6XXX_PORT_ETH_TYPE_DEFAULT); |
3160 | } |
3161 | |
3162 | static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) |
3163 | { |
3164 | return mv88e6xxx_set_port_mode(chip, port, frame: MV88E6XXX_FRAME_MODE_DSA, |
3165 | egress: MV88E6XXX_EGRESS_MODE_UNMODIFIED, |
3166 | MV88E6XXX_PORT_ETH_TYPE_DEFAULT); |
3167 | } |
3168 | |
3169 | static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) |
3170 | { |
3171 | return mv88e6xxx_set_port_mode(chip, port, |
3172 | frame: MV88E6XXX_FRAME_MODE_ETHERTYPE, |
3173 | egress: MV88E6XXX_EGRESS_MODE_ETHERTYPE, |
3174 | ETH_P_EDSA); |
3175 | } |
3176 | |
3177 | static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) |
3178 | { |
3179 | if (dsa_is_dsa_port(ds: chip->ds, p: port)) |
3180 | return mv88e6xxx_set_port_mode_dsa(chip, port); |
3181 | |
3182 | if (dsa_is_user_port(ds: chip->ds, p: port)) |
3183 | return mv88e6xxx_set_port_mode_normal(chip, port); |
3184 | |
3185 | /* Setup CPU port mode depending on its supported tag format */ |
3186 | if (chip->tag_protocol == DSA_TAG_PROTO_DSA) |
3187 | return mv88e6xxx_set_port_mode_dsa(chip, port); |
3188 | |
3189 | if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) |
3190 | return mv88e6xxx_set_port_mode_edsa(chip, port); |
3191 | |
3192 | return -EINVAL; |
3193 | } |
3194 | |
3195 | static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) |
3196 | { |
3197 | bool message = dsa_is_dsa_port(ds: chip->ds, p: port); |
3198 | |
3199 | return mv88e6xxx_port_set_message_port(chip, port, message_port: message); |
3200 | } |
3201 | |
3202 | static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) |
3203 | { |
3204 | int err; |
3205 | |
3206 | if (chip->info->ops->port_set_ucast_flood) { |
3207 | err = chip->info->ops->port_set_ucast_flood(chip, port, true); |
3208 | if (err) |
3209 | return err; |
3210 | } |
3211 | if (chip->info->ops->port_set_mcast_flood) { |
3212 | err = chip->info->ops->port_set_mcast_flood(chip, port, true); |
3213 | if (err) |
3214 | return err; |
3215 | } |
3216 | |
3217 | return 0; |
3218 | } |
3219 | |
3220 | static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, |
3221 | enum mv88e6xxx_egress_direction direction, |
3222 | int port) |
3223 | { |
3224 | int err; |
3225 | |
3226 | if (!chip->info->ops->set_egress_port) |
3227 | return -EOPNOTSUPP; |
3228 | |
3229 | err = chip->info->ops->set_egress_port(chip, direction, port); |
3230 | if (err) |
3231 | return err; |
3232 | |
3233 | if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) |
3234 | chip->ingress_dest_port = port; |
3235 | else |
3236 | chip->egress_dest_port = port; |
3237 | |
3238 | return 0; |
3239 | } |
3240 | |
3241 | static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) |
3242 | { |
3243 | struct dsa_switch *ds = chip->ds; |
3244 | int upstream_port; |
3245 | int err; |
3246 | |
3247 | upstream_port = dsa_upstream_port(ds, port); |
3248 | if (chip->info->ops->port_set_upstream_port) { |
3249 | err = chip->info->ops->port_set_upstream_port(chip, port, |
3250 | upstream_port); |
3251 | if (err) |
3252 | return err; |
3253 | } |
3254 | |
3255 | if (port == upstream_port) { |
3256 | if (chip->info->ops->set_cpu_port) { |
3257 | err = chip->info->ops->set_cpu_port(chip, |
3258 | upstream_port); |
3259 | if (err) |
3260 | return err; |
3261 | } |
3262 | |
3263 | err = mv88e6xxx_set_egress_port(chip, |
3264 | direction: MV88E6XXX_EGRESS_DIR_INGRESS, |
3265 | port: upstream_port); |
3266 | if (err && err != -EOPNOTSUPP) |
3267 | return err; |
3268 | |
3269 | err = mv88e6xxx_set_egress_port(chip, |
3270 | direction: MV88E6XXX_EGRESS_DIR_EGRESS, |
3271 | port: upstream_port); |
3272 | if (err && err != -EOPNOTSUPP) |
3273 | return err; |
3274 | } |
3275 | |
3276 | return 0; |
3277 | } |
3278 | |
3279 | static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) |
3280 | { |
3281 | struct device_node *phy_handle = NULL; |
3282 | struct dsa_switch *ds = chip->ds; |
3283 | struct dsa_port *dp; |
3284 | int tx_amp; |
3285 | int err; |
3286 | u16 reg; |
3287 | |
3288 | chip->ports[port].chip = chip; |
3289 | chip->ports[port].port = port; |
3290 | |
3291 | err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, |
3292 | SPEED_UNFORCED, DUPLEX_UNFORCED, |
3293 | PAUSE_ON, mode: PHY_INTERFACE_MODE_NA); |
3294 | if (err) |
3295 | return err; |
3296 | |
3297 | /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, |
3298 | * disable Header mode, enable IGMP/MLD snooping, disable VLAN |
3299 | * tunneling, determine priority by looking at 802.1p and IP |
3300 | * priority fields (IP prio has precedence), and set STP state |
3301 | * to Forwarding. |
3302 | * |
3303 | * If this is the CPU link, use DSA or EDSA tagging depending |
3304 | * on which tagging mode was configured. |
3305 | * |
3306 | * If this is a link to another switch, use DSA tagging mode. |
3307 | * |
3308 | * If this is the upstream port for this switch, enable |
3309 | * forwarding of unknown unicasts and multicasts. |
3310 | */ |
3311 | reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | |
3312 | MV88E6XXX_PORT_CTL0_STATE_FORWARDING; |
3313 | /* Forward any IPv4 IGMP or IPv6 MLD frames received |
3314 | * by a USER port to the CPU port to allow snooping. |
3315 | */ |
3316 | if (dsa_is_user_port(ds, p: port)) |
3317 | reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; |
3318 | |
3319 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, val: reg); |
3320 | if (err) |
3321 | return err; |
3322 | |
3323 | err = mv88e6xxx_setup_port_mode(chip, port); |
3324 | if (err) |
3325 | return err; |
3326 | |
3327 | err = mv88e6xxx_setup_egress_floods(chip, port); |
3328 | if (err) |
3329 | return err; |
3330 | |
3331 | /* Port Control 2: don't force a good FCS, set the MTU size to |
3332 | * 10222 bytes, disable 802.1q tags checking, don't discard |
3333 | * tagged or untagged frames on this port, skip destination |
3334 | * address lookup on user ports, disable ARP mirroring and don't |
3335 | * send a copy of all transmitted/received frames on this port |
3336 | * to the CPU. |
3337 | */ |
3338 | err = mv88e6xxx_port_set_map_da(chip, port, map: !dsa_is_user_port(ds, p: port)); |
3339 | if (err) |
3340 | return err; |
3341 | |
3342 | err = mv88e6xxx_setup_upstream_port(chip, port); |
3343 | if (err) |
3344 | return err; |
3345 | |
3346 | /* On chips that support it, set all downstream DSA ports' |
3347 | * VLAN policy to TRAP. In combination with loading |
3348 | * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this |
3349 | * provides a better isolation barrier between standalone |
3350 | * ports, as the ATU is bypassed on any intermediate switches |
3351 | * between the incoming port and the CPU. |
3352 | */ |
3353 | if (dsa_is_downstream_port(ds, port) && |
3354 | chip->info->ops->port_set_policy) { |
3355 | err = chip->info->ops->port_set_policy(chip, port, |
3356 | MV88E6XXX_POLICY_MAPPING_VTU, |
3357 | MV88E6XXX_POLICY_ACTION_TRAP); |
3358 | if (err) |
3359 | return err; |
3360 | } |
3361 | |
3362 | /* User ports start out in standalone mode and 802.1Q is |
3363 | * therefore disabled. On DSA ports, all valid VIDs are always |
3364 | * loaded in the VTU - therefore, enable 802.1Q in order to take |
3365 | * advantage of VLAN policy on chips that supports it. |
3366 | */ |
3367 | err = mv88e6xxx_port_set_8021q_mode(chip, port, |
3368 | mode: dsa_is_user_port(ds, p: port) ? |
3369 | MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : |
3370 | MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); |
3371 | if (err) |
3372 | return err; |
3373 | |
3374 | /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by |
3375 | * virtue of the fact that mv88e6xxx_atu_new() will pick it as |
3376 | * the first free FID. This will be used as the private PVID for |
3377 | * unbridged ports. Shared (DSA and CPU) ports must also be |
3378 | * members of this VID, in order to trap all frames assigned to |
3379 | * it to the CPU. |
3380 | */ |
3381 | err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, |
3382 | MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, |
3383 | warn: false); |
3384 | if (err) |
3385 | return err; |
3386 | |
3387 | /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the |
3388 | * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as |
3389 | * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used |
3390 | * as the private PVID on ports under a VLAN-unaware bridge. |
3391 | * Shared (DSA and CPU) ports must also be members of it, to translate |
3392 | * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of |
3393 | * relying on their port default FID. |
3394 | */ |
3395 | err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, |
3396 | MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, |
3397 | warn: false); |
3398 | if (err) |
3399 | return err; |
3400 | |
3401 | if (chip->info->ops->port_set_jumbo_size) { |
3402 | err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); |
3403 | if (err) |
3404 | return err; |
3405 | } |
3406 | |
3407 | /* Port Association Vector: disable automatic address learning |
3408 | * on all user ports since they start out in standalone |
3409 | * mode. When joining a bridge, learning will be configured to |
3410 | * match the bridge port settings. Enable learning on all |
3411 | * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the |
3412 | * learning process. |
3413 | * |
3414 | * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, |
3415 | * and RefreshLocked. I.e. setup standard automatic learning. |
3416 | */ |
3417 | if (dsa_is_user_port(ds, p: port)) |
3418 | reg = 0; |
3419 | else |
3420 | reg = 1 << port; |
3421 | |
3422 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, |
3423 | val: reg); |
3424 | if (err) |
3425 | return err; |
3426 | |
3427 | /* Egress rate control 2: disable egress rate control. */ |
3428 | err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, |
3429 | val: 0x0000); |
3430 | if (err) |
3431 | return err; |
3432 | |
3433 | if (chip->info->ops->port_pause_limit) { |
3434 | err = chip->info->ops->port_pause_limit(chip, port, 0, 0); |
3435 | if (err) |
3436 | return err; |
3437 | } |
3438 | |
3439 | if (chip->info->ops->port_disable_learn_limit) { |
3440 | err = chip->info->ops->port_disable_learn_limit(chip, port); |
3441 | if (err) |
3442 | return err; |
3443 | } |
3444 | |
3445 | if (chip->info->ops->port_disable_pri_override) { |
3446 | err = chip->info->ops->port_disable_pri_override(chip, port); |
3447 | if (err) |
3448 | return err; |
3449 | } |
3450 | |
3451 | if (chip->info->ops->port_tag_remap) { |
3452 | err = chip->info->ops->port_tag_remap(chip, port); |
3453 | if (err) |
3454 | return err; |
3455 | } |
3456 | |
3457 | if (chip->info->ops->port_egress_rate_limiting) { |
3458 | err = chip->info->ops->port_egress_rate_limiting(chip, port); |
3459 | if (err) |
3460 | return err; |
3461 | } |
3462 | |
3463 | if (chip->info->ops->port_setup_message_port) { |
3464 | err = chip->info->ops->port_setup_message_port(chip, port); |
3465 | if (err) |
3466 | return err; |
3467 | } |
3468 | |
3469 | if (chip->info->ops->serdes_set_tx_amplitude) { |
3470 | dp = dsa_to_port(ds, p: port); |
3471 | if (dp) |
3472 | phy_handle = of_parse_phandle(np: dp->dn, phandle_name: "phy-handle" , index: 0); |
3473 | |
3474 | if (phy_handle && !of_property_read_u32(np: phy_handle, |
3475 | propname: "tx-p2p-microvolt" , |
3476 | out_value: &tx_amp)) |
3477 | err = chip->info->ops->serdes_set_tx_amplitude(chip, |
3478 | port, tx_amp); |
3479 | if (phy_handle) { |
3480 | of_node_put(node: phy_handle); |
3481 | if (err) |
3482 | return err; |
3483 | } |
3484 | } |
3485 | |
3486 | /* Port based VLAN map: give each port the same default address |
3487 | * database, and allow bidirectional communication between the |
3488 | * CPU and DSA port(s), and the other ports. |
3489 | */ |
3490 | err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); |
3491 | if (err) |
3492 | return err; |
3493 | |
3494 | err = mv88e6xxx_port_vlan_map(chip, port); |
3495 | if (err) |
3496 | return err; |
3497 | |
3498 | /* Default VLAN ID and priority: don't set a default VLAN |
3499 | * ID, and set the default packet priority to zero. |
3500 | */ |
3501 | return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, val: 0); |
3502 | } |
3503 | |
3504 | static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) |
3505 | { |
3506 | struct mv88e6xxx_chip *chip = ds->priv; |
3507 | |
3508 | if (chip->info->ops->port_set_jumbo_size) |
3509 | return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; |
3510 | else if (chip->info->ops->set_max_frame_size) |
3511 | return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; |
3512 | return ETH_DATA_LEN; |
3513 | } |
3514 | |
3515 | static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) |
3516 | { |
3517 | struct mv88e6xxx_chip *chip = ds->priv; |
3518 | int ret = 0; |
3519 | |
3520 | /* For families where we don't know how to alter the MTU, |
3521 | * just accept any value up to ETH_DATA_LEN |
3522 | */ |
3523 | if (!chip->info->ops->port_set_jumbo_size && |
3524 | !chip->info->ops->set_max_frame_size) { |
3525 | if (new_mtu > ETH_DATA_LEN) |
3526 | return -EINVAL; |
3527 | |
3528 | return 0; |
3529 | } |
3530 | |
3531 | if (dsa_is_dsa_port(ds, p: port) || dsa_is_cpu_port(ds, p: port)) |
3532 | new_mtu += EDSA_HLEN; |
3533 | |
3534 | mv88e6xxx_reg_lock(chip); |
3535 | if (chip->info->ops->port_set_jumbo_size) |
3536 | ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); |
3537 | else if (chip->info->ops->set_max_frame_size) |
3538 | ret = chip->info->ops->set_max_frame_size(chip, new_mtu); |
3539 | mv88e6xxx_reg_unlock(chip); |
3540 | |
3541 | return ret; |
3542 | } |
3543 | |
3544 | static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, |
3545 | unsigned int ageing_time) |
3546 | { |
3547 | struct mv88e6xxx_chip *chip = ds->priv; |
3548 | int err; |
3549 | |
3550 | mv88e6xxx_reg_lock(chip); |
3551 | err = mv88e6xxx_g1_atu_set_age_time(chip, msecs: ageing_time); |
3552 | mv88e6xxx_reg_unlock(chip); |
3553 | |
3554 | return err; |
3555 | } |
3556 | |
3557 | static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) |
3558 | { |
3559 | int err; |
3560 | |
3561 | /* Initialize the statistics unit */ |
3562 | if (chip->info->ops->stats_set_histogram) { |
3563 | err = chip->info->ops->stats_set_histogram(chip); |
3564 | if (err) |
3565 | return err; |
3566 | } |
3567 | |
3568 | return mv88e6xxx_g1_stats_clear(chip); |
3569 | } |
3570 | |
3571 | /* Check if the errata has already been applied. */ |
3572 | static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) |
3573 | { |
3574 | int port; |
3575 | int err; |
3576 | u16 val; |
3577 | |
3578 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { |
3579 | err = mv88e6xxx_port_hidden_read(chip, block: 0xf, port, reg: 0, val: &val); |
3580 | if (err) { |
3581 | dev_err(chip->dev, |
3582 | "Error reading hidden register: %d\n" , err); |
3583 | return false; |
3584 | } |
3585 | if (val != 0x01c0) |
3586 | return false; |
3587 | } |
3588 | |
3589 | return true; |
3590 | } |
3591 | |
3592 | /* The 6390 copper ports have an errata which require poking magic |
3593 | * values into undocumented hidden registers and then performing a |
3594 | * software reset. |
3595 | */ |
3596 | static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) |
3597 | { |
3598 | int port; |
3599 | int err; |
3600 | |
3601 | if (mv88e6390_setup_errata_applied(chip)) |
3602 | return 0; |
3603 | |
3604 | /* Set the ports into blocking mode */ |
3605 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { |
3606 | err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); |
3607 | if (err) |
3608 | return err; |
3609 | } |
3610 | |
3611 | for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { |
3612 | err = mv88e6xxx_port_hidden_write(chip, block: 0xf, port, reg: 0, val: 0x01c0); |
3613 | if (err) |
3614 | return err; |
3615 | } |
3616 | |
3617 | return mv88e6xxx_software_reset(chip); |
3618 | } |
3619 | |
3620 | /* prod_id for switch families which do not have a PHY model number */ |
3621 | static const u16 family_prod_id_table[] = { |
3622 | [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, |
3623 | [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, |
3624 | [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, |
3625 | }; |
3626 | |
3627 | static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) |
3628 | { |
3629 | struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; |
3630 | struct mv88e6xxx_chip *chip = mdio_bus->chip; |
3631 | u16 prod_id; |
3632 | u16 val; |
3633 | int err; |
3634 | |
3635 | if (!chip->info->ops->phy_read) |
3636 | return -EOPNOTSUPP; |
3637 | |
3638 | mv88e6xxx_reg_lock(chip); |
3639 | err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); |
3640 | mv88e6xxx_reg_unlock(chip); |
3641 | |
3642 | /* Some internal PHYs don't have a model number. */ |
3643 | if (reg == MII_PHYSID2 && !(val & 0x3f0) && |
3644 | chip->info->family < ARRAY_SIZE(family_prod_id_table)) { |
3645 | prod_id = family_prod_id_table[chip->info->family]; |
3646 | if (prod_id) |
3647 | val |= prod_id >> 4; |
3648 | } |
3649 | |
3650 | return err ? err : val; |
3651 | } |
3652 | |
3653 | static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, |
3654 | int reg) |
3655 | { |
3656 | struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; |
3657 | struct mv88e6xxx_chip *chip = mdio_bus->chip; |
3658 | u16 val; |
3659 | int err; |
3660 | |
3661 | if (!chip->info->ops->phy_read_c45) |
3662 | return -ENODEV; |
3663 | |
3664 | mv88e6xxx_reg_lock(chip); |
3665 | err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); |
3666 | mv88e6xxx_reg_unlock(chip); |
3667 | |
3668 | return err ? err : val; |
3669 | } |
3670 | |
3671 | static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) |
3672 | { |
3673 | struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; |
3674 | struct mv88e6xxx_chip *chip = mdio_bus->chip; |
3675 | int err; |
3676 | |
3677 | if (!chip->info->ops->phy_write) |
3678 | return -EOPNOTSUPP; |
3679 | |
3680 | mv88e6xxx_reg_lock(chip); |
3681 | err = chip->info->ops->phy_write(chip, bus, phy, reg, val); |
3682 | mv88e6xxx_reg_unlock(chip); |
3683 | |
3684 | return err; |
3685 | } |
3686 | |
3687 | static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, |
3688 | int reg, u16 val) |
3689 | { |
3690 | struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; |
3691 | struct mv88e6xxx_chip *chip = mdio_bus->chip; |
3692 | int err; |
3693 | |
3694 | if (!chip->info->ops->phy_write_c45) |
3695 | return -EOPNOTSUPP; |
3696 | |
3697 | mv88e6xxx_reg_lock(chip); |
3698 | err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); |
3699 | mv88e6xxx_reg_unlock(chip); |
3700 | |
3701 | return err; |
3702 | } |
3703 | |
3704 | static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, |
3705 | struct device_node *np, |
3706 | bool external) |
3707 | { |
3708 | static int index; |
3709 | struct mv88e6xxx_mdio_bus *mdio_bus; |
3710 | struct mii_bus *bus; |
3711 | int err; |
3712 | |
3713 | if (external) { |
3714 | mv88e6xxx_reg_lock(chip); |
3715 | if (chip->info->family == MV88E6XXX_FAMILY_6393) |
3716 | err = mv88e6393x_g2_scratch_gpio_set_smi(chip, external: true); |
3717 | else |
3718 | err = mv88e6390_g2_scratch_gpio_set_smi(chip, external: true); |
3719 | mv88e6xxx_reg_unlock(chip); |
3720 | |
3721 | if (err) |
3722 | return err; |
3723 | } |
3724 | |
3725 | bus = mdiobus_alloc_size(size: sizeof(*mdio_bus)); |
3726 | if (!bus) |
3727 | return -ENOMEM; |
3728 | |
3729 | mdio_bus = bus->priv; |
3730 | mdio_bus->bus = bus; |
3731 | mdio_bus->chip = chip; |
3732 | INIT_LIST_HEAD(list: &mdio_bus->list); |
3733 | mdio_bus->external = external; |
3734 | |
3735 | if (np) { |
3736 | bus->name = np->full_name; |
3737 | snprintf(buf: bus->id, MII_BUS_ID_SIZE, fmt: "%pOF" , np); |
3738 | } else { |
3739 | bus->name = "mv88e6xxx SMI" ; |
3740 | snprintf(buf: bus->id, MII_BUS_ID_SIZE, fmt: "mv88e6xxx-%d" , index++); |
3741 | } |
3742 | |
3743 | bus->read = mv88e6xxx_mdio_read; |
3744 | bus->write = mv88e6xxx_mdio_write; |
3745 | bus->read_c45 = mv88e6xxx_mdio_read_c45; |
3746 | bus->write_c45 = mv88e6xxx_mdio_write_c45; |
3747 | bus->parent = chip->dev; |
3748 | bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + |
3749 | mv88e6xxx_num_ports(chip) - 1, |
3750 | chip->info->phy_base_addr); |
3751 | |
3752 | if (!external) { |
3753 | err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); |
3754 | if (err) |
3755 | goto out; |
3756 | } |
3757 | |
3758 | err = of_mdiobus_register(mdio: bus, np); |
3759 | if (err) { |
3760 | dev_err(chip->dev, "Cannot register MDIO bus (%d)\n" , err); |
3761 | mv88e6xxx_g2_irq_mdio_free(chip, bus); |
3762 | goto out; |
3763 | } |
3764 | |
3765 | if (external) |
3766 | list_add_tail(new: &mdio_bus->list, head: &chip->mdios); |
3767 | else |
3768 | list_add(new: &mdio_bus->list, head: &chip->mdios); |
3769 | |
3770 | return 0; |
3771 | |
3772 | out: |
3773 | mdiobus_free(bus); |
3774 | return err; |
3775 | } |
3776 | |
3777 | static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) |
3778 | |
3779 | { |
3780 | struct mv88e6xxx_mdio_bus *mdio_bus, *p; |
3781 | struct mii_bus *bus; |
3782 | |
3783 | list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { |
3784 | bus = mdio_bus->bus; |
3785 | |
3786 | if (!mdio_bus->external) |
3787 | mv88e6xxx_g2_irq_mdio_free(chip, bus); |
3788 | |
3789 | mdiobus_unregister(bus); |
3790 | mdiobus_free(bus); |
3791 | } |
3792 | } |
3793 | |
3794 | static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) |
3795 | { |
3796 | struct device_node *np = chip->dev->of_node; |
3797 | struct device_node *child; |
3798 | int err; |
3799 | |
3800 | /* Always register one mdio bus for the internal/default mdio |
3801 | * bus. This maybe represented in the device tree, but is |
3802 | * optional. |
3803 | */ |
3804 | child = of_get_child_by_name(node: np, name: "mdio" ); |
3805 | err = mv88e6xxx_mdio_register(chip, np: child, external: false); |
3806 | of_node_put(node: child); |
3807 | if (err) |
3808 | return err; |
3809 | |
3810 | /* Walk the device tree, and see if there are any other nodes |
3811 | * which say they are compatible with the external mdio |
3812 | * bus. |
3813 | */ |
3814 | for_each_available_child_of_node(np, child) { |
3815 | if (of_device_is_compatible( |
3816 | device: child, "marvell,mv88e6xxx-mdio-external" )) { |
3817 | err = mv88e6xxx_mdio_register(chip, np: child, external: true); |
3818 | if (err) { |
3819 | mv88e6xxx_mdios_unregister(chip); |
3820 | of_node_put(node: child); |
3821 | return err; |
3822 | } |
3823 | } |
3824 | } |
3825 | |
3826 | return 0; |
3827 | } |
3828 | |
3829 | static void mv88e6xxx_teardown(struct dsa_switch *ds) |
3830 | { |
3831 | struct mv88e6xxx_chip *chip = ds->priv; |
3832 | |
3833 | mv88e6xxx_teardown_devlink_params(ds); |
3834 | dsa_devlink_resources_unregister(ds); |
3835 | mv88e6xxx_teardown_devlink_regions_global(ds); |
3836 | mv88e6xxx_mdios_unregister(chip); |
3837 | } |
3838 | |
3839 | static int mv88e6xxx_setup(struct dsa_switch *ds) |
3840 | { |
3841 | struct mv88e6xxx_chip *chip = ds->priv; |
3842 | u8 cmode; |
3843 | int err; |
3844 | int i; |
3845 | |
3846 | err = mv88e6xxx_mdios_register(chip); |
3847 | if (err) |
3848 | return err; |
3849 | |
3850 | chip->ds = ds; |
3851 | ds->user_mii_bus = mv88e6xxx_default_mdio_bus(chip); |
3852 | |
3853 | /* Since virtual bridges are mapped in the PVT, the number we support |
3854 | * depends on the physical switch topology. We need to let DSA figure |
3855 | * that out and therefore we cannot set this at dsa_register_switch() |
3856 | * time. |
3857 | */ |
3858 | if (mv88e6xxx_has_pvt(chip)) |
3859 | ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - |
3860 | ds->dst->last_switch - 1; |
3861 | |
3862 | mv88e6xxx_reg_lock(chip); |
3863 | |
3864 | if (chip->info->ops->setup_errata) { |
3865 | err = chip->info->ops->setup_errata(chip); |
3866 | if (err) |
3867 | goto unlock; |
3868 | } |
3869 | |
3870 | /* Cache the cmode of each port. */ |
3871 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
3872 | if (chip->info->ops->port_get_cmode) { |
3873 | err = chip->info->ops->port_get_cmode(chip, i, &cmode); |
3874 | if (err) |
3875 | goto unlock; |
3876 | |
3877 | chip->ports[i].cmode = cmode; |
3878 | } |
3879 | } |
3880 | |
3881 | err = mv88e6xxx_vtu_setup(chip); |
3882 | if (err) |
3883 | goto unlock; |
3884 | |
3885 | /* Must be called after mv88e6xxx_vtu_setup (which flushes the |
3886 | * VTU, thereby also flushing the STU). |
3887 | */ |
3888 | err = mv88e6xxx_stu_setup(chip); |
3889 | if (err) |
3890 | goto unlock; |
3891 | |
3892 | /* Setup Switch Port Registers */ |
3893 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { |
3894 | if (dsa_is_unused_port(ds, p: i)) |
3895 | continue; |
3896 | |
3897 | /* Prevent the use of an invalid port. */ |
3898 | if (mv88e6xxx_is_invalid_port(chip, port: i)) { |
3899 | dev_err(chip->dev, "port %d is invalid\n" , i); |
3900 | err = -EINVAL; |
3901 | goto unlock; |
3902 | } |
3903 | |
3904 | err = mv88e6xxx_setup_port(chip, port: i); |
3905 | if (err) |
3906 | goto unlock; |
3907 | } |
3908 | |
3909 | err = mv88e6xxx_irl_setup(chip); |
3910 | if (err) |
3911 | goto unlock; |
3912 | |
3913 | err = mv88e6xxx_mac_setup(chip); |
3914 | if (err) |
3915 | goto unlock; |
3916 | |
3917 | err = mv88e6xxx_phy_setup(chip); |
3918 | if (err) |
3919 | goto unlock; |
3920 | |
3921 | err = mv88e6xxx_pvt_setup(chip); |
3922 | if (err) |
3923 | goto unlock; |
3924 | |
3925 | err = mv88e6xxx_atu_setup(chip); |
3926 | if (err) |
3927 | goto unlock; |
3928 | |
3929 | err = mv88e6xxx_broadcast_setup(chip, vid: 0); |
3930 | if (err) |
3931 | goto unlock; |
3932 | |
3933 | err = mv88e6xxx_pot_setup(chip); |
3934 | if (err) |
3935 | goto unlock; |
3936 | |
3937 | err = mv88e6xxx_rmu_setup(chip); |
3938 | if (err) |
3939 | goto unlock; |
3940 | |
3941 | err = mv88e6xxx_rsvd2cpu_setup(chip); |
3942 | if (err) |
3943 | goto unlock; |
3944 | |
3945 | err = mv88e6xxx_trunk_setup(chip); |
3946 | if (err) |
3947 | goto unlock; |
3948 | |
3949 | err = mv88e6xxx_devmap_setup(chip); |
3950 | if (err) |
3951 | goto unlock; |
3952 | |
3953 | err = mv88e6xxx_pri_setup(chip); |
3954 | if (err) |
3955 | goto unlock; |
3956 | |
3957 | /* Setup PTP Hardware Clock and timestamping */ |
3958 | if (chip->info->ptp_support) { |
3959 | err = mv88e6xxx_ptp_setup(chip); |
3960 | if (err) |
3961 | goto unlock; |
3962 | |
3963 | err = mv88e6xxx_hwtstamp_setup(chip); |
3964 | if (err) |
3965 | goto unlock; |
3966 | } |
3967 | |
3968 | err = mv88e6xxx_stats_setup(chip); |
3969 | if (err) |
3970 | goto unlock; |
3971 | |
3972 | unlock: |
3973 | mv88e6xxx_reg_unlock(chip); |
3974 | |
3975 | if (err) |
3976 | goto out_mdios; |
3977 | |
3978 | /* Have to be called without holding the register lock, since |
3979 | * they take the devlink lock, and we later take the locks in |
3980 | * the reverse order when getting/setting parameters or |
3981 | * resource occupancy. |
3982 | */ |
3983 | err = mv88e6xxx_setup_devlink_resources(ds); |
3984 | if (err) |
3985 | goto out_mdios; |
3986 | |
3987 | err = mv88e6xxx_setup_devlink_params(ds); |
3988 | if (err) |
3989 | goto out_resources; |
3990 | |
3991 | err = mv88e6xxx_setup_devlink_regions_global(ds); |
3992 | if (err) |
3993 | goto out_params; |
3994 | |
3995 | return 0; |
3996 | |
3997 | out_params: |
3998 | mv88e6xxx_teardown_devlink_params(ds); |
3999 | out_resources: |
4000 | dsa_devlink_resources_unregister(ds); |
4001 | out_mdios: |
4002 | mv88e6xxx_mdios_unregister(chip); |
4003 | |
4004 | return err; |
4005 | } |
4006 | |
4007 | static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) |
4008 | { |
4009 | struct mv88e6xxx_chip *chip = ds->priv; |
4010 | int err; |
4011 | |
4012 | if (chip->info->ops->pcs_ops && |
4013 | chip->info->ops->pcs_ops->pcs_init) { |
4014 | err = chip->info->ops->pcs_ops->pcs_init(chip, port); |
4015 | if (err) |
4016 | return err; |
4017 | } |
4018 | |
4019 | return mv88e6xxx_setup_devlink_regions_port(ds, port); |
4020 | } |
4021 | |
4022 | static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) |
4023 | { |
4024 | struct mv88e6xxx_chip *chip = ds->priv; |
4025 | |
4026 | mv88e6xxx_teardown_devlink_regions_port(ds, port); |
4027 | |
4028 | if (chip->info->ops->pcs_ops && |
4029 | chip->info->ops->pcs_ops->pcs_teardown) |
4030 | chip->info->ops->pcs_ops->pcs_teardown(chip, port); |
4031 | } |
4032 | |
4033 | static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) |
4034 | { |
4035 | struct mv88e6xxx_chip *chip = ds->priv; |
4036 | |
4037 | return chip->eeprom_len; |
4038 | } |
4039 | |
4040 | static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, |
4041 | struct ethtool_eeprom *eeprom, u8 *data) |
4042 | { |
4043 | struct mv88e6xxx_chip *chip = ds->priv; |
4044 | int err; |
4045 | |
4046 | if (!chip->info->ops->get_eeprom) |
4047 | return -EOPNOTSUPP; |
4048 | |
4049 | mv88e6xxx_reg_lock(chip); |
4050 | err = chip->info->ops->get_eeprom(chip, eeprom, data); |
4051 | mv88e6xxx_reg_unlock(chip); |
4052 | |
4053 | if (err) |
4054 | return err; |
4055 | |
4056 | eeprom->magic = 0xc3ec4951; |
4057 | |
4058 | return 0; |
4059 | } |
4060 | |
4061 | static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, |
4062 | struct ethtool_eeprom *eeprom, u8 *data) |
4063 | { |
4064 | struct mv88e6xxx_chip *chip = ds->priv; |
4065 | int err; |
4066 | |
4067 | if (!chip->info->ops->set_eeprom) |
4068 | return -EOPNOTSUPP; |
4069 | |
4070 | if (eeprom->magic != 0xc3ec4951) |
4071 | return -EINVAL; |
4072 | |
4073 | mv88e6xxx_reg_lock(chip); |
4074 | err = chip->info->ops->set_eeprom(chip, eeprom, data); |
4075 | mv88e6xxx_reg_unlock(chip); |
4076 | |
4077 | return err; |
4078 | } |
4079 | |
4080 | static const struct mv88e6xxx_ops mv88e6085_ops = { |
4081 | /* MV88E6XXX_FAMILY_6097 */ |
4082 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4083 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
4084 | .irl_init_all = mv88e6352_g2_irl_init_all, |
4085 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
4086 | .phy_read = mv88e6185_phy_ppu_read, |
4087 | .phy_write = mv88e6185_phy_ppu_write, |
4088 | .port_set_link = mv88e6xxx_port_set_link, |
4089 | .port_sync_link = mv88e6xxx_port_sync_link, |
4090 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
4091 | .port_tag_remap = mv88e6095_port_tag_remap, |
4092 | .port_set_policy = mv88e6352_port_set_policy, |
4093 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4094 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4095 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
4096 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4097 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
4098 | .port_pause_limit = mv88e6097_port_pause_limit, |
4099 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4100 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4101 | .port_get_cmode = mv88e6185_port_get_cmode, |
4102 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4103 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
4104 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
4105 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4106 | .stats_get_strings = mv88e6095_stats_get_strings, |
4107 | .stats_get_stat = mv88e6095_stats_get_stat, |
4108 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4109 | .set_egress_port = mv88e6095_g1_set_egress_port, |
4110 | .watchdog_ops = &mv88e6097_watchdog_ops, |
4111 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
4112 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4113 | .ppu_enable = mv88e6185_g1_ppu_enable, |
4114 | .ppu_disable = mv88e6185_g1_ppu_disable, |
4115 | .reset = mv88e6185_g1_reset, |
4116 | .rmu_disable = mv88e6085_g1_rmu_disable, |
4117 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
4118 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
4119 | .stu_getnext = mv88e6352_g1_stu_getnext, |
4120 | .stu_loadpurge = mv88e6352_g1_stu_loadpurge, |
4121 | .phylink_get_caps = mv88e6185_phylink_get_caps, |
4122 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
4123 | }; |
4124 | |
4125 | static const struct mv88e6xxx_ops mv88e6095_ops = { |
4126 | /* MV88E6XXX_FAMILY_6095 */ |
4127 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4128 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
4129 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
4130 | .phy_read = mv88e6185_phy_ppu_read, |
4131 | .phy_write = mv88e6185_phy_ppu_write, |
4132 | .port_set_link = mv88e6xxx_port_set_link, |
4133 | .port_sync_link = mv88e6185_port_sync_link, |
4134 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
4135 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
4136 | .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, |
4137 | .port_set_mcast_flood = mv88e6185_port_set_default_forward, |
4138 | .port_set_upstream_port = mv88e6095_port_set_upstream_port, |
4139 | .port_get_cmode = mv88e6185_port_get_cmode, |
4140 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4141 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
4142 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
4143 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4144 | .stats_get_strings = mv88e6095_stats_get_strings, |
4145 | .stats_get_stat = mv88e6095_stats_get_stat, |
4146 | .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, |
4147 | .ppu_enable = mv88e6185_g1_ppu_enable, |
4148 | .ppu_disable = mv88e6185_g1_ppu_disable, |
4149 | .reset = mv88e6185_g1_reset, |
4150 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
4151 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
4152 | .phylink_get_caps = mv88e6095_phylink_get_caps, |
4153 | .pcs_ops = &mv88e6185_pcs_ops, |
4154 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
4155 | }; |
4156 | |
4157 | static const struct mv88e6xxx_ops mv88e6097_ops = { |
4158 | /* MV88E6XXX_FAMILY_6097 */ |
4159 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4160 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
4161 | .irl_init_all = mv88e6352_g2_irl_init_all, |
4162 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4163 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
4164 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
4165 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
4166 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
4167 | .port_set_link = mv88e6xxx_port_set_link, |
4168 | .port_sync_link = mv88e6185_port_sync_link, |
4169 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
4170 | .port_tag_remap = mv88e6095_port_tag_remap, |
4171 | .port_set_policy = mv88e6352_port_set_policy, |
4172 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4173 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4174 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
4175 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4176 | .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, |
4177 | .port_pause_limit = mv88e6097_port_pause_limit, |
4178 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4179 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4180 | .port_get_cmode = mv88e6185_port_get_cmode, |
4181 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4182 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
4183 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
4184 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4185 | .stats_get_strings = mv88e6095_stats_get_strings, |
4186 | .stats_get_stat = mv88e6095_stats_get_stat, |
4187 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4188 | .set_egress_port = mv88e6095_g1_set_egress_port, |
4189 | .watchdog_ops = &mv88e6097_watchdog_ops, |
4190 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
4191 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
4192 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4193 | .reset = mv88e6352_g1_reset, |
4194 | .rmu_disable = mv88e6085_g1_rmu_disable, |
4195 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
4196 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
4197 | .phylink_get_caps = mv88e6095_phylink_get_caps, |
4198 | .pcs_ops = &mv88e6185_pcs_ops, |
4199 | .stu_getnext = mv88e6352_g1_stu_getnext, |
4200 | .stu_loadpurge = mv88e6352_g1_stu_loadpurge, |
4201 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
4202 | }; |
4203 | |
4204 | static const struct mv88e6xxx_ops mv88e6123_ops = { |
4205 | /* MV88E6XXX_FAMILY_6165 */ |
4206 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4207 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
4208 | .irl_init_all = mv88e6352_g2_irl_init_all, |
4209 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4210 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
4211 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
4212 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
4213 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
4214 | .port_set_link = mv88e6xxx_port_set_link, |
4215 | .port_sync_link = mv88e6xxx_port_sync_link, |
4216 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
4217 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
4218 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4219 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
4220 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4221 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4222 | .port_get_cmode = mv88e6185_port_get_cmode, |
4223 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4224 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
4225 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
4226 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4227 | .stats_get_strings = mv88e6095_stats_get_strings, |
4228 | .stats_get_stat = mv88e6095_stats_get_stat, |
4229 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4230 | .set_egress_port = mv88e6095_g1_set_egress_port, |
4231 | .watchdog_ops = &mv88e6097_watchdog_ops, |
4232 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
4233 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4234 | .reset = mv88e6352_g1_reset, |
4235 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4236 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
4237 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
4238 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
4239 | .stu_getnext = mv88e6352_g1_stu_getnext, |
4240 | .stu_loadpurge = mv88e6352_g1_stu_loadpurge, |
4241 | .phylink_get_caps = mv88e6185_phylink_get_caps, |
4242 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
4243 | }; |
4244 | |
4245 | static const struct mv88e6xxx_ops mv88e6131_ops = { |
4246 | /* MV88E6XXX_FAMILY_6185 */ |
4247 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4248 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
4249 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
4250 | .phy_read = mv88e6185_phy_ppu_read, |
4251 | .phy_write = mv88e6185_phy_ppu_write, |
4252 | .port_set_link = mv88e6xxx_port_set_link, |
4253 | .port_sync_link = mv88e6xxx_port_sync_link, |
4254 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
4255 | .port_tag_remap = mv88e6095_port_tag_remap, |
4256 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4257 | .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, |
4258 | .port_set_mcast_flood = mv88e6185_port_set_default_forward, |
4259 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4260 | .port_set_upstream_port = mv88e6095_port_set_upstream_port, |
4261 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
4262 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
4263 | .port_pause_limit = mv88e6097_port_pause_limit, |
4264 | .port_set_pause = mv88e6185_port_set_pause, |
4265 | .port_get_cmode = mv88e6185_port_get_cmode, |
4266 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4267 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
4268 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
4269 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4270 | .stats_get_strings = mv88e6095_stats_get_strings, |
4271 | .stats_get_stat = mv88e6095_stats_get_stat, |
4272 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4273 | .set_egress_port = mv88e6095_g1_set_egress_port, |
4274 | .watchdog_ops = &mv88e6097_watchdog_ops, |
4275 | .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, |
4276 | .ppu_enable = mv88e6185_g1_ppu_enable, |
4277 | .set_cascade_port = mv88e6185_g1_set_cascade_port, |
4278 | .ppu_disable = mv88e6185_g1_ppu_disable, |
4279 | .reset = mv88e6185_g1_reset, |
4280 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
4281 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
4282 | .phylink_get_caps = mv88e6185_phylink_get_caps, |
4283 | }; |
4284 | |
4285 | static const struct mv88e6xxx_ops mv88e6141_ops = { |
4286 | /* MV88E6XXX_FAMILY_6341 */ |
4287 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4288 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
4289 | .irl_init_all = mv88e6352_g2_irl_init_all, |
4290 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
4291 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
4292 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4293 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
4294 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
4295 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
4296 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
4297 | .port_set_link = mv88e6xxx_port_set_link, |
4298 | .port_sync_link = mv88e6xxx_port_sync_link, |
4299 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
4300 | .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, |
4301 | .port_max_speed_mode = mv88e6341_port_max_speed_mode, |
4302 | .port_tag_remap = mv88e6095_port_tag_remap, |
4303 | .port_set_policy = mv88e6352_port_set_policy, |
4304 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4305 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4306 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
4307 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4308 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
4309 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
4310 | .port_pause_limit = mv88e6097_port_pause_limit, |
4311 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4312 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4313 | .port_get_cmode = mv88e6352_port_get_cmode, |
4314 | .port_set_cmode = mv88e6341_port_set_cmode, |
4315 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4316 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
4317 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
4318 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
4319 | .stats_get_strings = mv88e6320_stats_get_strings, |
4320 | .stats_get_stat = mv88e6390_stats_get_stat, |
4321 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
4322 | .set_egress_port = mv88e6390_g1_set_egress_port, |
4323 | .watchdog_ops = &mv88e6390_watchdog_ops, |
4324 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
4325 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4326 | .reset = mv88e6352_g1_reset, |
4327 | .rmu_disable = mv88e6390_g1_rmu_disable, |
4328 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4329 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
4330 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
4331 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
4332 | .stu_getnext = mv88e6352_g1_stu_getnext, |
4333 | .stu_loadpurge = mv88e6352_g1_stu_loadpurge, |
4334 | .serdes_get_lane = mv88e6341_serdes_get_lane, |
4335 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
4336 | .gpio_ops = &mv88e6352_gpio_ops, |
4337 | .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, |
4338 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
4339 | .serdes_get_stats = mv88e6390_serdes_get_stats, |
4340 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
4341 | .serdes_get_regs = mv88e6390_serdes_get_regs, |
4342 | .phylink_get_caps = mv88e6341_phylink_get_caps, |
4343 | .pcs_ops = &mv88e6390_pcs_ops, |
4344 | }; |
4345 | |
4346 | static const struct mv88e6xxx_ops mv88e6161_ops = { |
4347 | /* MV88E6XXX_FAMILY_6165 */ |
4348 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4349 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
4350 | .irl_init_all = mv88e6352_g2_irl_init_all, |
4351 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4352 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
4353 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
4354 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
4355 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
4356 | .port_set_link = mv88e6xxx_port_set_link, |
4357 | .port_sync_link = mv88e6xxx_port_sync_link, |
4358 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
4359 | .port_tag_remap = mv88e6095_port_tag_remap, |
4360 | .port_set_policy = mv88e6352_port_set_policy, |
4361 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4362 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4363 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
4364 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4365 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
4366 | .port_pause_limit = mv88e6097_port_pause_limit, |
4367 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4368 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4369 | .port_get_cmode = mv88e6185_port_get_cmode, |
4370 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4371 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
4372 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
4373 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4374 | .stats_get_strings = mv88e6095_stats_get_strings, |
4375 | .stats_get_stat = mv88e6095_stats_get_stat, |
4376 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4377 | .set_egress_port = mv88e6095_g1_set_egress_port, |
4378 | .watchdog_ops = &mv88e6097_watchdog_ops, |
4379 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
4380 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4381 | .reset = mv88e6352_g1_reset, |
4382 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4383 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
4384 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
4385 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
4386 | .stu_getnext = mv88e6352_g1_stu_getnext, |
4387 | .stu_loadpurge = mv88e6352_g1_stu_loadpurge, |
4388 | .avb_ops = &mv88e6165_avb_ops, |
4389 | .ptp_ops = &mv88e6165_ptp_ops, |
4390 | .phylink_get_caps = mv88e6185_phylink_get_caps, |
4391 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
4392 | }; |
4393 | |
4394 | static const struct mv88e6xxx_ops mv88e6165_ops = { |
4395 | /* MV88E6XXX_FAMILY_6165 */ |
4396 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4397 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
4398 | .irl_init_all = mv88e6352_g2_irl_init_all, |
4399 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4400 | .phy_read = mv88e6165_phy_read, |
4401 | .phy_write = mv88e6165_phy_write, |
4402 | .port_set_link = mv88e6xxx_port_set_link, |
4403 | .port_sync_link = mv88e6xxx_port_sync_link, |
4404 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
4405 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4406 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4407 | .port_get_cmode = mv88e6185_port_get_cmode, |
4408 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4409 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
4410 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
4411 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4412 | .stats_get_strings = mv88e6095_stats_get_strings, |
4413 | .stats_get_stat = mv88e6095_stats_get_stat, |
4414 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4415 | .set_egress_port = mv88e6095_g1_set_egress_port, |
4416 | .watchdog_ops = &mv88e6097_watchdog_ops, |
4417 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
4418 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4419 | .reset = mv88e6352_g1_reset, |
4420 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4421 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
4422 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
4423 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
4424 | .stu_getnext = mv88e6352_g1_stu_getnext, |
4425 | .stu_loadpurge = mv88e6352_g1_stu_loadpurge, |
4426 | .avb_ops = &mv88e6165_avb_ops, |
4427 | .ptp_ops = &mv88e6165_ptp_ops, |
4428 | .phylink_get_caps = mv88e6185_phylink_get_caps, |
4429 | }; |
4430 | |
4431 | static const struct mv88e6xxx_ops mv88e6171_ops = { |
4432 | /* MV88E6XXX_FAMILY_6351 */ |
4433 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4434 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
4435 | .irl_init_all = mv88e6352_g2_irl_init_all, |
4436 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4437 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
4438 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
4439 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
4440 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
4441 | .port_set_link = mv88e6xxx_port_set_link, |
4442 | .port_sync_link = mv88e6xxx_port_sync_link, |
4443 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
4444 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
4445 | .port_tag_remap = mv88e6095_port_tag_remap, |
4446 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4447 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4448 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
4449 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4450 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
4451 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
4452 | .port_pause_limit = mv88e6097_port_pause_limit, |
4453 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4454 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4455 | .port_get_cmode = mv88e6352_port_get_cmode, |
4456 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4457 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
4458 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
4459 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4460 | .stats_get_strings = mv88e6095_stats_get_strings, |
4461 | .stats_get_stat = mv88e6095_stats_get_stat, |
4462 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4463 | .set_egress_port = mv88e6095_g1_set_egress_port, |
4464 | .watchdog_ops = &mv88e6097_watchdog_ops, |
4465 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
4466 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4467 | .reset = mv88e6352_g1_reset, |
4468 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4469 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
4470 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
4471 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
4472 | .stu_getnext = mv88e6352_g1_stu_getnext, |
4473 | .stu_loadpurge = mv88e6352_g1_stu_loadpurge, |
4474 | .phylink_get_caps = mv88e6351_phylink_get_caps, |
4475 | }; |
4476 | |
4477 | static const struct mv88e6xxx_ops mv88e6172_ops = { |
4478 | /* MV88E6XXX_FAMILY_6352 */ |
4479 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4480 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
4481 | .irl_init_all = mv88e6352_g2_irl_init_all, |
4482 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
4483 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, |
4484 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4485 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
4486 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
4487 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
4488 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
4489 | .port_set_link = mv88e6xxx_port_set_link, |
4490 | .port_sync_link = mv88e6xxx_port_sync_link, |
4491 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
4492 | .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, |
4493 | .port_tag_remap = mv88e6095_port_tag_remap, |
4494 | .port_set_policy = mv88e6352_port_set_policy, |
4495 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4496 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4497 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
4498 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4499 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
4500 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
4501 | .port_pause_limit = mv88e6097_port_pause_limit, |
4502 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4503 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4504 | .port_get_cmode = mv88e6352_port_get_cmode, |
4505 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4506 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
4507 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
4508 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4509 | .stats_get_strings = mv88e6095_stats_get_strings, |
4510 | .stats_get_stat = mv88e6095_stats_get_stat, |
4511 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4512 | .set_egress_port = mv88e6095_g1_set_egress_port, |
4513 | .watchdog_ops = &mv88e6097_watchdog_ops, |
4514 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
4515 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4516 | .reset = mv88e6352_g1_reset, |
4517 | .rmu_disable = mv88e6352_g1_rmu_disable, |
4518 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4519 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
4520 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
4521 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
4522 | .stu_getnext = mv88e6352_g1_stu_getnext, |
4523 | .stu_loadpurge = mv88e6352_g1_stu_loadpurge, |
4524 | .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, |
4525 | .serdes_get_regs = mv88e6352_serdes_get_regs, |
4526 | .gpio_ops = &mv88e6352_gpio_ops, |
4527 | .phylink_get_caps = mv88e6352_phylink_get_caps, |
4528 | .pcs_ops = &mv88e6352_pcs_ops, |
4529 | }; |
4530 | |
4531 | static const struct mv88e6xxx_ops mv88e6175_ops = { |
4532 | /* MV88E6XXX_FAMILY_6351 */ |
4533 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4534 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
4535 | .irl_init_all = mv88e6352_g2_irl_init_all, |
4536 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4537 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
4538 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
4539 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
4540 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
4541 | .port_set_link = mv88e6xxx_port_set_link, |
4542 | .port_sync_link = mv88e6xxx_port_sync_link, |
4543 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
4544 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
4545 | .port_tag_remap = mv88e6095_port_tag_remap, |
4546 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4547 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4548 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
4549 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4550 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
4551 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
4552 | .port_pause_limit = mv88e6097_port_pause_limit, |
4553 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4554 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4555 | .port_get_cmode = mv88e6352_port_get_cmode, |
4556 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4557 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
4558 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
4559 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4560 | .stats_get_strings = mv88e6095_stats_get_strings, |
4561 | .stats_get_stat = mv88e6095_stats_get_stat, |
4562 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4563 | .set_egress_port = mv88e6095_g1_set_egress_port, |
4564 | .watchdog_ops = &mv88e6097_watchdog_ops, |
4565 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
4566 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4567 | .reset = mv88e6352_g1_reset, |
4568 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4569 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
4570 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
4571 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
4572 | .stu_getnext = mv88e6352_g1_stu_getnext, |
4573 | .stu_loadpurge = mv88e6352_g1_stu_loadpurge, |
4574 | .phylink_get_caps = mv88e6351_phylink_get_caps, |
4575 | }; |
4576 | |
4577 | static const struct mv88e6xxx_ops mv88e6176_ops = { |
4578 | /* MV88E6XXX_FAMILY_6352 */ |
4579 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4580 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
4581 | .irl_init_all = mv88e6352_g2_irl_init_all, |
4582 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
4583 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, |
4584 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4585 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
4586 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
4587 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
4588 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
4589 | .port_set_link = mv88e6xxx_port_set_link, |
4590 | .port_sync_link = mv88e6xxx_port_sync_link, |
4591 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
4592 | .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, |
4593 | .port_tag_remap = mv88e6095_port_tag_remap, |
4594 | .port_set_policy = mv88e6352_port_set_policy, |
4595 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4596 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4597 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
4598 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4599 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
4600 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
4601 | .port_pause_limit = mv88e6097_port_pause_limit, |
4602 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4603 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4604 | .port_get_cmode = mv88e6352_port_get_cmode, |
4605 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4606 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
4607 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
4608 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4609 | .stats_get_strings = mv88e6095_stats_get_strings, |
4610 | .stats_get_stat = mv88e6095_stats_get_stat, |
4611 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4612 | .set_egress_port = mv88e6095_g1_set_egress_port, |
4613 | .watchdog_ops = &mv88e6097_watchdog_ops, |
4614 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
4615 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4616 | .reset = mv88e6352_g1_reset, |
4617 | .rmu_disable = mv88e6352_g1_rmu_disable, |
4618 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4619 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
4620 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
4621 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
4622 | .stu_getnext = mv88e6352_g1_stu_getnext, |
4623 | .stu_loadpurge = mv88e6352_g1_stu_loadpurge, |
4624 | .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, |
4625 | .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, |
4626 | .serdes_get_regs = mv88e6352_serdes_get_regs, |
4627 | .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, |
4628 | .gpio_ops = &mv88e6352_gpio_ops, |
4629 | .phylink_get_caps = mv88e6352_phylink_get_caps, |
4630 | .pcs_ops = &mv88e6352_pcs_ops, |
4631 | }; |
4632 | |
4633 | static const struct mv88e6xxx_ops mv88e6185_ops = { |
4634 | /* MV88E6XXX_FAMILY_6185 */ |
4635 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4636 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
4637 | .set_switch_mac = mv88e6xxx_g1_set_switch_mac, |
4638 | .phy_read = mv88e6185_phy_ppu_read, |
4639 | .phy_write = mv88e6185_phy_ppu_write, |
4640 | .port_set_link = mv88e6xxx_port_set_link, |
4641 | .port_sync_link = mv88e6185_port_sync_link, |
4642 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
4643 | .port_set_frame_mode = mv88e6085_port_set_frame_mode, |
4644 | .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, |
4645 | .port_set_mcast_flood = mv88e6185_port_set_default_forward, |
4646 | .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, |
4647 | .port_set_upstream_port = mv88e6095_port_set_upstream_port, |
4648 | .port_set_pause = mv88e6185_port_set_pause, |
4649 | .port_get_cmode = mv88e6185_port_get_cmode, |
4650 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4651 | .stats_snapshot = mv88e6xxx_g1_stats_snapshot, |
4652 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
4653 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4654 | .stats_get_strings = mv88e6095_stats_get_strings, |
4655 | .stats_get_stat = mv88e6095_stats_get_stat, |
4656 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4657 | .set_egress_port = mv88e6095_g1_set_egress_port, |
4658 | .watchdog_ops = &mv88e6097_watchdog_ops, |
4659 | .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, |
4660 | .set_cascade_port = mv88e6185_g1_set_cascade_port, |
4661 | .ppu_enable = mv88e6185_g1_ppu_enable, |
4662 | .ppu_disable = mv88e6185_g1_ppu_disable, |
4663 | .reset = mv88e6185_g1_reset, |
4664 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
4665 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
4666 | .phylink_get_caps = mv88e6185_phylink_get_caps, |
4667 | .pcs_ops = &mv88e6185_pcs_ops, |
4668 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
4669 | }; |
4670 | |
4671 | static const struct mv88e6xxx_ops mv88e6190_ops = { |
4672 | /* MV88E6XXX_FAMILY_6390 */ |
4673 | .setup_errata = mv88e6390_setup_errata, |
4674 | .irl_init_all = mv88e6390_g2_irl_init_all, |
4675 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
4676 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
4677 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4678 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
4679 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
4680 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
4681 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
4682 | .port_set_link = mv88e6xxx_port_set_link, |
4683 | .port_sync_link = mv88e6xxx_port_sync_link, |
4684 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
4685 | .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, |
4686 | .port_max_speed_mode = mv88e6390_port_max_speed_mode, |
4687 | .port_tag_remap = mv88e6390_port_tag_remap, |
4688 | .port_set_policy = mv88e6352_port_set_policy, |
4689 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4690 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4691 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
4692 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4693 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
4694 | .port_pause_limit = mv88e6390_port_pause_limit, |
4695 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4696 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4697 | .port_get_cmode = mv88e6352_port_get_cmode, |
4698 | .port_set_cmode = mv88e6390_port_set_cmode, |
4699 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4700 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
4701 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
4702 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
4703 | .stats_get_strings = mv88e6320_stats_get_strings, |
4704 | .stats_get_stat = mv88e6390_stats_get_stat, |
4705 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
4706 | .set_egress_port = mv88e6390_g1_set_egress_port, |
4707 | .watchdog_ops = &mv88e6390_watchdog_ops, |
4708 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
4709 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4710 | .reset = mv88e6352_g1_reset, |
4711 | .rmu_disable = mv88e6390_g1_rmu_disable, |
4712 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4713 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
4714 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
4715 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, |
4716 | .stu_getnext = mv88e6390_g1_stu_getnext, |
4717 | .stu_loadpurge = mv88e6390_g1_stu_loadpurge, |
4718 | .serdes_get_lane = mv88e6390_serdes_get_lane, |
4719 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
4720 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
4721 | .serdes_get_stats = mv88e6390_serdes_get_stats, |
4722 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
4723 | .serdes_get_regs = mv88e6390_serdes_get_regs, |
4724 | .gpio_ops = &mv88e6352_gpio_ops, |
4725 | .phylink_get_caps = mv88e6390_phylink_get_caps, |
4726 | .pcs_ops = &mv88e6390_pcs_ops, |
4727 | }; |
4728 | |
4729 | static const struct mv88e6xxx_ops mv88e6190x_ops = { |
4730 | /* MV88E6XXX_FAMILY_6390 */ |
4731 | .setup_errata = mv88e6390_setup_errata, |
4732 | .irl_init_all = mv88e6390_g2_irl_init_all, |
4733 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
4734 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
4735 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4736 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
4737 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
4738 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
4739 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
4740 | .port_set_link = mv88e6xxx_port_set_link, |
4741 | .port_sync_link = mv88e6xxx_port_sync_link, |
4742 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
4743 | .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, |
4744 | .port_max_speed_mode = mv88e6390x_port_max_speed_mode, |
4745 | .port_tag_remap = mv88e6390_port_tag_remap, |
4746 | .port_set_policy = mv88e6352_port_set_policy, |
4747 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4748 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4749 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
4750 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4751 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
4752 | .port_pause_limit = mv88e6390_port_pause_limit, |
4753 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4754 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4755 | .port_get_cmode = mv88e6352_port_get_cmode, |
4756 | .port_set_cmode = mv88e6390x_port_set_cmode, |
4757 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4758 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
4759 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
4760 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
4761 | .stats_get_strings = mv88e6320_stats_get_strings, |
4762 | .stats_get_stat = mv88e6390_stats_get_stat, |
4763 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
4764 | .set_egress_port = mv88e6390_g1_set_egress_port, |
4765 | .watchdog_ops = &mv88e6390_watchdog_ops, |
4766 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
4767 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4768 | .reset = mv88e6352_g1_reset, |
4769 | .rmu_disable = mv88e6390_g1_rmu_disable, |
4770 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4771 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
4772 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
4773 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, |
4774 | .stu_getnext = mv88e6390_g1_stu_getnext, |
4775 | .stu_loadpurge = mv88e6390_g1_stu_loadpurge, |
4776 | .serdes_get_lane = mv88e6390x_serdes_get_lane, |
4777 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
4778 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
4779 | .serdes_get_stats = mv88e6390_serdes_get_stats, |
4780 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
4781 | .serdes_get_regs = mv88e6390_serdes_get_regs, |
4782 | .gpio_ops = &mv88e6352_gpio_ops, |
4783 | .phylink_get_caps = mv88e6390x_phylink_get_caps, |
4784 | .pcs_ops = &mv88e6390_pcs_ops, |
4785 | }; |
4786 | |
4787 | static const struct mv88e6xxx_ops mv88e6191_ops = { |
4788 | /* MV88E6XXX_FAMILY_6390 */ |
4789 | .setup_errata = mv88e6390_setup_errata, |
4790 | .irl_init_all = mv88e6390_g2_irl_init_all, |
4791 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
4792 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
4793 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4794 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
4795 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
4796 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
4797 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
4798 | .port_set_link = mv88e6xxx_port_set_link, |
4799 | .port_sync_link = mv88e6xxx_port_sync_link, |
4800 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
4801 | .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, |
4802 | .port_max_speed_mode = mv88e6390_port_max_speed_mode, |
4803 | .port_tag_remap = mv88e6390_port_tag_remap, |
4804 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4805 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4806 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
4807 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4808 | .port_pause_limit = mv88e6390_port_pause_limit, |
4809 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4810 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4811 | .port_get_cmode = mv88e6352_port_get_cmode, |
4812 | .port_set_cmode = mv88e6390_port_set_cmode, |
4813 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4814 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
4815 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
4816 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
4817 | .stats_get_strings = mv88e6320_stats_get_strings, |
4818 | .stats_get_stat = mv88e6390_stats_get_stat, |
4819 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
4820 | .set_egress_port = mv88e6390_g1_set_egress_port, |
4821 | .watchdog_ops = &mv88e6390_watchdog_ops, |
4822 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
4823 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4824 | .reset = mv88e6352_g1_reset, |
4825 | .rmu_disable = mv88e6390_g1_rmu_disable, |
4826 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4827 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
4828 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
4829 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, |
4830 | .stu_getnext = mv88e6390_g1_stu_getnext, |
4831 | .stu_loadpurge = mv88e6390_g1_stu_loadpurge, |
4832 | .serdes_get_lane = mv88e6390_serdes_get_lane, |
4833 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
4834 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
4835 | .serdes_get_stats = mv88e6390_serdes_get_stats, |
4836 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
4837 | .serdes_get_regs = mv88e6390_serdes_get_regs, |
4838 | .avb_ops = &mv88e6390_avb_ops, |
4839 | .ptp_ops = &mv88e6352_ptp_ops, |
4840 | .phylink_get_caps = mv88e6390_phylink_get_caps, |
4841 | .pcs_ops = &mv88e6390_pcs_ops, |
4842 | }; |
4843 | |
4844 | static const struct mv88e6xxx_ops mv88e6240_ops = { |
4845 | /* MV88E6XXX_FAMILY_6352 */ |
4846 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
4847 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
4848 | .irl_init_all = mv88e6352_g2_irl_init_all, |
4849 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
4850 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, |
4851 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4852 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
4853 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
4854 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
4855 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
4856 | .port_set_link = mv88e6xxx_port_set_link, |
4857 | .port_sync_link = mv88e6xxx_port_sync_link, |
4858 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
4859 | .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, |
4860 | .port_tag_remap = mv88e6095_port_tag_remap, |
4861 | .port_set_policy = mv88e6352_port_set_policy, |
4862 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4863 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4864 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
4865 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4866 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
4867 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
4868 | .port_pause_limit = mv88e6097_port_pause_limit, |
4869 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4870 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4871 | .port_get_cmode = mv88e6352_port_get_cmode, |
4872 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4873 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
4874 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
4875 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
4876 | .stats_get_strings = mv88e6095_stats_get_strings, |
4877 | .stats_get_stat = mv88e6095_stats_get_stat, |
4878 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4879 | .set_egress_port = mv88e6095_g1_set_egress_port, |
4880 | .watchdog_ops = &mv88e6097_watchdog_ops, |
4881 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
4882 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4883 | .reset = mv88e6352_g1_reset, |
4884 | .rmu_disable = mv88e6352_g1_rmu_disable, |
4885 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4886 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
4887 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
4888 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
4889 | .stu_getnext = mv88e6352_g1_stu_getnext, |
4890 | .stu_loadpurge = mv88e6352_g1_stu_loadpurge, |
4891 | .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, |
4892 | .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, |
4893 | .serdes_get_regs = mv88e6352_serdes_get_regs, |
4894 | .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, |
4895 | .gpio_ops = &mv88e6352_gpio_ops, |
4896 | .avb_ops = &mv88e6352_avb_ops, |
4897 | .ptp_ops = &mv88e6352_ptp_ops, |
4898 | .phylink_get_caps = mv88e6352_phylink_get_caps, |
4899 | .pcs_ops = &mv88e6352_pcs_ops, |
4900 | }; |
4901 | |
4902 | static const struct mv88e6xxx_ops mv88e6250_ops = { |
4903 | /* MV88E6XXX_FAMILY_6250 */ |
4904 | .ieee_pri_map = mv88e6250_g1_ieee_pri_map, |
4905 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
4906 | .irl_init_all = mv88e6352_g2_irl_init_all, |
4907 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
4908 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, |
4909 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4910 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
4911 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
4912 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
4913 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
4914 | .port_set_link = mv88e6xxx_port_set_link, |
4915 | .port_sync_link = mv88e6xxx_port_sync_link, |
4916 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
4917 | .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, |
4918 | .port_tag_remap = mv88e6095_port_tag_remap, |
4919 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4920 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4921 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
4922 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4923 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
4924 | .port_pause_limit = mv88e6097_port_pause_limit, |
4925 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4926 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
4927 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
4928 | .stats_get_sset_count = mv88e6250_stats_get_sset_count, |
4929 | .stats_get_strings = mv88e6250_stats_get_strings, |
4930 | .stats_get_stat = mv88e6250_stats_get_stat, |
4931 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
4932 | .set_egress_port = mv88e6095_g1_set_egress_port, |
4933 | .watchdog_ops = &mv88e6250_watchdog_ops, |
4934 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
4935 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4936 | .reset = mv88e6250_g1_reset, |
4937 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
4938 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
4939 | .avb_ops = &mv88e6352_avb_ops, |
4940 | .ptp_ops = &mv88e6250_ptp_ops, |
4941 | .phylink_get_caps = mv88e6250_phylink_get_caps, |
4942 | .set_max_frame_size = mv88e6185_g1_set_max_frame_size, |
4943 | }; |
4944 | |
4945 | static const struct mv88e6xxx_ops mv88e6290_ops = { |
4946 | /* MV88E6XXX_FAMILY_6390 */ |
4947 | .setup_errata = mv88e6390_setup_errata, |
4948 | .irl_init_all = mv88e6390_g2_irl_init_all, |
4949 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
4950 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
4951 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
4952 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
4953 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
4954 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
4955 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
4956 | .port_set_link = mv88e6xxx_port_set_link, |
4957 | .port_sync_link = mv88e6xxx_port_sync_link, |
4958 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
4959 | .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, |
4960 | .port_max_speed_mode = mv88e6390_port_max_speed_mode, |
4961 | .port_tag_remap = mv88e6390_port_tag_remap, |
4962 | .port_set_policy = mv88e6352_port_set_policy, |
4963 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
4964 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
4965 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
4966 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
4967 | .port_pause_limit = mv88e6390_port_pause_limit, |
4968 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
4969 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
4970 | .port_get_cmode = mv88e6352_port_get_cmode, |
4971 | .port_set_cmode = mv88e6390_port_set_cmode, |
4972 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
4973 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
4974 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
4975 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
4976 | .stats_get_strings = mv88e6320_stats_get_strings, |
4977 | .stats_get_stat = mv88e6390_stats_get_stat, |
4978 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
4979 | .set_egress_port = mv88e6390_g1_set_egress_port, |
4980 | .watchdog_ops = &mv88e6390_watchdog_ops, |
4981 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
4982 | .pot_clear = mv88e6xxx_g2_pot_clear, |
4983 | .reset = mv88e6352_g1_reset, |
4984 | .rmu_disable = mv88e6390_g1_rmu_disable, |
4985 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
4986 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
4987 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
4988 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, |
4989 | .stu_getnext = mv88e6390_g1_stu_getnext, |
4990 | .stu_loadpurge = mv88e6390_g1_stu_loadpurge, |
4991 | .serdes_get_lane = mv88e6390_serdes_get_lane, |
4992 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
4993 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
4994 | .serdes_get_stats = mv88e6390_serdes_get_stats, |
4995 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
4996 | .serdes_get_regs = mv88e6390_serdes_get_regs, |
4997 | .gpio_ops = &mv88e6352_gpio_ops, |
4998 | .avb_ops = &mv88e6390_avb_ops, |
4999 | .ptp_ops = &mv88e6390_ptp_ops, |
5000 | .phylink_get_caps = mv88e6390_phylink_get_caps, |
5001 | .pcs_ops = &mv88e6390_pcs_ops, |
5002 | }; |
5003 | |
5004 | static const struct mv88e6xxx_ops mv88e6320_ops = { |
5005 | /* MV88E6XXX_FAMILY_6320 */ |
5006 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
5007 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
5008 | .irl_init_all = mv88e6352_g2_irl_init_all, |
5009 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
5010 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, |
5011 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
5012 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
5013 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
5014 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
5015 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
5016 | .port_set_link = mv88e6xxx_port_set_link, |
5017 | .port_sync_link = mv88e6xxx_port_sync_link, |
5018 | .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, |
5019 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
5020 | .port_tag_remap = mv88e6095_port_tag_remap, |
5021 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
5022 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
5023 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
5024 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
5025 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
5026 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
5027 | .port_pause_limit = mv88e6097_port_pause_limit, |
5028 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
5029 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
5030 | .port_get_cmode = mv88e6352_port_get_cmode, |
5031 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
5032 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
5033 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
5034 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
5035 | .stats_get_strings = mv88e6320_stats_get_strings, |
5036 | .stats_get_stat = mv88e6320_stats_get_stat, |
5037 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
5038 | .set_egress_port = mv88e6095_g1_set_egress_port, |
5039 | .watchdog_ops = &mv88e6390_watchdog_ops, |
5040 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
5041 | .pot_clear = mv88e6xxx_g2_pot_clear, |
5042 | .reset = mv88e6352_g1_reset, |
5043 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
5044 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
5045 | .gpio_ops = &mv88e6352_gpio_ops, |
5046 | .avb_ops = &mv88e6352_avb_ops, |
5047 | .ptp_ops = &mv88e6352_ptp_ops, |
5048 | .phylink_get_caps = mv88e6185_phylink_get_caps, |
5049 | }; |
5050 | |
5051 | static const struct mv88e6xxx_ops mv88e6321_ops = { |
5052 | /* MV88E6XXX_FAMILY_6320 */ |
5053 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
5054 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
5055 | .irl_init_all = mv88e6352_g2_irl_init_all, |
5056 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
5057 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, |
5058 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
5059 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
5060 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
5061 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
5062 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
5063 | .port_set_link = mv88e6xxx_port_set_link, |
5064 | .port_sync_link = mv88e6xxx_port_sync_link, |
5065 | .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, |
5066 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
5067 | .port_tag_remap = mv88e6095_port_tag_remap, |
5068 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
5069 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
5070 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
5071 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
5072 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
5073 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
5074 | .port_pause_limit = mv88e6097_port_pause_limit, |
5075 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
5076 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
5077 | .port_get_cmode = mv88e6352_port_get_cmode, |
5078 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
5079 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
5080 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
5081 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
5082 | .stats_get_strings = mv88e6320_stats_get_strings, |
5083 | .stats_get_stat = mv88e6320_stats_get_stat, |
5084 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
5085 | .set_egress_port = mv88e6095_g1_set_egress_port, |
5086 | .watchdog_ops = &mv88e6390_watchdog_ops, |
5087 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
5088 | .reset = mv88e6352_g1_reset, |
5089 | .vtu_getnext = mv88e6185_g1_vtu_getnext, |
5090 | .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, |
5091 | .gpio_ops = &mv88e6352_gpio_ops, |
5092 | .avb_ops = &mv88e6352_avb_ops, |
5093 | .ptp_ops = &mv88e6352_ptp_ops, |
5094 | .phylink_get_caps = mv88e6185_phylink_get_caps, |
5095 | }; |
5096 | |
5097 | static const struct mv88e6xxx_ops mv88e6341_ops = { |
5098 | /* MV88E6XXX_FAMILY_6341 */ |
5099 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
5100 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
5101 | .irl_init_all = mv88e6352_g2_irl_init_all, |
5102 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
5103 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
5104 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
5105 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
5106 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
5107 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
5108 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
5109 | .port_set_link = mv88e6xxx_port_set_link, |
5110 | .port_sync_link = mv88e6xxx_port_sync_link, |
5111 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
5112 | .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, |
5113 | .port_max_speed_mode = mv88e6341_port_max_speed_mode, |
5114 | .port_tag_remap = mv88e6095_port_tag_remap, |
5115 | .port_set_policy = mv88e6352_port_set_policy, |
5116 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
5117 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
5118 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
5119 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
5120 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
5121 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
5122 | .port_pause_limit = mv88e6097_port_pause_limit, |
5123 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
5124 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
5125 | .port_get_cmode = mv88e6352_port_get_cmode, |
5126 | .port_set_cmode = mv88e6341_port_set_cmode, |
5127 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
5128 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
5129 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
5130 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
5131 | .stats_get_strings = mv88e6320_stats_get_strings, |
5132 | .stats_get_stat = mv88e6390_stats_get_stat, |
5133 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
5134 | .set_egress_port = mv88e6390_g1_set_egress_port, |
5135 | .watchdog_ops = &mv88e6390_watchdog_ops, |
5136 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
5137 | .pot_clear = mv88e6xxx_g2_pot_clear, |
5138 | .reset = mv88e6352_g1_reset, |
5139 | .rmu_disable = mv88e6390_g1_rmu_disable, |
5140 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
5141 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
5142 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
5143 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
5144 | .stu_getnext = mv88e6352_g1_stu_getnext, |
5145 | .stu_loadpurge = mv88e6352_g1_stu_loadpurge, |
5146 | .serdes_get_lane = mv88e6341_serdes_get_lane, |
5147 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
5148 | .gpio_ops = &mv88e6352_gpio_ops, |
5149 | .avb_ops = &mv88e6390_avb_ops, |
5150 | .ptp_ops = &mv88e6352_ptp_ops, |
5151 | .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, |
5152 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
5153 | .serdes_get_stats = mv88e6390_serdes_get_stats, |
5154 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
5155 | .serdes_get_regs = mv88e6390_serdes_get_regs, |
5156 | .phylink_get_caps = mv88e6341_phylink_get_caps, |
5157 | .pcs_ops = &mv88e6390_pcs_ops, |
5158 | }; |
5159 | |
5160 | static const struct mv88e6xxx_ops mv88e6350_ops = { |
5161 | /* MV88E6XXX_FAMILY_6351 */ |
5162 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
5163 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
5164 | .irl_init_all = mv88e6352_g2_irl_init_all, |
5165 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
5166 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
5167 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
5168 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
5169 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
5170 | .port_set_link = mv88e6xxx_port_set_link, |
5171 | .port_sync_link = mv88e6xxx_port_sync_link, |
5172 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
5173 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
5174 | .port_tag_remap = mv88e6095_port_tag_remap, |
5175 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
5176 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
5177 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
5178 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
5179 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
5180 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
5181 | .port_pause_limit = mv88e6097_port_pause_limit, |
5182 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
5183 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
5184 | .port_get_cmode = mv88e6352_port_get_cmode, |
5185 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
5186 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
5187 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
5188 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
5189 | .stats_get_strings = mv88e6095_stats_get_strings, |
5190 | .stats_get_stat = mv88e6095_stats_get_stat, |
5191 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
5192 | .set_egress_port = mv88e6095_g1_set_egress_port, |
5193 | .watchdog_ops = &mv88e6097_watchdog_ops, |
5194 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
5195 | .pot_clear = mv88e6xxx_g2_pot_clear, |
5196 | .reset = mv88e6352_g1_reset, |
5197 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
5198 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
5199 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
5200 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
5201 | .stu_getnext = mv88e6352_g1_stu_getnext, |
5202 | .stu_loadpurge = mv88e6352_g1_stu_loadpurge, |
5203 | .phylink_get_caps = mv88e6351_phylink_get_caps, |
5204 | }; |
5205 | |
5206 | static const struct mv88e6xxx_ops mv88e6351_ops = { |
5207 | /* MV88E6XXX_FAMILY_6351 */ |
5208 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
5209 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
5210 | .irl_init_all = mv88e6352_g2_irl_init_all, |
5211 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
5212 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
5213 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
5214 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
5215 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
5216 | .port_set_link = mv88e6xxx_port_set_link, |
5217 | .port_sync_link = mv88e6xxx_port_sync_link, |
5218 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
5219 | .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, |
5220 | .port_tag_remap = mv88e6095_port_tag_remap, |
5221 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
5222 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
5223 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
5224 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
5225 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
5226 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
5227 | .port_pause_limit = mv88e6097_port_pause_limit, |
5228 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
5229 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
5230 | .port_get_cmode = mv88e6352_port_get_cmode, |
5231 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
5232 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
5233 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
5234 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
5235 | .stats_get_strings = mv88e6095_stats_get_strings, |
5236 | .stats_get_stat = mv88e6095_stats_get_stat, |
5237 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
5238 | .set_egress_port = mv88e6095_g1_set_egress_port, |
5239 | .watchdog_ops = &mv88e6097_watchdog_ops, |
5240 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
5241 | .pot_clear = mv88e6xxx_g2_pot_clear, |
5242 | .reset = mv88e6352_g1_reset, |
5243 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
5244 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
5245 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
5246 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
5247 | .stu_getnext = mv88e6352_g1_stu_getnext, |
5248 | .stu_loadpurge = mv88e6352_g1_stu_loadpurge, |
5249 | .avb_ops = &mv88e6352_avb_ops, |
5250 | .ptp_ops = &mv88e6352_ptp_ops, |
5251 | .phylink_get_caps = mv88e6351_phylink_get_caps, |
5252 | }; |
5253 | |
5254 | static const struct mv88e6xxx_ops mv88e6352_ops = { |
5255 | /* MV88E6XXX_FAMILY_6352 */ |
5256 | .ieee_pri_map = mv88e6085_g1_ieee_pri_map, |
5257 | .ip_pri_map = mv88e6085_g1_ip_pri_map, |
5258 | .irl_init_all = mv88e6352_g2_irl_init_all, |
5259 | .get_eeprom = mv88e6xxx_g2_get_eeprom16, |
5260 | .set_eeprom = mv88e6xxx_g2_set_eeprom16, |
5261 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
5262 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
5263 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
5264 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
5265 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
5266 | .port_set_link = mv88e6xxx_port_set_link, |
5267 | .port_sync_link = mv88e6xxx_port_sync_link, |
5268 | .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, |
5269 | .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, |
5270 | .port_tag_remap = mv88e6095_port_tag_remap, |
5271 | .port_set_policy = mv88e6352_port_set_policy, |
5272 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
5273 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
5274 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
5275 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
5276 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
5277 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
5278 | .port_pause_limit = mv88e6097_port_pause_limit, |
5279 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
5280 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
5281 | .port_get_cmode = mv88e6352_port_get_cmode, |
5282 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
5283 | .stats_snapshot = mv88e6320_g1_stats_snapshot, |
5284 | .stats_set_histogram = mv88e6095_g1_stats_set_histogram, |
5285 | .stats_get_sset_count = mv88e6095_stats_get_sset_count, |
5286 | .stats_get_strings = mv88e6095_stats_get_strings, |
5287 | .stats_get_stat = mv88e6095_stats_get_stat, |
5288 | .set_cpu_port = mv88e6095_g1_set_cpu_port, |
5289 | .set_egress_port = mv88e6095_g1_set_egress_port, |
5290 | .watchdog_ops = &mv88e6097_watchdog_ops, |
5291 | .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, |
5292 | .pot_clear = mv88e6xxx_g2_pot_clear, |
5293 | .reset = mv88e6352_g1_reset, |
5294 | .rmu_disable = mv88e6352_g1_rmu_disable, |
5295 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
5296 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
5297 | .vtu_getnext = mv88e6352_g1_vtu_getnext, |
5298 | .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, |
5299 | .stu_getnext = mv88e6352_g1_stu_getnext, |
5300 | .stu_loadpurge = mv88e6352_g1_stu_loadpurge, |
5301 | .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, |
5302 | .gpio_ops = &mv88e6352_gpio_ops, |
5303 | .avb_ops = &mv88e6352_avb_ops, |
5304 | .ptp_ops = &mv88e6352_ptp_ops, |
5305 | .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, |
5306 | .serdes_get_strings = mv88e6352_serdes_get_strings, |
5307 | .serdes_get_stats = mv88e6352_serdes_get_stats, |
5308 | .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, |
5309 | .serdes_get_regs = mv88e6352_serdes_get_regs, |
5310 | .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, |
5311 | .phylink_get_caps = mv88e6352_phylink_get_caps, |
5312 | .pcs_ops = &mv88e6352_pcs_ops, |
5313 | }; |
5314 | |
5315 | static const struct mv88e6xxx_ops mv88e6390_ops = { |
5316 | /* MV88E6XXX_FAMILY_6390 */ |
5317 | .setup_errata = mv88e6390_setup_errata, |
5318 | .irl_init_all = mv88e6390_g2_irl_init_all, |
5319 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
5320 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
5321 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
5322 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
5323 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
5324 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
5325 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
5326 | .port_set_link = mv88e6xxx_port_set_link, |
5327 | .port_sync_link = mv88e6xxx_port_sync_link, |
5328 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
5329 | .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, |
5330 | .port_max_speed_mode = mv88e6390_port_max_speed_mode, |
5331 | .port_tag_remap = mv88e6390_port_tag_remap, |
5332 | .port_set_policy = mv88e6352_port_set_policy, |
5333 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
5334 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
5335 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
5336 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
5337 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
5338 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
5339 | .port_pause_limit = mv88e6390_port_pause_limit, |
5340 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
5341 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
5342 | .port_get_cmode = mv88e6352_port_get_cmode, |
5343 | .port_set_cmode = mv88e6390_port_set_cmode, |
5344 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
5345 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
5346 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
5347 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
5348 | .stats_get_strings = mv88e6320_stats_get_strings, |
5349 | .stats_get_stat = mv88e6390_stats_get_stat, |
5350 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
5351 | .set_egress_port = mv88e6390_g1_set_egress_port, |
5352 | .watchdog_ops = &mv88e6390_watchdog_ops, |
5353 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
5354 | .pot_clear = mv88e6xxx_g2_pot_clear, |
5355 | .reset = mv88e6352_g1_reset, |
5356 | .rmu_disable = mv88e6390_g1_rmu_disable, |
5357 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
5358 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
5359 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
5360 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, |
5361 | .stu_getnext = mv88e6390_g1_stu_getnext, |
5362 | .stu_loadpurge = mv88e6390_g1_stu_loadpurge, |
5363 | .serdes_get_lane = mv88e6390_serdes_get_lane, |
5364 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
5365 | .gpio_ops = &mv88e6352_gpio_ops, |
5366 | .avb_ops = &mv88e6390_avb_ops, |
5367 | .ptp_ops = &mv88e6390_ptp_ops, |
5368 | .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, |
5369 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
5370 | .serdes_get_stats = mv88e6390_serdes_get_stats, |
5371 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
5372 | .serdes_get_regs = mv88e6390_serdes_get_regs, |
5373 | .phylink_get_caps = mv88e6390_phylink_get_caps, |
5374 | .pcs_ops = &mv88e6390_pcs_ops, |
5375 | }; |
5376 | |
5377 | static const struct mv88e6xxx_ops mv88e6390x_ops = { |
5378 | /* MV88E6XXX_FAMILY_6390 */ |
5379 | .setup_errata = mv88e6390_setup_errata, |
5380 | .irl_init_all = mv88e6390_g2_irl_init_all, |
5381 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
5382 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
5383 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
5384 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
5385 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
5386 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
5387 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
5388 | .port_set_link = mv88e6xxx_port_set_link, |
5389 | .port_sync_link = mv88e6xxx_port_sync_link, |
5390 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
5391 | .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, |
5392 | .port_max_speed_mode = mv88e6390x_port_max_speed_mode, |
5393 | .port_tag_remap = mv88e6390_port_tag_remap, |
5394 | .port_set_policy = mv88e6352_port_set_policy, |
5395 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
5396 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
5397 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
5398 | .port_set_ether_type = mv88e6351_port_set_ether_type, |
5399 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
5400 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
5401 | .port_pause_limit = mv88e6390_port_pause_limit, |
5402 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
5403 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
5404 | .port_get_cmode = mv88e6352_port_get_cmode, |
5405 | .port_set_cmode = mv88e6390x_port_set_cmode, |
5406 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
5407 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
5408 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
5409 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
5410 | .stats_get_strings = mv88e6320_stats_get_strings, |
5411 | .stats_get_stat = mv88e6390_stats_get_stat, |
5412 | .set_cpu_port = mv88e6390_g1_set_cpu_port, |
5413 | .set_egress_port = mv88e6390_g1_set_egress_port, |
5414 | .watchdog_ops = &mv88e6390_watchdog_ops, |
5415 | .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, |
5416 | .pot_clear = mv88e6xxx_g2_pot_clear, |
5417 | .reset = mv88e6352_g1_reset, |
5418 | .rmu_disable = mv88e6390_g1_rmu_disable, |
5419 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
5420 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
5421 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
5422 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, |
5423 | .stu_getnext = mv88e6390_g1_stu_getnext, |
5424 | .stu_loadpurge = mv88e6390_g1_stu_loadpurge, |
5425 | .serdes_get_lane = mv88e6390x_serdes_get_lane, |
5426 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
5427 | .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, |
5428 | .serdes_get_strings = mv88e6390_serdes_get_strings, |
5429 | .serdes_get_stats = mv88e6390_serdes_get_stats, |
5430 | .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, |
5431 | .serdes_get_regs = mv88e6390_serdes_get_regs, |
5432 | .gpio_ops = &mv88e6352_gpio_ops, |
5433 | .avb_ops = &mv88e6390_avb_ops, |
5434 | .ptp_ops = &mv88e6390_ptp_ops, |
5435 | .phylink_get_caps = mv88e6390x_phylink_get_caps, |
5436 | .pcs_ops = &mv88e6390_pcs_ops, |
5437 | }; |
5438 | |
5439 | static const struct mv88e6xxx_ops mv88e6393x_ops = { |
5440 | /* MV88E6XXX_FAMILY_6393 */ |
5441 | .irl_init_all = mv88e6390_g2_irl_init_all, |
5442 | .get_eeprom = mv88e6xxx_g2_get_eeprom8, |
5443 | .set_eeprom = mv88e6xxx_g2_set_eeprom8, |
5444 | .set_switch_mac = mv88e6xxx_g2_set_switch_mac, |
5445 | .phy_read = mv88e6xxx_g2_smi_phy_read_c22, |
5446 | .phy_write = mv88e6xxx_g2_smi_phy_write_c22, |
5447 | .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, |
5448 | .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, |
5449 | .port_set_link = mv88e6xxx_port_set_link, |
5450 | .port_sync_link = mv88e6xxx_port_sync_link, |
5451 | .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, |
5452 | .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, |
5453 | .port_max_speed_mode = mv88e6393x_port_max_speed_mode, |
5454 | .port_tag_remap = mv88e6390_port_tag_remap, |
5455 | .port_set_policy = mv88e6393x_port_set_policy, |
5456 | .port_set_frame_mode = mv88e6351_port_set_frame_mode, |
5457 | .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, |
5458 | .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, |
5459 | .port_set_ether_type = mv88e6393x_port_set_ether_type, |
5460 | .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, |
5461 | .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, |
5462 | .port_pause_limit = mv88e6390_port_pause_limit, |
5463 | .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, |
5464 | .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, |
5465 | .port_get_cmode = mv88e6352_port_get_cmode, |
5466 | .port_set_cmode = mv88e6393x_port_set_cmode, |
5467 | .port_setup_message_port = mv88e6xxx_setup_message_port, |
5468 | .port_set_upstream_port = mv88e6393x_port_set_upstream_port, |
5469 | .stats_snapshot = mv88e6390_g1_stats_snapshot, |
5470 | .stats_set_histogram = mv88e6390_g1_stats_set_histogram, |
5471 | .stats_get_sset_count = mv88e6320_stats_get_sset_count, |
5472 | .stats_get_strings = mv88e6320_stats_get_strings, |
5473 | .stats_get_stat = mv88e6390_stats_get_stat, |
5474 | /* .set_cpu_port is missing because this family does not support a global |
5475 | * CPU port, only per port CPU port which is set via |
5476 | * .port_set_upstream_port method. |
5477 | */ |
5478 | .set_egress_port = mv88e6393x_set_egress_port, |
5479 | .watchdog_ops = &mv88e6393x_watchdog_ops, |
5480 | .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, |
5481 | .pot_clear = mv88e6xxx_g2_pot_clear, |
5482 | .reset = mv88e6352_g1_reset, |
5483 | .rmu_disable = mv88e6390_g1_rmu_disable, |
5484 | .atu_get_hash = mv88e6165_g1_atu_get_hash, |
5485 | .atu_set_hash = mv88e6165_g1_atu_set_hash, |
5486 | .vtu_getnext = mv88e6390_g1_vtu_getnext, |
5487 | .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, |
5488 | .stu_getnext = mv88e6390_g1_stu_getnext, |
5489 | .stu_loadpurge = mv88e6390_g1_stu_loadpurge, |
5490 | .serdes_get_lane = mv88e6393x_serdes_get_lane, |
5491 | .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, |
5492 | /* TODO: serdes stats */ |
5493 | .gpio_ops = &mv88e6352_gpio_ops, |
5494 | .avb_ops = &mv88e6390_avb_ops, |
5495 | .ptp_ops = &mv88e6352_ptp_ops, |
5496 | .phylink_get_caps = mv88e6393x_phylink_get_caps, |
5497 | .pcs_ops = &mv88e6393x_pcs_ops, |
5498 | }; |
5499 | |
5500 | static const struct mv88e6xxx_info mv88e6xxx_table[] = { |
5501 | [MV88E6020] = { |
5502 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, |
5503 | .family = MV88E6XXX_FAMILY_6250, |
5504 | .name = "Marvell 88E6020" , |
5505 | .num_databases = 64, |
5506 | /* Ports 2-4 are not routed to pins |
5507 | * => usable ports 0, 1, 5, 6 |
5508 | */ |
5509 | .num_ports = 7, |
5510 | .num_internal_phys = 2, |
5511 | .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), |
5512 | .max_vid = 4095, |
5513 | .port_base_addr = 0x8, |
5514 | .phy_base_addr = 0x0, |
5515 | .global1_addr = 0xf, |
5516 | .global2_addr = 0x7, |
5517 | .age_time_coeff = 15000, |
5518 | .g1_irqs = 9, |
5519 | .g2_irqs = 5, |
5520 | .atu_move_port_mask = 0xf, |
5521 | .dual_chip = true, |
5522 | .ops = &mv88e6250_ops, |
5523 | }, |
5524 | |
5525 | [MV88E6071] = { |
5526 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, |
5527 | .family = MV88E6XXX_FAMILY_6250, |
5528 | .name = "Marvell 88E6071" , |
5529 | .num_databases = 64, |
5530 | .num_ports = 7, |
5531 | .num_internal_phys = 5, |
5532 | .max_vid = 4095, |
5533 | .port_base_addr = 0x08, |
5534 | .phy_base_addr = 0x00, |
5535 | .global1_addr = 0x0f, |
5536 | .global2_addr = 0x07, |
5537 | .age_time_coeff = 15000, |
5538 | .g1_irqs = 9, |
5539 | .g2_irqs = 5, |
5540 | .atu_move_port_mask = 0xf, |
5541 | .dual_chip = true, |
5542 | .ops = &mv88e6250_ops, |
5543 | }, |
5544 | |
5545 | [MV88E6085] = { |
5546 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, |
5547 | .family = MV88E6XXX_FAMILY_6097, |
5548 | .name = "Marvell 88E6085" , |
5549 | .num_databases = 4096, |
5550 | .num_macs = 8192, |
5551 | .num_ports = 10, |
5552 | .num_internal_phys = 5, |
5553 | .max_vid = 4095, |
5554 | .max_sid = 63, |
5555 | .port_base_addr = 0x10, |
5556 | .phy_base_addr = 0x0, |
5557 | .global1_addr = 0x1b, |
5558 | .global2_addr = 0x1c, |
5559 | .age_time_coeff = 15000, |
5560 | .g1_irqs = 8, |
5561 | .g2_irqs = 10, |
5562 | .atu_move_port_mask = 0xf, |
5563 | .pvt = true, |
5564 | .multi_chip = true, |
5565 | .ops = &mv88e6085_ops, |
5566 | }, |
5567 | |
5568 | [MV88E6095] = { |
5569 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, |
5570 | .family = MV88E6XXX_FAMILY_6095, |
5571 | .name = "Marvell 88E6095/88E6095F" , |
5572 | .num_databases = 256, |
5573 | .num_macs = 8192, |
5574 | .num_ports = 11, |
5575 | .num_internal_phys = 0, |
5576 | .max_vid = 4095, |
5577 | .port_base_addr = 0x10, |
5578 | .phy_base_addr = 0x0, |
5579 | .global1_addr = 0x1b, |
5580 | .global2_addr = 0x1c, |
5581 | .age_time_coeff = 15000, |
5582 | .g1_irqs = 8, |
5583 | .atu_move_port_mask = 0xf, |
5584 | .multi_chip = true, |
5585 | .ops = &mv88e6095_ops, |
5586 | }, |
5587 | |
5588 | [MV88E6097] = { |
5589 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, |
5590 | .family = MV88E6XXX_FAMILY_6097, |
5591 | .name = "Marvell 88E6097/88E6097F" , |
5592 | .num_databases = 4096, |
5593 | .num_macs = 8192, |
5594 | .num_ports = 11, |
5595 | .num_internal_phys = 8, |
5596 | .max_vid = 4095, |
5597 | .max_sid = 63, |
5598 | .port_base_addr = 0x10, |
5599 | .phy_base_addr = 0x0, |
5600 | .global1_addr = 0x1b, |
5601 | .global2_addr = 0x1c, |
5602 | .age_time_coeff = 15000, |
5603 | .g1_irqs = 8, |
5604 | .g2_irqs = 10, |
5605 | .atu_move_port_mask = 0xf, |
5606 | .pvt = true, |
5607 | .multi_chip = true, |
5608 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
5609 | .ops = &mv88e6097_ops, |
5610 | }, |
5611 | |
5612 | [MV88E6123] = { |
5613 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, |
5614 | .family = MV88E6XXX_FAMILY_6165, |
5615 | .name = "Marvell 88E6123" , |
5616 | .num_databases = 4096, |
5617 | .num_macs = 1024, |
5618 | .num_ports = 3, |
5619 | .num_internal_phys = 5, |
5620 | .max_vid = 4095, |
5621 | .max_sid = 63, |
5622 | .port_base_addr = 0x10, |
5623 | .phy_base_addr = 0x0, |
5624 | .global1_addr = 0x1b, |
5625 | .global2_addr = 0x1c, |
5626 | .age_time_coeff = 15000, |
5627 | .g1_irqs = 9, |
5628 | .g2_irqs = 10, |
5629 | .atu_move_port_mask = 0xf, |
5630 | .pvt = true, |
5631 | .multi_chip = true, |
5632 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
5633 | .ops = &mv88e6123_ops, |
5634 | }, |
5635 | |
5636 | [MV88E6131] = { |
5637 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, |
5638 | .family = MV88E6XXX_FAMILY_6185, |
5639 | .name = "Marvell 88E6131" , |
5640 | .num_databases = 256, |
5641 | .num_macs = 8192, |
5642 | .num_ports = 8, |
5643 | .num_internal_phys = 0, |
5644 | .max_vid = 4095, |
5645 | .port_base_addr = 0x10, |
5646 | .phy_base_addr = 0x0, |
5647 | .global1_addr = 0x1b, |
5648 | .global2_addr = 0x1c, |
5649 | .age_time_coeff = 15000, |
5650 | .g1_irqs = 9, |
5651 | .atu_move_port_mask = 0xf, |
5652 | .multi_chip = true, |
5653 | .ops = &mv88e6131_ops, |
5654 | }, |
5655 | |
5656 | [MV88E6141] = { |
5657 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, |
5658 | .family = MV88E6XXX_FAMILY_6341, |
5659 | .name = "Marvell 88E6141" , |
5660 | .num_databases = 4096, |
5661 | .num_macs = 2048, |
5662 | .num_ports = 6, |
5663 | .num_internal_phys = 5, |
5664 | .num_gpio = 11, |
5665 | .max_vid = 4095, |
5666 | .max_sid = 63, |
5667 | .port_base_addr = 0x10, |
5668 | .phy_base_addr = 0x10, |
5669 | .global1_addr = 0x1b, |
5670 | .global2_addr = 0x1c, |
5671 | .age_time_coeff = 3750, |
5672 | .atu_move_port_mask = 0x1f, |
5673 | .g1_irqs = 9, |
5674 | .g2_irqs = 10, |
5675 | .pvt = true, |
5676 | .multi_chip = true, |
5677 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
5678 | .ops = &mv88e6141_ops, |
5679 | }, |
5680 | |
5681 | [MV88E6161] = { |
5682 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, |
5683 | .family = MV88E6XXX_FAMILY_6165, |
5684 | .name = "Marvell 88E6161" , |
5685 | .num_databases = 4096, |
5686 | .num_macs = 1024, |
5687 | .num_ports = 6, |
5688 | .num_internal_phys = 5, |
5689 | .max_vid = 4095, |
5690 | .max_sid = 63, |
5691 | .port_base_addr = 0x10, |
5692 | .phy_base_addr = 0x0, |
5693 | .global1_addr = 0x1b, |
5694 | .global2_addr = 0x1c, |
5695 | .age_time_coeff = 15000, |
5696 | .g1_irqs = 9, |
5697 | .g2_irqs = 10, |
5698 | .atu_move_port_mask = 0xf, |
5699 | .pvt = true, |
5700 | .multi_chip = true, |
5701 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
5702 | .ptp_support = true, |
5703 | .ops = &mv88e6161_ops, |
5704 | }, |
5705 | |
5706 | [MV88E6165] = { |
5707 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, |
5708 | .family = MV88E6XXX_FAMILY_6165, |
5709 | .name = "Marvell 88E6165" , |
5710 | .num_databases = 4096, |
5711 | .num_macs = 8192, |
5712 | .num_ports = 6, |
5713 | .num_internal_phys = 0, |
5714 | .max_vid = 4095, |
5715 | .max_sid = 63, |
5716 | .port_base_addr = 0x10, |
5717 | .phy_base_addr = 0x0, |
5718 | .global1_addr = 0x1b, |
5719 | .global2_addr = 0x1c, |
5720 | .age_time_coeff = 15000, |
5721 | .g1_irqs = 9, |
5722 | .g2_irqs = 10, |
5723 | .atu_move_port_mask = 0xf, |
5724 | .pvt = true, |
5725 | .multi_chip = true, |
5726 | .ptp_support = true, |
5727 | .ops = &mv88e6165_ops, |
5728 | }, |
5729 | |
5730 | [MV88E6171] = { |
5731 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, |
5732 | .family = MV88E6XXX_FAMILY_6351, |
5733 | .name = "Marvell 88E6171" , |
5734 | .num_databases = 4096, |
5735 | .num_macs = 8192, |
5736 | .num_ports = 7, |
5737 | .num_internal_phys = 5, |
5738 | .max_vid = 4095, |
5739 | .max_sid = 63, |
5740 | .port_base_addr = 0x10, |
5741 | .phy_base_addr = 0x0, |
5742 | .global1_addr = 0x1b, |
5743 | .global2_addr = 0x1c, |
5744 | .age_time_coeff = 15000, |
5745 | .g1_irqs = 9, |
5746 | .g2_irqs = 10, |
5747 | .atu_move_port_mask = 0xf, |
5748 | .pvt = true, |
5749 | .multi_chip = true, |
5750 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
5751 | .ops = &mv88e6171_ops, |
5752 | }, |
5753 | |
5754 | [MV88E6172] = { |
5755 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, |
5756 | .family = MV88E6XXX_FAMILY_6352, |
5757 | .name = "Marvell 88E6172" , |
5758 | .num_databases = 4096, |
5759 | .num_macs = 8192, |
5760 | .num_ports = 7, |
5761 | .num_internal_phys = 5, |
5762 | .num_gpio = 15, |
5763 | .max_vid = 4095, |
5764 | .max_sid = 63, |
5765 | .port_base_addr = 0x10, |
5766 | .phy_base_addr = 0x0, |
5767 | .global1_addr = 0x1b, |
5768 | .global2_addr = 0x1c, |
5769 | .age_time_coeff = 15000, |
5770 | .g1_irqs = 9, |
5771 | .g2_irqs = 10, |
5772 | .atu_move_port_mask = 0xf, |
5773 | .pvt = true, |
5774 | .multi_chip = true, |
5775 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
5776 | .ops = &mv88e6172_ops, |
5777 | }, |
5778 | |
5779 | [MV88E6175] = { |
5780 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, |
5781 | .family = MV88E6XXX_FAMILY_6351, |
5782 | .name = "Marvell 88E6175" , |
5783 | .num_databases = 4096, |
5784 | .num_macs = 8192, |
5785 | .num_ports = 7, |
5786 | .num_internal_phys = 5, |
5787 | .max_vid = 4095, |
5788 | .max_sid = 63, |
5789 | .port_base_addr = 0x10, |
5790 | .phy_base_addr = 0x0, |
5791 | .global1_addr = 0x1b, |
5792 | .global2_addr = 0x1c, |
5793 | .age_time_coeff = 15000, |
5794 | .g1_irqs = 9, |
5795 | .g2_irqs = 10, |
5796 | .atu_move_port_mask = 0xf, |
5797 | .pvt = true, |
5798 | .multi_chip = true, |
5799 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
5800 | .ops = &mv88e6175_ops, |
5801 | }, |
5802 | |
5803 | [MV88E6176] = { |
5804 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, |
5805 | .family = MV88E6XXX_FAMILY_6352, |
5806 | .name = "Marvell 88E6176" , |
5807 | .num_databases = 4096, |
5808 | .num_macs = 8192, |
5809 | .num_ports = 7, |
5810 | .num_internal_phys = 5, |
5811 | .num_gpio = 15, |
5812 | .max_vid = 4095, |
5813 | .max_sid = 63, |
5814 | .port_base_addr = 0x10, |
5815 | .phy_base_addr = 0x0, |
5816 | .global1_addr = 0x1b, |
5817 | .global2_addr = 0x1c, |
5818 | .age_time_coeff = 15000, |
5819 | .g1_irqs = 9, |
5820 | .g2_irqs = 10, |
5821 | .atu_move_port_mask = 0xf, |
5822 | .pvt = true, |
5823 | .multi_chip = true, |
5824 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
5825 | .ops = &mv88e6176_ops, |
5826 | }, |
5827 | |
5828 | [MV88E6185] = { |
5829 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, |
5830 | .family = MV88E6XXX_FAMILY_6185, |
5831 | .name = "Marvell 88E6185" , |
5832 | .num_databases = 256, |
5833 | .num_macs = 8192, |
5834 | .num_ports = 10, |
5835 | .num_internal_phys = 0, |
5836 | .max_vid = 4095, |
5837 | .port_base_addr = 0x10, |
5838 | .phy_base_addr = 0x0, |
5839 | .global1_addr = 0x1b, |
5840 | .global2_addr = 0x1c, |
5841 | .age_time_coeff = 15000, |
5842 | .g1_irqs = 8, |
5843 | .atu_move_port_mask = 0xf, |
5844 | .multi_chip = true, |
5845 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
5846 | .ops = &mv88e6185_ops, |
5847 | }, |
5848 | |
5849 | [MV88E6190] = { |
5850 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, |
5851 | .family = MV88E6XXX_FAMILY_6390, |
5852 | .name = "Marvell 88E6190" , |
5853 | .num_databases = 4096, |
5854 | .num_macs = 16384, |
5855 | .num_ports = 11, /* 10 + Z80 */ |
5856 | .num_internal_phys = 9, |
5857 | .num_gpio = 16, |
5858 | .max_vid = 8191, |
5859 | .max_sid = 63, |
5860 | .port_base_addr = 0x0, |
5861 | .phy_base_addr = 0x0, |
5862 | .global1_addr = 0x1b, |
5863 | .global2_addr = 0x1c, |
5864 | .age_time_coeff = 3750, |
5865 | .g1_irqs = 9, |
5866 | .g2_irqs = 14, |
5867 | .pvt = true, |
5868 | .multi_chip = true, |
5869 | .atu_move_port_mask = 0x1f, |
5870 | .ops = &mv88e6190_ops, |
5871 | }, |
5872 | |
5873 | [MV88E6190X] = { |
5874 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, |
5875 | .family = MV88E6XXX_FAMILY_6390, |
5876 | .name = "Marvell 88E6190X" , |
5877 | .num_databases = 4096, |
5878 | .num_macs = 16384, |
5879 | .num_ports = 11, /* 10 + Z80 */ |
5880 | .num_internal_phys = 9, |
5881 | .num_gpio = 16, |
5882 | .max_vid = 8191, |
5883 | .max_sid = 63, |
5884 | .port_base_addr = 0x0, |
5885 | .phy_base_addr = 0x0, |
5886 | .global1_addr = 0x1b, |
5887 | .global2_addr = 0x1c, |
5888 | .age_time_coeff = 3750, |
5889 | .g1_irqs = 9, |
5890 | .g2_irqs = 14, |
5891 | .atu_move_port_mask = 0x1f, |
5892 | .pvt = true, |
5893 | .multi_chip = true, |
5894 | .ops = &mv88e6190x_ops, |
5895 | }, |
5896 | |
5897 | [MV88E6191] = { |
5898 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, |
5899 | .family = MV88E6XXX_FAMILY_6390, |
5900 | .name = "Marvell 88E6191" , |
5901 | .num_databases = 4096, |
5902 | .num_macs = 16384, |
5903 | .num_ports = 11, /* 10 + Z80 */ |
5904 | .num_internal_phys = 9, |
5905 | .max_vid = 8191, |
5906 | .max_sid = 63, |
5907 | .port_base_addr = 0x0, |
5908 | .phy_base_addr = 0x0, |
5909 | .global1_addr = 0x1b, |
5910 | .global2_addr = 0x1c, |
5911 | .age_time_coeff = 3750, |
5912 | .g1_irqs = 9, |
5913 | .g2_irqs = 14, |
5914 | .atu_move_port_mask = 0x1f, |
5915 | .pvt = true, |
5916 | .multi_chip = true, |
5917 | .ptp_support = true, |
5918 | .ops = &mv88e6191_ops, |
5919 | }, |
5920 | |
5921 | [MV88E6191X] = { |
5922 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, |
5923 | .family = MV88E6XXX_FAMILY_6393, |
5924 | .name = "Marvell 88E6191X" , |
5925 | .num_databases = 4096, |
5926 | .num_ports = 11, /* 10 + Z80 */ |
5927 | .num_internal_phys = 8, |
5928 | .internal_phys_offset = 1, |
5929 | .max_vid = 8191, |
5930 | .max_sid = 63, |
5931 | .port_base_addr = 0x0, |
5932 | .phy_base_addr = 0x0, |
5933 | .global1_addr = 0x1b, |
5934 | .global2_addr = 0x1c, |
5935 | .age_time_coeff = 3750, |
5936 | .g1_irqs = 10, |
5937 | .g2_irqs = 14, |
5938 | .atu_move_port_mask = 0x1f, |
5939 | .pvt = true, |
5940 | .multi_chip = true, |
5941 | .ptp_support = true, |
5942 | .ops = &mv88e6393x_ops, |
5943 | }, |
5944 | |
5945 | [MV88E6193X] = { |
5946 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, |
5947 | .family = MV88E6XXX_FAMILY_6393, |
5948 | .name = "Marvell 88E6193X" , |
5949 | .num_databases = 4096, |
5950 | .num_ports = 11, /* 10 + Z80 */ |
5951 | .num_internal_phys = 8, |
5952 | .internal_phys_offset = 1, |
5953 | .max_vid = 8191, |
5954 | .max_sid = 63, |
5955 | .port_base_addr = 0x0, |
5956 | .phy_base_addr = 0x0, |
5957 | .global1_addr = 0x1b, |
5958 | .global2_addr = 0x1c, |
5959 | .age_time_coeff = 3750, |
5960 | .g1_irqs = 10, |
5961 | .g2_irqs = 14, |
5962 | .atu_move_port_mask = 0x1f, |
5963 | .pvt = true, |
5964 | .multi_chip = true, |
5965 | .ptp_support = true, |
5966 | .ops = &mv88e6393x_ops, |
5967 | }, |
5968 | |
5969 | [MV88E6220] = { |
5970 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, |
5971 | .family = MV88E6XXX_FAMILY_6250, |
5972 | .name = "Marvell 88E6220" , |
5973 | .num_databases = 64, |
5974 | |
5975 | /* Ports 2-4 are not routed to pins |
5976 | * => usable ports 0, 1, 5, 6 |
5977 | */ |
5978 | .num_ports = 7, |
5979 | .num_internal_phys = 2, |
5980 | .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), |
5981 | .max_vid = 4095, |
5982 | .port_base_addr = 0x08, |
5983 | .phy_base_addr = 0x00, |
5984 | .global1_addr = 0x0f, |
5985 | .global2_addr = 0x07, |
5986 | .age_time_coeff = 15000, |
5987 | .g1_irqs = 9, |
5988 | .g2_irqs = 10, |
5989 | .atu_move_port_mask = 0xf, |
5990 | .dual_chip = true, |
5991 | .ptp_support = true, |
5992 | .ops = &mv88e6250_ops, |
5993 | }, |
5994 | |
5995 | [MV88E6240] = { |
5996 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, |
5997 | .family = MV88E6XXX_FAMILY_6352, |
5998 | .name = "Marvell 88E6240" , |
5999 | .num_databases = 4096, |
6000 | .num_macs = 8192, |
6001 | .num_ports = 7, |
6002 | .num_internal_phys = 5, |
6003 | .num_gpio = 15, |
6004 | .max_vid = 4095, |
6005 | .max_sid = 63, |
6006 | .port_base_addr = 0x10, |
6007 | .phy_base_addr = 0x0, |
6008 | .global1_addr = 0x1b, |
6009 | .global2_addr = 0x1c, |
6010 | .age_time_coeff = 15000, |
6011 | .g1_irqs = 9, |
6012 | .g2_irqs = 10, |
6013 | .atu_move_port_mask = 0xf, |
6014 | .pvt = true, |
6015 | .multi_chip = true, |
6016 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
6017 | .ptp_support = true, |
6018 | .ops = &mv88e6240_ops, |
6019 | }, |
6020 | |
6021 | [MV88E6250] = { |
6022 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, |
6023 | .family = MV88E6XXX_FAMILY_6250, |
6024 | .name = "Marvell 88E6250" , |
6025 | .num_databases = 64, |
6026 | .num_ports = 7, |
6027 | .num_internal_phys = 5, |
6028 | .max_vid = 4095, |
6029 | .port_base_addr = 0x08, |
6030 | .phy_base_addr = 0x00, |
6031 | .global1_addr = 0x0f, |
6032 | .global2_addr = 0x07, |
6033 | .age_time_coeff = 15000, |
6034 | .g1_irqs = 9, |
6035 | .g2_irqs = 10, |
6036 | .atu_move_port_mask = 0xf, |
6037 | .dual_chip = true, |
6038 | .ptp_support = true, |
6039 | .ops = &mv88e6250_ops, |
6040 | }, |
6041 | |
6042 | [MV88E6290] = { |
6043 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, |
6044 | .family = MV88E6XXX_FAMILY_6390, |
6045 | .name = "Marvell 88E6290" , |
6046 | .num_databases = 4096, |
6047 | .num_ports = 11, /* 10 + Z80 */ |
6048 | .num_internal_phys = 9, |
6049 | .num_gpio = 16, |
6050 | .max_vid = 8191, |
6051 | .max_sid = 63, |
6052 | .port_base_addr = 0x0, |
6053 | .phy_base_addr = 0x0, |
6054 | .global1_addr = 0x1b, |
6055 | .global2_addr = 0x1c, |
6056 | .age_time_coeff = 3750, |
6057 | .g1_irqs = 9, |
6058 | .g2_irqs = 14, |
6059 | .atu_move_port_mask = 0x1f, |
6060 | .pvt = true, |
6061 | .multi_chip = true, |
6062 | .ptp_support = true, |
6063 | .ops = &mv88e6290_ops, |
6064 | }, |
6065 | |
6066 | [MV88E6320] = { |
6067 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, |
6068 | .family = MV88E6XXX_FAMILY_6320, |
6069 | .name = "Marvell 88E6320" , |
6070 | .num_databases = 4096, |
6071 | .num_macs = 8192, |
6072 | .num_ports = 7, |
6073 | .num_internal_phys = 5, |
6074 | .num_gpio = 15, |
6075 | .max_vid = 4095, |
6076 | .port_base_addr = 0x10, |
6077 | .phy_base_addr = 0x0, |
6078 | .global1_addr = 0x1b, |
6079 | .global2_addr = 0x1c, |
6080 | .age_time_coeff = 15000, |
6081 | .g1_irqs = 8, |
6082 | .g2_irqs = 10, |
6083 | .atu_move_port_mask = 0xf, |
6084 | .pvt = true, |
6085 | .multi_chip = true, |
6086 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
6087 | .ptp_support = true, |
6088 | .ops = &mv88e6320_ops, |
6089 | }, |
6090 | |
6091 | [MV88E6321] = { |
6092 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, |
6093 | .family = MV88E6XXX_FAMILY_6320, |
6094 | .name = "Marvell 88E6321" , |
6095 | .num_databases = 4096, |
6096 | .num_macs = 8192, |
6097 | .num_ports = 7, |
6098 | .num_internal_phys = 5, |
6099 | .num_gpio = 15, |
6100 | .max_vid = 4095, |
6101 | .port_base_addr = 0x10, |
6102 | .phy_base_addr = 0x0, |
6103 | .global1_addr = 0x1b, |
6104 | .global2_addr = 0x1c, |
6105 | .age_time_coeff = 15000, |
6106 | .g1_irqs = 8, |
6107 | .g2_irqs = 10, |
6108 | .atu_move_port_mask = 0xf, |
6109 | .multi_chip = true, |
6110 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
6111 | .ptp_support = true, |
6112 | .ops = &mv88e6321_ops, |
6113 | }, |
6114 | |
6115 | [MV88E6341] = { |
6116 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, |
6117 | .family = MV88E6XXX_FAMILY_6341, |
6118 | .name = "Marvell 88E6341" , |
6119 | .num_databases = 4096, |
6120 | .num_macs = 2048, |
6121 | .num_internal_phys = 5, |
6122 | .num_ports = 6, |
6123 | .num_gpio = 11, |
6124 | .max_vid = 4095, |
6125 | .max_sid = 63, |
6126 | .port_base_addr = 0x10, |
6127 | .phy_base_addr = 0x10, |
6128 | .global1_addr = 0x1b, |
6129 | .global2_addr = 0x1c, |
6130 | .age_time_coeff = 3750, |
6131 | .atu_move_port_mask = 0x1f, |
6132 | .g1_irqs = 9, |
6133 | .g2_irqs = 10, |
6134 | .pvt = true, |
6135 | .multi_chip = true, |
6136 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
6137 | .ptp_support = true, |
6138 | .ops = &mv88e6341_ops, |
6139 | }, |
6140 | |
6141 | [MV88E6350] = { |
6142 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, |
6143 | .family = MV88E6XXX_FAMILY_6351, |
6144 | .name = "Marvell 88E6350" , |
6145 | .num_databases = 4096, |
6146 | .num_macs = 8192, |
6147 | .num_ports = 7, |
6148 | .num_internal_phys = 5, |
6149 | .max_vid = 4095, |
6150 | .max_sid = 63, |
6151 | .port_base_addr = 0x10, |
6152 | .phy_base_addr = 0x0, |
6153 | .global1_addr = 0x1b, |
6154 | .global2_addr = 0x1c, |
6155 | .age_time_coeff = 15000, |
6156 | .g1_irqs = 9, |
6157 | .g2_irqs = 10, |
6158 | .atu_move_port_mask = 0xf, |
6159 | .pvt = true, |
6160 | .multi_chip = true, |
6161 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
6162 | .ops = &mv88e6350_ops, |
6163 | }, |
6164 | |
6165 | [MV88E6351] = { |
6166 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, |
6167 | .family = MV88E6XXX_FAMILY_6351, |
6168 | .name = "Marvell 88E6351" , |
6169 | .num_databases = 4096, |
6170 | .num_macs = 8192, |
6171 | .num_ports = 7, |
6172 | .num_internal_phys = 5, |
6173 | .max_vid = 4095, |
6174 | .max_sid = 63, |
6175 | .port_base_addr = 0x10, |
6176 | .phy_base_addr = 0x0, |
6177 | .global1_addr = 0x1b, |
6178 | .global2_addr = 0x1c, |
6179 | .age_time_coeff = 15000, |
6180 | .g1_irqs = 9, |
6181 | .g2_irqs = 10, |
6182 | .atu_move_port_mask = 0xf, |
6183 | .pvt = true, |
6184 | .multi_chip = true, |
6185 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
6186 | .ops = &mv88e6351_ops, |
6187 | }, |
6188 | |
6189 | [MV88E6352] = { |
6190 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, |
6191 | .family = MV88E6XXX_FAMILY_6352, |
6192 | .name = "Marvell 88E6352" , |
6193 | .num_databases = 4096, |
6194 | .num_macs = 8192, |
6195 | .num_ports = 7, |
6196 | .num_internal_phys = 5, |
6197 | .num_gpio = 15, |
6198 | .max_vid = 4095, |
6199 | .max_sid = 63, |
6200 | .port_base_addr = 0x10, |
6201 | .phy_base_addr = 0x0, |
6202 | .global1_addr = 0x1b, |
6203 | .global2_addr = 0x1c, |
6204 | .age_time_coeff = 15000, |
6205 | .g1_irqs = 9, |
6206 | .g2_irqs = 10, |
6207 | .atu_move_port_mask = 0xf, |
6208 | .pvt = true, |
6209 | .multi_chip = true, |
6210 | .edsa_support = MV88E6XXX_EDSA_SUPPORTED, |
6211 | .ptp_support = true, |
6212 | .ops = &mv88e6352_ops, |
6213 | }, |
6214 | [MV88E6361] = { |
6215 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, |
6216 | .family = MV88E6XXX_FAMILY_6393, |
6217 | .name = "Marvell 88E6361" , |
6218 | .num_databases = 4096, |
6219 | .num_macs = 16384, |
6220 | .num_ports = 11, |
6221 | /* Ports 1, 2 and 8 are not routed */ |
6222 | .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), |
6223 | .num_internal_phys = 5, |
6224 | .internal_phys_offset = 3, |
6225 | .max_vid = 4095, |
6226 | .max_sid = 63, |
6227 | .port_base_addr = 0x0, |
6228 | .phy_base_addr = 0x0, |
6229 | .global1_addr = 0x1b, |
6230 | .global2_addr = 0x1c, |
6231 | .age_time_coeff = 3750, |
6232 | .g1_irqs = 10, |
6233 | .g2_irqs = 14, |
6234 | .atu_move_port_mask = 0x1f, |
6235 | .pvt = true, |
6236 | .multi_chip = true, |
6237 | .ptp_support = true, |
6238 | .ops = &mv88e6393x_ops, |
6239 | }, |
6240 | [MV88E6390] = { |
6241 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, |
6242 | .family = MV88E6XXX_FAMILY_6390, |
6243 | .name = "Marvell 88E6390" , |
6244 | .num_databases = 4096, |
6245 | .num_macs = 16384, |
6246 | .num_ports = 11, /* 10 + Z80 */ |
6247 | .num_internal_phys = 9, |
6248 | .num_gpio = 16, |
6249 | .max_vid = 8191, |
6250 | .max_sid = 63, |
6251 | .port_base_addr = 0x0, |
6252 | .phy_base_addr = 0x0, |
6253 | .global1_addr = 0x1b, |
6254 | .global2_addr = 0x1c, |
6255 | .age_time_coeff = 3750, |
6256 | .g1_irqs = 9, |
6257 | .g2_irqs = 14, |
6258 | .atu_move_port_mask = 0x1f, |
6259 | .pvt = true, |
6260 | .multi_chip = true, |
6261 | .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, |
6262 | .ptp_support = true, |
6263 | .ops = &mv88e6390_ops, |
6264 | }, |
6265 | [MV88E6390X] = { |
6266 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, |
6267 | .family = MV88E6XXX_FAMILY_6390, |
6268 | .name = "Marvell 88E6390X" , |
6269 | .num_databases = 4096, |
6270 | .num_macs = 16384, |
6271 | .num_ports = 11, /* 10 + Z80 */ |
6272 | .num_internal_phys = 9, |
6273 | .num_gpio = 16, |
6274 | .max_vid = 8191, |
6275 | .max_sid = 63, |
6276 | .port_base_addr = 0x0, |
6277 | .phy_base_addr = 0x0, |
6278 | .global1_addr = 0x1b, |
6279 | .global2_addr = 0x1c, |
6280 | .age_time_coeff = 3750, |
6281 | .g1_irqs = 9, |
6282 | .g2_irqs = 14, |
6283 | .atu_move_port_mask = 0x1f, |
6284 | .pvt = true, |
6285 | .multi_chip = true, |
6286 | .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, |
6287 | .ptp_support = true, |
6288 | .ops = &mv88e6390x_ops, |
6289 | }, |
6290 | |
6291 | [MV88E6393X] = { |
6292 | .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, |
6293 | .family = MV88E6XXX_FAMILY_6393, |
6294 | .name = "Marvell 88E6393X" , |
6295 | .num_databases = 4096, |
6296 | .num_ports = 11, /* 10 + Z80 */ |
6297 | .num_internal_phys = 8, |
6298 | .internal_phys_offset = 1, |
6299 | .max_vid = 8191, |
6300 | .max_sid = 63, |
6301 | .port_base_addr = 0x0, |
6302 | .phy_base_addr = 0x0, |
6303 | .global1_addr = 0x1b, |
6304 | .global2_addr = 0x1c, |
6305 | .age_time_coeff = 3750, |
6306 | .g1_irqs = 10, |
6307 | .g2_irqs = 14, |
6308 | .atu_move_port_mask = 0x1f, |
6309 | .pvt = true, |
6310 | .multi_chip = true, |
6311 | .ptp_support = true, |
6312 | .ops = &mv88e6393x_ops, |
6313 | }, |
6314 | }; |
6315 | |
6316 | static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) |
6317 | { |
6318 | int i; |
6319 | |
6320 | for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) |
6321 | if (mv88e6xxx_table[i].prod_num == prod_num) |
6322 | return &mv88e6xxx_table[i]; |
6323 | |
6324 | return NULL; |
6325 | } |
6326 | |
6327 | static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) |
6328 | { |
6329 | const struct mv88e6xxx_info *info; |
6330 | unsigned int prod_num, rev; |
6331 | u16 id; |
6332 | int err; |
6333 | |
6334 | mv88e6xxx_reg_lock(chip); |
6335 | err = mv88e6xxx_port_read(chip, port: 0, MV88E6XXX_PORT_SWITCH_ID, val: &id); |
6336 | mv88e6xxx_reg_unlock(chip); |
6337 | if (err) |
6338 | return err; |
6339 | |
6340 | prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; |
6341 | rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; |
6342 | |
6343 | info = mv88e6xxx_lookup_info(prod_num); |
6344 | if (!info) |
6345 | return -ENODEV; |
6346 | |
6347 | /* Update the compatible info with the probed one */ |
6348 | chip->info = info; |
6349 | |
6350 | dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n" , |
6351 | chip->info->prod_num, chip->info->name, rev); |
6352 | |
6353 | return 0; |
6354 | } |
6355 | |
6356 | static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, |
6357 | struct mdio_device *mdiodev) |
6358 | { |
6359 | int err; |
6360 | |
6361 | /* dual_chip takes precedence over single/multi-chip modes */ |
6362 | if (chip->info->dual_chip) |
6363 | return -EINVAL; |
6364 | |
6365 | /* If the mdio addr is 16 indicating the first port address of a switch |
6366 | * (e.g. mv88e6*41) in single chip addressing mode the device may be |
6367 | * configured in single chip addressing mode. Setup the smi access as |
6368 | * single chip addressing mode and attempt to detect the model of the |
6369 | * switch, if this fails the device is not configured in single chip |
6370 | * addressing mode. |
6371 | */ |
6372 | if (mdiodev->addr != 16) |
6373 | return -EINVAL; |
6374 | |
6375 | err = mv88e6xxx_smi_init(chip, bus: mdiodev->bus, sw_addr: 0); |
6376 | if (err) |
6377 | return err; |
6378 | |
6379 | return mv88e6xxx_detect(chip); |
6380 | } |
6381 | |
6382 | static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) |
6383 | { |
6384 | struct mv88e6xxx_chip *chip; |
6385 | |
6386 | chip = devm_kzalloc(dev, size: sizeof(*chip), GFP_KERNEL); |
6387 | if (!chip) |
6388 | return NULL; |
6389 | |
6390 | chip->dev = dev; |
6391 | |
6392 | mutex_init(&chip->reg_lock); |
6393 | INIT_LIST_HEAD(list: &chip->mdios); |
6394 | idr_init(idr: &chip->policies); |
6395 | INIT_LIST_HEAD(list: &chip->msts); |
6396 | |
6397 | return chip; |
6398 | } |
6399 | |
6400 | static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, |
6401 | int port, |
6402 | enum dsa_tag_protocol m) |
6403 | { |
6404 | struct mv88e6xxx_chip *chip = ds->priv; |
6405 | |
6406 | return chip->tag_protocol; |
6407 | } |
6408 | |
6409 | static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, |
6410 | enum dsa_tag_protocol proto) |
6411 | { |
6412 | struct mv88e6xxx_chip *chip = ds->priv; |
6413 | enum dsa_tag_protocol old_protocol; |
6414 | struct dsa_port *cpu_dp; |
6415 | int err; |
6416 | |
6417 | switch (proto) { |
6418 | case DSA_TAG_PROTO_EDSA: |
6419 | switch (chip->info->edsa_support) { |
6420 | case MV88E6XXX_EDSA_UNSUPPORTED: |
6421 | return -EPROTONOSUPPORT; |
6422 | case MV88E6XXX_EDSA_UNDOCUMENTED: |
6423 | dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n" ); |
6424 | fallthrough; |
6425 | case MV88E6XXX_EDSA_SUPPORTED: |
6426 | break; |
6427 | } |
6428 | break; |
6429 | case DSA_TAG_PROTO_DSA: |
6430 | break; |
6431 | default: |
6432 | return -EPROTONOSUPPORT; |
6433 | } |
6434 | |
6435 | old_protocol = chip->tag_protocol; |
6436 | chip->tag_protocol = proto; |
6437 | |
6438 | mv88e6xxx_reg_lock(chip); |
6439 | dsa_switch_for_each_cpu_port(cpu_dp, ds) { |
6440 | err = mv88e6xxx_setup_port_mode(chip, port: cpu_dp->index); |
6441 | if (err) { |
6442 | mv88e6xxx_reg_unlock(chip); |
6443 | goto unwind; |
6444 | } |
6445 | } |
6446 | mv88e6xxx_reg_unlock(chip); |
6447 | |
6448 | return 0; |
6449 | |
6450 | unwind: |
6451 | chip->tag_protocol = old_protocol; |
6452 | |
6453 | mv88e6xxx_reg_lock(chip); |
6454 | dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) |
6455 | mv88e6xxx_setup_port_mode(chip, port: cpu_dp->index); |
6456 | mv88e6xxx_reg_unlock(chip); |
6457 | |
6458 | return err; |
6459 | } |
6460 | |
6461 | static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, |
6462 | const struct switchdev_obj_port_mdb *mdb, |
6463 | struct dsa_db db) |
6464 | { |
6465 | struct mv88e6xxx_chip *chip = ds->priv; |
6466 | int err; |
6467 | |
6468 | mv88e6xxx_reg_lock(chip); |
6469 | err = mv88e6xxx_port_db_load_purge(chip, port, addr: mdb->addr, vid: mdb->vid, |
6470 | MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); |
6471 | mv88e6xxx_reg_unlock(chip); |
6472 | |
6473 | return err; |
6474 | } |
6475 | |
6476 | static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, |
6477 | const struct switchdev_obj_port_mdb *mdb, |
6478 | struct dsa_db db) |
6479 | { |
6480 | struct mv88e6xxx_chip *chip = ds->priv; |
6481 | int err; |
6482 | |
6483 | mv88e6xxx_reg_lock(chip); |
6484 | err = mv88e6xxx_port_db_load_purge(chip, port, addr: mdb->addr, vid: mdb->vid, state: 0); |
6485 | mv88e6xxx_reg_unlock(chip); |
6486 | |
6487 | return err; |
6488 | } |
6489 | |
6490 | static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, |
6491 | struct dsa_mall_mirror_tc_entry *mirror, |
6492 | bool ingress, |
6493 | struct netlink_ext_ack *extack) |
6494 | { |
6495 | enum mv88e6xxx_egress_direction direction = ingress ? |
6496 | MV88E6XXX_EGRESS_DIR_INGRESS : |
6497 | MV88E6XXX_EGRESS_DIR_EGRESS; |
6498 | struct mv88e6xxx_chip *chip = ds->priv; |
6499 | bool other_mirrors = false; |
6500 | int i; |
6501 | int err; |
6502 | |
6503 | mutex_lock(&chip->reg_lock); |
6504 | if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != |
6505 | mirror->to_local_port) { |
6506 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) |
6507 | other_mirrors |= ingress ? |
6508 | chip->ports[i].mirror_ingress : |
6509 | chip->ports[i].mirror_egress; |
6510 | |
6511 | /* Can't change egress port when other mirror is active */ |
6512 | if (other_mirrors) { |
6513 | err = -EBUSY; |
6514 | goto out; |
6515 | } |
6516 | |
6517 | err = mv88e6xxx_set_egress_port(chip, direction, |
6518 | port: mirror->to_local_port); |
6519 | if (err) |
6520 | goto out; |
6521 | } |
6522 | |
6523 | err = mv88e6xxx_port_set_mirror(chip, port, direction, mirror: true); |
6524 | out: |
6525 | mutex_unlock(lock: &chip->reg_lock); |
6526 | |
6527 | return err; |
6528 | } |
6529 | |
6530 | static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, |
6531 | struct dsa_mall_mirror_tc_entry *mirror) |
6532 | { |
6533 | enum mv88e6xxx_egress_direction direction = mirror->ingress ? |
6534 | MV88E6XXX_EGRESS_DIR_INGRESS : |
6535 | MV88E6XXX_EGRESS_DIR_EGRESS; |
6536 | struct mv88e6xxx_chip *chip = ds->priv; |
6537 | bool other_mirrors = false; |
6538 | int i; |
6539 | |
6540 | mutex_lock(&chip->reg_lock); |
6541 | if (mv88e6xxx_port_set_mirror(chip, port, direction, mirror: false)) |
6542 | dev_err(ds->dev, "p%d: failed to disable mirroring\n" , port); |
6543 | |
6544 | for (i = 0; i < mv88e6xxx_num_ports(chip); i++) |
6545 | other_mirrors |= mirror->ingress ? |
6546 | chip->ports[i].mirror_ingress : |
6547 | chip->ports[i].mirror_egress; |
6548 | |
6549 | /* Reset egress port when no other mirror is active */ |
6550 | if (!other_mirrors) { |
6551 | if (mv88e6xxx_set_egress_port(chip, direction, |
6552 | port: dsa_upstream_port(ds, port))) |
6553 | dev_err(ds->dev, "failed to set egress port\n" ); |
6554 | } |
6555 | |
6556 | mutex_unlock(lock: &chip->reg_lock); |
6557 | } |
6558 | |
6559 | static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, |
6560 | struct switchdev_brport_flags flags, |
6561 | struct netlink_ext_ack *extack) |
6562 | { |
6563 | struct mv88e6xxx_chip *chip = ds->priv; |
6564 | const struct mv88e6xxx_ops *ops; |
6565 | |
6566 | if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | |
6567 | BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) |
6568 | return -EINVAL; |
6569 | |
6570 | ops = chip->info->ops; |
6571 | |
6572 | if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) |
6573 | return -EINVAL; |
6574 | |
6575 | if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) |
6576 | return -EINVAL; |
6577 | |
6578 | return 0; |
6579 | } |
6580 | |
6581 | static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, |
6582 | struct switchdev_brport_flags flags, |
6583 | struct netlink_ext_ack *extack) |
6584 | { |
6585 | struct mv88e6xxx_chip *chip = ds->priv; |
6586 | int err = 0; |
6587 | |
6588 | mv88e6xxx_reg_lock(chip); |
6589 | |
6590 | if (flags.mask & BR_LEARNING) { |
6591 | bool learning = !!(flags.val & BR_LEARNING); |
6592 | u16 pav = learning ? (1 << port) : 0; |
6593 | |
6594 | err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); |
6595 | if (err) |
6596 | goto out; |
6597 | } |
6598 | |
6599 | if (flags.mask & BR_FLOOD) { |
6600 | bool unicast = !!(flags.val & BR_FLOOD); |
6601 | |
6602 | err = chip->info->ops->port_set_ucast_flood(chip, port, |
6603 | unicast); |
6604 | if (err) |
6605 | goto out; |
6606 | } |
6607 | |
6608 | if (flags.mask & BR_MCAST_FLOOD) { |
6609 | bool multicast = !!(flags.val & BR_MCAST_FLOOD); |
6610 | |
6611 | err = chip->info->ops->port_set_mcast_flood(chip, port, |
6612 | multicast); |
6613 | if (err) |
6614 | goto out; |
6615 | } |
6616 | |
6617 | if (flags.mask & BR_BCAST_FLOOD) { |
6618 | bool broadcast = !!(flags.val & BR_BCAST_FLOOD); |
6619 | |
6620 | err = mv88e6xxx_port_broadcast_sync(chip, port, flood: broadcast); |
6621 | if (err) |
6622 | goto out; |
6623 | } |
6624 | |
6625 | if (flags.mask & BR_PORT_MAB) { |
6626 | bool mab = !!(flags.val & BR_PORT_MAB); |
6627 | |
6628 | mv88e6xxx_port_set_mab(chip, port, mab); |
6629 | } |
6630 | |
6631 | if (flags.mask & BR_PORT_LOCKED) { |
6632 | bool locked = !!(flags.val & BR_PORT_LOCKED); |
6633 | |
6634 | err = mv88e6xxx_port_set_lock(chip, port, locked); |
6635 | if (err) |
6636 | goto out; |
6637 | } |
6638 | out: |
6639 | mv88e6xxx_reg_unlock(chip); |
6640 | |
6641 | return err; |
6642 | } |
6643 | |
6644 | static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, |
6645 | struct dsa_lag lag, |
6646 | struct netdev_lag_upper_info *info, |
6647 | struct netlink_ext_ack *extack) |
6648 | { |
6649 | struct mv88e6xxx_chip *chip = ds->priv; |
6650 | struct dsa_port *dp; |
6651 | int members = 0; |
6652 | |
6653 | if (!mv88e6xxx_has_lag(chip)) { |
6654 | NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload" ); |
6655 | return false; |
6656 | } |
6657 | |
6658 | if (!lag.id) |
6659 | return false; |
6660 | |
6661 | dsa_lag_foreach_port(dp, ds->dst, &lag) |
6662 | /* Includes the port joining the LAG */ |
6663 | members++; |
6664 | |
6665 | if (members > 8) { |
6666 | NL_SET_ERR_MSG_MOD(extack, |
6667 | "Cannot offload more than 8 LAG ports" ); |
6668 | return false; |
6669 | } |
6670 | |
6671 | /* We could potentially relax this to include active |
6672 | * backup in the future. |
6673 | */ |
6674 | if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { |
6675 | NL_SET_ERR_MSG_MOD(extack, |
6676 | "Can only offload LAG using hash TX type" ); |
6677 | return false; |
6678 | } |
6679 | |
6680 | /* Ideally we would also validate that the hash type matches |
6681 | * the hardware. Alas, this is always set to unknown on team |
6682 | * interfaces. |
6683 | */ |
6684 | return true; |
6685 | } |
6686 | |
6687 | static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) |
6688 | { |
6689 | struct mv88e6xxx_chip *chip = ds->priv; |
6690 | struct dsa_port *dp; |
6691 | u16 map = 0; |
6692 | int id; |
6693 | |
6694 | /* DSA LAG IDs are one-based, hardware is zero-based */ |
6695 | id = lag.id - 1; |
6696 | |
6697 | /* Build the map of all ports to distribute flows destined for |
6698 | * this LAG. This can be either a local user port, or a DSA |
6699 | * port if the LAG port is on a remote chip. |
6700 | */ |
6701 | dsa_lag_foreach_port(dp, ds->dst, &lag) |
6702 | map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); |
6703 | |
6704 | return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); |
6705 | } |
6706 | |
6707 | static const u8 mv88e6xxx_lag_mask_table[8][8] = { |
6708 | /* Row number corresponds to the number of active members in a |
6709 | * LAG. Each column states which of the eight hash buckets are |
6710 | * mapped to the column:th port in the LAG. |
6711 | * |
6712 | * Example: In a LAG with three active ports, the second port |
6713 | * ([2][1]) would be selected for traffic mapped to buckets |
6714 | * 3,4,5 (0x38). |
6715 | */ |
6716 | { 0xff, 0, 0, 0, 0, 0, 0, 0 }, |
6717 | { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, |
6718 | { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, |
6719 | { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, |
6720 | { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, |
6721 | { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, |
6722 | { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, |
6723 | { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, |
6724 | }; |
6725 | |
6726 | static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, |
6727 | int num_tx, int nth) |
6728 | { |
6729 | u8 active = 0; |
6730 | int i; |
6731 | |
6732 | num_tx = num_tx <= 8 ? num_tx : 8; |
6733 | if (nth < num_tx) |
6734 | active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; |
6735 | |
6736 | for (i = 0; i < 8; i++) { |
6737 | if (BIT(i) & active) |
6738 | mask[i] |= BIT(port); |
6739 | } |
6740 | } |
6741 | |
6742 | static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) |
6743 | { |
6744 | struct mv88e6xxx_chip *chip = ds->priv; |
6745 | unsigned int id, num_tx; |
6746 | struct dsa_port *dp; |
6747 | struct dsa_lag *lag; |
6748 | int i, err, nth; |
6749 | u16 mask[8]; |
6750 | u16 ivec; |
6751 | |
6752 | /* Assume no port is a member of any LAG. */ |
6753 | ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; |
6754 | |
6755 | /* Disable all masks for ports that _are_ members of a LAG. */ |
6756 | dsa_switch_for_each_port(dp, ds) { |
6757 | if (!dp->lag) |
6758 | continue; |
6759 | |
6760 | ivec &= ~BIT(dp->index); |
6761 | } |
6762 | |
6763 | for (i = 0; i < 8; i++) |
6764 | mask[i] = ivec; |
6765 | |
6766 | /* Enable the correct subset of masks for all LAG ports that |
6767 | * are in the Tx set. |
6768 | */ |
6769 | dsa_lags_foreach_id(id, ds->dst) { |
6770 | lag = dsa_lag_by_id(dst: ds->dst, id); |
6771 | if (!lag) |
6772 | continue; |
6773 | |
6774 | num_tx = 0; |
6775 | dsa_lag_foreach_port(dp, ds->dst, lag) { |
6776 | if (dp->lag_tx_enabled) |
6777 | num_tx++; |
6778 | } |
6779 | |
6780 | if (!num_tx) |
6781 | continue; |
6782 | |
6783 | nth = 0; |
6784 | dsa_lag_foreach_port(dp, ds->dst, lag) { |
6785 | if (!dp->lag_tx_enabled) |
6786 | continue; |
6787 | |
6788 | if (dp->ds == ds) |
6789 | mv88e6xxx_lag_set_port_mask(mask, port: dp->index, |
6790 | num_tx, nth); |
6791 | |
6792 | nth++; |
6793 | } |
6794 | } |
6795 | |
6796 | for (i = 0; i < 8; i++) { |
6797 | err = mv88e6xxx_g2_trunk_mask_write(chip, num: i, hash: true, mask: mask[i]); |
6798 | if (err) |
6799 | return err; |
6800 | } |
6801 | |
6802 | return 0; |
6803 | } |
6804 | |
6805 | static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, |
6806 | struct dsa_lag lag) |
6807 | { |
6808 | int err; |
6809 | |
6810 | err = mv88e6xxx_lag_sync_masks(ds); |
6811 | |
6812 | if (!err) |
6813 | err = mv88e6xxx_lag_sync_map(ds, lag); |
6814 | |
6815 | return err; |
6816 | } |
6817 | |
6818 | static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) |
6819 | { |
6820 | struct mv88e6xxx_chip *chip = ds->priv; |
6821 | int err; |
6822 | |
6823 | mv88e6xxx_reg_lock(chip); |
6824 | err = mv88e6xxx_lag_sync_masks(ds); |
6825 | mv88e6xxx_reg_unlock(chip); |
6826 | return err; |
6827 | } |
6828 | |
6829 | static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, |
6830 | struct dsa_lag lag, |
6831 | struct netdev_lag_upper_info *info, |
6832 | struct netlink_ext_ack *extack) |
6833 | { |
6834 | struct mv88e6xxx_chip *chip = ds->priv; |
6835 | int err, id; |
6836 | |
6837 | if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) |
6838 | return -EOPNOTSUPP; |
6839 | |
6840 | /* DSA LAG IDs are one-based */ |
6841 | id = lag.id - 1; |
6842 | |
6843 | mv88e6xxx_reg_lock(chip); |
6844 | |
6845 | err = mv88e6xxx_port_set_trunk(chip, port, trunk: true, id); |
6846 | if (err) |
6847 | goto err_unlock; |
6848 | |
6849 | err = mv88e6xxx_lag_sync_masks_map(ds, lag); |
6850 | if (err) |
6851 | goto err_clear_trunk; |
6852 | |
6853 | mv88e6xxx_reg_unlock(chip); |
6854 | return 0; |
6855 | |
6856 | err_clear_trunk: |
6857 | mv88e6xxx_port_set_trunk(chip, port, trunk: false, id: 0); |
6858 | err_unlock: |
6859 | mv88e6xxx_reg_unlock(chip); |
6860 | return err; |
6861 | } |
6862 | |
6863 | static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, |
6864 | struct dsa_lag lag) |
6865 | { |
6866 | struct mv88e6xxx_chip *chip = ds->priv; |
6867 | int err_sync, err_trunk; |
6868 | |
6869 | mv88e6xxx_reg_lock(chip); |
6870 | err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); |
6871 | err_trunk = mv88e6xxx_port_set_trunk(chip, port, trunk: false, id: 0); |
6872 | mv88e6xxx_reg_unlock(chip); |
6873 | return err_sync ? : err_trunk; |
6874 | } |
6875 | |
6876 | static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, |
6877 | int port) |
6878 | { |
6879 | struct mv88e6xxx_chip *chip = ds->priv; |
6880 | int err; |
6881 | |
6882 | mv88e6xxx_reg_lock(chip); |
6883 | err = mv88e6xxx_lag_sync_masks(ds); |
6884 | mv88e6xxx_reg_unlock(chip); |
6885 | return err; |
6886 | } |
6887 | |
6888 | static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, |
6889 | int port, struct dsa_lag lag, |
6890 | struct netdev_lag_upper_info *info, |
6891 | struct netlink_ext_ack *extack) |
6892 | { |
6893 | struct mv88e6xxx_chip *chip = ds->priv; |
6894 | int err; |
6895 | |
6896 | if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) |
6897 | return -EOPNOTSUPP; |
6898 | |
6899 | mv88e6xxx_reg_lock(chip); |
6900 | |
6901 | err = mv88e6xxx_lag_sync_masks_map(ds, lag); |
6902 | if (err) |
6903 | goto unlock; |
6904 | |
6905 | err = mv88e6xxx_pvt_map(chip, dev: sw_index, port); |
6906 | |
6907 | unlock: |
6908 | mv88e6xxx_reg_unlock(chip); |
6909 | return err; |
6910 | } |
6911 | |
6912 | static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, |
6913 | int port, struct dsa_lag lag) |
6914 | { |
6915 | struct mv88e6xxx_chip *chip = ds->priv; |
6916 | int err_sync, err_pvt; |
6917 | |
6918 | mv88e6xxx_reg_lock(chip); |
6919 | err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); |
6920 | err_pvt = mv88e6xxx_pvt_map(chip, dev: sw_index, port); |
6921 | mv88e6xxx_reg_unlock(chip); |
6922 | return err_sync ? : err_pvt; |
6923 | } |
6924 | |
6925 | static const struct dsa_switch_ops mv88e6xxx_switch_ops = { |
6926 | .get_tag_protocol = mv88e6xxx_get_tag_protocol, |
6927 | .change_tag_protocol = mv88e6xxx_change_tag_protocol, |
6928 | .setup = mv88e6xxx_setup, |
6929 | .teardown = mv88e6xxx_teardown, |
6930 | .port_setup = mv88e6xxx_port_setup, |
6931 | .port_teardown = mv88e6xxx_port_teardown, |
6932 | .phylink_get_caps = mv88e6xxx_get_caps, |
6933 | .phylink_mac_select_pcs = mv88e6xxx_mac_select_pcs, |
6934 | .phylink_mac_prepare = mv88e6xxx_mac_prepare, |
6935 | .phylink_mac_config = mv88e6xxx_mac_config, |
6936 | .phylink_mac_finish = mv88e6xxx_mac_finish, |
6937 | .phylink_mac_link_down = mv88e6xxx_mac_link_down, |
6938 | .phylink_mac_link_up = mv88e6xxx_mac_link_up, |
6939 | .get_strings = mv88e6xxx_get_strings, |
6940 | .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, |
6941 | .get_eth_mac_stats = mv88e6xxx_get_eth_mac_stats, |
6942 | .get_rmon_stats = mv88e6xxx_get_rmon_stats, |
6943 | .get_sset_count = mv88e6xxx_get_sset_count, |
6944 | .port_max_mtu = mv88e6xxx_get_max_mtu, |
6945 | .port_change_mtu = mv88e6xxx_change_mtu, |
6946 | .get_mac_eee = mv88e6xxx_get_mac_eee, |
6947 | .set_mac_eee = mv88e6xxx_set_mac_eee, |
6948 | .get_eeprom_len = mv88e6xxx_get_eeprom_len, |
6949 | .get_eeprom = mv88e6xxx_get_eeprom, |
6950 | .set_eeprom = mv88e6xxx_set_eeprom, |
6951 | .get_regs_len = mv88e6xxx_get_regs_len, |
6952 | .get_regs = mv88e6xxx_get_regs, |
6953 | .get_rxnfc = mv88e6xxx_get_rxnfc, |
6954 | .set_rxnfc = mv88e6xxx_set_rxnfc, |
6955 | .set_ageing_time = mv88e6xxx_set_ageing_time, |
6956 | .port_bridge_join = mv88e6xxx_port_bridge_join, |
6957 | .port_bridge_leave = mv88e6xxx_port_bridge_leave, |
6958 | .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, |
6959 | .port_bridge_flags = mv88e6xxx_port_bridge_flags, |
6960 | .port_stp_state_set = mv88e6xxx_port_stp_state_set, |
6961 | .port_mst_state_set = mv88e6xxx_port_mst_state_set, |
6962 | .port_fast_age = mv88e6xxx_port_fast_age, |
6963 | .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, |
6964 | .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, |
6965 | .port_vlan_add = mv88e6xxx_port_vlan_add, |
6966 | .port_vlan_del = mv88e6xxx_port_vlan_del, |
6967 | .vlan_msti_set = mv88e6xxx_vlan_msti_set, |
6968 | .port_fdb_add = mv88e6xxx_port_fdb_add, |
6969 | .port_fdb_del = mv88e6xxx_port_fdb_del, |
6970 | .port_fdb_dump = mv88e6xxx_port_fdb_dump, |
6971 | .port_mdb_add = mv88e6xxx_port_mdb_add, |
6972 | .port_mdb_del = mv88e6xxx_port_mdb_del, |
6973 | .port_mirror_add = mv88e6xxx_port_mirror_add, |
6974 | .port_mirror_del = mv88e6xxx_port_mirror_del, |
6975 | .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, |
6976 | .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, |
6977 | .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, |
6978 | .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, |
6979 | .port_txtstamp = mv88e6xxx_port_txtstamp, |
6980 | .port_rxtstamp = mv88e6xxx_port_rxtstamp, |
6981 | .get_ts_info = mv88e6xxx_get_ts_info, |
6982 | .devlink_param_get = mv88e6xxx_devlink_param_get, |
6983 | .devlink_param_set = mv88e6xxx_devlink_param_set, |
6984 | .devlink_info_get = mv88e6xxx_devlink_info_get, |
6985 | .port_lag_change = mv88e6xxx_port_lag_change, |
6986 | .port_lag_join = mv88e6xxx_port_lag_join, |
6987 | .port_lag_leave = mv88e6xxx_port_lag_leave, |
6988 | .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, |
6989 | .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, |
6990 | .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, |
6991 | }; |
6992 | |
6993 | static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) |
6994 | { |
6995 | struct device *dev = chip->dev; |
6996 | struct dsa_switch *ds; |
6997 | |
6998 | ds = devm_kzalloc(dev, size: sizeof(*ds), GFP_KERNEL); |
6999 | if (!ds) |
7000 | return -ENOMEM; |
7001 | |
7002 | ds->dev = dev; |
7003 | ds->num_ports = mv88e6xxx_num_ports(chip); |
7004 | ds->priv = chip; |
7005 | ds->dev = dev; |
7006 | ds->ops = &mv88e6xxx_switch_ops; |
7007 | ds->ageing_time_min = chip->info->age_time_coeff; |
7008 | ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; |
7009 | |
7010 | /* Some chips support up to 32, but that requires enabling the |
7011 | * 5-bit port mode, which we do not support. 640k^W16 ought to |
7012 | * be enough for anyone. |
7013 | */ |
7014 | ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; |
7015 | |
7016 | dev_set_drvdata(dev, data: ds); |
7017 | |
7018 | return dsa_register_switch(ds); |
7019 | } |
7020 | |
7021 | static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) |
7022 | { |
7023 | dsa_unregister_switch(ds: chip->ds); |
7024 | } |
7025 | |
7026 | static const void *pdata_device_get_match_data(struct device *dev) |
7027 | { |
7028 | const struct of_device_id *matches = dev->driver->of_match_table; |
7029 | const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; |
7030 | |
7031 | for (; matches->name[0] || matches->type[0] || matches->compatible[0]; |
7032 | matches++) { |
7033 | if (!strcmp(pdata->compatible, matches->compatible)) |
7034 | return matches->data; |
7035 | } |
7036 | return NULL; |
7037 | } |
7038 | |
7039 | /* There is no suspend to RAM support at DSA level yet, the switch configuration |
7040 | * would be lost after a power cycle so prevent it to be suspended. |
7041 | */ |
7042 | static int __maybe_unused mv88e6xxx_suspend(struct device *dev) |
7043 | { |
7044 | return -EOPNOTSUPP; |
7045 | } |
7046 | |
7047 | static int __maybe_unused mv88e6xxx_resume(struct device *dev) |
7048 | { |
7049 | return 0; |
7050 | } |
7051 | |
7052 | static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); |
7053 | |
7054 | static int mv88e6xxx_probe(struct mdio_device *mdiodev) |
7055 | { |
7056 | struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; |
7057 | const struct mv88e6xxx_info *compat_info = NULL; |
7058 | struct device *dev = &mdiodev->dev; |
7059 | struct device_node *np = dev->of_node; |
7060 | struct mv88e6xxx_chip *chip; |
7061 | int port; |
7062 | int err; |
7063 | |
7064 | if (!np && !pdata) |
7065 | return -EINVAL; |
7066 | |
7067 | if (np) |
7068 | compat_info = of_device_get_match_data(dev); |
7069 | |
7070 | if (pdata) { |
7071 | compat_info = pdata_device_get_match_data(dev); |
7072 | |
7073 | if (!pdata->netdev) |
7074 | return -EINVAL; |
7075 | |
7076 | for (port = 0; port < DSA_MAX_PORTS; port++) { |
7077 | if (!(pdata->enabled_ports & (1 << port))) |
7078 | continue; |
7079 | if (strcmp(pdata->cd.port_names[port], "cpu" )) |
7080 | continue; |
7081 | pdata->cd.netdev[port] = &pdata->netdev->dev; |
7082 | break; |
7083 | } |
7084 | } |
7085 | |
7086 | if (!compat_info) |
7087 | return -EINVAL; |
7088 | |
7089 | chip = mv88e6xxx_alloc_chip(dev); |
7090 | if (!chip) { |
7091 | err = -ENOMEM; |
7092 | goto out; |
7093 | } |
7094 | |
7095 | chip->info = compat_info; |
7096 | |
7097 | chip->reset = devm_gpiod_get_optional(dev, con_id: "reset" , flags: GPIOD_OUT_LOW); |
7098 | if (IS_ERR(ptr: chip->reset)) { |
7099 | err = PTR_ERR(ptr: chip->reset); |
7100 | goto out; |
7101 | } |
7102 | if (chip->reset) |
7103 | usleep_range(min: 10000, max: 20000); |
7104 | |
7105 | /* Detect if the device is configured in single chip addressing mode, |
7106 | * otherwise continue with address specific smi init/detection. |
7107 | */ |
7108 | err = mv88e6xxx_single_chip_detect(chip, mdiodev); |
7109 | if (err) { |
7110 | err = mv88e6xxx_smi_init(chip, bus: mdiodev->bus, sw_addr: mdiodev->addr); |
7111 | if (err) |
7112 | goto out; |
7113 | |
7114 | err = mv88e6xxx_detect(chip); |
7115 | if (err) |
7116 | goto out; |
7117 | } |
7118 | |
7119 | if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) |
7120 | chip->tag_protocol = DSA_TAG_PROTO_EDSA; |
7121 | else |
7122 | chip->tag_protocol = DSA_TAG_PROTO_DSA; |
7123 | |
7124 | mv88e6xxx_phy_init(chip); |
7125 | |
7126 | if (chip->info->ops->get_eeprom) { |
7127 | if (np) |
7128 | of_property_read_u32(np, propname: "eeprom-length" , |
7129 | out_value: &chip->eeprom_len); |
7130 | else |
7131 | chip->eeprom_len = pdata->eeprom_len; |
7132 | } |
7133 | |
7134 | mv88e6xxx_reg_lock(chip); |
7135 | err = mv88e6xxx_switch_reset(chip); |
7136 | mv88e6xxx_reg_unlock(chip); |
7137 | if (err) |
7138 | goto out; |
7139 | |
7140 | if (np) { |
7141 | chip->irq = of_irq_get(dev: np, index: 0); |
7142 | if (chip->irq == -EPROBE_DEFER) { |
7143 | err = chip->irq; |
7144 | goto out; |
7145 | } |
7146 | } |
7147 | |
7148 | if (pdata) |
7149 | chip->irq = pdata->irq; |
7150 | |
7151 | /* Has to be performed before the MDIO bus is created, because |
7152 | * the PHYs will link their interrupts to these interrupt |
7153 | * controllers |
7154 | */ |
7155 | mv88e6xxx_reg_lock(chip); |
7156 | if (chip->irq > 0) |
7157 | err = mv88e6xxx_g1_irq_setup(chip); |
7158 | else |
7159 | err = mv88e6xxx_irq_poll_setup(chip); |
7160 | mv88e6xxx_reg_unlock(chip); |
7161 | |
7162 | if (err) |
7163 | goto out; |
7164 | |
7165 | if (chip->info->g2_irqs > 0) { |
7166 | err = mv88e6xxx_g2_irq_setup(chip); |
7167 | if (err) |
7168 | goto out_g1_irq; |
7169 | } |
7170 | |
7171 | err = mv88e6xxx_g1_atu_prob_irq_setup(chip); |
7172 | if (err) |
7173 | goto out_g2_irq; |
7174 | |
7175 | err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); |
7176 | if (err) |
7177 | goto out_g1_atu_prob_irq; |
7178 | |
7179 | err = mv88e6xxx_register_switch(chip); |
7180 | if (err) |
7181 | goto out_g1_vtu_prob_irq; |
7182 | |
7183 | return 0; |
7184 | |
7185 | out_g1_vtu_prob_irq: |
7186 | mv88e6xxx_g1_vtu_prob_irq_free(chip); |
7187 | out_g1_atu_prob_irq: |
7188 | mv88e6xxx_g1_atu_prob_irq_free(chip); |
7189 | out_g2_irq: |
7190 | if (chip->info->g2_irqs > 0) |
7191 | mv88e6xxx_g2_irq_free(chip); |
7192 | out_g1_irq: |
7193 | if (chip->irq > 0) |
7194 | mv88e6xxx_g1_irq_free(chip); |
7195 | else |
7196 | mv88e6xxx_irq_poll_free(chip); |
7197 | out: |
7198 | if (pdata) |
7199 | dev_put(dev: pdata->netdev); |
7200 | |
7201 | return err; |
7202 | } |
7203 | |
7204 | static void mv88e6xxx_remove(struct mdio_device *mdiodev) |
7205 | { |
7206 | struct dsa_switch *ds = dev_get_drvdata(dev: &mdiodev->dev); |
7207 | struct mv88e6xxx_chip *chip; |
7208 | |
7209 | if (!ds) |
7210 | return; |
7211 | |
7212 | chip = ds->priv; |
7213 | |
7214 | if (chip->info->ptp_support) { |
7215 | mv88e6xxx_hwtstamp_free(chip); |
7216 | mv88e6xxx_ptp_free(chip); |
7217 | } |
7218 | |
7219 | mv88e6xxx_phy_destroy(chip); |
7220 | mv88e6xxx_unregister_switch(chip); |
7221 | |
7222 | mv88e6xxx_g1_vtu_prob_irq_free(chip); |
7223 | mv88e6xxx_g1_atu_prob_irq_free(chip); |
7224 | |
7225 | if (chip->info->g2_irqs > 0) |
7226 | mv88e6xxx_g2_irq_free(chip); |
7227 | |
7228 | if (chip->irq > 0) |
7229 | mv88e6xxx_g1_irq_free(chip); |
7230 | else |
7231 | mv88e6xxx_irq_poll_free(chip); |
7232 | } |
7233 | |
7234 | static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) |
7235 | { |
7236 | struct dsa_switch *ds = dev_get_drvdata(dev: &mdiodev->dev); |
7237 | |
7238 | if (!ds) |
7239 | return; |
7240 | |
7241 | dsa_switch_shutdown(ds); |
7242 | |
7243 | dev_set_drvdata(dev: &mdiodev->dev, NULL); |
7244 | } |
7245 | |
7246 | static const struct of_device_id mv88e6xxx_of_match[] = { |
7247 | { |
7248 | .compatible = "marvell,mv88e6085" , |
7249 | .data = &mv88e6xxx_table[MV88E6085], |
7250 | }, |
7251 | { |
7252 | .compatible = "marvell,mv88e6190" , |
7253 | .data = &mv88e6xxx_table[MV88E6190], |
7254 | }, |
7255 | { |
7256 | .compatible = "marvell,mv88e6250" , |
7257 | .data = &mv88e6xxx_table[MV88E6250], |
7258 | }, |
7259 | { /* sentinel */ }, |
7260 | }; |
7261 | |
7262 | MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); |
7263 | |
7264 | static struct mdio_driver mv88e6xxx_driver = { |
7265 | .probe = mv88e6xxx_probe, |
7266 | .remove = mv88e6xxx_remove, |
7267 | .shutdown = mv88e6xxx_shutdown, |
7268 | .mdiodrv.driver = { |
7269 | .name = "mv88e6085" , |
7270 | .of_match_table = mv88e6xxx_of_match, |
7271 | .pm = &mv88e6xxx_pm_ops, |
7272 | }, |
7273 | }; |
7274 | |
7275 | mdio_module_driver(mv88e6xxx_driver); |
7276 | |
7277 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>" ); |
7278 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips" ); |
7279 | MODULE_LICENSE("GPL" ); |
7280 | |