1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH |
3 | * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> |
4 | */ |
5 | |
6 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
7 | |
8 | #include <linux/delay.h> |
9 | #include <linux/module.h> |
10 | #include <linux/printk.h> |
11 | #include <linux/spi/spi.h> |
12 | #include <linux/errno.h> |
13 | #include <linux/gpio/consumer.h> |
14 | #include <linux/phylink.h> |
15 | #include <linux/of.h> |
16 | #include <linux/of_net.h> |
17 | #include <linux/of_mdio.h> |
18 | #include <linux/pcs/pcs-xpcs.h> |
19 | #include <linux/netdev_features.h> |
20 | #include <linux/netdevice.h> |
21 | #include <linux/if_bridge.h> |
22 | #include <linux/if_ether.h> |
23 | #include <linux/dsa/8021q.h> |
24 | #include <linux/units.h> |
25 | |
26 | #include "sja1105.h" |
27 | #include "sja1105_tas.h" |
28 | |
29 | #define SJA1105_UNKNOWN_MULTICAST 0x010000000000ull |
30 | |
31 | /* Configure the optional reset pin and bring up switch */ |
32 | static int sja1105_hw_reset(struct device *dev, unsigned int pulse_len, |
33 | unsigned int startup_delay) |
34 | { |
35 | struct gpio_desc *gpio; |
36 | |
37 | gpio = gpiod_get_optional(dev, con_id: "reset" , flags: GPIOD_OUT_HIGH); |
38 | if (IS_ERR(ptr: gpio)) |
39 | return PTR_ERR(ptr: gpio); |
40 | |
41 | if (!gpio) |
42 | return 0; |
43 | |
44 | gpiod_set_value_cansleep(desc: gpio, value: 1); |
45 | /* Wait for minimum reset pulse length */ |
46 | msleep(msecs: pulse_len); |
47 | gpiod_set_value_cansleep(desc: gpio, value: 0); |
48 | /* Wait until chip is ready after reset */ |
49 | msleep(msecs: startup_delay); |
50 | |
51 | gpiod_put(desc: gpio); |
52 | |
53 | return 0; |
54 | } |
55 | |
56 | static void |
57 | sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd, |
58 | int from, int to, bool allow) |
59 | { |
60 | if (allow) |
61 | l2_fwd[from].reach_port |= BIT(to); |
62 | else |
63 | l2_fwd[from].reach_port &= ~BIT(to); |
64 | } |
65 | |
66 | static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd, |
67 | int from, int to) |
68 | { |
69 | return !!(l2_fwd[from].reach_port & BIT(to)); |
70 | } |
71 | |
72 | static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid) |
73 | { |
74 | struct sja1105_vlan_lookup_entry *vlan; |
75 | int count, i; |
76 | |
77 | vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries; |
78 | count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count; |
79 | |
80 | for (i = 0; i < count; i++) |
81 | if (vlan[i].vlanid == vid) |
82 | return i; |
83 | |
84 | /* Return an invalid entry index if not found */ |
85 | return -1; |
86 | } |
87 | |
88 | static int sja1105_drop_untagged(struct dsa_switch *ds, int port, bool drop) |
89 | { |
90 | struct sja1105_private *priv = ds->priv; |
91 | struct sja1105_mac_config_entry *mac; |
92 | |
93 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; |
94 | |
95 | if (mac[port].drpuntag == drop) |
96 | return 0; |
97 | |
98 | mac[port].drpuntag = drop; |
99 | |
100 | return sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_MAC_CONFIG, index: port, |
101 | entry: &mac[port], keep: true); |
102 | } |
103 | |
104 | static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid) |
105 | { |
106 | struct sja1105_mac_config_entry *mac; |
107 | |
108 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; |
109 | |
110 | if (mac[port].vlanid == pvid) |
111 | return 0; |
112 | |
113 | mac[port].vlanid = pvid; |
114 | |
115 | return sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_MAC_CONFIG, index: port, |
116 | entry: &mac[port], keep: true); |
117 | } |
118 | |
119 | static int sja1105_commit_pvid(struct dsa_switch *ds, int port) |
120 | { |
121 | struct dsa_port *dp = dsa_to_port(ds, p: port); |
122 | struct net_device *br = dsa_port_bridge_dev_get(dp); |
123 | struct sja1105_private *priv = ds->priv; |
124 | struct sja1105_vlan_lookup_entry *vlan; |
125 | bool drop_untagged = false; |
126 | int match, rc; |
127 | u16 pvid; |
128 | |
129 | if (br && br_vlan_enabled(dev: br)) |
130 | pvid = priv->bridge_pvid[port]; |
131 | else |
132 | pvid = priv->tag_8021q_pvid[port]; |
133 | |
134 | rc = sja1105_pvid_apply(priv, port, pvid); |
135 | if (rc) |
136 | return rc; |
137 | |
138 | /* Only force dropping of untagged packets when the port is under a |
139 | * VLAN-aware bridge. When the tag_8021q pvid is used, we are |
140 | * deliberately removing the RX VLAN from the port's VMEMB_PORT list, |
141 | * to prevent DSA tag spoofing from the link partner. Untagged packets |
142 | * are the only ones that should be received with tag_8021q, so |
143 | * definitely don't drop them. |
144 | */ |
145 | if (pvid == priv->bridge_pvid[port]) { |
146 | vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries; |
147 | |
148 | match = sja1105_is_vlan_configured(priv, vid: pvid); |
149 | |
150 | if (match < 0 || !(vlan[match].vmemb_port & BIT(port))) |
151 | drop_untagged = true; |
152 | } |
153 | |
154 | if (dsa_is_cpu_port(ds, p: port) || dsa_is_dsa_port(ds, p: port)) |
155 | drop_untagged = true; |
156 | |
157 | return sja1105_drop_untagged(ds, port, drop: drop_untagged); |
158 | } |
159 | |
160 | static int sja1105_init_mac_settings(struct sja1105_private *priv) |
161 | { |
162 | struct sja1105_mac_config_entry default_mac = { |
163 | /* Enable all 8 priority queues on egress. |
164 | * Every queue i holds top[i] - base[i] frames. |
165 | * Sum of top[i] - base[i] is 511 (max hardware limit). |
166 | */ |
167 | .top = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF}, |
168 | .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0}, |
169 | .enabled = {true, true, true, true, true, true, true, true}, |
170 | /* Keep standard IFG of 12 bytes on egress. */ |
171 | .ifg = 0, |
172 | /* Always put the MAC speed in automatic mode, where it can be |
173 | * adjusted at runtime by PHYLINK. |
174 | */ |
175 | .speed = priv->info->port_speed[SJA1105_SPEED_AUTO], |
176 | /* No static correction for 1-step 1588 events */ |
177 | .tp_delin = 0, |
178 | .tp_delout = 0, |
179 | /* Disable aging for critical TTEthernet traffic */ |
180 | .maxage = 0xFF, |
181 | /* Internal VLAN (pvid) to apply to untagged ingress */ |
182 | .vlanprio = 0, |
183 | .vlanid = 1, |
184 | .ing_mirr = false, |
185 | .egr_mirr = false, |
186 | /* Don't drop traffic with other EtherType than ETH_P_IP */ |
187 | .drpnona664 = false, |
188 | /* Don't drop double-tagged traffic */ |
189 | .drpdtag = false, |
190 | /* Don't drop untagged traffic */ |
191 | .drpuntag = false, |
192 | /* Don't retag 802.1p (VID 0) traffic with the pvid */ |
193 | .retag = false, |
194 | /* Disable learning and I/O on user ports by default - |
195 | * STP will enable it. |
196 | */ |
197 | .dyn_learn = false, |
198 | .egress = false, |
199 | .ingress = false, |
200 | }; |
201 | struct sja1105_mac_config_entry *mac; |
202 | struct dsa_switch *ds = priv->ds; |
203 | struct sja1105_table *table; |
204 | struct dsa_port *dp; |
205 | |
206 | table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG]; |
207 | |
208 | /* Discard previous MAC Configuration Table */ |
209 | if (table->entry_count) { |
210 | kfree(objp: table->entries); |
211 | table->entry_count = 0; |
212 | } |
213 | |
214 | table->entries = kcalloc(n: table->ops->max_entry_count, |
215 | size: table->ops->unpacked_entry_size, GFP_KERNEL); |
216 | if (!table->entries) |
217 | return -ENOMEM; |
218 | |
219 | table->entry_count = table->ops->max_entry_count; |
220 | |
221 | mac = table->entries; |
222 | |
223 | list_for_each_entry(dp, &ds->dst->ports, list) { |
224 | if (dp->ds != ds) |
225 | continue; |
226 | |
227 | mac[dp->index] = default_mac; |
228 | |
229 | /* Let sja1105_bridge_stp_state_set() keep address learning |
230 | * enabled for the DSA ports. CPU ports use software-assisted |
231 | * learning to ensure that only FDB entries belonging to the |
232 | * bridge are learned, and that they are learned towards all |
233 | * CPU ports in a cross-chip topology if multiple CPU ports |
234 | * exist. |
235 | */ |
236 | if (dsa_port_is_dsa(port: dp)) |
237 | dp->learning = true; |
238 | |
239 | /* Disallow untagged packets from being received on the |
240 | * CPU and DSA ports. |
241 | */ |
242 | if (dsa_port_is_cpu(port: dp) || dsa_port_is_dsa(port: dp)) |
243 | mac[dp->index].drpuntag = true; |
244 | } |
245 | |
246 | return 0; |
247 | } |
248 | |
249 | static int sja1105_init_mii_settings(struct sja1105_private *priv) |
250 | { |
251 | struct device *dev = &priv->spidev->dev; |
252 | struct sja1105_xmii_params_entry *mii; |
253 | struct dsa_switch *ds = priv->ds; |
254 | struct sja1105_table *table; |
255 | int i; |
256 | |
257 | table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS]; |
258 | |
259 | /* Discard previous xMII Mode Parameters Table */ |
260 | if (table->entry_count) { |
261 | kfree(objp: table->entries); |
262 | table->entry_count = 0; |
263 | } |
264 | |
265 | table->entries = kcalloc(n: table->ops->max_entry_count, |
266 | size: table->ops->unpacked_entry_size, GFP_KERNEL); |
267 | if (!table->entries) |
268 | return -ENOMEM; |
269 | |
270 | /* Override table based on PHYLINK DT bindings */ |
271 | table->entry_count = table->ops->max_entry_count; |
272 | |
273 | mii = table->entries; |
274 | |
275 | for (i = 0; i < ds->num_ports; i++) { |
276 | sja1105_mii_role_t role = XMII_MAC; |
277 | |
278 | if (dsa_is_unused_port(ds: priv->ds, p: i)) |
279 | continue; |
280 | |
281 | switch (priv->phy_mode[i]) { |
282 | case PHY_INTERFACE_MODE_INTERNAL: |
283 | if (priv->info->internal_phy[i] == SJA1105_NO_PHY) |
284 | goto unsupported; |
285 | |
286 | mii->xmii_mode[i] = XMII_MODE_MII; |
287 | if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX) |
288 | mii->special[i] = true; |
289 | |
290 | break; |
291 | case PHY_INTERFACE_MODE_REVMII: |
292 | role = XMII_PHY; |
293 | fallthrough; |
294 | case PHY_INTERFACE_MODE_MII: |
295 | if (!priv->info->supports_mii[i]) |
296 | goto unsupported; |
297 | |
298 | mii->xmii_mode[i] = XMII_MODE_MII; |
299 | break; |
300 | case PHY_INTERFACE_MODE_REVRMII: |
301 | role = XMII_PHY; |
302 | fallthrough; |
303 | case PHY_INTERFACE_MODE_RMII: |
304 | if (!priv->info->supports_rmii[i]) |
305 | goto unsupported; |
306 | |
307 | mii->xmii_mode[i] = XMII_MODE_RMII; |
308 | break; |
309 | case PHY_INTERFACE_MODE_RGMII: |
310 | case PHY_INTERFACE_MODE_RGMII_ID: |
311 | case PHY_INTERFACE_MODE_RGMII_RXID: |
312 | case PHY_INTERFACE_MODE_RGMII_TXID: |
313 | if (!priv->info->supports_rgmii[i]) |
314 | goto unsupported; |
315 | |
316 | mii->xmii_mode[i] = XMII_MODE_RGMII; |
317 | break; |
318 | case PHY_INTERFACE_MODE_SGMII: |
319 | if (!priv->info->supports_sgmii[i]) |
320 | goto unsupported; |
321 | |
322 | mii->xmii_mode[i] = XMII_MODE_SGMII; |
323 | mii->special[i] = true; |
324 | break; |
325 | case PHY_INTERFACE_MODE_2500BASEX: |
326 | if (!priv->info->supports_2500basex[i]) |
327 | goto unsupported; |
328 | |
329 | mii->xmii_mode[i] = XMII_MODE_SGMII; |
330 | mii->special[i] = true; |
331 | break; |
332 | unsupported: |
333 | default: |
334 | dev_err(dev, "Unsupported PHY mode %s on port %d!\n" , |
335 | phy_modes(priv->phy_mode[i]), i); |
336 | return -EINVAL; |
337 | } |
338 | |
339 | mii->phy_mac[i] = role; |
340 | } |
341 | return 0; |
342 | } |
343 | |
344 | static int sja1105_init_static_fdb(struct sja1105_private *priv) |
345 | { |
346 | struct sja1105_l2_lookup_entry *l2_lookup; |
347 | struct sja1105_table *table; |
348 | int port; |
349 | |
350 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; |
351 | |
352 | /* We only populate the FDB table through dynamic L2 Address Lookup |
353 | * entries, except for a special entry at the end which is a catch-all |
354 | * for unknown multicast and will be used to control flooding domain. |
355 | */ |
356 | if (table->entry_count) { |
357 | kfree(objp: table->entries); |
358 | table->entry_count = 0; |
359 | } |
360 | |
361 | if (!priv->info->can_limit_mcast_flood) |
362 | return 0; |
363 | |
364 | table->entries = kcalloc(n: 1, size: table->ops->unpacked_entry_size, |
365 | GFP_KERNEL); |
366 | if (!table->entries) |
367 | return -ENOMEM; |
368 | |
369 | table->entry_count = 1; |
370 | l2_lookup = table->entries; |
371 | |
372 | /* All L2 multicast addresses have an odd first octet */ |
373 | l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST; |
374 | l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST; |
375 | l2_lookup[0].lockeds = true; |
376 | l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1; |
377 | |
378 | /* Flood multicast to every port by default */ |
379 | for (port = 0; port < priv->ds->num_ports; port++) |
380 | if (!dsa_is_unused_port(ds: priv->ds, p: port)) |
381 | l2_lookup[0].destports |= BIT(port); |
382 | |
383 | return 0; |
384 | } |
385 | |
386 | static int sja1105_init_l2_lookup_params(struct sja1105_private *priv) |
387 | { |
388 | struct sja1105_l2_lookup_params_entry default_l2_lookup_params = { |
389 | /* Learned FDB entries are forgotten after 300 seconds */ |
390 | .maxage = SJA1105_AGEING_TIME_MS(300000), |
391 | /* All entries within a FDB bin are available for learning */ |
392 | .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE, |
393 | /* And the P/Q/R/S equivalent setting: */ |
394 | .start_dynspc = 0, |
395 | /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */ |
396 | .poly = 0x97, |
397 | /* Always use Independent VLAN Learning (IVL) */ |
398 | .shared_learn = false, |
399 | /* Don't discard management traffic based on ENFPORT - |
400 | * we don't perform SMAC port enforcement anyway, so |
401 | * what we are setting here doesn't matter. |
402 | */ |
403 | .no_enf_hostprt = false, |
404 | /* Don't learn SMAC for mac_fltres1 and mac_fltres0. |
405 | * Maybe correlate with no_linklocal_learn from bridge driver? |
406 | */ |
407 | .no_mgmt_learn = true, |
408 | /* P/Q/R/S only */ |
409 | .use_static = true, |
410 | /* Dynamically learned FDB entries can overwrite other (older) |
411 | * dynamic FDB entries |
412 | */ |
413 | .owr_dyn = true, |
414 | .drpnolearn = true, |
415 | }; |
416 | struct dsa_switch *ds = priv->ds; |
417 | int port, num_used_ports = 0; |
418 | struct sja1105_table *table; |
419 | u64 max_fdb_entries; |
420 | |
421 | for (port = 0; port < ds->num_ports; port++) |
422 | if (!dsa_is_unused_port(ds, p: port)) |
423 | num_used_ports++; |
424 | |
425 | max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports; |
426 | |
427 | for (port = 0; port < ds->num_ports; port++) { |
428 | if (dsa_is_unused_port(ds, p: port)) |
429 | continue; |
430 | |
431 | default_l2_lookup_params.maxaddrp[port] = max_fdb_entries; |
432 | } |
433 | |
434 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS]; |
435 | |
436 | if (table->entry_count) { |
437 | kfree(objp: table->entries); |
438 | table->entry_count = 0; |
439 | } |
440 | |
441 | table->entries = kcalloc(n: table->ops->max_entry_count, |
442 | size: table->ops->unpacked_entry_size, GFP_KERNEL); |
443 | if (!table->entries) |
444 | return -ENOMEM; |
445 | |
446 | table->entry_count = table->ops->max_entry_count; |
447 | |
448 | /* This table only has a single entry */ |
449 | ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] = |
450 | default_l2_lookup_params; |
451 | |
452 | return 0; |
453 | } |
454 | |
455 | /* Set up a default VLAN for untagged traffic injected from the CPU |
456 | * using management routes (e.g. STP, PTP) as opposed to tag_8021q. |
457 | * All DT-defined ports are members of this VLAN, and there are no |
458 | * restrictions on forwarding (since the CPU selects the destination). |
459 | * Frames from this VLAN will always be transmitted as untagged, and |
460 | * neither the bridge nor the 8021q module cannot create this VLAN ID. |
461 | */ |
462 | static int sja1105_init_static_vlan(struct sja1105_private *priv) |
463 | { |
464 | struct sja1105_table *table; |
465 | struct sja1105_vlan_lookup_entry pvid = { |
466 | .type_entry = SJA1110_VLAN_D_TAG, |
467 | .ving_mirr = 0, |
468 | .vegr_mirr = 0, |
469 | .vmemb_port = 0, |
470 | .vlan_bc = 0, |
471 | .tag_port = 0, |
472 | .vlanid = SJA1105_DEFAULT_VLAN, |
473 | }; |
474 | struct dsa_switch *ds = priv->ds; |
475 | int port; |
476 | |
477 | table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP]; |
478 | |
479 | if (table->entry_count) { |
480 | kfree(objp: table->entries); |
481 | table->entry_count = 0; |
482 | } |
483 | |
484 | table->entries = kzalloc(size: table->ops->unpacked_entry_size, |
485 | GFP_KERNEL); |
486 | if (!table->entries) |
487 | return -ENOMEM; |
488 | |
489 | table->entry_count = 1; |
490 | |
491 | for (port = 0; port < ds->num_ports; port++) { |
492 | if (dsa_is_unused_port(ds, p: port)) |
493 | continue; |
494 | |
495 | pvid.vmemb_port |= BIT(port); |
496 | pvid.vlan_bc |= BIT(port); |
497 | pvid.tag_port &= ~BIT(port); |
498 | |
499 | if (dsa_is_cpu_port(ds, p: port) || dsa_is_dsa_port(ds, p: port)) { |
500 | priv->tag_8021q_pvid[port] = SJA1105_DEFAULT_VLAN; |
501 | priv->bridge_pvid[port] = SJA1105_DEFAULT_VLAN; |
502 | } |
503 | } |
504 | |
505 | ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid; |
506 | return 0; |
507 | } |
508 | |
509 | static int sja1105_init_l2_forwarding(struct sja1105_private *priv) |
510 | { |
511 | struct sja1105_l2_forwarding_entry *l2fwd; |
512 | struct dsa_switch *ds = priv->ds; |
513 | struct dsa_switch_tree *dst; |
514 | struct sja1105_table *table; |
515 | struct dsa_link *dl; |
516 | int port, tc; |
517 | int from, to; |
518 | |
519 | table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING]; |
520 | |
521 | if (table->entry_count) { |
522 | kfree(objp: table->entries); |
523 | table->entry_count = 0; |
524 | } |
525 | |
526 | table->entries = kcalloc(n: table->ops->max_entry_count, |
527 | size: table->ops->unpacked_entry_size, GFP_KERNEL); |
528 | if (!table->entries) |
529 | return -ENOMEM; |
530 | |
531 | table->entry_count = table->ops->max_entry_count; |
532 | |
533 | l2fwd = table->entries; |
534 | |
535 | /* First 5 entries in the L2 Forwarding Table define the forwarding |
536 | * rules and the VLAN PCP to ingress queue mapping. |
537 | * Set up the ingress queue mapping first. |
538 | */ |
539 | for (port = 0; port < ds->num_ports; port++) { |
540 | if (dsa_is_unused_port(ds, p: port)) |
541 | continue; |
542 | |
543 | for (tc = 0; tc < SJA1105_NUM_TC; tc++) |
544 | l2fwd[port].vlan_pmap[tc] = tc; |
545 | } |
546 | |
547 | /* Then manage the forwarding domain for user ports. These can forward |
548 | * only to the always-on domain (CPU port and DSA links) |
549 | */ |
550 | for (from = 0; from < ds->num_ports; from++) { |
551 | if (!dsa_is_user_port(ds, p: from)) |
552 | continue; |
553 | |
554 | for (to = 0; to < ds->num_ports; to++) { |
555 | if (!dsa_is_cpu_port(ds, p: to) && |
556 | !dsa_is_dsa_port(ds, p: to)) |
557 | continue; |
558 | |
559 | l2fwd[from].bc_domain |= BIT(to); |
560 | l2fwd[from].fl_domain |= BIT(to); |
561 | |
562 | sja1105_port_allow_traffic(l2_fwd: l2fwd, from, to, allow: true); |
563 | } |
564 | } |
565 | |
566 | /* Then manage the forwarding domain for DSA links and CPU ports (the |
567 | * always-on domain). These can send packets to any enabled port except |
568 | * themselves. |
569 | */ |
570 | for (from = 0; from < ds->num_ports; from++) { |
571 | if (!dsa_is_cpu_port(ds, p: from) && !dsa_is_dsa_port(ds, p: from)) |
572 | continue; |
573 | |
574 | for (to = 0; to < ds->num_ports; to++) { |
575 | if (dsa_is_unused_port(ds, p: to)) |
576 | continue; |
577 | |
578 | if (from == to) |
579 | continue; |
580 | |
581 | l2fwd[from].bc_domain |= BIT(to); |
582 | l2fwd[from].fl_domain |= BIT(to); |
583 | |
584 | sja1105_port_allow_traffic(l2_fwd: l2fwd, from, to, allow: true); |
585 | } |
586 | } |
587 | |
588 | /* In odd topologies ("H" connections where there is a DSA link to |
589 | * another switch which also has its own CPU port), TX packets can loop |
590 | * back into the system (they are flooded from CPU port 1 to the DSA |
591 | * link, and from there to CPU port 2). Prevent this from happening by |
592 | * cutting RX from DSA links towards our CPU port, if the remote switch |
593 | * has its own CPU port and therefore doesn't need ours for network |
594 | * stack termination. |
595 | */ |
596 | dst = ds->dst; |
597 | |
598 | list_for_each_entry(dl, &dst->rtable, list) { |
599 | if (dl->dp->ds != ds || dl->link_dp->cpu_dp == dl->dp->cpu_dp) |
600 | continue; |
601 | |
602 | from = dl->dp->index; |
603 | to = dsa_upstream_port(ds, port: from); |
604 | |
605 | dev_warn(ds->dev, |
606 | "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n" , |
607 | from, to); |
608 | |
609 | sja1105_port_allow_traffic(l2_fwd: l2fwd, from, to, allow: false); |
610 | |
611 | l2fwd[from].bc_domain &= ~BIT(to); |
612 | l2fwd[from].fl_domain &= ~BIT(to); |
613 | } |
614 | |
615 | /* Finally, manage the egress flooding domain. All ports start up with |
616 | * flooding enabled, including the CPU port and DSA links. |
617 | */ |
618 | for (port = 0; port < ds->num_ports; port++) { |
619 | if (dsa_is_unused_port(ds, p: port)) |
620 | continue; |
621 | |
622 | priv->ucast_egress_floods |= BIT(port); |
623 | priv->bcast_egress_floods |= BIT(port); |
624 | } |
625 | |
626 | /* Next 8 entries define VLAN PCP mapping from ingress to egress. |
627 | * Create a one-to-one mapping. |
628 | */ |
629 | for (tc = 0; tc < SJA1105_NUM_TC; tc++) { |
630 | for (port = 0; port < ds->num_ports; port++) { |
631 | if (dsa_is_unused_port(ds, p: port)) |
632 | continue; |
633 | |
634 | l2fwd[ds->num_ports + tc].vlan_pmap[port] = tc; |
635 | } |
636 | |
637 | l2fwd[ds->num_ports + tc].type_egrpcp2outputq = true; |
638 | } |
639 | |
640 | return 0; |
641 | } |
642 | |
643 | static int sja1110_init_pcp_remapping(struct sja1105_private *priv) |
644 | { |
645 | struct sja1110_pcp_remapping_entry *pcp_remap; |
646 | struct dsa_switch *ds = priv->ds; |
647 | struct sja1105_table *table; |
648 | int port, tc; |
649 | |
650 | table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING]; |
651 | |
652 | /* Nothing to do for SJA1105 */ |
653 | if (!table->ops->max_entry_count) |
654 | return 0; |
655 | |
656 | if (table->entry_count) { |
657 | kfree(objp: table->entries); |
658 | table->entry_count = 0; |
659 | } |
660 | |
661 | table->entries = kcalloc(n: table->ops->max_entry_count, |
662 | size: table->ops->unpacked_entry_size, GFP_KERNEL); |
663 | if (!table->entries) |
664 | return -ENOMEM; |
665 | |
666 | table->entry_count = table->ops->max_entry_count; |
667 | |
668 | pcp_remap = table->entries; |
669 | |
670 | /* Repeat the configuration done for vlan_pmap */ |
671 | for (port = 0; port < ds->num_ports; port++) { |
672 | if (dsa_is_unused_port(ds, p: port)) |
673 | continue; |
674 | |
675 | for (tc = 0; tc < SJA1105_NUM_TC; tc++) |
676 | pcp_remap[port].egrpcp[tc] = tc; |
677 | } |
678 | |
679 | return 0; |
680 | } |
681 | |
682 | static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv) |
683 | { |
684 | struct sja1105_l2_forwarding_params_entry *l2fwd_params; |
685 | struct sja1105_table *table; |
686 | |
687 | table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS]; |
688 | |
689 | if (table->entry_count) { |
690 | kfree(objp: table->entries); |
691 | table->entry_count = 0; |
692 | } |
693 | |
694 | table->entries = kcalloc(n: table->ops->max_entry_count, |
695 | size: table->ops->unpacked_entry_size, GFP_KERNEL); |
696 | if (!table->entries) |
697 | return -ENOMEM; |
698 | |
699 | table->entry_count = table->ops->max_entry_count; |
700 | |
701 | /* This table only has a single entry */ |
702 | l2fwd_params = table->entries; |
703 | |
704 | /* Disallow dynamic reconfiguration of vlan_pmap */ |
705 | l2fwd_params->max_dynp = 0; |
706 | /* Use a single memory partition for all ingress queues */ |
707 | l2fwd_params->part_spc[0] = priv->info->max_frame_mem; |
708 | |
709 | return 0; |
710 | } |
711 | |
712 | void sja1105_frame_memory_partitioning(struct sja1105_private *priv) |
713 | { |
714 | struct sja1105_l2_forwarding_params_entry *l2_fwd_params; |
715 | struct sja1105_vl_forwarding_params_entry *vl_fwd_params; |
716 | struct sja1105_table *table; |
717 | |
718 | table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS]; |
719 | l2_fwd_params = table->entries; |
720 | l2_fwd_params->part_spc[0] = SJA1105_MAX_FRAME_MEMORY; |
721 | |
722 | /* If we have any critical-traffic virtual links, we need to reserve |
723 | * some frame buffer memory for them. At the moment, hardcode the value |
724 | * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks |
725 | * remaining for best-effort traffic. TODO: figure out a more flexible |
726 | * way to perform the frame buffer partitioning. |
727 | */ |
728 | if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count) |
729 | return; |
730 | |
731 | table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS]; |
732 | vl_fwd_params = table->entries; |
733 | |
734 | l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY; |
735 | vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY; |
736 | } |
737 | |
738 | /* SJA1110 TDMACONFIGIDX values: |
739 | * |
740 | * | 100 Mbps ports | 1Gbps ports | 2.5Gbps ports | Disabled ports |
741 | * -----+----------------+---------------+---------------+--------------- |
742 | * 0 | 0, [5:10] | [1:2] | [3:4] | retag |
743 | * 1 |0, [5:10], retag| [1:2] | [3:4] | - |
744 | * 2 | 0, [5:10] | [1:3], retag | 4 | - |
745 | * 3 | 0, [5:10] |[1:2], 4, retag| 3 | - |
746 | * 4 | 0, 2, [5:10] | 1, retag | [3:4] | - |
747 | * 5 | 0, 1, [5:10] | 2, retag | [3:4] | - |
748 | * 14 | 0, [5:10] | [1:4], retag | - | - |
749 | * 15 | [5:10] | [0:4], retag | - | - |
750 | */ |
751 | static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv) |
752 | { |
753 | struct sja1105_general_params_entry *general_params; |
754 | struct sja1105_table *table; |
755 | bool port_1_is_base_tx; |
756 | bool port_3_is_2500; |
757 | bool port_4_is_2500; |
758 | u64 tdmaconfigidx; |
759 | |
760 | if (priv->info->device_id != SJA1110_DEVICE_ID) |
761 | return; |
762 | |
763 | table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; |
764 | general_params = table->entries; |
765 | |
766 | /* All the settings below are "as opposed to SGMII", which is the |
767 | * other pinmuxing option. |
768 | */ |
769 | port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL; |
770 | port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX; |
771 | port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX; |
772 | |
773 | if (port_1_is_base_tx) |
774 | /* Retagging port will operate at 1 Gbps */ |
775 | tdmaconfigidx = 5; |
776 | else if (port_3_is_2500 && port_4_is_2500) |
777 | /* Retagging port will operate at 100 Mbps */ |
778 | tdmaconfigidx = 1; |
779 | else if (port_3_is_2500) |
780 | /* Retagging port will operate at 1 Gbps */ |
781 | tdmaconfigidx = 3; |
782 | else if (port_4_is_2500) |
783 | /* Retagging port will operate at 1 Gbps */ |
784 | tdmaconfigidx = 2; |
785 | else |
786 | /* Retagging port will operate at 1 Gbps */ |
787 | tdmaconfigidx = 14; |
788 | |
789 | general_params->tdmaconfigidx = tdmaconfigidx; |
790 | } |
791 | |
792 | static int sja1105_init_topology(struct sja1105_private *priv, |
793 | struct sja1105_general_params_entry *general_params) |
794 | { |
795 | struct dsa_switch *ds = priv->ds; |
796 | int port; |
797 | |
798 | /* The host port is the destination for traffic matching mac_fltres1 |
799 | * and mac_fltres0 on all ports except itself. Default to an invalid |
800 | * value. |
801 | */ |
802 | general_params->host_port = ds->num_ports; |
803 | |
804 | /* Link-local traffic received on casc_port will be forwarded |
805 | * to host_port without embedding the source port and device ID |
806 | * info in the destination MAC address, and no RX timestamps will be |
807 | * taken either (presumably because it is a cascaded port and a |
808 | * downstream SJA switch already did that). |
809 | * To disable the feature, we need to do different things depending on |
810 | * switch generation. On SJA1105 we need to set an invalid port, while |
811 | * on SJA1110 which support multiple cascaded ports, this field is a |
812 | * bitmask so it must be left zero. |
813 | */ |
814 | if (!priv->info->multiple_cascade_ports) |
815 | general_params->casc_port = ds->num_ports; |
816 | |
817 | for (port = 0; port < ds->num_ports; port++) { |
818 | bool is_upstream = dsa_is_upstream_port(ds, port); |
819 | bool is_dsa_link = dsa_is_dsa_port(ds, p: port); |
820 | |
821 | /* Upstream ports can be dedicated CPU ports or |
822 | * upstream-facing DSA links |
823 | */ |
824 | if (is_upstream) { |
825 | if (general_params->host_port == ds->num_ports) { |
826 | general_params->host_port = port; |
827 | } else { |
828 | dev_err(ds->dev, |
829 | "Port %llu is already a host port, configuring %d as one too is not supported\n" , |
830 | general_params->host_port, port); |
831 | return -EINVAL; |
832 | } |
833 | } |
834 | |
835 | /* Cascade ports are downstream-facing DSA links */ |
836 | if (is_dsa_link && !is_upstream) { |
837 | if (priv->info->multiple_cascade_ports) { |
838 | general_params->casc_port |= BIT(port); |
839 | } else if (general_params->casc_port == ds->num_ports) { |
840 | general_params->casc_port = port; |
841 | } else { |
842 | dev_err(ds->dev, |
843 | "Port %llu is already a cascade port, configuring %d as one too is not supported\n" , |
844 | general_params->casc_port, port); |
845 | return -EINVAL; |
846 | } |
847 | } |
848 | } |
849 | |
850 | if (general_params->host_port == ds->num_ports) { |
851 | dev_err(ds->dev, "No host port configured\n" ); |
852 | return -EINVAL; |
853 | } |
854 | |
855 | return 0; |
856 | } |
857 | |
858 | static int sja1105_init_general_params(struct sja1105_private *priv) |
859 | { |
860 | struct sja1105_general_params_entry default_general_params = { |
861 | /* Allow dynamic changing of the mirror port */ |
862 | .mirr_ptacu = true, |
863 | .switchid = priv->ds->index, |
864 | /* Priority queue for link-local management frames |
865 | * (both ingress to and egress from CPU - PTP, STP etc) |
866 | */ |
867 | .hostprio = 7, |
868 | .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A, |
869 | .mac_flt1 = SJA1105_LINKLOCAL_FILTER_A_MASK, |
870 | .incl_srcpt1 = true, |
871 | .send_meta1 = true, |
872 | .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B, |
873 | .mac_flt0 = SJA1105_LINKLOCAL_FILTER_B_MASK, |
874 | .incl_srcpt0 = true, |
875 | .send_meta0 = true, |
876 | /* Default to an invalid value */ |
877 | .mirr_port = priv->ds->num_ports, |
878 | /* No TTEthernet */ |
879 | .vllupformat = SJA1105_VL_FORMAT_PSFP, |
880 | .vlmarker = 0, |
881 | .vlmask = 0, |
882 | /* Only update correctionField for 1-step PTP (L2 transport) */ |
883 | .ignore2stf = 0, |
884 | /* Forcefully disable VLAN filtering by telling |
885 | * the switch that VLAN has a different EtherType. |
886 | */ |
887 | .tpid = ETH_P_SJA1105, |
888 | .tpid2 = ETH_P_SJA1105, |
889 | /* Enable the TTEthernet engine on SJA1110 */ |
890 | .tte_en = true, |
891 | /* Set up the EtherType for control packets on SJA1110 */ |
892 | .header_type = ETH_P_SJA1110, |
893 | }; |
894 | struct sja1105_general_params_entry *general_params; |
895 | struct sja1105_table *table; |
896 | int rc; |
897 | |
898 | rc = sja1105_init_topology(priv, general_params: &default_general_params); |
899 | if (rc) |
900 | return rc; |
901 | |
902 | table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; |
903 | |
904 | if (table->entry_count) { |
905 | kfree(objp: table->entries); |
906 | table->entry_count = 0; |
907 | } |
908 | |
909 | table->entries = kcalloc(n: table->ops->max_entry_count, |
910 | size: table->ops->unpacked_entry_size, GFP_KERNEL); |
911 | if (!table->entries) |
912 | return -ENOMEM; |
913 | |
914 | table->entry_count = table->ops->max_entry_count; |
915 | |
916 | general_params = table->entries; |
917 | |
918 | /* This table only has a single entry */ |
919 | general_params[0] = default_general_params; |
920 | |
921 | sja1110_select_tdmaconfigidx(priv); |
922 | |
923 | return 0; |
924 | } |
925 | |
926 | static int sja1105_init_avb_params(struct sja1105_private *priv) |
927 | { |
928 | struct sja1105_avb_params_entry *avb; |
929 | struct sja1105_table *table; |
930 | |
931 | table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS]; |
932 | |
933 | /* Discard previous AVB Parameters Table */ |
934 | if (table->entry_count) { |
935 | kfree(objp: table->entries); |
936 | table->entry_count = 0; |
937 | } |
938 | |
939 | table->entries = kcalloc(n: table->ops->max_entry_count, |
940 | size: table->ops->unpacked_entry_size, GFP_KERNEL); |
941 | if (!table->entries) |
942 | return -ENOMEM; |
943 | |
944 | table->entry_count = table->ops->max_entry_count; |
945 | |
946 | avb = table->entries; |
947 | |
948 | /* Configure the MAC addresses for meta frames */ |
949 | avb->destmeta = SJA1105_META_DMAC; |
950 | avb->srcmeta = SJA1105_META_SMAC; |
951 | /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by |
952 | * default. This is because there might be boards with a hardware |
953 | * layout where enabling the pin as output might cause an electrical |
954 | * clash. On E/T the pin is always an output, which the board designers |
955 | * probably already knew, so even if there are going to be electrical |
956 | * issues, there's nothing we can do. |
957 | */ |
958 | avb->cas_master = false; |
959 | |
960 | return 0; |
961 | } |
962 | |
963 | /* The L2 policing table is 2-stage. The table is looked up for each frame |
964 | * according to the ingress port, whether it was broadcast or not, and the |
965 | * classified traffic class (given by VLAN PCP). This portion of the lookup is |
966 | * fixed, and gives access to the SHARINDX, an indirection register pointing |
967 | * within the policing table itself, which is used to resolve the policer that |
968 | * will be used for this frame. |
969 | * |
970 | * Stage 1 Stage 2 |
971 | * +------------+--------+ +---------------------------------+ |
972 | * |Port 0 TC 0 |SHARINDX| | Policer 0: Rate, Burst, MTU | |
973 | * +------------+--------+ +---------------------------------+ |
974 | * |Port 0 TC 1 |SHARINDX| | Policer 1: Rate, Burst, MTU | |
975 | * +------------+--------+ +---------------------------------+ |
976 | * ... | Policer 2: Rate, Burst, MTU | |
977 | * +------------+--------+ +---------------------------------+ |
978 | * |Port 0 TC 7 |SHARINDX| | Policer 3: Rate, Burst, MTU | |
979 | * +------------+--------+ +---------------------------------+ |
980 | * |Port 1 TC 0 |SHARINDX| | Policer 4: Rate, Burst, MTU | |
981 | * +------------+--------+ +---------------------------------+ |
982 | * ... | Policer 5: Rate, Burst, MTU | |
983 | * +------------+--------+ +---------------------------------+ |
984 | * |Port 1 TC 7 |SHARINDX| | Policer 6: Rate, Burst, MTU | |
985 | * +------------+--------+ +---------------------------------+ |
986 | * ... | Policer 7: Rate, Burst, MTU | |
987 | * +------------+--------+ +---------------------------------+ |
988 | * |Port 4 TC 7 |SHARINDX| ... |
989 | * +------------+--------+ |
990 | * |Port 0 BCAST|SHARINDX| ... |
991 | * +------------+--------+ |
992 | * |Port 1 BCAST|SHARINDX| ... |
993 | * +------------+--------+ |
994 | * ... ... |
995 | * +------------+--------+ +---------------------------------+ |
996 | * |Port 4 BCAST|SHARINDX| | Policer 44: Rate, Burst, MTU | |
997 | * +------------+--------+ +---------------------------------+ |
998 | * |
999 | * In this driver, we shall use policers 0-4 as statically alocated port |
1000 | * (matchall) policers. So we need to make the SHARINDX for all lookups |
1001 | * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast |
1002 | * lookup) equal. |
1003 | * The remaining policers (40) shall be dynamically allocated for flower |
1004 | * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff. |
1005 | */ |
1006 | #define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000) |
1007 | |
1008 | static int sja1105_init_l2_policing(struct sja1105_private *priv) |
1009 | { |
1010 | struct sja1105_l2_policing_entry *policing; |
1011 | struct dsa_switch *ds = priv->ds; |
1012 | struct sja1105_table *table; |
1013 | int port, tc; |
1014 | |
1015 | table = &priv->static_config.tables[BLK_IDX_L2_POLICING]; |
1016 | |
1017 | /* Discard previous L2 Policing Table */ |
1018 | if (table->entry_count) { |
1019 | kfree(objp: table->entries); |
1020 | table->entry_count = 0; |
1021 | } |
1022 | |
1023 | table->entries = kcalloc(n: table->ops->max_entry_count, |
1024 | size: table->ops->unpacked_entry_size, GFP_KERNEL); |
1025 | if (!table->entries) |
1026 | return -ENOMEM; |
1027 | |
1028 | table->entry_count = table->ops->max_entry_count; |
1029 | |
1030 | policing = table->entries; |
1031 | |
1032 | /* Setup shared indices for the matchall policers */ |
1033 | for (port = 0; port < ds->num_ports; port++) { |
1034 | int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port; |
1035 | int bcast = (ds->num_ports * SJA1105_NUM_TC) + port; |
1036 | |
1037 | for (tc = 0; tc < SJA1105_NUM_TC; tc++) |
1038 | policing[port * SJA1105_NUM_TC + tc].sharindx = port; |
1039 | |
1040 | policing[bcast].sharindx = port; |
1041 | /* Only SJA1110 has multicast policers */ |
1042 | if (mcast < table->ops->max_entry_count) |
1043 | policing[mcast].sharindx = port; |
1044 | } |
1045 | |
1046 | /* Setup the matchall policer parameters */ |
1047 | for (port = 0; port < ds->num_ports; port++) { |
1048 | int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; |
1049 | |
1050 | if (dsa_is_cpu_port(ds, p: port) || dsa_is_dsa_port(ds, p: port)) |
1051 | mtu += VLAN_HLEN; |
1052 | |
1053 | policing[port].smax = 65535; /* Burst size in bytes */ |
1054 | policing[port].rate = SJA1105_RATE_MBPS(1000); |
1055 | policing[port].maxlen = mtu; |
1056 | policing[port].partition = 0; |
1057 | } |
1058 | |
1059 | return 0; |
1060 | } |
1061 | |
1062 | static int sja1105_static_config_load(struct sja1105_private *priv) |
1063 | { |
1064 | int rc; |
1065 | |
1066 | sja1105_static_config_free(config: &priv->static_config); |
1067 | rc = sja1105_static_config_init(config: &priv->static_config, |
1068 | static_ops: priv->info->static_ops, |
1069 | device_id: priv->info->device_id); |
1070 | if (rc) |
1071 | return rc; |
1072 | |
1073 | /* Build static configuration */ |
1074 | rc = sja1105_init_mac_settings(priv); |
1075 | if (rc < 0) |
1076 | return rc; |
1077 | rc = sja1105_init_mii_settings(priv); |
1078 | if (rc < 0) |
1079 | return rc; |
1080 | rc = sja1105_init_static_fdb(priv); |
1081 | if (rc < 0) |
1082 | return rc; |
1083 | rc = sja1105_init_static_vlan(priv); |
1084 | if (rc < 0) |
1085 | return rc; |
1086 | rc = sja1105_init_l2_lookup_params(priv); |
1087 | if (rc < 0) |
1088 | return rc; |
1089 | rc = sja1105_init_l2_forwarding(priv); |
1090 | if (rc < 0) |
1091 | return rc; |
1092 | rc = sja1105_init_l2_forwarding_params(priv); |
1093 | if (rc < 0) |
1094 | return rc; |
1095 | rc = sja1105_init_l2_policing(priv); |
1096 | if (rc < 0) |
1097 | return rc; |
1098 | rc = sja1105_init_general_params(priv); |
1099 | if (rc < 0) |
1100 | return rc; |
1101 | rc = sja1105_init_avb_params(priv); |
1102 | if (rc < 0) |
1103 | return rc; |
1104 | rc = sja1110_init_pcp_remapping(priv); |
1105 | if (rc < 0) |
1106 | return rc; |
1107 | |
1108 | /* Send initial configuration to hardware via SPI */ |
1109 | return sja1105_static_config_upload(priv); |
1110 | } |
1111 | |
1112 | /* This is the "new way" for a MAC driver to configure its RGMII delay lines, |
1113 | * based on the explicit "rx-internal-delay-ps" and "tx-internal-delay-ps" |
1114 | * properties. It has the advantage of working with fixed links and with PHYs |
1115 | * that apply RGMII delays too, and the MAC driver needs not perform any |
1116 | * special checks. |
1117 | * |
1118 | * Previously we were acting upon the "phy-mode" property when we were |
1119 | * operating in fixed-link, basically acting as a PHY, but with a reversed |
1120 | * interpretation: PHY_INTERFACE_MODE_RGMII_TXID means that the MAC should |
1121 | * behave as if it is connected to a PHY which has applied RGMII delays in the |
1122 | * TX direction. So if anything, RX delays should have been added by the MAC, |
1123 | * but we were adding TX delays. |
1124 | * |
1125 | * If the "{rx,tx}-internal-delay-ps" properties are not specified, we fall |
1126 | * back to the legacy behavior and apply delays on fixed-link ports based on |
1127 | * the reverse interpretation of the phy-mode. This is a deviation from the |
1128 | * expected default behavior which is to simply apply no delays. To achieve |
1129 | * that behavior with the new bindings, it is mandatory to specify |
1130 | * "{rx,tx}-internal-delay-ps" with a value of 0. |
1131 | */ |
1132 | static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, int port, |
1133 | struct device_node *port_dn) |
1134 | { |
1135 | phy_interface_t phy_mode = priv->phy_mode[port]; |
1136 | struct device *dev = &priv->spidev->dev; |
1137 | int rx_delay = -1, tx_delay = -1; |
1138 | |
1139 | if (!phy_interface_mode_is_rgmii(mode: phy_mode)) |
1140 | return 0; |
1141 | |
1142 | of_property_read_u32(np: port_dn, propname: "rx-internal-delay-ps" , out_value: &rx_delay); |
1143 | of_property_read_u32(np: port_dn, propname: "tx-internal-delay-ps" , out_value: &tx_delay); |
1144 | |
1145 | if (rx_delay == -1 && tx_delay == -1 && priv->fixed_link[port]) { |
1146 | dev_warn(dev, |
1147 | "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " |
1148 | "please update device tree to specify \"rx-internal-delay-ps\" and " |
1149 | "\"tx-internal-delay-ps\"" , |
1150 | port); |
1151 | |
1152 | if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || |
1153 | phy_mode == PHY_INTERFACE_MODE_RGMII_ID) |
1154 | rx_delay = 2000; |
1155 | |
1156 | if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || |
1157 | phy_mode == PHY_INTERFACE_MODE_RGMII_ID) |
1158 | tx_delay = 2000; |
1159 | } |
1160 | |
1161 | if (rx_delay < 0) |
1162 | rx_delay = 0; |
1163 | if (tx_delay < 0) |
1164 | tx_delay = 0; |
1165 | |
1166 | if ((rx_delay || tx_delay) && !priv->info->setup_rgmii_delay) { |
1167 | dev_err(dev, "Chip cannot apply RGMII delays\n" ); |
1168 | return -EINVAL; |
1169 | } |
1170 | |
1171 | if ((rx_delay && rx_delay < SJA1105_RGMII_DELAY_MIN_PS) || |
1172 | (tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) || |
1173 | (rx_delay > SJA1105_RGMII_DELAY_MAX_PS) || |
1174 | (tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) { |
1175 | dev_err(dev, |
1176 | "port %d RGMII delay values out of range, must be between %d and %d ps\n" , |
1177 | port, SJA1105_RGMII_DELAY_MIN_PS, SJA1105_RGMII_DELAY_MAX_PS); |
1178 | return -ERANGE; |
1179 | } |
1180 | |
1181 | priv->rgmii_rx_delay_ps[port] = rx_delay; |
1182 | priv->rgmii_tx_delay_ps[port] = tx_delay; |
1183 | |
1184 | return 0; |
1185 | } |
1186 | |
1187 | static int sja1105_parse_ports_node(struct sja1105_private *priv, |
1188 | struct device_node *ports_node) |
1189 | { |
1190 | struct device *dev = &priv->spidev->dev; |
1191 | struct device_node *child; |
1192 | |
1193 | for_each_available_child_of_node(ports_node, child) { |
1194 | struct device_node *phy_node; |
1195 | phy_interface_t phy_mode; |
1196 | u32 index; |
1197 | int err; |
1198 | |
1199 | /* Get switch port number from DT */ |
1200 | if (of_property_read_u32(np: child, propname: "reg" , out_value: &index) < 0) { |
1201 | dev_err(dev, "Port number not defined in device tree " |
1202 | "(property \"reg\")\n" ); |
1203 | of_node_put(node: child); |
1204 | return -ENODEV; |
1205 | } |
1206 | |
1207 | /* Get PHY mode from DT */ |
1208 | err = of_get_phy_mode(np: child, interface: &phy_mode); |
1209 | if (err) { |
1210 | dev_err(dev, "Failed to read phy-mode or " |
1211 | "phy-interface-type property for port %d\n" , |
1212 | index); |
1213 | of_node_put(node: child); |
1214 | return -ENODEV; |
1215 | } |
1216 | |
1217 | phy_node = of_parse_phandle(np: child, phandle_name: "phy-handle" , index: 0); |
1218 | if (!phy_node) { |
1219 | if (!of_phy_is_fixed_link(np: child)) { |
1220 | dev_err(dev, "phy-handle or fixed-link " |
1221 | "properties missing!\n" ); |
1222 | of_node_put(node: child); |
1223 | return -ENODEV; |
1224 | } |
1225 | /* phy-handle is missing, but fixed-link isn't. |
1226 | * So it's a fixed link. Default to PHY role. |
1227 | */ |
1228 | priv->fixed_link[index] = true; |
1229 | } else { |
1230 | of_node_put(node: phy_node); |
1231 | } |
1232 | |
1233 | priv->phy_mode[index] = phy_mode; |
1234 | |
1235 | err = sja1105_parse_rgmii_delays(priv, port: index, port_dn: child); |
1236 | if (err) { |
1237 | of_node_put(node: child); |
1238 | return err; |
1239 | } |
1240 | } |
1241 | |
1242 | return 0; |
1243 | } |
1244 | |
1245 | static int sja1105_parse_dt(struct sja1105_private *priv) |
1246 | { |
1247 | struct device *dev = &priv->spidev->dev; |
1248 | struct device_node *switch_node = dev->of_node; |
1249 | struct device_node *ports_node; |
1250 | int rc; |
1251 | |
1252 | ports_node = of_get_child_by_name(node: switch_node, name: "ports" ); |
1253 | if (!ports_node) |
1254 | ports_node = of_get_child_by_name(node: switch_node, name: "ethernet-ports" ); |
1255 | if (!ports_node) { |
1256 | dev_err(dev, "Incorrect bindings: absent \"ports\" node\n" ); |
1257 | return -ENODEV; |
1258 | } |
1259 | |
1260 | rc = sja1105_parse_ports_node(priv, ports_node); |
1261 | of_node_put(node: ports_node); |
1262 | |
1263 | return rc; |
1264 | } |
1265 | |
1266 | /* Convert link speed from SJA1105 to ethtool encoding */ |
1267 | static int sja1105_port_speed_to_ethtool(struct sja1105_private *priv, |
1268 | u64 speed) |
1269 | { |
1270 | if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS]) |
1271 | return SPEED_10; |
1272 | if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS]) |
1273 | return SPEED_100; |
1274 | if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS]) |
1275 | return SPEED_1000; |
1276 | if (speed == priv->info->port_speed[SJA1105_SPEED_2500MBPS]) |
1277 | return SPEED_2500; |
1278 | return SPEED_UNKNOWN; |
1279 | } |
1280 | |
1281 | /* Set link speed in the MAC configuration for a specific port. */ |
1282 | static int sja1105_adjust_port_config(struct sja1105_private *priv, int port, |
1283 | int speed_mbps) |
1284 | { |
1285 | struct sja1105_mac_config_entry *mac; |
1286 | struct device *dev = priv->ds->dev; |
1287 | u64 speed; |
1288 | int rc; |
1289 | |
1290 | /* On P/Q/R/S, one can read from the device via the MAC reconfiguration |
1291 | * tables. On E/T, MAC reconfig tables are not readable, only writable. |
1292 | * We have to *know* what the MAC looks like. For the sake of keeping |
1293 | * the code common, we'll use the static configuration tables as a |
1294 | * reasonable approximation for both E/T and P/Q/R/S. |
1295 | */ |
1296 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; |
1297 | |
1298 | switch (speed_mbps) { |
1299 | case SPEED_UNKNOWN: |
1300 | /* PHYLINK called sja1105_mac_config() to inform us about |
1301 | * the state->interface, but AN has not completed and the |
1302 | * speed is not yet valid. UM10944.pdf says that setting |
1303 | * SJA1105_SPEED_AUTO at runtime disables the port, so that is |
1304 | * ok for power consumption in case AN will never complete - |
1305 | * otherwise PHYLINK should come back with a new update. |
1306 | */ |
1307 | speed = priv->info->port_speed[SJA1105_SPEED_AUTO]; |
1308 | break; |
1309 | case SPEED_10: |
1310 | speed = priv->info->port_speed[SJA1105_SPEED_10MBPS]; |
1311 | break; |
1312 | case SPEED_100: |
1313 | speed = priv->info->port_speed[SJA1105_SPEED_100MBPS]; |
1314 | break; |
1315 | case SPEED_1000: |
1316 | speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS]; |
1317 | break; |
1318 | case SPEED_2500: |
1319 | speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS]; |
1320 | break; |
1321 | default: |
1322 | dev_err(dev, "Invalid speed %iMbps\n" , speed_mbps); |
1323 | return -EINVAL; |
1324 | } |
1325 | |
1326 | /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration |
1327 | * table, since this will be used for the clocking setup, and we no |
1328 | * longer need to store it in the static config (already told hardware |
1329 | * we want auto during upload phase). |
1330 | * Actually for the SGMII port, the MAC is fixed at 1 Gbps and |
1331 | * we need to configure the PCS only (if even that). |
1332 | */ |
1333 | if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII) |
1334 | mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS]; |
1335 | else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX) |
1336 | mac[port].speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS]; |
1337 | else |
1338 | mac[port].speed = speed; |
1339 | |
1340 | /* Write to the dynamic reconfiguration tables */ |
1341 | rc = sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_MAC_CONFIG, index: port, |
1342 | entry: &mac[port], keep: true); |
1343 | if (rc < 0) { |
1344 | dev_err(dev, "Failed to write MAC config: %d\n" , rc); |
1345 | return rc; |
1346 | } |
1347 | |
1348 | /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at |
1349 | * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and |
1350 | * RMII no change of the clock setup is required. Actually, changing |
1351 | * the clock setup does interrupt the clock signal for a certain time |
1352 | * which causes trouble for all PHYs relying on this signal. |
1353 | */ |
1354 | if (!phy_interface_mode_is_rgmii(mode: priv->phy_mode[port])) |
1355 | return 0; |
1356 | |
1357 | return sja1105_clocking_setup_port(priv, port); |
1358 | } |
1359 | |
1360 | static struct phylink_pcs * |
1361 | sja1105_mac_select_pcs(struct dsa_switch *ds, int port, phy_interface_t iface) |
1362 | { |
1363 | struct sja1105_private *priv = ds->priv; |
1364 | struct dw_xpcs *xpcs = priv->xpcs[port]; |
1365 | |
1366 | if (xpcs) |
1367 | return &xpcs->pcs; |
1368 | |
1369 | return NULL; |
1370 | } |
1371 | |
1372 | static void sja1105_mac_link_down(struct dsa_switch *ds, int port, |
1373 | unsigned int mode, |
1374 | phy_interface_t interface) |
1375 | { |
1376 | sja1105_inhibit_tx(priv: ds->priv, BIT(port), tx_inhibited: true); |
1377 | } |
1378 | |
1379 | static void sja1105_mac_link_up(struct dsa_switch *ds, int port, |
1380 | unsigned int mode, |
1381 | phy_interface_t interface, |
1382 | struct phy_device *phydev, |
1383 | int speed, int duplex, |
1384 | bool tx_pause, bool rx_pause) |
1385 | { |
1386 | struct sja1105_private *priv = ds->priv; |
1387 | |
1388 | sja1105_adjust_port_config(priv, port, speed_mbps: speed); |
1389 | |
1390 | sja1105_inhibit_tx(priv, BIT(port), tx_inhibited: false); |
1391 | } |
1392 | |
1393 | static void sja1105_phylink_get_caps(struct dsa_switch *ds, int port, |
1394 | struct phylink_config *config) |
1395 | { |
1396 | struct sja1105_private *priv = ds->priv; |
1397 | struct sja1105_xmii_params_entry *mii; |
1398 | phy_interface_t phy_mode; |
1399 | |
1400 | phy_mode = priv->phy_mode[port]; |
1401 | if (phy_mode == PHY_INTERFACE_MODE_SGMII || |
1402 | phy_mode == PHY_INTERFACE_MODE_2500BASEX) { |
1403 | /* Changing the PHY mode on SERDES ports is possible and makes |
1404 | * sense, because that is done through the XPCS. We allow |
1405 | * changes between SGMII and 2500base-X. |
1406 | */ |
1407 | if (priv->info->supports_sgmii[port]) |
1408 | __set_bit(PHY_INTERFACE_MODE_SGMII, |
1409 | config->supported_interfaces); |
1410 | |
1411 | if (priv->info->supports_2500basex[port]) |
1412 | __set_bit(PHY_INTERFACE_MODE_2500BASEX, |
1413 | config->supported_interfaces); |
1414 | } else { |
1415 | /* The SJA1105 MAC programming model is through the static |
1416 | * config (the xMII Mode table cannot be dynamically |
1417 | * reconfigured), and we have to program that early. |
1418 | */ |
1419 | __set_bit(phy_mode, config->supported_interfaces); |
1420 | } |
1421 | |
1422 | /* The MAC does not support pause frames, and also doesn't |
1423 | * support half-duplex traffic modes. |
1424 | */ |
1425 | config->mac_capabilities = MAC_10FD | MAC_100FD; |
1426 | |
1427 | mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries; |
1428 | if (mii->xmii_mode[port] == XMII_MODE_RGMII || |
1429 | mii->xmii_mode[port] == XMII_MODE_SGMII) |
1430 | config->mac_capabilities |= MAC_1000FD; |
1431 | |
1432 | if (priv->info->supports_2500basex[port]) |
1433 | config->mac_capabilities |= MAC_2500FD; |
1434 | } |
1435 | |
1436 | static int |
1437 | sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port, |
1438 | const struct sja1105_l2_lookup_entry *requested) |
1439 | { |
1440 | struct sja1105_l2_lookup_entry *l2_lookup; |
1441 | struct sja1105_table *table; |
1442 | int i; |
1443 | |
1444 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; |
1445 | l2_lookup = table->entries; |
1446 | |
1447 | for (i = 0; i < table->entry_count; i++) |
1448 | if (l2_lookup[i].macaddr == requested->macaddr && |
1449 | l2_lookup[i].vlanid == requested->vlanid && |
1450 | l2_lookup[i].destports & BIT(port)) |
1451 | return i; |
1452 | |
1453 | return -1; |
1454 | } |
1455 | |
1456 | /* We want FDB entries added statically through the bridge command to persist |
1457 | * across switch resets, which are a common thing during normal SJA1105 |
1458 | * operation. So we have to back them up in the static configuration tables |
1459 | * and hence apply them on next static config upload... yay! |
1460 | */ |
1461 | static int |
1462 | sja1105_static_fdb_change(struct sja1105_private *priv, int port, |
1463 | const struct sja1105_l2_lookup_entry *requested, |
1464 | bool keep) |
1465 | { |
1466 | struct sja1105_l2_lookup_entry *l2_lookup; |
1467 | struct sja1105_table *table; |
1468 | int rc, match; |
1469 | |
1470 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; |
1471 | |
1472 | match = sja1105_find_static_fdb_entry(priv, port, requested); |
1473 | if (match < 0) { |
1474 | /* Can't delete a missing entry. */ |
1475 | if (!keep) |
1476 | return 0; |
1477 | |
1478 | /* No match => new entry */ |
1479 | rc = sja1105_table_resize(table, new_count: table->entry_count + 1); |
1480 | if (rc) |
1481 | return rc; |
1482 | |
1483 | match = table->entry_count - 1; |
1484 | } |
1485 | |
1486 | /* Assign pointer after the resize (it may be new memory) */ |
1487 | l2_lookup = table->entries; |
1488 | |
1489 | /* We have a match. |
1490 | * If the job was to add this FDB entry, it's already done (mostly |
1491 | * anyway, since the port forwarding mask may have changed, case in |
1492 | * which we update it). |
1493 | * Otherwise we have to delete it. |
1494 | */ |
1495 | if (keep) { |
1496 | l2_lookup[match] = *requested; |
1497 | return 0; |
1498 | } |
1499 | |
1500 | /* To remove, the strategy is to overwrite the element with |
1501 | * the last one, and then reduce the array size by 1 |
1502 | */ |
1503 | l2_lookup[match] = l2_lookup[table->entry_count - 1]; |
1504 | return sja1105_table_resize(table, new_count: table->entry_count - 1); |
1505 | } |
1506 | |
1507 | /* First-generation switches have a 4-way set associative TCAM that |
1508 | * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of |
1509 | * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin). |
1510 | * For the placement of a newly learnt FDB entry, the switch selects the bin |
1511 | * based on a hash function, and the way within that bin incrementally. |
1512 | */ |
1513 | static int sja1105et_fdb_index(int bin, int way) |
1514 | { |
1515 | return bin * SJA1105ET_FDB_BIN_SIZE + way; |
1516 | } |
1517 | |
1518 | static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin, |
1519 | const u8 *addr, u16 vid, |
1520 | struct sja1105_l2_lookup_entry *match, |
1521 | int *last_unused) |
1522 | { |
1523 | int way; |
1524 | |
1525 | for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) { |
1526 | struct sja1105_l2_lookup_entry l2_lookup = {0}; |
1527 | int index = sja1105et_fdb_index(bin, way); |
1528 | |
1529 | /* Skip unused entries, optionally marking them |
1530 | * into the return value |
1531 | */ |
1532 | if (sja1105_dynamic_config_read(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
1533 | index, entry: &l2_lookup)) { |
1534 | if (last_unused) |
1535 | *last_unused = way; |
1536 | continue; |
1537 | } |
1538 | |
1539 | if (l2_lookup.macaddr == ether_addr_to_u64(addr) && |
1540 | l2_lookup.vlanid == vid) { |
1541 | if (match) |
1542 | *match = l2_lookup; |
1543 | return way; |
1544 | } |
1545 | } |
1546 | /* Return an invalid entry index if not found */ |
1547 | return -1; |
1548 | } |
1549 | |
1550 | int sja1105et_fdb_add(struct dsa_switch *ds, int port, |
1551 | const unsigned char *addr, u16 vid) |
1552 | { |
1553 | struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp; |
1554 | struct sja1105_private *priv = ds->priv; |
1555 | struct device *dev = ds->dev; |
1556 | int last_unused = -1; |
1557 | int start, end, i; |
1558 | int bin, way, rc; |
1559 | |
1560 | bin = sja1105et_fdb_hash(priv, addr, vid); |
1561 | |
1562 | way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid, |
1563 | match: &l2_lookup, last_unused: &last_unused); |
1564 | if (way >= 0) { |
1565 | /* We have an FDB entry. Is our port in the destination |
1566 | * mask? If yes, we need to do nothing. If not, we need |
1567 | * to rewrite the entry by adding this port to it. |
1568 | */ |
1569 | if ((l2_lookup.destports & BIT(port)) && l2_lookup.lockeds) |
1570 | return 0; |
1571 | l2_lookup.destports |= BIT(port); |
1572 | } else { |
1573 | int index = sja1105et_fdb_index(bin, way); |
1574 | |
1575 | /* We don't have an FDB entry. We construct a new one and |
1576 | * try to find a place for it within the FDB table. |
1577 | */ |
1578 | l2_lookup.macaddr = ether_addr_to_u64(addr); |
1579 | l2_lookup.destports = BIT(port); |
1580 | l2_lookup.vlanid = vid; |
1581 | |
1582 | if (last_unused >= 0) { |
1583 | way = last_unused; |
1584 | } else { |
1585 | /* Bin is full, need to evict somebody. |
1586 | * Choose victim at random. If you get these messages |
1587 | * often, you may need to consider changing the |
1588 | * distribution function: |
1589 | * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly |
1590 | */ |
1591 | get_random_bytes(buf: &way, len: sizeof(u8)); |
1592 | way %= SJA1105ET_FDB_BIN_SIZE; |
1593 | dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n" , |
1594 | bin, addr, way); |
1595 | /* Evict entry */ |
1596 | sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
1597 | index, NULL, keep: false); |
1598 | } |
1599 | } |
1600 | l2_lookup.lockeds = true; |
1601 | l2_lookup.index = sja1105et_fdb_index(bin, way); |
1602 | |
1603 | rc = sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
1604 | index: l2_lookup.index, entry: &l2_lookup, |
1605 | keep: true); |
1606 | if (rc < 0) |
1607 | return rc; |
1608 | |
1609 | /* Invalidate a dynamically learned entry if that exists */ |
1610 | start = sja1105et_fdb_index(bin, way: 0); |
1611 | end = sja1105et_fdb_index(bin, way); |
1612 | |
1613 | for (i = start; i < end; i++) { |
1614 | rc = sja1105_dynamic_config_read(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
1615 | index: i, entry: &tmp); |
1616 | if (rc == -ENOENT) |
1617 | continue; |
1618 | if (rc) |
1619 | return rc; |
1620 | |
1621 | if (tmp.macaddr != ether_addr_to_u64(addr) || tmp.vlanid != vid) |
1622 | continue; |
1623 | |
1624 | rc = sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
1625 | index: i, NULL, keep: false); |
1626 | if (rc) |
1627 | return rc; |
1628 | |
1629 | break; |
1630 | } |
1631 | |
1632 | return sja1105_static_fdb_change(priv, port, requested: &l2_lookup, keep: true); |
1633 | } |
1634 | |
1635 | int sja1105et_fdb_del(struct dsa_switch *ds, int port, |
1636 | const unsigned char *addr, u16 vid) |
1637 | { |
1638 | struct sja1105_l2_lookup_entry l2_lookup = {0}; |
1639 | struct sja1105_private *priv = ds->priv; |
1640 | int index, bin, way, rc; |
1641 | bool keep; |
1642 | |
1643 | bin = sja1105et_fdb_hash(priv, addr, vid); |
1644 | way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid, |
1645 | match: &l2_lookup, NULL); |
1646 | if (way < 0) |
1647 | return 0; |
1648 | index = sja1105et_fdb_index(bin, way); |
1649 | |
1650 | /* We have an FDB entry. Is our port in the destination mask? If yes, |
1651 | * we need to remove it. If the resulting port mask becomes empty, we |
1652 | * need to completely evict the FDB entry. |
1653 | * Otherwise we just write it back. |
1654 | */ |
1655 | l2_lookup.destports &= ~BIT(port); |
1656 | |
1657 | if (l2_lookup.destports) |
1658 | keep = true; |
1659 | else |
1660 | keep = false; |
1661 | |
1662 | rc = sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
1663 | index, entry: &l2_lookup, keep); |
1664 | if (rc < 0) |
1665 | return rc; |
1666 | |
1667 | return sja1105_static_fdb_change(priv, port, requested: &l2_lookup, keep); |
1668 | } |
1669 | |
1670 | int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port, |
1671 | const unsigned char *addr, u16 vid) |
1672 | { |
1673 | struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp; |
1674 | struct sja1105_private *priv = ds->priv; |
1675 | int rc, i; |
1676 | |
1677 | /* Search for an existing entry in the FDB table */ |
1678 | l2_lookup.macaddr = ether_addr_to_u64(addr); |
1679 | l2_lookup.vlanid = vid; |
1680 | l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0); |
1681 | l2_lookup.mask_vlanid = VLAN_VID_MASK; |
1682 | l2_lookup.destports = BIT(port); |
1683 | |
1684 | tmp = l2_lookup; |
1685 | |
1686 | rc = sja1105_dynamic_config_read(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
1687 | SJA1105_SEARCH, entry: &tmp); |
1688 | if (rc == 0 && tmp.index != SJA1105_MAX_L2_LOOKUP_COUNT - 1) { |
1689 | /* Found a static entry and this port is already in the entry's |
1690 | * port mask => job done |
1691 | */ |
1692 | if ((tmp.destports & BIT(port)) && tmp.lockeds) |
1693 | return 0; |
1694 | |
1695 | l2_lookup = tmp; |
1696 | |
1697 | /* l2_lookup.index is populated by the switch in case it |
1698 | * found something. |
1699 | */ |
1700 | l2_lookup.destports |= BIT(port); |
1701 | goto skip_finding_an_index; |
1702 | } |
1703 | |
1704 | /* Not found, so try to find an unused spot in the FDB. |
1705 | * This is slightly inefficient because the strategy is knock-knock at |
1706 | * every possible position from 0 to 1023. |
1707 | */ |
1708 | for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) { |
1709 | rc = sja1105_dynamic_config_read(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
1710 | index: i, NULL); |
1711 | if (rc < 0) |
1712 | break; |
1713 | } |
1714 | if (i == SJA1105_MAX_L2_LOOKUP_COUNT) { |
1715 | dev_err(ds->dev, "FDB is full, cannot add entry.\n" ); |
1716 | return -EINVAL; |
1717 | } |
1718 | l2_lookup.index = i; |
1719 | |
1720 | skip_finding_an_index: |
1721 | l2_lookup.lockeds = true; |
1722 | |
1723 | rc = sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
1724 | index: l2_lookup.index, entry: &l2_lookup, |
1725 | keep: true); |
1726 | if (rc < 0) |
1727 | return rc; |
1728 | |
1729 | /* The switch learns dynamic entries and looks up the FDB left to |
1730 | * right. It is possible that our addition was concurrent with the |
1731 | * dynamic learning of the same address, so now that the static entry |
1732 | * has been installed, we are certain that address learning for this |
1733 | * particular address has been turned off, so the dynamic entry either |
1734 | * is in the FDB at an index smaller than the static one, or isn't (it |
1735 | * can also be at a larger index, but in that case it is inactive |
1736 | * because the static FDB entry will match first, and the dynamic one |
1737 | * will eventually age out). Search for a dynamically learned address |
1738 | * prior to our static one and invalidate it. |
1739 | */ |
1740 | tmp = l2_lookup; |
1741 | |
1742 | rc = sja1105_dynamic_config_read(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
1743 | SJA1105_SEARCH, entry: &tmp); |
1744 | if (rc < 0) { |
1745 | dev_err(ds->dev, |
1746 | "port %d failed to read back entry for %pM vid %d: %pe\n" , |
1747 | port, addr, vid, ERR_PTR(rc)); |
1748 | return rc; |
1749 | } |
1750 | |
1751 | if (tmp.index < l2_lookup.index) { |
1752 | rc = sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
1753 | index: tmp.index, NULL, keep: false); |
1754 | if (rc < 0) |
1755 | return rc; |
1756 | } |
1757 | |
1758 | return sja1105_static_fdb_change(priv, port, requested: &l2_lookup, keep: true); |
1759 | } |
1760 | |
1761 | int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port, |
1762 | const unsigned char *addr, u16 vid) |
1763 | { |
1764 | struct sja1105_l2_lookup_entry l2_lookup = {0}; |
1765 | struct sja1105_private *priv = ds->priv; |
1766 | bool keep; |
1767 | int rc; |
1768 | |
1769 | l2_lookup.macaddr = ether_addr_to_u64(addr); |
1770 | l2_lookup.vlanid = vid; |
1771 | l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0); |
1772 | l2_lookup.mask_vlanid = VLAN_VID_MASK; |
1773 | l2_lookup.destports = BIT(port); |
1774 | |
1775 | rc = sja1105_dynamic_config_read(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
1776 | SJA1105_SEARCH, entry: &l2_lookup); |
1777 | if (rc < 0) |
1778 | return 0; |
1779 | |
1780 | l2_lookup.destports &= ~BIT(port); |
1781 | |
1782 | /* Decide whether we remove just this port from the FDB entry, |
1783 | * or if we remove it completely. |
1784 | */ |
1785 | if (l2_lookup.destports) |
1786 | keep = true; |
1787 | else |
1788 | keep = false; |
1789 | |
1790 | rc = sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
1791 | index: l2_lookup.index, entry: &l2_lookup, keep); |
1792 | if (rc < 0) |
1793 | return rc; |
1794 | |
1795 | return sja1105_static_fdb_change(priv, port, requested: &l2_lookup, keep); |
1796 | } |
1797 | |
1798 | static int sja1105_fdb_add(struct dsa_switch *ds, int port, |
1799 | const unsigned char *addr, u16 vid, |
1800 | struct dsa_db db) |
1801 | { |
1802 | struct sja1105_private *priv = ds->priv; |
1803 | int rc; |
1804 | |
1805 | if (!vid) { |
1806 | switch (db.type) { |
1807 | case DSA_DB_PORT: |
1808 | vid = dsa_tag_8021q_standalone_vid(dp: db.dp); |
1809 | break; |
1810 | case DSA_DB_BRIDGE: |
1811 | vid = dsa_tag_8021q_bridge_vid(bridge_num: db.bridge.num); |
1812 | break; |
1813 | default: |
1814 | return -EOPNOTSUPP; |
1815 | } |
1816 | } |
1817 | |
1818 | mutex_lock(&priv->fdb_lock); |
1819 | rc = priv->info->fdb_add_cmd(ds, port, addr, vid); |
1820 | mutex_unlock(lock: &priv->fdb_lock); |
1821 | |
1822 | return rc; |
1823 | } |
1824 | |
1825 | static int __sja1105_fdb_del(struct dsa_switch *ds, int port, |
1826 | const unsigned char *addr, u16 vid, |
1827 | struct dsa_db db) |
1828 | { |
1829 | struct sja1105_private *priv = ds->priv; |
1830 | |
1831 | if (!vid) { |
1832 | switch (db.type) { |
1833 | case DSA_DB_PORT: |
1834 | vid = dsa_tag_8021q_standalone_vid(dp: db.dp); |
1835 | break; |
1836 | case DSA_DB_BRIDGE: |
1837 | vid = dsa_tag_8021q_bridge_vid(bridge_num: db.bridge.num); |
1838 | break; |
1839 | default: |
1840 | return -EOPNOTSUPP; |
1841 | } |
1842 | } |
1843 | |
1844 | return priv->info->fdb_del_cmd(ds, port, addr, vid); |
1845 | } |
1846 | |
1847 | static int sja1105_fdb_del(struct dsa_switch *ds, int port, |
1848 | const unsigned char *addr, u16 vid, |
1849 | struct dsa_db db) |
1850 | { |
1851 | struct sja1105_private *priv = ds->priv; |
1852 | int rc; |
1853 | |
1854 | mutex_lock(&priv->fdb_lock); |
1855 | rc = __sja1105_fdb_del(ds, port, addr, vid, db); |
1856 | mutex_unlock(lock: &priv->fdb_lock); |
1857 | |
1858 | return rc; |
1859 | } |
1860 | |
1861 | static int sja1105_fdb_dump(struct dsa_switch *ds, int port, |
1862 | dsa_fdb_dump_cb_t *cb, void *data) |
1863 | { |
1864 | struct sja1105_private *priv = ds->priv; |
1865 | struct device *dev = ds->dev; |
1866 | int i; |
1867 | |
1868 | for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) { |
1869 | struct sja1105_l2_lookup_entry l2_lookup = {0}; |
1870 | u8 macaddr[ETH_ALEN]; |
1871 | int rc; |
1872 | |
1873 | rc = sja1105_dynamic_config_read(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
1874 | index: i, entry: &l2_lookup); |
1875 | /* No fdb entry at i, not an issue */ |
1876 | if (rc == -ENOENT) |
1877 | continue; |
1878 | if (rc) { |
1879 | dev_err(dev, "Failed to dump FDB: %d\n" , rc); |
1880 | return rc; |
1881 | } |
1882 | |
1883 | /* FDB dump callback is per port. This means we have to |
1884 | * disregard a valid entry if it's not for this port, even if |
1885 | * only to revisit it later. This is inefficient because the |
1886 | * 1024-sized FDB table needs to be traversed 4 times through |
1887 | * SPI during a 'bridge fdb show' command. |
1888 | */ |
1889 | if (!(l2_lookup.destports & BIT(port))) |
1890 | continue; |
1891 | |
1892 | u64_to_ether_addr(u: l2_lookup.macaddr, addr: macaddr); |
1893 | |
1894 | /* Hardware FDB is shared for fdb and mdb, "bridge fdb show" |
1895 | * only wants to see unicast |
1896 | */ |
1897 | if (is_multicast_ether_addr(addr: macaddr)) |
1898 | continue; |
1899 | |
1900 | /* We need to hide the dsa_8021q VLANs from the user. */ |
1901 | if (vid_is_dsa_8021q(vid: l2_lookup.vlanid)) |
1902 | l2_lookup.vlanid = 0; |
1903 | rc = cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data); |
1904 | if (rc) |
1905 | return rc; |
1906 | } |
1907 | return 0; |
1908 | } |
1909 | |
1910 | static void sja1105_fast_age(struct dsa_switch *ds, int port) |
1911 | { |
1912 | struct dsa_port *dp = dsa_to_port(ds, p: port); |
1913 | struct sja1105_private *priv = ds->priv; |
1914 | struct dsa_db db = { |
1915 | .type = DSA_DB_BRIDGE, |
1916 | .bridge = { |
1917 | .dev = dsa_port_bridge_dev_get(dp), |
1918 | .num = dsa_port_bridge_num_get(dp), |
1919 | }, |
1920 | }; |
1921 | int i; |
1922 | |
1923 | mutex_lock(&priv->fdb_lock); |
1924 | |
1925 | for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) { |
1926 | struct sja1105_l2_lookup_entry l2_lookup = {0}; |
1927 | u8 macaddr[ETH_ALEN]; |
1928 | int rc; |
1929 | |
1930 | rc = sja1105_dynamic_config_read(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
1931 | index: i, entry: &l2_lookup); |
1932 | /* No fdb entry at i, not an issue */ |
1933 | if (rc == -ENOENT) |
1934 | continue; |
1935 | if (rc) { |
1936 | dev_err(ds->dev, "Failed to read FDB: %pe\n" , |
1937 | ERR_PTR(rc)); |
1938 | break; |
1939 | } |
1940 | |
1941 | if (!(l2_lookup.destports & BIT(port))) |
1942 | continue; |
1943 | |
1944 | /* Don't delete static FDB entries */ |
1945 | if (l2_lookup.lockeds) |
1946 | continue; |
1947 | |
1948 | u64_to_ether_addr(u: l2_lookup.macaddr, addr: macaddr); |
1949 | |
1950 | rc = __sja1105_fdb_del(ds, port, addr: macaddr, vid: l2_lookup.vlanid, db); |
1951 | if (rc) { |
1952 | dev_err(ds->dev, |
1953 | "Failed to delete FDB entry %pM vid %lld: %pe\n" , |
1954 | macaddr, l2_lookup.vlanid, ERR_PTR(rc)); |
1955 | break; |
1956 | } |
1957 | } |
1958 | |
1959 | mutex_unlock(lock: &priv->fdb_lock); |
1960 | } |
1961 | |
1962 | static int sja1105_mdb_add(struct dsa_switch *ds, int port, |
1963 | const struct switchdev_obj_port_mdb *mdb, |
1964 | struct dsa_db db) |
1965 | { |
1966 | return sja1105_fdb_add(ds, port, addr: mdb->addr, vid: mdb->vid, db); |
1967 | } |
1968 | |
1969 | static int sja1105_mdb_del(struct dsa_switch *ds, int port, |
1970 | const struct switchdev_obj_port_mdb *mdb, |
1971 | struct dsa_db db) |
1972 | { |
1973 | return sja1105_fdb_del(ds, port, addr: mdb->addr, vid: mdb->vid, db); |
1974 | } |
1975 | |
1976 | /* Common function for unicast and broadcast flood configuration. |
1977 | * Flooding is configured between each {ingress, egress} port pair, and since |
1978 | * the bridge's semantics are those of "egress flooding", it means we must |
1979 | * enable flooding towards this port from all ingress ports that are in the |
1980 | * same forwarding domain. |
1981 | */ |
1982 | static int sja1105_manage_flood_domains(struct sja1105_private *priv) |
1983 | { |
1984 | struct sja1105_l2_forwarding_entry *l2_fwd; |
1985 | struct dsa_switch *ds = priv->ds; |
1986 | int from, to, rc; |
1987 | |
1988 | l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries; |
1989 | |
1990 | for (from = 0; from < ds->num_ports; from++) { |
1991 | u64 fl_domain = 0, bc_domain = 0; |
1992 | |
1993 | for (to = 0; to < priv->ds->num_ports; to++) { |
1994 | if (!sja1105_can_forward(l2_fwd, from, to)) |
1995 | continue; |
1996 | |
1997 | if (priv->ucast_egress_floods & BIT(to)) |
1998 | fl_domain |= BIT(to); |
1999 | if (priv->bcast_egress_floods & BIT(to)) |
2000 | bc_domain |= BIT(to); |
2001 | } |
2002 | |
2003 | /* Nothing changed, nothing to do */ |
2004 | if (l2_fwd[from].fl_domain == fl_domain && |
2005 | l2_fwd[from].bc_domain == bc_domain) |
2006 | continue; |
2007 | |
2008 | l2_fwd[from].fl_domain = fl_domain; |
2009 | l2_fwd[from].bc_domain = bc_domain; |
2010 | |
2011 | rc = sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_L2_FORWARDING, |
2012 | index: from, entry: &l2_fwd[from], keep: true); |
2013 | if (rc < 0) |
2014 | return rc; |
2015 | } |
2016 | |
2017 | return 0; |
2018 | } |
2019 | |
2020 | static int sja1105_bridge_member(struct dsa_switch *ds, int port, |
2021 | struct dsa_bridge bridge, bool member) |
2022 | { |
2023 | struct sja1105_l2_forwarding_entry *l2_fwd; |
2024 | struct sja1105_private *priv = ds->priv; |
2025 | int i, rc; |
2026 | |
2027 | l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries; |
2028 | |
2029 | for (i = 0; i < ds->num_ports; i++) { |
2030 | /* Add this port to the forwarding matrix of the |
2031 | * other ports in the same bridge, and viceversa. |
2032 | */ |
2033 | if (!dsa_is_user_port(ds, p: i)) |
2034 | continue; |
2035 | /* For the ports already under the bridge, only one thing needs |
2036 | * to be done, and that is to add this port to their |
2037 | * reachability domain. So we can perform the SPI write for |
2038 | * them immediately. However, for this port itself (the one |
2039 | * that is new to the bridge), we need to add all other ports |
2040 | * to its reachability domain. So we do that incrementally in |
2041 | * this loop, and perform the SPI write only at the end, once |
2042 | * the domain contains all other bridge ports. |
2043 | */ |
2044 | if (i == port) |
2045 | continue; |
2046 | if (!dsa_port_offloads_bridge(dp: dsa_to_port(ds, p: i), bridge: &bridge)) |
2047 | continue; |
2048 | sja1105_port_allow_traffic(l2_fwd, from: i, to: port, allow: member); |
2049 | sja1105_port_allow_traffic(l2_fwd, from: port, to: i, allow: member); |
2050 | |
2051 | rc = sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_L2_FORWARDING, |
2052 | index: i, entry: &l2_fwd[i], keep: true); |
2053 | if (rc < 0) |
2054 | return rc; |
2055 | } |
2056 | |
2057 | rc = sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_L2_FORWARDING, |
2058 | index: port, entry: &l2_fwd[port], keep: true); |
2059 | if (rc) |
2060 | return rc; |
2061 | |
2062 | rc = sja1105_commit_pvid(ds, port); |
2063 | if (rc) |
2064 | return rc; |
2065 | |
2066 | return sja1105_manage_flood_domains(priv); |
2067 | } |
2068 | |
2069 | static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port, |
2070 | u8 state) |
2071 | { |
2072 | struct dsa_port *dp = dsa_to_port(ds, p: port); |
2073 | struct sja1105_private *priv = ds->priv; |
2074 | struct sja1105_mac_config_entry *mac; |
2075 | |
2076 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; |
2077 | |
2078 | switch (state) { |
2079 | case BR_STATE_DISABLED: |
2080 | case BR_STATE_BLOCKING: |
2081 | /* From UM10944 description of DRPDTAG (why put this there?): |
2082 | * "Management traffic flows to the port regardless of the state |
2083 | * of the INGRESS flag". So BPDUs are still be allowed to pass. |
2084 | * At the moment no difference between DISABLED and BLOCKING. |
2085 | */ |
2086 | mac[port].ingress = false; |
2087 | mac[port].egress = false; |
2088 | mac[port].dyn_learn = false; |
2089 | break; |
2090 | case BR_STATE_LISTENING: |
2091 | mac[port].ingress = true; |
2092 | mac[port].egress = false; |
2093 | mac[port].dyn_learn = false; |
2094 | break; |
2095 | case BR_STATE_LEARNING: |
2096 | mac[port].ingress = true; |
2097 | mac[port].egress = false; |
2098 | mac[port].dyn_learn = dp->learning; |
2099 | break; |
2100 | case BR_STATE_FORWARDING: |
2101 | mac[port].ingress = true; |
2102 | mac[port].egress = true; |
2103 | mac[port].dyn_learn = dp->learning; |
2104 | break; |
2105 | default: |
2106 | dev_err(ds->dev, "invalid STP state: %d\n" , state); |
2107 | return; |
2108 | } |
2109 | |
2110 | sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_MAC_CONFIG, index: port, |
2111 | entry: &mac[port], keep: true); |
2112 | } |
2113 | |
2114 | static int sja1105_bridge_join(struct dsa_switch *ds, int port, |
2115 | struct dsa_bridge bridge, |
2116 | bool *tx_fwd_offload, |
2117 | struct netlink_ext_ack *extack) |
2118 | { |
2119 | int rc; |
2120 | |
2121 | rc = sja1105_bridge_member(ds, port, bridge, member: true); |
2122 | if (rc) |
2123 | return rc; |
2124 | |
2125 | rc = dsa_tag_8021q_bridge_join(ds, port, bridge); |
2126 | if (rc) { |
2127 | sja1105_bridge_member(ds, port, bridge, member: false); |
2128 | return rc; |
2129 | } |
2130 | |
2131 | *tx_fwd_offload = true; |
2132 | |
2133 | return 0; |
2134 | } |
2135 | |
2136 | static void sja1105_bridge_leave(struct dsa_switch *ds, int port, |
2137 | struct dsa_bridge bridge) |
2138 | { |
2139 | dsa_tag_8021q_bridge_leave(ds, port, bridge); |
2140 | sja1105_bridge_member(ds, port, bridge, member: false); |
2141 | } |
2142 | |
2143 | /* Port 0 (the uC port) does not have CBS shapers */ |
2144 | #define SJA1110_FIXED_CBS(port, prio) ((((port) - 1) * SJA1105_NUM_TC) + (prio)) |
2145 | |
2146 | static int sja1105_find_cbs_shaper(struct sja1105_private *priv, |
2147 | int port, int prio) |
2148 | { |
2149 | int i; |
2150 | |
2151 | if (priv->info->fixed_cbs_mapping) { |
2152 | i = SJA1110_FIXED_CBS(port, prio); |
2153 | if (i >= 0 && i < priv->info->num_cbs_shapers) |
2154 | return i; |
2155 | |
2156 | return -1; |
2157 | } |
2158 | |
2159 | for (i = 0; i < priv->info->num_cbs_shapers; i++) |
2160 | if (priv->cbs[i].port == port && priv->cbs[i].prio == prio) |
2161 | return i; |
2162 | |
2163 | return -1; |
2164 | } |
2165 | |
2166 | static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv) |
2167 | { |
2168 | int i; |
2169 | |
2170 | if (priv->info->fixed_cbs_mapping) |
2171 | return -1; |
2172 | |
2173 | for (i = 0; i < priv->info->num_cbs_shapers; i++) |
2174 | if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope) |
2175 | return i; |
2176 | |
2177 | return -1; |
2178 | } |
2179 | |
2180 | static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port, |
2181 | int prio) |
2182 | { |
2183 | int i; |
2184 | |
2185 | for (i = 0; i < priv->info->num_cbs_shapers; i++) { |
2186 | struct sja1105_cbs_entry *cbs = &priv->cbs[i]; |
2187 | |
2188 | if (cbs->port == port && cbs->prio == prio) { |
2189 | memset(cbs, 0, sizeof(*cbs)); |
2190 | return sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_CBS, |
2191 | index: i, entry: cbs, keep: true); |
2192 | } |
2193 | } |
2194 | |
2195 | return 0; |
2196 | } |
2197 | |
2198 | static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port, |
2199 | struct tc_cbs_qopt_offload *offload) |
2200 | { |
2201 | struct sja1105_private *priv = ds->priv; |
2202 | struct sja1105_cbs_entry *cbs; |
2203 | s64 port_transmit_rate_kbps; |
2204 | int index; |
2205 | |
2206 | if (!offload->enable) |
2207 | return sja1105_delete_cbs_shaper(priv, port, prio: offload->queue); |
2208 | |
2209 | /* The user may be replacing an existing shaper */ |
2210 | index = sja1105_find_cbs_shaper(priv, port, prio: offload->queue); |
2211 | if (index < 0) { |
2212 | /* That isn't the case - see if we can allocate a new one */ |
2213 | index = sja1105_find_unused_cbs_shaper(priv); |
2214 | if (index < 0) |
2215 | return -ENOSPC; |
2216 | } |
2217 | |
2218 | cbs = &priv->cbs[index]; |
2219 | cbs->port = port; |
2220 | cbs->prio = offload->queue; |
2221 | /* locredit and sendslope are negative by definition. In hardware, |
2222 | * positive values must be provided, and the negative sign is implicit. |
2223 | */ |
2224 | cbs->credit_hi = offload->hicredit; |
2225 | cbs->credit_lo = abs(offload->locredit); |
2226 | /* User space is in kbits/sec, while the hardware in bytes/sec times |
2227 | * link speed. Since the given offload->sendslope is good only for the |
2228 | * current link speed anyway, and user space is likely to reprogram it |
2229 | * when that changes, don't even bother to track the port's link speed, |
2230 | * but deduce the port transmit rate from idleslope - sendslope. |
2231 | */ |
2232 | port_transmit_rate_kbps = offload->idleslope - offload->sendslope; |
2233 | cbs->idle_slope = div_s64(dividend: offload->idleslope * BYTES_PER_KBIT, |
2234 | divisor: port_transmit_rate_kbps); |
2235 | cbs->send_slope = div_s64(abs(offload->sendslope * BYTES_PER_KBIT), |
2236 | divisor: port_transmit_rate_kbps); |
2237 | /* Convert the negative values from 64-bit 2's complement |
2238 | * to 32-bit 2's complement (for the case of 0x80000000 whose |
2239 | * negative is still negative). |
2240 | */ |
2241 | cbs->credit_lo &= GENMASK_ULL(31, 0); |
2242 | cbs->send_slope &= GENMASK_ULL(31, 0); |
2243 | |
2244 | return sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_CBS, index, entry: cbs, |
2245 | keep: true); |
2246 | } |
2247 | |
2248 | static int sja1105_reload_cbs(struct sja1105_private *priv) |
2249 | { |
2250 | int rc = 0, i; |
2251 | |
2252 | /* The credit based shapers are only allocated if |
2253 | * CONFIG_NET_SCH_CBS is enabled. |
2254 | */ |
2255 | if (!priv->cbs) |
2256 | return 0; |
2257 | |
2258 | for (i = 0; i < priv->info->num_cbs_shapers; i++) { |
2259 | struct sja1105_cbs_entry *cbs = &priv->cbs[i]; |
2260 | |
2261 | if (!cbs->idle_slope && !cbs->send_slope) |
2262 | continue; |
2263 | |
2264 | rc = sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_CBS, index: i, entry: cbs, |
2265 | keep: true); |
2266 | if (rc) |
2267 | break; |
2268 | } |
2269 | |
2270 | return rc; |
2271 | } |
2272 | |
2273 | static const char * const sja1105_reset_reasons[] = { |
2274 | [SJA1105_VLAN_FILTERING] = "VLAN filtering" , |
2275 | [SJA1105_AGEING_TIME] = "Ageing time" , |
2276 | [SJA1105_SCHEDULING] = "Time-aware scheduling" , |
2277 | [SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing" , |
2278 | [SJA1105_VIRTUAL_LINKS] = "Virtual links" , |
2279 | }; |
2280 | |
2281 | /* For situations where we need to change a setting at runtime that is only |
2282 | * available through the static configuration, resetting the switch in order |
2283 | * to upload the new static config is unavoidable. Back up the settings we |
2284 | * modify at runtime (currently only MAC) and restore them after uploading, |
2285 | * such that this operation is relatively seamless. |
2286 | */ |
2287 | int sja1105_static_config_reload(struct sja1105_private *priv, |
2288 | enum sja1105_reset_reason reason) |
2289 | { |
2290 | struct ptp_system_timestamp ptp_sts_before; |
2291 | struct ptp_system_timestamp ptp_sts_after; |
2292 | int speed_mbps[SJA1105_MAX_NUM_PORTS]; |
2293 | u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0}; |
2294 | struct sja1105_mac_config_entry *mac; |
2295 | struct dsa_switch *ds = priv->ds; |
2296 | s64 t1, t2, t3, t4; |
2297 | s64 t12, t34; |
2298 | int rc, i; |
2299 | s64 now; |
2300 | |
2301 | mutex_lock(&priv->fdb_lock); |
2302 | mutex_lock(&priv->mgmt_lock); |
2303 | |
2304 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; |
2305 | |
2306 | /* Back up the dynamic link speed changed by sja1105_adjust_port_config |
2307 | * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the |
2308 | * switch wants to see in the static config in order to allow us to |
2309 | * change it through the dynamic interface later. |
2310 | */ |
2311 | for (i = 0; i < ds->num_ports; i++) { |
2312 | speed_mbps[i] = sja1105_port_speed_to_ethtool(priv, |
2313 | speed: mac[i].speed); |
2314 | mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO]; |
2315 | |
2316 | if (priv->xpcs[i]) |
2317 | bmcr[i] = mdiobus_c45_read(bus: priv->mdio_pcs, addr: i, |
2318 | MDIO_MMD_VEND2, MDIO_CTRL1); |
2319 | } |
2320 | |
2321 | /* No PTP operations can run right now */ |
2322 | mutex_lock(&priv->ptp_data.lock); |
2323 | |
2324 | rc = __sja1105_ptp_gettimex(ds, ns: &now, sts: &ptp_sts_before); |
2325 | if (rc < 0) { |
2326 | mutex_unlock(lock: &priv->ptp_data.lock); |
2327 | goto out; |
2328 | } |
2329 | |
2330 | /* Reset switch and send updated static configuration */ |
2331 | rc = sja1105_static_config_upload(priv); |
2332 | if (rc < 0) { |
2333 | mutex_unlock(lock: &priv->ptp_data.lock); |
2334 | goto out; |
2335 | } |
2336 | |
2337 | rc = __sja1105_ptp_settime(ds, ns: 0, ptp_sts: &ptp_sts_after); |
2338 | if (rc < 0) { |
2339 | mutex_unlock(lock: &priv->ptp_data.lock); |
2340 | goto out; |
2341 | } |
2342 | |
2343 | t1 = timespec64_to_ns(ts: &ptp_sts_before.pre_ts); |
2344 | t2 = timespec64_to_ns(ts: &ptp_sts_before.post_ts); |
2345 | t3 = timespec64_to_ns(ts: &ptp_sts_after.pre_ts); |
2346 | t4 = timespec64_to_ns(ts: &ptp_sts_after.post_ts); |
2347 | /* Mid point, corresponds to pre-reset PTPCLKVAL */ |
2348 | t12 = t1 + (t2 - t1) / 2; |
2349 | /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */ |
2350 | t34 = t3 + (t4 - t3) / 2; |
2351 | /* Advance PTPCLKVAL by the time it took since its readout */ |
2352 | now += (t34 - t12); |
2353 | |
2354 | __sja1105_ptp_adjtime(ds, delta: now); |
2355 | |
2356 | mutex_unlock(lock: &priv->ptp_data.lock); |
2357 | |
2358 | dev_info(priv->ds->dev, |
2359 | "Reset switch and programmed static config. Reason: %s\n" , |
2360 | sja1105_reset_reasons[reason]); |
2361 | |
2362 | /* Configure the CGU (PLLs) for MII and RMII PHYs. |
2363 | * For these interfaces there is no dynamic configuration |
2364 | * needed, since PLLs have same settings at all speeds. |
2365 | */ |
2366 | if (priv->info->clocking_setup) { |
2367 | rc = priv->info->clocking_setup(priv); |
2368 | if (rc < 0) |
2369 | goto out; |
2370 | } |
2371 | |
2372 | for (i = 0; i < ds->num_ports; i++) { |
2373 | struct dw_xpcs *xpcs = priv->xpcs[i]; |
2374 | unsigned int neg_mode; |
2375 | |
2376 | rc = sja1105_adjust_port_config(priv, port: i, speed_mbps: speed_mbps[i]); |
2377 | if (rc < 0) |
2378 | goto out; |
2379 | |
2380 | if (!xpcs) |
2381 | continue; |
2382 | |
2383 | if (bmcr[i] & BMCR_ANENABLE) |
2384 | neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; |
2385 | else |
2386 | neg_mode = PHYLINK_PCS_NEG_OUTBAND; |
2387 | |
2388 | rc = xpcs_do_config(xpcs, interface: priv->phy_mode[i], NULL, neg_mode); |
2389 | if (rc < 0) |
2390 | goto out; |
2391 | |
2392 | if (neg_mode == PHYLINK_PCS_NEG_OUTBAND) { |
2393 | int speed = SPEED_UNKNOWN; |
2394 | |
2395 | if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX) |
2396 | speed = SPEED_2500; |
2397 | else if (bmcr[i] & BMCR_SPEED1000) |
2398 | speed = SPEED_1000; |
2399 | else if (bmcr[i] & BMCR_SPEED100) |
2400 | speed = SPEED_100; |
2401 | else |
2402 | speed = SPEED_10; |
2403 | |
2404 | xpcs_link_up(pcs: &xpcs->pcs, neg_mode, interface: priv->phy_mode[i], |
2405 | speed, DUPLEX_FULL); |
2406 | } |
2407 | } |
2408 | |
2409 | rc = sja1105_reload_cbs(priv); |
2410 | if (rc < 0) |
2411 | goto out; |
2412 | out: |
2413 | mutex_unlock(lock: &priv->mgmt_lock); |
2414 | mutex_unlock(lock: &priv->fdb_lock); |
2415 | |
2416 | return rc; |
2417 | } |
2418 | |
2419 | static enum dsa_tag_protocol |
2420 | sja1105_get_tag_protocol(struct dsa_switch *ds, int port, |
2421 | enum dsa_tag_protocol mp) |
2422 | { |
2423 | struct sja1105_private *priv = ds->priv; |
2424 | |
2425 | return priv->info->tag_proto; |
2426 | } |
2427 | |
2428 | /* The TPID setting belongs to the General Parameters table, |
2429 | * which can only be partially reconfigured at runtime (and not the TPID). |
2430 | * So a switch reset is required. |
2431 | */ |
2432 | int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, |
2433 | struct netlink_ext_ack *extack) |
2434 | { |
2435 | struct sja1105_general_params_entry *general_params; |
2436 | struct sja1105_private *priv = ds->priv; |
2437 | struct sja1105_table *table; |
2438 | struct sja1105_rule *rule; |
2439 | u16 tpid, tpid2; |
2440 | int rc; |
2441 | |
2442 | list_for_each_entry(rule, &priv->flow_block.rules, list) { |
2443 | if (rule->type == SJA1105_RULE_VL) { |
2444 | NL_SET_ERR_MSG_MOD(extack, |
2445 | "Cannot change VLAN filtering with active VL rules" ); |
2446 | return -EBUSY; |
2447 | } |
2448 | } |
2449 | |
2450 | if (enabled) { |
2451 | /* Enable VLAN filtering. */ |
2452 | tpid = ETH_P_8021Q; |
2453 | tpid2 = ETH_P_8021AD; |
2454 | } else { |
2455 | /* Disable VLAN filtering. */ |
2456 | tpid = ETH_P_SJA1105; |
2457 | tpid2 = ETH_P_SJA1105; |
2458 | } |
2459 | |
2460 | table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; |
2461 | general_params = table->entries; |
2462 | /* EtherType used to identify inner tagged (C-tag) VLAN traffic */ |
2463 | general_params->tpid = tpid; |
2464 | /* EtherType used to identify outer tagged (S-tag) VLAN traffic */ |
2465 | general_params->tpid2 = tpid2; |
2466 | |
2467 | for (port = 0; port < ds->num_ports; port++) { |
2468 | if (dsa_is_unused_port(ds, p: port)) |
2469 | continue; |
2470 | |
2471 | rc = sja1105_commit_pvid(ds, port); |
2472 | if (rc) |
2473 | return rc; |
2474 | } |
2475 | |
2476 | rc = sja1105_static_config_reload(priv, reason: SJA1105_VLAN_FILTERING); |
2477 | if (rc) |
2478 | NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype" ); |
2479 | |
2480 | return rc; |
2481 | } |
2482 | |
2483 | static int sja1105_vlan_add(struct sja1105_private *priv, int port, u16 vid, |
2484 | u16 flags, bool allowed_ingress) |
2485 | { |
2486 | struct sja1105_vlan_lookup_entry *vlan; |
2487 | struct sja1105_table *table; |
2488 | int match, rc; |
2489 | |
2490 | table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP]; |
2491 | |
2492 | match = sja1105_is_vlan_configured(priv, vid); |
2493 | if (match < 0) { |
2494 | rc = sja1105_table_resize(table, new_count: table->entry_count + 1); |
2495 | if (rc) |
2496 | return rc; |
2497 | match = table->entry_count - 1; |
2498 | } |
2499 | |
2500 | /* Assign pointer after the resize (it's new memory) */ |
2501 | vlan = table->entries; |
2502 | |
2503 | vlan[match].type_entry = SJA1110_VLAN_D_TAG; |
2504 | vlan[match].vlanid = vid; |
2505 | vlan[match].vlan_bc |= BIT(port); |
2506 | |
2507 | if (allowed_ingress) |
2508 | vlan[match].vmemb_port |= BIT(port); |
2509 | else |
2510 | vlan[match].vmemb_port &= ~BIT(port); |
2511 | |
2512 | if (flags & BRIDGE_VLAN_INFO_UNTAGGED) |
2513 | vlan[match].tag_port &= ~BIT(port); |
2514 | else |
2515 | vlan[match].tag_port |= BIT(port); |
2516 | |
2517 | return sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_VLAN_LOOKUP, index: vid, |
2518 | entry: &vlan[match], keep: true); |
2519 | } |
2520 | |
2521 | static int sja1105_vlan_del(struct sja1105_private *priv, int port, u16 vid) |
2522 | { |
2523 | struct sja1105_vlan_lookup_entry *vlan; |
2524 | struct sja1105_table *table; |
2525 | bool keep = true; |
2526 | int match, rc; |
2527 | |
2528 | table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP]; |
2529 | |
2530 | match = sja1105_is_vlan_configured(priv, vid); |
2531 | /* Can't delete a missing entry. */ |
2532 | if (match < 0) |
2533 | return 0; |
2534 | |
2535 | /* Assign pointer after the resize (it's new memory) */ |
2536 | vlan = table->entries; |
2537 | |
2538 | vlan[match].vlanid = vid; |
2539 | vlan[match].vlan_bc &= ~BIT(port); |
2540 | vlan[match].vmemb_port &= ~BIT(port); |
2541 | /* Also unset tag_port, just so we don't have a confusing bitmap |
2542 | * (no practical purpose). |
2543 | */ |
2544 | vlan[match].tag_port &= ~BIT(port); |
2545 | |
2546 | /* If there's no port left as member of this VLAN, |
2547 | * it's time for it to go. |
2548 | */ |
2549 | if (!vlan[match].vmemb_port) |
2550 | keep = false; |
2551 | |
2552 | rc = sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_VLAN_LOOKUP, index: vid, |
2553 | entry: &vlan[match], keep); |
2554 | if (rc < 0) |
2555 | return rc; |
2556 | |
2557 | if (!keep) |
2558 | return sja1105_table_delete_entry(table, i: match); |
2559 | |
2560 | return 0; |
2561 | } |
2562 | |
2563 | static int sja1105_bridge_vlan_add(struct dsa_switch *ds, int port, |
2564 | const struct switchdev_obj_port_vlan *vlan, |
2565 | struct netlink_ext_ack *extack) |
2566 | { |
2567 | struct sja1105_private *priv = ds->priv; |
2568 | u16 flags = vlan->flags; |
2569 | int rc; |
2570 | |
2571 | /* Be sure to deny alterations to the configuration done by tag_8021q. |
2572 | */ |
2573 | if (vid_is_dsa_8021q(vid: vlan->vid)) { |
2574 | NL_SET_ERR_MSG_MOD(extack, |
2575 | "Range 3072-4095 reserved for dsa_8021q operation" ); |
2576 | return -EBUSY; |
2577 | } |
2578 | |
2579 | /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */ |
2580 | if (dsa_is_cpu_port(ds, p: port) || dsa_is_dsa_port(ds, p: port)) |
2581 | flags = 0; |
2582 | |
2583 | rc = sja1105_vlan_add(priv, port, vid: vlan->vid, flags, allowed_ingress: true); |
2584 | if (rc) |
2585 | return rc; |
2586 | |
2587 | if (vlan->flags & BRIDGE_VLAN_INFO_PVID) |
2588 | priv->bridge_pvid[port] = vlan->vid; |
2589 | |
2590 | return sja1105_commit_pvid(ds, port); |
2591 | } |
2592 | |
2593 | static int sja1105_bridge_vlan_del(struct dsa_switch *ds, int port, |
2594 | const struct switchdev_obj_port_vlan *vlan) |
2595 | { |
2596 | struct sja1105_private *priv = ds->priv; |
2597 | int rc; |
2598 | |
2599 | rc = sja1105_vlan_del(priv, port, vid: vlan->vid); |
2600 | if (rc) |
2601 | return rc; |
2602 | |
2603 | /* In case the pvid was deleted, make sure that untagged packets will |
2604 | * be dropped. |
2605 | */ |
2606 | return sja1105_commit_pvid(ds, port); |
2607 | } |
2608 | |
2609 | static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, |
2610 | u16 flags) |
2611 | { |
2612 | struct sja1105_private *priv = ds->priv; |
2613 | bool allowed_ingress = true; |
2614 | int rc; |
2615 | |
2616 | /* Prevent attackers from trying to inject a DSA tag from |
2617 | * the outside world. |
2618 | */ |
2619 | if (dsa_is_user_port(ds, p: port)) |
2620 | allowed_ingress = false; |
2621 | |
2622 | rc = sja1105_vlan_add(priv, port, vid, flags, allowed_ingress); |
2623 | if (rc) |
2624 | return rc; |
2625 | |
2626 | if (flags & BRIDGE_VLAN_INFO_PVID) |
2627 | priv->tag_8021q_pvid[port] = vid; |
2628 | |
2629 | return sja1105_commit_pvid(ds, port); |
2630 | } |
2631 | |
2632 | static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) |
2633 | { |
2634 | struct sja1105_private *priv = ds->priv; |
2635 | |
2636 | return sja1105_vlan_del(priv, port, vid); |
2637 | } |
2638 | |
2639 | static int sja1105_prechangeupper(struct dsa_switch *ds, int port, |
2640 | struct netdev_notifier_changeupper_info *info) |
2641 | { |
2642 | struct netlink_ext_ack *extack = info->info.extack; |
2643 | struct net_device *upper = info->upper_dev; |
2644 | struct dsa_switch_tree *dst = ds->dst; |
2645 | struct dsa_port *dp; |
2646 | |
2647 | if (is_vlan_dev(dev: upper)) { |
2648 | NL_SET_ERR_MSG_MOD(extack, "8021q uppers are not supported" ); |
2649 | return -EBUSY; |
2650 | } |
2651 | |
2652 | if (netif_is_bridge_master(dev: upper)) { |
2653 | list_for_each_entry(dp, &dst->ports, list) { |
2654 | struct net_device *br = dsa_port_bridge_dev_get(dp); |
2655 | |
2656 | if (br && br != upper && br_vlan_enabled(dev: br)) { |
2657 | NL_SET_ERR_MSG_MOD(extack, |
2658 | "Only one VLAN-aware bridge is supported" ); |
2659 | return -EBUSY; |
2660 | } |
2661 | } |
2662 | } |
2663 | |
2664 | return 0; |
2665 | } |
2666 | |
2667 | static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot, |
2668 | struct sk_buff *skb, bool takets) |
2669 | { |
2670 | struct sja1105_mgmt_entry mgmt_route = {0}; |
2671 | struct sja1105_private *priv = ds->priv; |
2672 | struct ethhdr *hdr; |
2673 | int timeout = 10; |
2674 | int rc; |
2675 | |
2676 | hdr = eth_hdr(skb); |
2677 | |
2678 | mgmt_route.macaddr = ether_addr_to_u64(addr: hdr->h_dest); |
2679 | mgmt_route.destports = BIT(port); |
2680 | mgmt_route.enfport = 1; |
2681 | mgmt_route.tsreg = 0; |
2682 | mgmt_route.takets = takets; |
2683 | |
2684 | rc = sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_MGMT_ROUTE, |
2685 | index: slot, entry: &mgmt_route, keep: true); |
2686 | if (rc < 0) { |
2687 | kfree_skb(skb); |
2688 | return rc; |
2689 | } |
2690 | |
2691 | /* Transfer skb to the host port. */ |
2692 | dsa_enqueue_skb(skb, dev: dsa_to_port(ds, p: port)->user); |
2693 | |
2694 | /* Wait until the switch has processed the frame */ |
2695 | do { |
2696 | rc = sja1105_dynamic_config_read(priv, blk_idx: BLK_IDX_MGMT_ROUTE, |
2697 | index: slot, entry: &mgmt_route); |
2698 | if (rc < 0) { |
2699 | dev_err_ratelimited(priv->ds->dev, |
2700 | "failed to poll for mgmt route\n" ); |
2701 | continue; |
2702 | } |
2703 | |
2704 | /* UM10944: The ENFPORT flag of the respective entry is |
2705 | * cleared when a match is found. The host can use this |
2706 | * flag as an acknowledgment. |
2707 | */ |
2708 | cpu_relax(); |
2709 | } while (mgmt_route.enfport && --timeout); |
2710 | |
2711 | if (!timeout) { |
2712 | /* Clean up the management route so that a follow-up |
2713 | * frame may not match on it by mistake. |
2714 | * This is only hardware supported on P/Q/R/S - on E/T it is |
2715 | * a no-op and we are silently discarding the -EOPNOTSUPP. |
2716 | */ |
2717 | sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_MGMT_ROUTE, |
2718 | index: slot, entry: &mgmt_route, keep: false); |
2719 | dev_err_ratelimited(priv->ds->dev, "xmit timed out\n" ); |
2720 | } |
2721 | |
2722 | return NETDEV_TX_OK; |
2723 | } |
2724 | |
2725 | #define work_to_xmit_work(w) \ |
2726 | container_of((w), struct sja1105_deferred_xmit_work, work) |
2727 | |
2728 | /* Deferred work is unfortunately necessary because setting up the management |
2729 | * route cannot be done from atomit context (SPI transfer takes a sleepable |
2730 | * lock on the bus) |
2731 | */ |
2732 | static void sja1105_port_deferred_xmit(struct kthread_work *work) |
2733 | { |
2734 | struct sja1105_deferred_xmit_work *xmit_work = work_to_xmit_work(work); |
2735 | struct sk_buff *clone, *skb = xmit_work->skb; |
2736 | struct dsa_switch *ds = xmit_work->dp->ds; |
2737 | struct sja1105_private *priv = ds->priv; |
2738 | int port = xmit_work->dp->index; |
2739 | |
2740 | clone = SJA1105_SKB_CB(skb)->clone; |
2741 | |
2742 | mutex_lock(&priv->mgmt_lock); |
2743 | |
2744 | sja1105_mgmt_xmit(ds, port, slot: 0, skb, takets: !!clone); |
2745 | |
2746 | /* The clone, if there, was made by dsa_skb_tx_timestamp */ |
2747 | if (clone) |
2748 | sja1105_ptp_txtstamp_skb(ds, slot: port, clone); |
2749 | |
2750 | mutex_unlock(lock: &priv->mgmt_lock); |
2751 | |
2752 | kfree(objp: xmit_work); |
2753 | } |
2754 | |
2755 | static int sja1105_connect_tag_protocol(struct dsa_switch *ds, |
2756 | enum dsa_tag_protocol proto) |
2757 | { |
2758 | struct sja1105_private *priv = ds->priv; |
2759 | struct sja1105_tagger_data *tagger_data; |
2760 | |
2761 | if (proto != priv->info->tag_proto) |
2762 | return -EPROTONOSUPPORT; |
2763 | |
2764 | tagger_data = sja1105_tagger_data(ds); |
2765 | tagger_data->xmit_work_fn = sja1105_port_deferred_xmit; |
2766 | tagger_data->meta_tstamp_handler = sja1110_process_meta_tstamp; |
2767 | |
2768 | return 0; |
2769 | } |
2770 | |
2771 | /* The MAXAGE setting belongs to the L2 Forwarding Parameters table, |
2772 | * which cannot be reconfigured at runtime. So a switch reset is required. |
2773 | */ |
2774 | static int sja1105_set_ageing_time(struct dsa_switch *ds, |
2775 | unsigned int ageing_time) |
2776 | { |
2777 | struct sja1105_l2_lookup_params_entry *l2_lookup_params; |
2778 | struct sja1105_private *priv = ds->priv; |
2779 | struct sja1105_table *table; |
2780 | unsigned int maxage; |
2781 | |
2782 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS]; |
2783 | l2_lookup_params = table->entries; |
2784 | |
2785 | maxage = SJA1105_AGEING_TIME_MS(ageing_time); |
2786 | |
2787 | if (l2_lookup_params->maxage == maxage) |
2788 | return 0; |
2789 | |
2790 | l2_lookup_params->maxage = maxage; |
2791 | |
2792 | return sja1105_static_config_reload(priv, reason: SJA1105_AGEING_TIME); |
2793 | } |
2794 | |
2795 | static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu) |
2796 | { |
2797 | struct sja1105_l2_policing_entry *policing; |
2798 | struct sja1105_private *priv = ds->priv; |
2799 | |
2800 | new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN; |
2801 | |
2802 | if (dsa_is_cpu_port(ds, p: port) || dsa_is_dsa_port(ds, p: port)) |
2803 | new_mtu += VLAN_HLEN; |
2804 | |
2805 | policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries; |
2806 | |
2807 | if (policing[port].maxlen == new_mtu) |
2808 | return 0; |
2809 | |
2810 | policing[port].maxlen = new_mtu; |
2811 | |
2812 | return sja1105_static_config_reload(priv, reason: SJA1105_BEST_EFFORT_POLICING); |
2813 | } |
2814 | |
2815 | static int sja1105_get_max_mtu(struct dsa_switch *ds, int port) |
2816 | { |
2817 | return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN; |
2818 | } |
2819 | |
2820 | static int sja1105_port_setup_tc(struct dsa_switch *ds, int port, |
2821 | enum tc_setup_type type, |
2822 | void *type_data) |
2823 | { |
2824 | switch (type) { |
2825 | case TC_SETUP_QDISC_TAPRIO: |
2826 | return sja1105_setup_tc_taprio(ds, port, admin: type_data); |
2827 | case TC_SETUP_QDISC_CBS: |
2828 | return sja1105_setup_tc_cbs(ds, port, offload: type_data); |
2829 | default: |
2830 | return -EOPNOTSUPP; |
2831 | } |
2832 | } |
2833 | |
2834 | /* We have a single mirror (@to) port, but can configure ingress and egress |
2835 | * mirroring on all other (@from) ports. |
2836 | * We need to allow mirroring rules only as long as the @to port is always the |
2837 | * same, and we need to unset the @to port from mirr_port only when there is no |
2838 | * mirroring rule that references it. |
2839 | */ |
2840 | static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to, |
2841 | bool ingress, bool enabled) |
2842 | { |
2843 | struct sja1105_general_params_entry *general_params; |
2844 | struct sja1105_mac_config_entry *mac; |
2845 | struct dsa_switch *ds = priv->ds; |
2846 | struct sja1105_table *table; |
2847 | bool already_enabled; |
2848 | u64 new_mirr_port; |
2849 | int rc; |
2850 | |
2851 | table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; |
2852 | general_params = table->entries; |
2853 | |
2854 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; |
2855 | |
2856 | already_enabled = (general_params->mirr_port != ds->num_ports); |
2857 | if (already_enabled && enabled && general_params->mirr_port != to) { |
2858 | dev_err(priv->ds->dev, |
2859 | "Delete mirroring rules towards port %llu first\n" , |
2860 | general_params->mirr_port); |
2861 | return -EBUSY; |
2862 | } |
2863 | |
2864 | new_mirr_port = to; |
2865 | if (!enabled) { |
2866 | bool keep = false; |
2867 | int port; |
2868 | |
2869 | /* Anybody still referencing mirr_port? */ |
2870 | for (port = 0; port < ds->num_ports; port++) { |
2871 | if (mac[port].ing_mirr || mac[port].egr_mirr) { |
2872 | keep = true; |
2873 | break; |
2874 | } |
2875 | } |
2876 | /* Unset already_enabled for next time */ |
2877 | if (!keep) |
2878 | new_mirr_port = ds->num_ports; |
2879 | } |
2880 | if (new_mirr_port != general_params->mirr_port) { |
2881 | general_params->mirr_port = new_mirr_port; |
2882 | |
2883 | rc = sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_GENERAL_PARAMS, |
2884 | index: 0, entry: general_params, keep: true); |
2885 | if (rc < 0) |
2886 | return rc; |
2887 | } |
2888 | |
2889 | if (ingress) |
2890 | mac[from].ing_mirr = enabled; |
2891 | else |
2892 | mac[from].egr_mirr = enabled; |
2893 | |
2894 | return sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_MAC_CONFIG, index: from, |
2895 | entry: &mac[from], keep: true); |
2896 | } |
2897 | |
2898 | static int sja1105_mirror_add(struct dsa_switch *ds, int port, |
2899 | struct dsa_mall_mirror_tc_entry *mirror, |
2900 | bool ingress, struct netlink_ext_ack *extack) |
2901 | { |
2902 | return sja1105_mirror_apply(priv: ds->priv, from: port, to: mirror->to_local_port, |
2903 | ingress, enabled: true); |
2904 | } |
2905 | |
2906 | static void sja1105_mirror_del(struct dsa_switch *ds, int port, |
2907 | struct dsa_mall_mirror_tc_entry *mirror) |
2908 | { |
2909 | sja1105_mirror_apply(priv: ds->priv, from: port, to: mirror->to_local_port, |
2910 | ingress: mirror->ingress, enabled: false); |
2911 | } |
2912 | |
2913 | static int sja1105_port_policer_add(struct dsa_switch *ds, int port, |
2914 | struct dsa_mall_policer_tc_entry *policer) |
2915 | { |
2916 | struct sja1105_l2_policing_entry *policing; |
2917 | struct sja1105_private *priv = ds->priv; |
2918 | |
2919 | policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries; |
2920 | |
2921 | /* In hardware, every 8 microseconds the credit level is incremented by |
2922 | * the value of RATE bytes divided by 64, up to a maximum of SMAX |
2923 | * bytes. |
2924 | */ |
2925 | policing[port].rate = div_u64(dividend: 512 * policer->rate_bytes_per_sec, |
2926 | divisor: 1000000); |
2927 | policing[port].smax = policer->burst; |
2928 | |
2929 | return sja1105_static_config_reload(priv, reason: SJA1105_BEST_EFFORT_POLICING); |
2930 | } |
2931 | |
2932 | static void sja1105_port_policer_del(struct dsa_switch *ds, int port) |
2933 | { |
2934 | struct sja1105_l2_policing_entry *policing; |
2935 | struct sja1105_private *priv = ds->priv; |
2936 | |
2937 | policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries; |
2938 | |
2939 | policing[port].rate = SJA1105_RATE_MBPS(1000); |
2940 | policing[port].smax = 65535; |
2941 | |
2942 | sja1105_static_config_reload(priv, reason: SJA1105_BEST_EFFORT_POLICING); |
2943 | } |
2944 | |
2945 | static int sja1105_port_set_learning(struct sja1105_private *priv, int port, |
2946 | bool enabled) |
2947 | { |
2948 | struct sja1105_mac_config_entry *mac; |
2949 | |
2950 | mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; |
2951 | |
2952 | mac[port].dyn_learn = enabled; |
2953 | |
2954 | return sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_MAC_CONFIG, index: port, |
2955 | entry: &mac[port], keep: true); |
2956 | } |
2957 | |
2958 | static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to, |
2959 | struct switchdev_brport_flags flags) |
2960 | { |
2961 | if (flags.mask & BR_FLOOD) { |
2962 | if (flags.val & BR_FLOOD) |
2963 | priv->ucast_egress_floods |= BIT(to); |
2964 | else |
2965 | priv->ucast_egress_floods &= ~BIT(to); |
2966 | } |
2967 | |
2968 | if (flags.mask & BR_BCAST_FLOOD) { |
2969 | if (flags.val & BR_BCAST_FLOOD) |
2970 | priv->bcast_egress_floods |= BIT(to); |
2971 | else |
2972 | priv->bcast_egress_floods &= ~BIT(to); |
2973 | } |
2974 | |
2975 | return sja1105_manage_flood_domains(priv); |
2976 | } |
2977 | |
2978 | static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to, |
2979 | struct switchdev_brport_flags flags, |
2980 | struct netlink_ext_ack *extack) |
2981 | { |
2982 | struct sja1105_l2_lookup_entry *l2_lookup; |
2983 | struct sja1105_table *table; |
2984 | int match, rc; |
2985 | |
2986 | mutex_lock(&priv->fdb_lock); |
2987 | |
2988 | table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; |
2989 | l2_lookup = table->entries; |
2990 | |
2991 | for (match = 0; match < table->entry_count; match++) |
2992 | if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST && |
2993 | l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST) |
2994 | break; |
2995 | |
2996 | if (match == table->entry_count) { |
2997 | NL_SET_ERR_MSG_MOD(extack, |
2998 | "Could not find FDB entry for unknown multicast" ); |
2999 | rc = -ENOSPC; |
3000 | goto out; |
3001 | } |
3002 | |
3003 | if (flags.val & BR_MCAST_FLOOD) |
3004 | l2_lookup[match].destports |= BIT(to); |
3005 | else |
3006 | l2_lookup[match].destports &= ~BIT(to); |
3007 | |
3008 | rc = sja1105_dynamic_config_write(priv, blk_idx: BLK_IDX_L2_LOOKUP, |
3009 | index: l2_lookup[match].index, |
3010 | entry: &l2_lookup[match], keep: true); |
3011 | out: |
3012 | mutex_unlock(lock: &priv->fdb_lock); |
3013 | |
3014 | return rc; |
3015 | } |
3016 | |
3017 | static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port, |
3018 | struct switchdev_brport_flags flags, |
3019 | struct netlink_ext_ack *extack) |
3020 | { |
3021 | struct sja1105_private *priv = ds->priv; |
3022 | |
3023 | if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | |
3024 | BR_BCAST_FLOOD)) |
3025 | return -EINVAL; |
3026 | |
3027 | if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) && |
3028 | !priv->info->can_limit_mcast_flood) { |
3029 | bool multicast = !!(flags.val & BR_MCAST_FLOOD); |
3030 | bool unicast = !!(flags.val & BR_FLOOD); |
3031 | |
3032 | if (unicast != multicast) { |
3033 | NL_SET_ERR_MSG_MOD(extack, |
3034 | "This chip cannot configure multicast flooding independently of unicast" ); |
3035 | return -EINVAL; |
3036 | } |
3037 | } |
3038 | |
3039 | return 0; |
3040 | } |
3041 | |
3042 | static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port, |
3043 | struct switchdev_brport_flags flags, |
3044 | struct netlink_ext_ack *extack) |
3045 | { |
3046 | struct sja1105_private *priv = ds->priv; |
3047 | int rc; |
3048 | |
3049 | if (flags.mask & BR_LEARNING) { |
3050 | bool learn_ena = !!(flags.val & BR_LEARNING); |
3051 | |
3052 | rc = sja1105_port_set_learning(priv, port, enabled: learn_ena); |
3053 | if (rc) |
3054 | return rc; |
3055 | } |
3056 | |
3057 | if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) { |
3058 | rc = sja1105_port_ucast_bcast_flood(priv, to: port, flags); |
3059 | if (rc) |
3060 | return rc; |
3061 | } |
3062 | |
3063 | /* For chips that can't offload BR_MCAST_FLOOD independently, there |
3064 | * is nothing to do here, we ensured the configuration is in sync by |
3065 | * offloading BR_FLOOD. |
3066 | */ |
3067 | if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) { |
3068 | rc = sja1105_port_mcast_flood(priv, to: port, flags, |
3069 | extack); |
3070 | if (rc) |
3071 | return rc; |
3072 | } |
3073 | |
3074 | return 0; |
3075 | } |
3076 | |
3077 | /* The programming model for the SJA1105 switch is "all-at-once" via static |
3078 | * configuration tables. Some of these can be dynamically modified at runtime, |
3079 | * but not the xMII mode parameters table. |
3080 | * Furthermode, some PHYs may not have crystals for generating their clocks |
3081 | * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's |
3082 | * ref_clk pin. So port clocking needs to be initialized early, before |
3083 | * connecting to PHYs is attempted, otherwise they won't respond through MDIO. |
3084 | * Setting correct PHY link speed does not matter now. |
3085 | * But dsa_user_phy_setup is called later than sja1105_setup, so the PHY |
3086 | * bindings are not yet parsed by DSA core. We need to parse early so that we |
3087 | * can populate the xMII mode parameters table. |
3088 | */ |
3089 | static int sja1105_setup(struct dsa_switch *ds) |
3090 | { |
3091 | struct sja1105_private *priv = ds->priv; |
3092 | int rc; |
3093 | |
3094 | if (priv->info->disable_microcontroller) { |
3095 | rc = priv->info->disable_microcontroller(priv); |
3096 | if (rc < 0) { |
3097 | dev_err(ds->dev, |
3098 | "Failed to disable microcontroller: %pe\n" , |
3099 | ERR_PTR(rc)); |
3100 | return rc; |
3101 | } |
3102 | } |
3103 | |
3104 | /* Create and send configuration down to device */ |
3105 | rc = sja1105_static_config_load(priv); |
3106 | if (rc < 0) { |
3107 | dev_err(ds->dev, "Failed to load static config: %d\n" , rc); |
3108 | return rc; |
3109 | } |
3110 | |
3111 | /* Configure the CGU (PHY link modes and speeds) */ |
3112 | if (priv->info->clocking_setup) { |
3113 | rc = priv->info->clocking_setup(priv); |
3114 | if (rc < 0) { |
3115 | dev_err(ds->dev, |
3116 | "Failed to configure MII clocking: %pe\n" , |
3117 | ERR_PTR(rc)); |
3118 | goto out_static_config_free; |
3119 | } |
3120 | } |
3121 | |
3122 | sja1105_tas_setup(ds); |
3123 | sja1105_flower_setup(ds); |
3124 | |
3125 | rc = sja1105_ptp_clock_register(ds); |
3126 | if (rc < 0) { |
3127 | dev_err(ds->dev, "Failed to register PTP clock: %d\n" , rc); |
3128 | goto out_flower_teardown; |
3129 | } |
3130 | |
3131 | rc = sja1105_mdiobus_register(ds); |
3132 | if (rc < 0) { |
3133 | dev_err(ds->dev, "Failed to register MDIO bus: %pe\n" , |
3134 | ERR_PTR(rc)); |
3135 | goto out_ptp_clock_unregister; |
3136 | } |
3137 | |
3138 | rc = sja1105_devlink_setup(ds); |
3139 | if (rc < 0) |
3140 | goto out_mdiobus_unregister; |
3141 | |
3142 | rtnl_lock(); |
3143 | rc = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q)); |
3144 | rtnl_unlock(); |
3145 | if (rc) |
3146 | goto out_devlink_teardown; |
3147 | |
3148 | /* On SJA1105, VLAN filtering per se is always enabled in hardware. |
3149 | * The only thing we can do to disable it is lie about what the 802.1Q |
3150 | * EtherType is. |
3151 | * So it will still try to apply VLAN filtering, but all ingress |
3152 | * traffic (except frames received with EtherType of ETH_P_SJA1105) |
3153 | * will be internally tagged with a distorted VLAN header where the |
3154 | * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid. |
3155 | */ |
3156 | ds->vlan_filtering_is_global = true; |
3157 | ds->untag_bridge_pvid = true; |
3158 | ds->fdb_isolation = true; |
3159 | /* tag_8021q has 3 bits for the VBID, and the value 0 is reserved */ |
3160 | ds->max_num_bridges = 7; |
3161 | |
3162 | /* Advertise the 8 egress queues */ |
3163 | ds->num_tx_queues = SJA1105_NUM_TC; |
3164 | |
3165 | ds->mtu_enforcement_ingress = true; |
3166 | ds->assisted_learning_on_cpu_port = true; |
3167 | |
3168 | return 0; |
3169 | |
3170 | out_devlink_teardown: |
3171 | sja1105_devlink_teardown(ds); |
3172 | out_mdiobus_unregister: |
3173 | sja1105_mdiobus_unregister(ds); |
3174 | out_ptp_clock_unregister: |
3175 | sja1105_ptp_clock_unregister(ds); |
3176 | out_flower_teardown: |
3177 | sja1105_flower_teardown(ds); |
3178 | sja1105_tas_teardown(ds); |
3179 | out_static_config_free: |
3180 | sja1105_static_config_free(config: &priv->static_config); |
3181 | |
3182 | return rc; |
3183 | } |
3184 | |
3185 | static void sja1105_teardown(struct dsa_switch *ds) |
3186 | { |
3187 | struct sja1105_private *priv = ds->priv; |
3188 | |
3189 | rtnl_lock(); |
3190 | dsa_tag_8021q_unregister(ds); |
3191 | rtnl_unlock(); |
3192 | |
3193 | sja1105_devlink_teardown(ds); |
3194 | sja1105_mdiobus_unregister(ds); |
3195 | sja1105_ptp_clock_unregister(ds); |
3196 | sja1105_flower_teardown(ds); |
3197 | sja1105_tas_teardown(ds); |
3198 | sja1105_static_config_free(config: &priv->static_config); |
3199 | } |
3200 | |
3201 | static const struct dsa_switch_ops sja1105_switch_ops = { |
3202 | .get_tag_protocol = sja1105_get_tag_protocol, |
3203 | .connect_tag_protocol = sja1105_connect_tag_protocol, |
3204 | .setup = sja1105_setup, |
3205 | .teardown = sja1105_teardown, |
3206 | .set_ageing_time = sja1105_set_ageing_time, |
3207 | .port_change_mtu = sja1105_change_mtu, |
3208 | .port_max_mtu = sja1105_get_max_mtu, |
3209 | .phylink_get_caps = sja1105_phylink_get_caps, |
3210 | .phylink_mac_select_pcs = sja1105_mac_select_pcs, |
3211 | .phylink_mac_link_up = sja1105_mac_link_up, |
3212 | .phylink_mac_link_down = sja1105_mac_link_down, |
3213 | .get_strings = sja1105_get_strings, |
3214 | .get_ethtool_stats = sja1105_get_ethtool_stats, |
3215 | .get_sset_count = sja1105_get_sset_count, |
3216 | .get_ts_info = sja1105_get_ts_info, |
3217 | .port_fdb_dump = sja1105_fdb_dump, |
3218 | .port_fdb_add = sja1105_fdb_add, |
3219 | .port_fdb_del = sja1105_fdb_del, |
3220 | .port_fast_age = sja1105_fast_age, |
3221 | .port_bridge_join = sja1105_bridge_join, |
3222 | .port_bridge_leave = sja1105_bridge_leave, |
3223 | .port_pre_bridge_flags = sja1105_port_pre_bridge_flags, |
3224 | .port_bridge_flags = sja1105_port_bridge_flags, |
3225 | .port_stp_state_set = sja1105_bridge_stp_state_set, |
3226 | .port_vlan_filtering = sja1105_vlan_filtering, |
3227 | .port_vlan_add = sja1105_bridge_vlan_add, |
3228 | .port_vlan_del = sja1105_bridge_vlan_del, |
3229 | .port_mdb_add = sja1105_mdb_add, |
3230 | .port_mdb_del = sja1105_mdb_del, |
3231 | .port_hwtstamp_get = sja1105_hwtstamp_get, |
3232 | .port_hwtstamp_set = sja1105_hwtstamp_set, |
3233 | .port_rxtstamp = sja1105_port_rxtstamp, |
3234 | .port_txtstamp = sja1105_port_txtstamp, |
3235 | .port_setup_tc = sja1105_port_setup_tc, |
3236 | .port_mirror_add = sja1105_mirror_add, |
3237 | .port_mirror_del = sja1105_mirror_del, |
3238 | .port_policer_add = sja1105_port_policer_add, |
3239 | .port_policer_del = sja1105_port_policer_del, |
3240 | .cls_flower_add = sja1105_cls_flower_add, |
3241 | .cls_flower_del = sja1105_cls_flower_del, |
3242 | .cls_flower_stats = sja1105_cls_flower_stats, |
3243 | .devlink_info_get = sja1105_devlink_info_get, |
3244 | .tag_8021q_vlan_add = sja1105_dsa_8021q_vlan_add, |
3245 | .tag_8021q_vlan_del = sja1105_dsa_8021q_vlan_del, |
3246 | .port_prechangeupper = sja1105_prechangeupper, |
3247 | }; |
3248 | |
3249 | static const struct of_device_id sja1105_dt_ids[]; |
3250 | |
3251 | static int sja1105_check_device_id(struct sja1105_private *priv) |
3252 | { |
3253 | const struct sja1105_regs *regs = priv->info->regs; |
3254 | u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0}; |
3255 | struct device *dev = &priv->spidev->dev; |
3256 | const struct of_device_id *match; |
3257 | u32 device_id; |
3258 | u64 part_no; |
3259 | int rc; |
3260 | |
3261 | rc = sja1105_xfer_u32(priv, rw: SPI_READ, reg_addr: regs->device_id, value: &device_id, |
3262 | NULL); |
3263 | if (rc < 0) |
3264 | return rc; |
3265 | |
3266 | rc = sja1105_xfer_buf(priv, rw: SPI_READ, reg_addr: regs->prod_id, buf: prod_id, |
3267 | SJA1105_SIZE_DEVICE_ID); |
3268 | if (rc < 0) |
3269 | return rc; |
3270 | |
3271 | sja1105_unpack(buf: prod_id, val: &part_no, start: 19, end: 4, SJA1105_SIZE_DEVICE_ID); |
3272 | |
3273 | for (match = sja1105_dt_ids; match->compatible[0]; match++) { |
3274 | const struct sja1105_info *info = match->data; |
3275 | |
3276 | /* Is what's been probed in our match table at all? */ |
3277 | if (info->device_id != device_id || info->part_no != part_no) |
3278 | continue; |
3279 | |
3280 | /* But is it what's in the device tree? */ |
3281 | if (priv->info->device_id != device_id || |
3282 | priv->info->part_no != part_no) { |
3283 | dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n" , |
3284 | priv->info->name, info->name); |
3285 | /* It isn't. No problem, pick that up. */ |
3286 | priv->info = info; |
3287 | } |
3288 | |
3289 | return 0; |
3290 | } |
3291 | |
3292 | dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n" , |
3293 | device_id, part_no); |
3294 | |
3295 | return -ENODEV; |
3296 | } |
3297 | |
3298 | static int sja1105_probe(struct spi_device *spi) |
3299 | { |
3300 | struct device *dev = &spi->dev; |
3301 | struct sja1105_private *priv; |
3302 | size_t max_xfer, max_msg; |
3303 | struct dsa_switch *ds; |
3304 | int rc; |
3305 | |
3306 | if (!dev->of_node) { |
3307 | dev_err(dev, "No DTS bindings for SJA1105 driver\n" ); |
3308 | return -EINVAL; |
3309 | } |
3310 | |
3311 | rc = sja1105_hw_reset(dev, pulse_len: 1, startup_delay: 1); |
3312 | if (rc) |
3313 | return rc; |
3314 | |
3315 | priv = devm_kzalloc(dev, size: sizeof(struct sja1105_private), GFP_KERNEL); |
3316 | if (!priv) |
3317 | return -ENOMEM; |
3318 | |
3319 | /* Populate our driver private structure (priv) based on |
3320 | * the device tree node that was probed (spi) |
3321 | */ |
3322 | priv->spidev = spi; |
3323 | spi_set_drvdata(spi, data: priv); |
3324 | |
3325 | /* Configure the SPI bus */ |
3326 | spi->bits_per_word = 8; |
3327 | rc = spi_setup(spi); |
3328 | if (rc < 0) { |
3329 | dev_err(dev, "Could not init SPI\n" ); |
3330 | return rc; |
3331 | } |
3332 | |
3333 | /* In sja1105_xfer, we send spi_messages composed of two spi_transfers: |
3334 | * a small one for the message header and another one for the current |
3335 | * chunk of the packed buffer. |
3336 | * Check that the restrictions imposed by the SPI controller are |
3337 | * respected: the chunk buffer is smaller than the max transfer size, |
3338 | * and the total length of the chunk plus its message header is smaller |
3339 | * than the max message size. |
3340 | * We do that during probe time since the maximum transfer size is a |
3341 | * runtime invariant. |
3342 | */ |
3343 | max_xfer = spi_max_transfer_size(spi); |
3344 | max_msg = spi_max_message_size(spi); |
3345 | |
3346 | /* We need to send at least one 64-bit word of SPI payload per message |
3347 | * in order to be able to make useful progress. |
3348 | */ |
3349 | if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) { |
3350 | dev_err(dev, "SPI master cannot send large enough buffers, aborting\n" ); |
3351 | return -EINVAL; |
3352 | } |
3353 | |
3354 | priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN; |
3355 | if (priv->max_xfer_len > max_xfer) |
3356 | priv->max_xfer_len = max_xfer; |
3357 | if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER) |
3358 | priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER; |
3359 | |
3360 | priv->info = of_device_get_match_data(dev); |
3361 | |
3362 | /* Detect hardware device */ |
3363 | rc = sja1105_check_device_id(priv); |
3364 | if (rc < 0) { |
3365 | dev_err(dev, "Device ID check failed: %d\n" , rc); |
3366 | return rc; |
3367 | } |
3368 | |
3369 | dev_info(dev, "Probed switch chip: %s\n" , priv->info->name); |
3370 | |
3371 | ds = devm_kzalloc(dev, size: sizeof(*ds), GFP_KERNEL); |
3372 | if (!ds) |
3373 | return -ENOMEM; |
3374 | |
3375 | ds->dev = dev; |
3376 | ds->num_ports = priv->info->num_ports; |
3377 | ds->ops = &sja1105_switch_ops; |
3378 | ds->priv = priv; |
3379 | priv->ds = ds; |
3380 | |
3381 | mutex_init(&priv->ptp_data.lock); |
3382 | mutex_init(&priv->dynamic_config_lock); |
3383 | mutex_init(&priv->mgmt_lock); |
3384 | mutex_init(&priv->fdb_lock); |
3385 | spin_lock_init(&priv->ts_id_lock); |
3386 | |
3387 | rc = sja1105_parse_dt(priv); |
3388 | if (rc < 0) { |
3389 | dev_err(ds->dev, "Failed to parse DT: %d\n" , rc); |
3390 | return rc; |
3391 | } |
3392 | |
3393 | if (IS_ENABLED(CONFIG_NET_SCH_CBS)) { |
3394 | priv->cbs = devm_kcalloc(dev, n: priv->info->num_cbs_shapers, |
3395 | size: sizeof(struct sja1105_cbs_entry), |
3396 | GFP_KERNEL); |
3397 | if (!priv->cbs) |
3398 | return -ENOMEM; |
3399 | } |
3400 | |
3401 | return dsa_register_switch(ds: priv->ds); |
3402 | } |
3403 | |
3404 | static void sja1105_remove(struct spi_device *spi) |
3405 | { |
3406 | struct sja1105_private *priv = spi_get_drvdata(spi); |
3407 | |
3408 | if (!priv) |
3409 | return; |
3410 | |
3411 | dsa_unregister_switch(ds: priv->ds); |
3412 | } |
3413 | |
3414 | static void sja1105_shutdown(struct spi_device *spi) |
3415 | { |
3416 | struct sja1105_private *priv = spi_get_drvdata(spi); |
3417 | |
3418 | if (!priv) |
3419 | return; |
3420 | |
3421 | dsa_switch_shutdown(ds: priv->ds); |
3422 | |
3423 | spi_set_drvdata(spi, NULL); |
3424 | } |
3425 | |
3426 | static const struct of_device_id sja1105_dt_ids[] = { |
3427 | { .compatible = "nxp,sja1105e" , .data = &sja1105e_info }, |
3428 | { .compatible = "nxp,sja1105t" , .data = &sja1105t_info }, |
3429 | { .compatible = "nxp,sja1105p" , .data = &sja1105p_info }, |
3430 | { .compatible = "nxp,sja1105q" , .data = &sja1105q_info }, |
3431 | { .compatible = "nxp,sja1105r" , .data = &sja1105r_info }, |
3432 | { .compatible = "nxp,sja1105s" , .data = &sja1105s_info }, |
3433 | { .compatible = "nxp,sja1110a" , .data = &sja1110a_info }, |
3434 | { .compatible = "nxp,sja1110b" , .data = &sja1110b_info }, |
3435 | { .compatible = "nxp,sja1110c" , .data = &sja1110c_info }, |
3436 | { .compatible = "nxp,sja1110d" , .data = &sja1110d_info }, |
3437 | { /* sentinel */ }, |
3438 | }; |
3439 | MODULE_DEVICE_TABLE(of, sja1105_dt_ids); |
3440 | |
3441 | static const struct spi_device_id sja1105_spi_ids[] = { |
3442 | { "sja1105e" }, |
3443 | { "sja1105t" }, |
3444 | { "sja1105p" }, |
3445 | { "sja1105q" }, |
3446 | { "sja1105r" }, |
3447 | { "sja1105s" }, |
3448 | { "sja1110a" }, |
3449 | { "sja1110b" }, |
3450 | { "sja1110c" }, |
3451 | { "sja1110d" }, |
3452 | { }, |
3453 | }; |
3454 | MODULE_DEVICE_TABLE(spi, sja1105_spi_ids); |
3455 | |
3456 | static struct spi_driver sja1105_driver = { |
3457 | .driver = { |
3458 | .name = "sja1105" , |
3459 | .owner = THIS_MODULE, |
3460 | .of_match_table = of_match_ptr(sja1105_dt_ids), |
3461 | }, |
3462 | .id_table = sja1105_spi_ids, |
3463 | .probe = sja1105_probe, |
3464 | .remove = sja1105_remove, |
3465 | .shutdown = sja1105_shutdown, |
3466 | }; |
3467 | |
3468 | module_spi_driver(sja1105_driver); |
3469 | |
3470 | MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>" ); |
3471 | MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>" ); |
3472 | MODULE_DESCRIPTION("SJA1105 Driver" ); |
3473 | MODULE_LICENSE("GPL v2" ); |
3474 | |