1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* Copyright (c) 2016-2017 Hisilicon Limited. */ |
3 | |
4 | #ifndef __HCLGE_ERR_H |
5 | #define __HCLGE_ERR_H |
6 | |
7 | #include "hclge_main.h" |
8 | #include "hnae3.h" |
9 | |
10 | #define HCLGE_MPF_RAS_INT_MIN_BD_NUM 10 |
11 | #define HCLGE_PF_RAS_INT_MIN_BD_NUM 4 |
12 | #define HCLGE_MPF_MSIX_INT_MIN_BD_NUM 10 |
13 | #define HCLGE_PF_MSIX_INT_MIN_BD_NUM 4 |
14 | |
15 | #define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00 |
16 | #define HCLGE_RAS_REG_NFE_MASK 0xFF00 |
17 | #define HCLGE_RAS_REG_ROCEE_ERR_MASK 0x3000000 |
18 | #define HCLGE_RAS_REG_ERR_MASK \ |
19 | (HCLGE_RAS_REG_NFE_MASK | HCLGE_RAS_REG_ROCEE_ERR_MASK) |
20 | |
21 | #define HCLGE_VECTOR0_REG_MSIX_MASK 0x1FF00 |
22 | |
23 | #define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000 |
24 | #define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000 |
25 | #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x300 |
26 | #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300 |
27 | #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF |
28 | #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF |
29 | #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN 0xFFFF0000 |
30 | #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK 0xFFFF0000 |
31 | #define HCLGE_IMP_RD_POISON_ERR_INT_EN 0x0100 |
32 | #define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100 |
33 | #define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF |
34 | #define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF |
35 | #define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000 |
36 | #define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000 |
37 | #define HCLGE_IGU_ERR_INT_EN 0x0000000F |
38 | #define HCLGE_IGU_ERR_INT_TYPE 0x00000660 |
39 | #define HCLGE_IGU_ERR_INT_EN_MASK 0x000F |
40 | #define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF |
41 | #define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F |
42 | #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF |
43 | #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF |
44 | #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF |
45 | #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF |
46 | #define HCLGE_PPP_PF_ERR_INT_EN 0x0003 |
47 | #define HCLGE_PPP_PF_ERR_INT_EN_MASK 0x0003 |
48 | #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN 0x003F |
49 | #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F |
50 | #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F |
51 | #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F |
52 | #define HCLGE_TM_SCH_ECC_ERR_INT_EN 0x3 |
53 | #define HCLGE_TM_QCN_ERR_INT_TYPE 0x29 |
54 | #define HCLGE_TM_QCN_FIFO_INT_EN 0xFFFF00 |
55 | #define HCLGE_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF |
56 | #define HCLGE_NCSI_ERR_INT_EN 0x3 |
57 | #define HCLGE_NCSI_ERR_INT_TYPE 0x9 |
58 | #define HCLGE_MAC_COMMON_ERR_INT_EN 0x107FF |
59 | #define HCLGE_MAC_COMMON_ERR_INT_EN_MASK 0x107FF |
60 | #define HCLGE_MAC_TNL_INT_EN GENMASK(9, 0) |
61 | #define HCLGE_MAC_TNL_INT_EN_MASK GENMASK(9, 0) |
62 | #define HCLGE_MAC_TNL_INT_CLR GENMASK(9, 0) |
63 | #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0) |
64 | #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0) |
65 | #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0) |
66 | #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0) |
67 | #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF |
68 | #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF |
69 | #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2 0xB |
70 | #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB |
71 | #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0) |
72 | #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16) |
73 | #define HCLGE_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0) |
74 | #define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0) |
75 | #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0) |
76 | #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0) |
77 | #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0) |
78 | #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0) |
79 | #define HCLGE_SSU_BIT32_ECC_ERR_INT_EN 0x0101 |
80 | #define HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101 |
81 | #define HCLGE_SSU_COMMON_INT_EN GENMASK(9, 0) |
82 | #define HCLGE_SSU_COMMON_INT_EN_MASK GENMASK(9, 0) |
83 | #define HCLGE_SSU_PORT_BASED_ERR_INT_EN 0x0BFF |
84 | #define HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000 |
85 | #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0) |
86 | #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0) |
87 | |
88 | #define HCLGE_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0) |
89 | #define HCLGE_SSU_PORT_INT_MSIX_MASK 0x7BFF |
90 | #define HCLGE_IGU_INT_MASK GENMASK(3, 0) |
91 | #define HCLGE_IGU_EGU_TNL_INT_MASK GENMASK(5, 0) |
92 | #define HCLGE_PPP_MPF_INT_ST3_MASK GENMASK(5, 0) |
93 | #define HCLGE_PPU_MPF_INT_ST3_MASK GENMASK(7, 0) |
94 | #define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK BIT(29) |
95 | #define HCLGE_PPU_PF_INT_RAS_MASK 0x18 |
96 | #define HCLGE_PPU_PF_INT_MSIX_MASK 0x26 |
97 | #define HCLGE_PPU_PF_OVER_8BD_ERR_MASK 0x01 |
98 | #define HCLGE_QCN_FIFO_INT_MASK GENMASK(17, 0) |
99 | #define HCLGE_QCN_ECC_INT_MASK GENMASK(21, 0) |
100 | #define HCLGE_NCSI_ECC_INT_MASK GENMASK(1, 0) |
101 | |
102 | #define HCLGE_ROCEE_RAS_NFE_INT_EN 0xF |
103 | #define HCLGE_ROCEE_RAS_CE_INT_EN 0x1 |
104 | #define HCLGE_ROCEE_RAS_NFE_INT_EN_MASK 0xF |
105 | #define HCLGE_ROCEE_RAS_CE_INT_EN_MASK 0x1 |
106 | #define HCLGE_ROCEE_RERR_INT_MASK BIT(0) |
107 | #define HCLGE_ROCEE_BERR_INT_MASK BIT(1) |
108 | #define HCLGE_ROCEE_AXI_ERR_INT_MASK GENMASK(1, 0) |
109 | #define HCLGE_ROCEE_ECC_INT_MASK BIT(2) |
110 | #define HCLGE_ROCEE_OVF_INT_MASK BIT(3) |
111 | #define HCLGE_ROCEE_OVF_ERR_INT_MASK 0x10000 |
112 | #define HCLGE_ROCEE_OVF_ERR_TYPE_MASK 0x3F |
113 | |
114 | #define HCLGE_DESC_DATA_MAX 8 |
115 | #define HCLGE_REG_NUM_MAX 256 |
116 | #define HCLGE_DESC_NO_DATA_LEN 8 |
117 | |
118 | enum hclge_err_int_type { |
119 | HCLGE_ERR_INT_MSIX = 0, |
120 | HCLGE_ERR_INT_RAS_CE = 1, |
121 | HCLGE_ERR_INT_RAS_NFE = 2, |
122 | HCLGE_ERR_INT_RAS_FE = 3, |
123 | }; |
124 | |
125 | enum hclge_mod_name_list { |
126 | MODULE_NONE = 0, |
127 | MODULE_BIOS_COMMON = 1, |
128 | MODULE_GE = 2, |
129 | MODULE_IGU_EGU = 3, |
130 | MODULE_LGE = 4, |
131 | MODULE_NCSI = 5, |
132 | MODULE_PPP = 6, |
133 | MODULE_QCN = 7, |
134 | MODULE_RCB_RX = 8, |
135 | MODULE_RTC = 9, |
136 | MODULE_SSU = 10, |
137 | MODULE_TM = 11, |
138 | MODULE_RCB_TX = 12, |
139 | MODULE_TXDMA = 13, |
140 | MODULE_MASTER = 14, |
141 | MODULE_HIMAC = 15, |
142 | /* add new MODULE NAME for NIC here in order */ |
143 | MODULE_ROCEE_TOP = 40, |
144 | MODULE_ROCEE_TIMER = 41, |
145 | MODULE_ROCEE_MDB = 42, |
146 | MODULE_ROCEE_TSP = 43, |
147 | MODULE_ROCEE_TRP = 44, |
148 | MODULE_ROCEE_SCC = 45, |
149 | MODULE_ROCEE_CAEP = 46, |
150 | MODULE_ROCEE_GEN_AC = 47, |
151 | MODULE_ROCEE_QMM = 48, |
152 | MODULE_ROCEE_LSAN = 49, |
153 | /* add new MODULE NAME for RoCEE here in order */ |
154 | }; |
155 | |
156 | enum hclge_err_type_list { |
157 | NONE_ERROR = 0, |
158 | FIFO_ERROR = 1, |
159 | MEMORY_ERROR = 2, |
160 | POISON_ERROR = 3, |
161 | MSIX_ECC_ERROR = 4, |
162 | TQP_INT_ECC_ERROR = 5, |
163 | PF_ABNORMAL_INT_ERROR = 6, |
164 | MPF_ABNORMAL_INT_ERROR = 7, |
165 | COMMON_ERROR = 8, |
166 | PORT_ERROR = 9, |
167 | ETS_ERROR = 10, |
168 | NCSI_ERROR = 11, |
169 | GLB_ERROR = 12, |
170 | LINK_ERROR = 13, |
171 | PTP_ERROR = 14, |
172 | /* add new ERROR TYPE for NIC here in order */ |
173 | ROCEE_NORMAL_ERR = 40, |
174 | ROCEE_OVF_ERR = 41, |
175 | ROCEE_BUS_ERR = 42, |
176 | /* add new ERROR TYPE for ROCEE here in order */ |
177 | }; |
178 | |
179 | struct hclge_hw_blk { |
180 | u32 msk; |
181 | const char *name; |
182 | int (*config_err_int)(struct hclge_dev *hdev, bool en); |
183 | }; |
184 | |
185 | struct hclge_hw_error { |
186 | u32 int_msk; |
187 | const char *msg; |
188 | enum hnae3_reset_type reset_level; |
189 | }; |
190 | |
191 | struct hclge_hw_module_id { |
192 | enum hclge_mod_name_list module_id; |
193 | const char *msg; |
194 | }; |
195 | |
196 | struct hclge_hw_type_id { |
197 | enum hclge_err_type_list type_id; |
198 | const char *msg; |
199 | bool cause_by_vf; /* indicate the error may from vf exception */ |
200 | }; |
201 | |
202 | struct hclge_sum_err_info { |
203 | u8 reset_type; |
204 | u8 mod_num; |
205 | u8 rsv[2]; |
206 | }; |
207 | |
208 | struct hclge_mod_err_info { |
209 | u8 mod_id; |
210 | u8 err_num; |
211 | u8 rsv[2]; |
212 | }; |
213 | |
214 | struct hclge_type_reg_err_info { |
215 | u8 type_id; |
216 | u8 reg_num; |
217 | u8 rsv[2]; |
218 | u32 hclge_reg[HCLGE_REG_NUM_MAX]; |
219 | }; |
220 | |
221 | int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en); |
222 | int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state); |
223 | int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en); |
224 | void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev); |
225 | bool hclge_find_error_source(struct hclge_dev *hdev); |
226 | void hclge_handle_occurred_error(struct hclge_dev *hdev); |
227 | pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev); |
228 | int hclge_handle_hw_msix_error(struct hclge_dev *hdev, |
229 | unsigned long *reset_requests); |
230 | int hclge_handle_error_info_log(struct hnae3_ae_dev *ae_dev); |
231 | int hclge_handle_mac_tnl(struct hclge_dev *hdev); |
232 | int hclge_handle_vf_queue_err_ras(struct hclge_dev *hdev); |
233 | #endif |
234 | |