ice_common.h source code [linux/drivers/net/ethernet/intel/ice/ice_common.h]

1	/ SPDX-License-Identifier: GPL-2.0 /
2	/ Copyright (c) 2018, Intel Corporation. /
3
4	#ifndef _ICE_COMMON_H_
5	#define _ICE_COMMON_H_
6
7	#include <linux/bitfield.h>
8
9	#include "ice.h"
10	#include "ice_type.h"
11	#include "ice_nvm.h"
12	#include "ice_flex_pipe.h"
13	#include <linux/avf/virtchnl.h>
14	#include "ice_switch.h"
15	#include "ice_fdir.h"
16
17	#define ICE_SQ_SEND_DELAY_TIME_MS 10
18	#define ICE_SQ_SEND_MAX_EXECUTE 3
19
20	int ice_init_hw(struct ice_hw *hw);
21	void ice_deinit_hw(struct ice_hw *hw);
22	int ice_check_reset(struct ice_hw *hw);
23	int ice_reset(struct ice_hw hw, enum* ice_reset_req req);
24	int ice_create_all_ctrlq(struct ice_hw *hw);
25	int ice_init_all_ctrlq(struct ice_hw *hw);
26	void ice_shutdown_all_ctrlq(struct ice_hw *hw);
27	void ice_destroy_all_ctrlq(struct ice_hw *hw);
28	int
29	ice_clean_rq_elem(struct ice_hw hw, struct* ice_ctl_q_info *cq,
30	struct ice_rq_event_info e, u16 pending);
31	int
32	ice_get_link_status(struct ice_port_info pi, bool link_up);
33	int ice_update_link_info(struct ice_port_info *pi);
34	int
35	ice_acquire_res(struct ice_hw hw, enum* ice_aq_res_ids res,
36	enum ice_aq_res_access_type access, u32 timeout);
37	void ice_release_res(struct ice_hw hw, enum* ice_aq_res_ids res);
38	int
39	ice_alloc_hw_res(struct ice_hw hw, u16 type, u16 num, bool btm, u16 res);
40	int
41	ice_free_hw_res(struct ice_hw hw, u16 type, u16 num, u16 res);
42	int ice_aq_alloc_free_res(struct ice_hw *hw,
43	struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
44	enum ice_adminq_opc opc);
45	bool ice_is_sbq_supported(struct ice_hw *hw);
46	struct ice_ctl_q_info ice_get_sbq(struct* ice_hw *hw);
47	int
48	ice_sq_send_cmd(struct ice_hw hw, struct* ice_ctl_q_info *cq,
49	struct ice_aq_desc desc, void* *buf, u16 buf_size,
50	struct ice_sq_cd *cd);
51	void ice_clear_pxe_mode(struct ice_hw *hw);
52	int ice_get_caps(struct ice_hw *hw);
53
54	void ice_set_safe_mode_caps(struct ice_hw *hw);
55
56	int ice_write_rxq_ctx(struct ice_hw hw, struct* ice_rlan_ctx *rlan_ctx,
57	u32 rxq_index);
58
59	int
60	ice_aq_get_rss_lut(struct ice_hw hw, struct* ice_aq_get_set_rss_lut_params *get_params);
61	int
62	ice_aq_set_rss_lut(struct ice_hw hw, struct* ice_aq_get_set_rss_lut_params *set_params);
63	int
64	ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
65	struct ice_aqc_get_set_rss_keys *keys);
66	int
67	ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
68	struct ice_aqc_get_set_rss_keys *keys);
69
70	bool ice_check_sq_alive(struct ice_hw hw, struct* ice_ctl_q_info *cq);
71	int ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
72	void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
73	extern const struct ice_ctx_ele ice_tlan_ctx_info[];
74	int ice_set_ctx(struct ice_hw hw, u8 src_ctx, u8 *dest_ctx,
75	const struct ice_ctx_ele *ce_info);
76
77	extern struct mutex ice_global_cfg_lock_sw;
78
79	int
80	ice_aq_send_cmd(struct ice_hw hw, struct* ice_aq_desc *desc,
81	void buf, u16 buf_size, struct* ice_sq_cd *cd);
82	int ice_aq_get_fw_ver(struct ice_hw hw, struct* ice_sq_cd *cd);
83
84	int
85	ice_aq_send_driver_ver(struct ice_hw hw, struct* ice_driver_ver *dv,
86	struct ice_sq_cd *cd);
87	int
88	ice_aq_set_port_params(struct ice_port_info *pi, bool double_vlan,
89	struct ice_sq_cd *cd);
90	int
91	ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
92	struct ice_aqc_get_phy_caps_data *caps,
93	struct ice_sq_cd *cd);
94	bool ice_is_pf_c827(struct ice_hw *hw);
95	bool ice_is_phy_rclk_in_netlist(struct ice_hw *hw);
96	bool ice_is_clock_mux_in_netlist(struct ice_hw *hw);
97	bool ice_is_cgu_in_netlist(struct ice_hw *hw);
98	bool ice_is_gps_in_netlist(struct ice_hw *hw);
99	int
100	ice_aq_get_netlist_node(struct ice_hw hw, struct* ice_aqc_get_link_topo *cmd,
101	u8 node_part_number, u16 node_handle);
102	int
103	ice_aq_list_caps(struct ice_hw hw, void* buf, u16 buf_size, u32 cap_count,
104	enum ice_adminq_opc opc, struct ice_sq_cd *cd);
105	int
106	ice_discover_dev_caps(struct ice_hw hw, struct* ice_hw_dev_caps *dev_caps);
107	void
108	ice_update_phy_type(u64 phy_type_low, u64 phy_type_high,
109	u16 link_speeds_bitmap);
110	int
111	ice_aq_manage_mac_write(struct ice_hw hw, const* u8 *mac_addr, u8 flags,
112	struct ice_sq_cd *cd);
113	bool ice_is_generic_mac(struct ice_hw *hw);
114	bool ice_is_e810(struct ice_hw *hw);
115	int ice_clear_pf_cfg(struct ice_hw *hw);
116	int
117	ice_aq_set_phy_cfg(struct ice_hw hw, struct* ice_port_info *pi,
118	struct ice_aqc_set_phy_cfg_data cfg, struct* ice_sq_cd *cd);
119	bool ice_fw_supports_link_override(struct ice_hw *hw);
120	int
121	ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
122	struct ice_port_info *pi);
123	bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps);
124
125	enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
126	enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
127	int
128	ice_set_fc(struct ice_port_info pi, u8 aq_failures,
129	bool ena_auto_link_update);
130	int
131	ice_cfg_phy_fc(struct ice_port_info pi, struct* ice_aqc_set_phy_cfg_data *cfg,
132	enum ice_fc_mode req_mode);
133	bool
134	ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
135	struct ice_aqc_set_phy_cfg_data *cfg);
136	void
137	ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
138	struct ice_aqc_get_phy_caps_data *caps,
139	struct ice_aqc_set_phy_cfg_data *cfg);
140	int
141	ice_cfg_phy_fec(struct ice_port_info pi, struct* ice_aqc_set_phy_cfg_data *cfg,
142	enum ice_fec_mode fec);
143	int
144	ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
145	struct ice_sq_cd *cd);
146	int
147	ice_aq_set_mac_cfg(struct ice_hw hw, u16 max_frame_size, struct* ice_sq_cd *cd);
148	int
149	ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
150	struct ice_link_status link, struct* ice_sq_cd *cd);
151	int
152	ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
153	struct ice_sq_cd *cd);
154	int
155	ice_aq_set_mac_loopback(struct ice_hw hw, bool ena_lpbk, struct* ice_sq_cd *cd);
156
157	int
158	ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
159	struct ice_sq_cd *cd);
160	int
161	ice_aq_get_port_options(struct ice_hw *hw,
162	struct ice_aqc_get_port_options_elem *options,
163	u8 *option_count, u8 lport, bool lport_valid,
164	u8 active_option_idx, bool active_option_valid,
165	u8 pending_option_idx, bool pending_option_valid);
166	int
167	ice_aq_set_port_option(struct ice_hw *hw, u8 lport, u8 lport_valid,
168	u8 new_option);
169	int
170	ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
171	u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
172	bool write, struct ice_sq_cd *cd);
173	u32 ice_get_link_speed(u16 index);
174
175	int
176	ice_cfg_vsi_rdma(struct ice_port_info *pi, u16 vsi_handle, u16 tc_bitmap,
177	u16 *max_rdmaqs);
178	int
179	ice_ena_vsi_rdma_qset(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
180	u16 rdma_qset, u16 num_qsets, u32 qset_teid);
181	int
182	ice_dis_vsi_rdma_qset(struct ice_port_info pi, u16 count, u32 qset_teid,
183	u16 *q_id);
184	int
185	ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
186	u16 q_handle, u16 q_ids, u32 *q_teids,
187	enum ice_disq_rst_src rst_src, u16 vmvf_num,
188	struct ice_sq_cd *cd);
189	int
190	ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
191	u16 *max_lanqs);
192	int
193	ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
194	u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
195	struct ice_sq_cd *cd);
196	int
197	ice_aq_cfg_lan_txq(struct ice_hw hw, struct* ice_aqc_cfg_txqs_buf *buf,
198	u16 buf_size, u16 num_qs, u8 oldport, u8 newport,
199	struct ice_sq_cd *cd);
200	int ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
201	void ice_replay_post(struct ice_hw *hw);
202	struct ice_q_ctx *
203	ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle);
204	int ice_sbq_rw_reg(struct ice_hw hw, struct* ice_sbq_msg_input *in);
205	int
206	ice_aq_get_cgu_abilities(struct ice_hw *hw,
207	struct ice_aqc_get_cgu_abilities *abilities);
208	int
209	ice_aq_set_input_pin_cfg(struct ice_hw *hw, u8 input_idx, u8 flags1, u8 flags2,
210	u32 freq, s32 phase_delay);
211	int
212	ice_aq_get_input_pin_cfg(struct ice_hw hw, u8 input_idx, u8 status, u8 *type,
213	u8 flags1, u8 flags2, u32 freq, s32 phase_delay);
214	int
215	ice_aq_set_output_pin_cfg(struct ice_hw *hw, u8 output_idx, u8 flags,
216	u8 src_sel, u32 freq, s32 phase_delay);
217	int
218	ice_aq_get_output_pin_cfg(struct ice_hw hw, u8 output_idx, u8 flags,
219	u8 src_sel, u32 freq, u32 *src_freq);
220	int
221	ice_aq_get_cgu_dpll_status(struct ice_hw hw, u8 dpll_num, u8 ref_state,
222	u8 dpll_state, u8 config, s64 *phase_offset,
223	u8 *eec_mode);
224	int
225	ice_aq_set_cgu_dpll_config(struct ice_hw *hw, u8 dpll_num, u8 ref_state,
226	u8 config, u8 eec_mode);
227	int
228	ice_aq_set_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
229	u8 ref_priority);
230	int
231	ice_aq_get_cgu_ref_prio(struct ice_hw *hw, u8 dpll_num, u8 ref_idx,
232	u8 *ref_prio);
233	int
234	ice_aq_get_cgu_info(struct ice_hw hw, u32 cgu_id, u32 *cgu_cfg_ver,
235	u32 *cgu_fw_ver);
236
237	int
238	ice_aq_set_phy_rec_clk_out(struct ice_hw *hw, u8 phy_output, bool enable,
239	u32 *freq);
240	int
241	ice_aq_get_phy_rec_clk_out(struct ice_hw hw, u8 phy_output, u8 *port_num,
242	u8 flags, u16 node_handle);
243	int ice_aq_get_sensor_reading(struct ice_hw *hw,
244	struct ice_aqc_get_sensor_reading_resp *data);
245	void
246	ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
247	u64 prev_stat, u64 cur_stat);
248	void
249	ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
250	u64 prev_stat, u64 cur_stat);
251	bool ice_is_e810t(struct ice_hw *hw);
252	bool ice_is_e823(struct ice_hw *hw);
253	bool ice_is_e825c(struct ice_hw *hw);
254	int
255	ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
256	struct ice_aqc_txsched_elem_data *buf);
257	int
258	ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx, bool value,
259	struct ice_sq_cd *cd);
260	int
261	ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,
262	bool value, struct* ice_sq_cd *cd);
263	bool ice_is_100m_speed_supported(struct ice_hw *hw);
264	int
265	ice_aq_set_lldp_mib(struct ice_hw hw, u8 mib_type, void* *buf, u16 buf_size,
266	struct ice_sq_cd *cd);
267	bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw);
268	int
269	ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add);
270	int ice_lldp_execute_pending_mib(struct ice_hw *hw);
271	int
272	ice_aq_read_i2c(struct ice_hw hw, struct* ice_aqc_link_topo_addr topo_addr,
273	u16 bus_addr, __le16 addr, u8 params, u8 *data,
274	struct ice_sq_cd *cd);
275	int
276	ice_aq_write_i2c(struct ice_hw hw, struct* ice_aqc_link_topo_addr topo_addr,
277	u16 bus_addr, __le16 addr, u8 params, const u8 *data,
278	struct ice_sq_cd *cd);
279	bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
280	#endif /* _ICE_COMMON_H_ */
281

source code of linux/drivers/net/ethernet/intel/ice/ice_common.h