1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018-2023, Intel Corporation. */
3
4#ifndef _ICE_TYPE_H_
5#define _ICE_TYPE_H_
6
7#define ICE_BYTES_PER_WORD 2
8#define ICE_BYTES_PER_DWORD 4
9#define ICE_CHNL_MAX_TC 16
10
11#include "ice_hw_autogen.h"
12#include "ice_devids.h"
13#include "ice_osdep.h"
14#include "ice_controlq.h"
15#include "ice_lan_tx_rx.h"
16#include "ice_flex_type.h"
17#include "ice_protocol_type.h"
18#include "ice_sbq_cmd.h"
19#include "ice_vlan_mode.h"
20#include "ice_fwlog.h"
21
22static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
23{
24 return test_bit(tc, &bitmap);
25}
26
27static inline u64 round_up_64bit(u64 a, u32 b)
28{
29 return div64_long(((a) + (b) / 2), (b));
30}
31
32static inline u32 ice_round_to_num(u32 N, u32 R)
33{
34 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
35 ((((N) + (R) - 1) / (R)) * (R)));
36}
37
38/* Driver always calls main vsi_handle first */
39#define ICE_MAIN_VSI_HANDLE 0
40
41/* debug masks - set these bits in hw->debug_mask to control output */
42#define ICE_DBG_INIT BIT_ULL(1)
43#define ICE_DBG_FW_LOG BIT_ULL(3)
44#define ICE_DBG_LINK BIT_ULL(4)
45#define ICE_DBG_PHY BIT_ULL(5)
46#define ICE_DBG_QCTX BIT_ULL(6)
47#define ICE_DBG_NVM BIT_ULL(7)
48#define ICE_DBG_LAN BIT_ULL(8)
49#define ICE_DBG_FLOW BIT_ULL(9)
50#define ICE_DBG_SW BIT_ULL(13)
51#define ICE_DBG_SCHED BIT_ULL(14)
52#define ICE_DBG_RDMA BIT_ULL(15)
53#define ICE_DBG_PKG BIT_ULL(16)
54#define ICE_DBG_RES BIT_ULL(17)
55#define ICE_DBG_PTP BIT_ULL(19)
56#define ICE_DBG_AQ_MSG BIT_ULL(24)
57#define ICE_DBG_AQ_DESC BIT_ULL(25)
58#define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
59#define ICE_DBG_AQ_CMD BIT_ULL(27)
60#define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
61 ICE_DBG_AQ_DESC | \
62 ICE_DBG_AQ_DESC_BUF | \
63 ICE_DBG_AQ_CMD)
64
65#define ICE_DBG_USER BIT_ULL(31)
66
67enum ice_aq_res_ids {
68 ICE_NVM_RES_ID = 1,
69 ICE_SPD_RES_ID,
70 ICE_CHANGE_LOCK_RES_ID,
71 ICE_GLOBAL_CFG_LOCK_RES_ID
72};
73
74/* FW update timeout definitions are in milliseconds */
75#define ICE_NVM_TIMEOUT 180000
76#define ICE_CHANGE_LOCK_TIMEOUT 1000
77#define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000
78
79enum ice_aq_res_access_type {
80 ICE_RES_READ = 1,
81 ICE_RES_WRITE
82};
83
84struct ice_driver_ver {
85 u8 major_ver;
86 u8 minor_ver;
87 u8 build_ver;
88 u8 subbuild_ver;
89 u8 driver_string[32];
90};
91
92enum ice_fc_mode {
93 ICE_FC_NONE = 0,
94 ICE_FC_RX_PAUSE,
95 ICE_FC_TX_PAUSE,
96 ICE_FC_FULL,
97 ICE_FC_PFC,
98 ICE_FC_DFLT
99};
100
101enum ice_phy_cache_mode {
102 ICE_FC_MODE = 0,
103 ICE_SPEED_MODE,
104 ICE_FEC_MODE
105};
106
107enum ice_fec_mode {
108 ICE_FEC_NONE = 0,
109 ICE_FEC_RS,
110 ICE_FEC_BASER,
111 ICE_FEC_AUTO
112};
113
114struct ice_phy_cache_mode_data {
115 union {
116 enum ice_fec_mode curr_user_fec_req;
117 enum ice_fc_mode curr_user_fc_req;
118 u16 curr_user_speed_req;
119 } data;
120};
121
122enum ice_set_fc_aq_failures {
123 ICE_SET_FC_AQ_FAIL_NONE = 0,
124 ICE_SET_FC_AQ_FAIL_GET,
125 ICE_SET_FC_AQ_FAIL_SET,
126 ICE_SET_FC_AQ_FAIL_UPDATE
127};
128
129/* Various MAC types */
130enum ice_mac_type {
131 ICE_MAC_UNKNOWN = 0,
132 ICE_MAC_E810,
133 ICE_MAC_E830,
134 ICE_MAC_GENERIC,
135 ICE_MAC_GENERIC_3K_E825,
136};
137
138/* Media Types */
139enum ice_media_type {
140 ICE_MEDIA_UNKNOWN = 0,
141 ICE_MEDIA_FIBER,
142 ICE_MEDIA_BASET,
143 ICE_MEDIA_BACKPLANE,
144 ICE_MEDIA_DA,
145};
146
147enum ice_vsi_type {
148 ICE_VSI_PF = 0,
149 ICE_VSI_VF = 1,
150 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
151 ICE_VSI_CHNL = 4,
152 ICE_VSI_LB = 6,
153 ICE_VSI_SWITCHDEV_CTRL = 7,
154};
155
156struct ice_link_status {
157 /* Refer to ice_aq_phy_type for bits definition */
158 u64 phy_type_low;
159 u64 phy_type_high;
160 u8 topo_media_conflict;
161 u16 max_frame_size;
162 u16 link_speed;
163 u16 req_speeds;
164 u8 link_cfg_err;
165 u8 lse_ena; /* Link Status Event notification */
166 u8 link_info;
167 u8 an_info;
168 u8 ext_info;
169 u8 fec_info;
170 u8 pacing;
171 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
172 * ice_aqc_get_phy_caps structure
173 */
174 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
175};
176
177/* Different reset sources for which a disable queue AQ call has to be made in
178 * order to clean the Tx scheduler as a part of the reset
179 */
180enum ice_disq_rst_src {
181 ICE_NO_RESET = 0,
182 ICE_VM_RESET,
183 ICE_VF_RESET,
184};
185
186/* PHY info such as phy_type, etc... */
187struct ice_phy_info {
188 struct ice_link_status link_info;
189 struct ice_link_status link_info_old;
190 u64 phy_type_low;
191 u64 phy_type_high;
192 enum ice_media_type media_type;
193 u8 get_link_info;
194 /* Please refer to struct ice_aqc_get_link_status_data to get
195 * detail of enable bit in curr_user_speed_req
196 */
197 u16 curr_user_speed_req;
198 enum ice_fec_mode curr_user_fec_req;
199 enum ice_fc_mode curr_user_fc_req;
200 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
201};
202
203/* protocol enumeration for filters */
204enum ice_fltr_ptype {
205 /* NONE - used for undef/error */
206 ICE_FLTR_PTYPE_NONF_NONE = 0,
207 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
208 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
209 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
210 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
211 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
212 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
213 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
214 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
215 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
216 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
217 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
218 ICE_FLTR_PTYPE_NONF_IPV4_ESP,
219 ICE_FLTR_PTYPE_NONF_IPV6_ESP,
220 ICE_FLTR_PTYPE_NONF_IPV4_AH,
221 ICE_FLTR_PTYPE_NONF_IPV6_AH,
222 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
223 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
224 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
225 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
226 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
227 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
228 ICE_FLTR_PTYPE_NON_IP_L2,
229 ICE_FLTR_PTYPE_FRAG_IPV4,
230 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
231 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
232 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
233 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
234 ICE_FLTR_PTYPE_MAX,
235};
236
237enum ice_fd_hw_seg {
238 ICE_FD_HW_SEG_NON_TUN = 0,
239 ICE_FD_HW_SEG_TUN,
240 ICE_FD_HW_SEG_MAX,
241};
242
243/* 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + ICE_CHNL_MAX_TC */
244#define ICE_MAX_FDIR_VSI_PER_FILTER (2 + ICE_CHNL_MAX_TC)
245
246struct ice_fd_hw_prof {
247 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
248 int cnt;
249 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
250 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
251 u64 prof_id[ICE_FD_HW_SEG_MAX];
252};
253
254/* Common HW capabilities for SW use */
255struct ice_hw_common_caps {
256 u32 valid_functions;
257 /* DCB capabilities */
258 u32 active_tc_bitmap;
259 u32 maxtc;
260
261 /* Tx/Rx queues */
262 u16 num_rxq; /* Number/Total Rx queues */
263 u16 rxq_first_id; /* First queue ID for Rx queues */
264 u16 num_txq; /* Number/Total Tx queues */
265 u16 txq_first_id; /* First queue ID for Tx queues */
266
267 /* MSI-X vectors */
268 u16 num_msix_vectors;
269 u16 msix_vector_first_id;
270
271 /* Max MTU for function or device */
272 u16 max_mtu;
273
274 /* Virtualization support */
275 u8 sr_iov_1_1; /* SR-IOV enabled */
276
277 /* RSS related capabilities */
278 u16 rss_table_size; /* 512 for PFs and 64 for VFs */
279 u8 rss_table_entry_width; /* RSS Entry width in bits */
280
281 u8 dcb;
282 u8 ieee_1588;
283 u8 rdma;
284 u8 roce_lag;
285 u8 sriov_lag;
286
287 bool nvm_update_pending_nvm;
288 bool nvm_update_pending_orom;
289 bool nvm_update_pending_netlist;
290#define ICE_NVM_PENDING_NVM_IMAGE BIT(0)
291#define ICE_NVM_PENDING_OROM BIT(1)
292#define ICE_NVM_PENDING_NETLIST BIT(2)
293 bool nvm_unified_update;
294#define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
295 /* PCIe reset avoidance */
296 bool pcie_reset_avoidance;
297 /* Post update reset restriction */
298 bool reset_restrict_support;
299};
300
301/* IEEE 1588 TIME_SYNC specific info */
302/* Function specific definitions */
303#define ICE_TS_FUNC_ENA_M BIT(0)
304#define ICE_TS_SRC_TMR_OWND_M BIT(1)
305#define ICE_TS_TMR_ENA_M BIT(2)
306#define ICE_TS_TMR_IDX_OWND_S 4
307#define ICE_TS_TMR_IDX_OWND_M BIT(4)
308#define ICE_TS_CLK_FREQ_S 16
309#define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S)
310#define ICE_TS_CLK_SRC_S 20
311#define ICE_TS_CLK_SRC_M BIT(20)
312#define ICE_TS_TMR_IDX_ASSOC_S 24
313#define ICE_TS_TMR_IDX_ASSOC_M BIT(24)
314
315/* TIME_REF clock rate specification */
316enum ice_time_ref_freq {
317 ICE_TIME_REF_FREQ_25_000 = 0,
318 ICE_TIME_REF_FREQ_122_880 = 1,
319 ICE_TIME_REF_FREQ_125_000 = 2,
320 ICE_TIME_REF_FREQ_153_600 = 3,
321 ICE_TIME_REF_FREQ_156_250 = 4,
322 ICE_TIME_REF_FREQ_245_760 = 5,
323
324 NUM_ICE_TIME_REF_FREQ
325};
326
327/* Clock source specification */
328enum ice_clk_src {
329 ICE_CLK_SRC_TCX0 = 0, /* Temperature compensated oscillator */
330 ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */
331
332 NUM_ICE_CLK_SRC
333};
334
335struct ice_ts_func_info {
336 /* Function specific info */
337 enum ice_time_ref_freq time_ref;
338 u8 clk_freq;
339 u8 clk_src;
340 u8 tmr_index_assoc;
341 u8 ena;
342 u8 tmr_index_owned;
343 u8 src_tmr_owned;
344 u8 tmr_ena;
345};
346
347/* Device specific definitions */
348#define ICE_TS_TMR0_OWNR_M 0x7
349#define ICE_TS_TMR0_OWND_M BIT(3)
350#define ICE_TS_TMR1_OWNR_S 4
351#define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S)
352#define ICE_TS_TMR1_OWND_M BIT(7)
353#define ICE_TS_DEV_ENA_M BIT(24)
354#define ICE_TS_TMR0_ENA_M BIT(25)
355#define ICE_TS_TMR1_ENA_M BIT(26)
356#define ICE_TS_LL_TX_TS_READ_M BIT(28)
357#define ICE_TS_LL_TX_TS_INT_READ_M BIT(29)
358
359struct ice_ts_dev_info {
360 /* Device specific info */
361 u32 ena_ports;
362 u32 tmr_own_map;
363 u32 tmr0_owner;
364 u32 tmr1_owner;
365 u8 tmr0_owned;
366 u8 tmr1_owned;
367 u8 ena;
368 u8 tmr0_ena;
369 u8 tmr1_ena;
370 u8 ts_ll_read;
371 u8 ts_ll_int_read;
372};
373
374/* Function specific capabilities */
375struct ice_hw_func_caps {
376 struct ice_hw_common_caps common_cap;
377 u32 num_allocd_vfs; /* Number of allocated VFs */
378 u32 vf_base_id; /* Logical ID of the first VF */
379 u32 guar_num_vsi;
380 u32 fd_fltr_guar; /* Number of filters guaranteed */
381 u32 fd_fltr_best_effort; /* Number of best effort filters */
382 struct ice_ts_func_info ts_func_info;
383};
384
385#define ICE_SENSOR_SUPPORT_E810_INT_TEMP_BIT 0
386
387/* Device wide capabilities */
388struct ice_hw_dev_caps {
389 struct ice_hw_common_caps common_cap;
390 u32 num_vfs_exposed; /* Total number of VFs exposed */
391 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
392 u32 num_flow_director_fltr; /* Number of FD filters available */
393 struct ice_ts_dev_info ts_dev_info;
394 u32 num_funcs;
395 /* bitmap of supported sensors
396 * bit 0 - internal temperature sensor
397 * bit 31:1 - Reserved
398 */
399 u32 supported_sensors;
400};
401
402/* MAC info */
403struct ice_mac_info {
404 u8 lan_addr[ETH_ALEN];
405 u8 perm_addr[ETH_ALEN];
406};
407
408/* Reset types used to determine which kind of reset was requested. These
409 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
410 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
411 * because its reset source is different than the other types listed.
412 */
413enum ice_reset_req {
414 ICE_RESET_POR = 0,
415 ICE_RESET_INVAL = 0,
416 ICE_RESET_CORER = 1,
417 ICE_RESET_GLOBR = 2,
418 ICE_RESET_EMPR = 3,
419 ICE_RESET_PFR = 4,
420};
421
422/* Bus parameters */
423struct ice_bus_info {
424 u16 device;
425 u8 func;
426};
427
428/* Flow control (FC) parameters */
429struct ice_fc_info {
430 enum ice_fc_mode current_mode; /* FC mode in effect */
431 enum ice_fc_mode req_mode; /* FC mode requested by caller */
432};
433
434/* Option ROM version information */
435struct ice_orom_info {
436 u8 major; /* Major version of OROM */
437 u8 patch; /* Patch version of OROM */
438 u16 build; /* Build version of OROM */
439};
440
441/* NVM version information */
442struct ice_nvm_info {
443 u32 eetrack;
444 u8 major;
445 u8 minor;
446};
447
448/* netlist version information */
449struct ice_netlist_info {
450 u32 major; /* major high/low */
451 u32 minor; /* minor high/low */
452 u32 type; /* type high/low */
453 u32 rev; /* revision high/low */
454 u32 hash; /* SHA-1 hash word */
455 u16 cust_ver; /* customer version */
456};
457
458/* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
459 * of the flash image.
460 */
461enum ice_flash_bank {
462 ICE_INVALID_FLASH_BANK,
463 ICE_1ST_FLASH_BANK,
464 ICE_2ND_FLASH_BANK,
465};
466
467/* Enumeration of which flash bank is desired to read from, either the active
468 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
469 * code which just wants to read the active or inactive flash bank.
470 */
471enum ice_bank_select {
472 ICE_ACTIVE_FLASH_BANK,
473 ICE_INACTIVE_FLASH_BANK,
474};
475
476/* information for accessing NVM, OROM, and Netlist flash banks */
477struct ice_bank_info {
478 u32 nvm_ptr; /* Pointer to 1st NVM bank */
479 u32 nvm_size; /* Size of NVM bank */
480 u32 orom_ptr; /* Pointer to 1st OROM bank */
481 u32 orom_size; /* Size of OROM bank */
482 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
483 u32 netlist_size; /* Size of Netlist bank */
484 enum ice_flash_bank nvm_bank; /* Active NVM bank */
485 enum ice_flash_bank orom_bank; /* Active OROM bank */
486 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
487};
488
489/* Flash Chip Information */
490struct ice_flash_info {
491 struct ice_orom_info orom; /* Option ROM version info */
492 struct ice_nvm_info nvm; /* NVM version information */
493 struct ice_netlist_info netlist;/* Netlist version info */
494 struct ice_bank_info banks; /* Flash Bank information */
495 u16 sr_words; /* Shadow RAM size in words */
496 u32 flash_size; /* Size of available flash in bytes */
497 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
498};
499
500struct ice_link_default_override_tlv {
501 u8 options;
502#define ICE_LINK_OVERRIDE_OPT_M 0x3F
503#define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
504#define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
505#define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
506#define ICE_LINK_OVERRIDE_EN BIT(3)
507#define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
508#define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
509 u8 phy_config;
510#define ICE_LINK_OVERRIDE_PHY_CFG_S 8
511#define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
512#define ICE_LINK_OVERRIDE_PAUSE_M 0x3
513#define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
514#define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
515 u8 fec_options;
516#define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
517 u8 rsvd1;
518 u64 phy_type_low;
519 u64 phy_type_high;
520};
521
522#define ICE_NVM_VER_LEN 32
523
524/* Max number of port to queue branches w.r.t topology */
525#define ICE_MAX_TRAFFIC_CLASS 8
526#define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
527
528#define ice_for_each_traffic_class(_i) \
529 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
530
531/* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
532 * to driver defined policy for default aggregator
533 */
534#define ICE_INVAL_TEID 0xFFFFFFFF
535#define ICE_DFLT_AGG_ID 0
536
537struct ice_sched_node {
538 struct ice_sched_node *parent;
539 struct ice_sched_node *sibling; /* next sibling in the same layer */
540 struct ice_sched_node **children;
541 struct ice_aqc_txsched_elem_data info;
542 char *name;
543 struct devlink_rate *rate_node;
544 u64 tx_max;
545 u64 tx_share;
546 u32 agg_id; /* aggregator group ID */
547 u32 id;
548 u32 tx_priority;
549 u32 tx_weight;
550 u16 vsi_handle;
551 u8 in_use; /* suspended or in use */
552 u8 tx_sched_layer; /* Logical Layer (1-9) */
553 u8 num_children;
554 u8 tc_num;
555 u8 owner;
556#define ICE_SCHED_NODE_OWNER_LAN 0
557#define ICE_SCHED_NODE_OWNER_RDMA 2
558};
559
560/* Access Macros for Tx Sched Elements data */
561#define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
562
563/* The aggregator type determines if identifier is for a VSI group,
564 * aggregator group, aggregator of queues, or queue group.
565 */
566enum ice_agg_type {
567 ICE_AGG_TYPE_UNKNOWN = 0,
568 ICE_AGG_TYPE_VSI,
569 ICE_AGG_TYPE_AGG, /* aggregator */
570 ICE_AGG_TYPE_Q,
571 ICE_AGG_TYPE_QG
572};
573
574/* Rate limit types */
575enum ice_rl_type {
576 ICE_UNKNOWN_BW = 0,
577 ICE_MIN_BW, /* for CIR profile */
578 ICE_MAX_BW, /* for EIR profile */
579 ICE_SHARED_BW /* for shared profile */
580};
581
582#define ICE_SCHED_MIN_BW 500 /* in Kbps */
583#define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
584#define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
585#define ICE_SCHED_DFLT_RL_PROF_ID 0
586#define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
587#define ICE_SCHED_DFLT_BW_WT 4
588#define ICE_SCHED_INVAL_PROF_ID 0xFFFF
589#define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
590
591#define ICE_MAX_PORT_PER_PCI_DEV 8
592
593 /* Data structure for saving BW information */
594enum ice_bw_type {
595 ICE_BW_TYPE_PRIO,
596 ICE_BW_TYPE_CIR,
597 ICE_BW_TYPE_CIR_WT,
598 ICE_BW_TYPE_EIR,
599 ICE_BW_TYPE_EIR_WT,
600 ICE_BW_TYPE_SHARED,
601 ICE_BW_TYPE_CNT /* This must be last */
602};
603
604struct ice_bw {
605 u32 bw;
606 u16 bw_alloc;
607};
608
609struct ice_bw_type_info {
610 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT);
611 u8 generic;
612 struct ice_bw cir_bw;
613 struct ice_bw eir_bw;
614 u32 shared_bw;
615};
616
617/* VSI queue context structure for given TC */
618struct ice_q_ctx {
619 u16 q_handle;
620 u32 q_teid;
621 /* bw_t_info saves queue BW information */
622 struct ice_bw_type_info bw_t_info;
623};
624
625/* VSI type list entry to locate corresponding VSI/aggregator nodes */
626struct ice_sched_vsi_info {
627 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
628 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
629 struct list_head list_entry;
630 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
631 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS];
632 /* bw_t_info saves VSI BW information */
633 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
634};
635
636/* driver defines the policy */
637struct ice_sched_tx_policy {
638 u16 max_num_vsis;
639 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
640 u8 rdma_ena;
641};
642
643/* CEE or IEEE 802.1Qaz ETS Configuration data */
644struct ice_dcb_ets_cfg {
645 u8 willing;
646 u8 cbs;
647 u8 maxtcs;
648 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
649 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
650 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
651};
652
653/* CEE or IEEE 802.1Qaz PFC Configuration data */
654struct ice_dcb_pfc_cfg {
655 u8 willing;
656 u8 mbc;
657 u8 pfccap;
658 u8 pfcena;
659};
660
661/* CEE or IEEE 802.1Qaz Application Priority data */
662struct ice_dcb_app_priority_table {
663 u16 prot_id;
664 u8 priority;
665 u8 selector;
666};
667
668#define ICE_MAX_USER_PRIORITY 8
669#define ICE_DCBX_MAX_APPS 64
670#define ICE_DSCP_NUM_VAL 64
671#define ICE_LLDPDU_SIZE 1500
672#define ICE_TLV_STATUS_OPER 0x1
673#define ICE_TLV_STATUS_SYNC 0x2
674#define ICE_TLV_STATUS_ERR 0x4
675#define ICE_APP_PROT_ID_ISCSI_860 0x035c
676#define ICE_APP_SEL_ETHTYPE 0x1
677#define ICE_APP_SEL_TCPIP 0x2
678#define ICE_CEE_APP_SEL_ETHTYPE 0x0
679#define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
680#define ICE_CEE_APP_SEL_TCPIP 0x1
681
682struct ice_dcbx_cfg {
683 u32 numapps;
684 u32 tlv_status; /* CEE mode TLV status */
685 struct ice_dcb_ets_cfg etscfg;
686 struct ice_dcb_ets_cfg etsrec;
687 struct ice_dcb_pfc_cfg pfc;
688#define ICE_QOS_MODE_VLAN 0x0
689#define ICE_QOS_MODE_DSCP 0x1
690 u8 pfc_mode;
691 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
692 /* when DSCP mapping defined by user set its bit to 1 */
693 DECLARE_BITMAP(dscp_mapped, ICE_DSCP_NUM_VAL);
694 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
695 u8 dscp_map[ICE_DSCP_NUM_VAL];
696 u8 dcbx_mode;
697#define ICE_DCBX_MODE_CEE 0x1
698#define ICE_DCBX_MODE_IEEE 0x2
699 u8 app_mode;
700#define ICE_DCBX_APPS_NON_WILLING 0x1
701};
702
703struct ice_qos_cfg {
704 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
705 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
706 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
707 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
708 u8 is_sw_lldp : 1;
709};
710
711struct ice_port_info {
712 struct ice_sched_node *root; /* Root Node per Port */
713 struct ice_hw *hw; /* back pointer to HW instance */
714 u32 last_node_teid; /* scheduler last node info */
715 u16 sw_id; /* Initial switch ID belongs to port */
716 u16 pf_vf_num;
717 u8 port_state;
718#define ICE_SCHED_PORT_STATE_INIT 0x0
719#define ICE_SCHED_PORT_STATE_READY 0x1
720 u8 lport;
721#define ICE_LPORT_MASK 0xff
722 struct ice_fc_info fc;
723 struct ice_mac_info mac;
724 struct ice_phy_info phy;
725 struct mutex sched_lock; /* protect access to TXSched tree */
726 struct ice_sched_node *
727 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
728 /* List contain profile ID(s) and other params per layer */
729 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
730 struct ice_qos_cfg qos_cfg;
731 struct xarray sched_node_ids;
732 u8 is_vf:1;
733 u8 is_custom_tx_enabled:1;
734};
735
736struct ice_switch_info {
737 struct list_head vsi_list_map_head;
738 struct ice_sw_recipe *recp_list;
739 u16 prof_res_bm_init;
740 u16 max_used_prof_index;
741
742 DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
743};
744
745/* Enum defining the different states of the mailbox snapshot in the
746 * PF-VF mailbox overflow detection algorithm. The snapshot can be in
747 * states:
748 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot
749 * within the mailbox buffer.
750 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot
751 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the
752 * mailbox and mark any VFs sending more messages than the threshold limit set.
753 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF.
754 */
755enum ice_mbx_snapshot_state {
756 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0,
757 ICE_MAL_VF_DETECT_STATE_TRAVERSE,
758 ICE_MAL_VF_DETECT_STATE_DETECT,
759 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF,
760};
761
762/* Structure to hold information of the static snapshot and the mailbox
763 * buffer data used to generate and track the snapshot.
764 * 1. state: the state of the mailbox snapshot in the malicious VF
765 * detection state handler ice_mbx_vf_state_handler()
766 * 2. head: head of the mailbox snapshot in a circular mailbox buffer
767 * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer
768 * 4. num_iterations: number of messages traversed in circular mailbox buffer
769 * 5. num_msg_proc: number of messages processed in mailbox
770 * 6. num_pending_arq: number of pending asynchronous messages
771 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently
772 * serviced work item or interrupt.
773 */
774struct ice_mbx_snap_buffer_data {
775 enum ice_mbx_snapshot_state state;
776 u32 head;
777 u32 tail;
778 u32 num_iterations;
779 u16 num_msg_proc;
780 u16 num_pending_arq;
781 u16 max_num_msgs_mbx;
782};
783
784/* Structure used to track a single VF's messages on the mailbox:
785 * 1. list_entry: linked list entry node
786 * 2. msg_count: the number of asynchronous messages sent by this VF
787 * 3. malicious: whether this VF has been detected as malicious before
788 */
789struct ice_mbx_vf_info {
790 struct list_head list_entry;
791 u32 msg_count;
792 u8 malicious : 1;
793};
794
795/* Structure to hold data relevant to the captured static snapshot
796 * of the PF-VF mailbox.
797 */
798struct ice_mbx_snapshot {
799 struct ice_mbx_snap_buffer_data mbx_buf;
800 struct list_head mbx_vf;
801};
802
803/* Structure to hold data to be used for capturing or updating a
804 * static snapshot.
805 * 1. num_msg_proc: number of messages processed in mailbox
806 * 2. num_pending_arq: number of pending asynchronous messages
807 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently
808 * serviced work item or interrupt.
809 * 4. async_watermark_val: An upper threshold set by caller to determine
810 * if the pending arq count is large enough to assume that there is
811 * the possibility of a mailicious VF.
812 */
813struct ice_mbx_data {
814 u16 num_msg_proc;
815 u16 num_pending_arq;
816 u16 max_num_msgs_mbx;
817 u16 async_watermark_val;
818};
819
820/* PHY model */
821enum ice_phy_model {
822 ICE_PHY_UNSUP = -1,
823 ICE_PHY_E810 = 1,
824 ICE_PHY_E82X,
825};
826
827/* Port hardware description */
828struct ice_hw {
829 u8 __iomem *hw_addr;
830 void *back;
831 struct ice_aqc_layer_props *layer_info;
832 struct ice_port_info *port_info;
833 /* PSM clock frequency for calculating RL profile params */
834 u32 psm_clk_freq;
835 u64 debug_mask; /* bitmap for debug mask */
836 enum ice_mac_type mac_type;
837
838 u16 fd_ctr_base; /* FD counter base index */
839
840 /* pci info */
841 u16 device_id;
842 u16 vendor_id;
843 u16 subsystem_device_id;
844 u16 subsystem_vendor_id;
845 u8 revision_id;
846
847 u8 pf_id; /* device profile info */
848 enum ice_phy_model phy_model;
849
850 u16 max_burst_size; /* driver sets this value */
851
852 /* Tx Scheduler values */
853 u8 num_tx_sched_layers;
854 u8 num_tx_sched_phys_layers;
855 u8 flattened_layers;
856 u8 max_cgds;
857 u8 sw_entry_point_layer;
858 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
859 struct list_head agg_list; /* lists all aggregator */
860
861 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
862 u8 evb_veb; /* true for VEB, false for VEPA */
863 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
864 struct ice_bus_info bus;
865 struct ice_flash_info flash;
866 struct ice_hw_dev_caps dev_caps; /* device capabilities */
867 struct ice_hw_func_caps func_caps; /* function capabilities */
868
869 struct ice_switch_info *switch_info; /* switch filter lists */
870
871 /* Control Queue info */
872 struct ice_ctl_q_info adminq;
873 struct ice_ctl_q_info sbq;
874 struct ice_ctl_q_info mailboxq;
875
876 u8 api_branch; /* API branch version */
877 u8 api_maj_ver; /* API major version */
878 u8 api_min_ver; /* API minor version */
879 u8 api_patch; /* API patch version */
880 u8 fw_branch; /* firmware branch version */
881 u8 fw_maj_ver; /* firmware major version */
882 u8 fw_min_ver; /* firmware minor version */
883 u8 fw_patch; /* firmware patch version */
884 u32 fw_build; /* firmware build number */
885
886 struct ice_fwlog_cfg fwlog_cfg;
887 bool fwlog_supported; /* does hardware support FW logging? */
888 struct ice_fwlog_ring fwlog_ring;
889
890/* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
891 * register. Used for determining the ITR/INTRL granularity during
892 * initialization.
893 */
894#define ICE_MAX_AGG_BW_200G 0x0
895#define ICE_MAX_AGG_BW_100G 0X1
896#define ICE_MAX_AGG_BW_50G 0x2
897#define ICE_MAX_AGG_BW_25G 0x3
898 /* ITR granularity for different speeds */
899#define ICE_ITR_GRAN_ABOVE_25 2
900#define ICE_ITR_GRAN_MAX_25 4
901 /* ITR granularity in 1 us */
902 u8 itr_gran;
903 /* INTRL granularity for different speeds */
904#define ICE_INTRL_GRAN_ABOVE_25 4
905#define ICE_INTRL_GRAN_MAX_25 8
906 /* INTRL granularity in 1 us */
907 u8 intrl_gran;
908
909#define ICE_MAX_QUAD 2
910#define ICE_QUADS_PER_PHY_E82X 2
911#define ICE_PORTS_PER_PHY_E82X 8
912#define ICE_PORTS_PER_QUAD 4
913#define ICE_PORTS_PER_PHY_E810 4
914#define ICE_NUM_EXTERNAL_PORTS (ICE_MAX_QUAD * ICE_PORTS_PER_QUAD)
915
916 /* Active package version (currently active) */
917 struct ice_pkg_ver active_pkg_ver;
918 u32 pkg_seg_id;
919 u32 pkg_sign_type;
920 u32 active_track_id;
921 u8 pkg_has_signing_seg:1;
922 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
923 u8 active_pkg_in_nvm;
924
925 /* Driver's package ver - (from the Ice Metadata section) */
926 struct ice_pkg_ver pkg_ver;
927 u8 pkg_name[ICE_PKG_NAME_SIZE];
928
929 /* Driver's Ice segment format version and ID (from the Ice seg) */
930 struct ice_pkg_ver ice_seg_fmt_ver;
931 u8 ice_seg_id[ICE_SEG_ID_SIZE];
932
933 /* Pointer to the ice segment */
934 struct ice_seg *seg;
935
936 /* Pointer to allocated copy of pkg memory */
937 u8 *pkg_copy;
938 u32 pkg_size;
939
940 /* tunneling info */
941 struct mutex tnl_lock;
942 struct ice_tunnel_table tnl;
943
944 struct udp_tunnel_nic_shared udp_tunnel_shared;
945 struct udp_tunnel_nic_info udp_tunnel_nic;
946
947 /* dvm boost update information */
948 struct ice_dvm_table dvm_upd;
949
950 /* HW block tables */
951 struct ice_blk_info blk[ICE_BLK_COUNT];
952 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
953 struct list_head fl_profs[ICE_BLK_COUNT];
954
955 /* Flow Director filter info */
956 int fdir_active_fltr;
957
958 struct mutex fdir_fltr_lock; /* protect Flow Director */
959 struct list_head fdir_list_head;
960
961 /* Book-keeping of side-band filter count per flow-type.
962 * This is used to detect and handle input set changes for
963 * respective flow-type.
964 */
965 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
966
967 struct ice_fd_hw_prof **fdir_prof;
968 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
969 struct mutex rss_locks; /* protect RSS configuration */
970 struct list_head rss_list_head;
971 struct ice_mbx_snapshot mbx_snapshot;
972 DECLARE_BITMAP(hw_ptype, ICE_FLOW_PTYPE_MAX);
973 u8 dvm_ena;
974 u16 io_expander_handle;
975 u8 cgu_part_number;
976};
977
978/* Statistics collected by each port, VSI, VEB, and S-channel */
979struct ice_eth_stats {
980 u64 rx_bytes; /* gorc */
981 u64 rx_unicast; /* uprc */
982 u64 rx_multicast; /* mprc */
983 u64 rx_broadcast; /* bprc */
984 u64 rx_discards; /* rdpc */
985 u64 rx_unknown_protocol; /* rupp */
986 u64 tx_bytes; /* gotc */
987 u64 tx_unicast; /* uptc */
988 u64 tx_multicast; /* mptc */
989 u64 tx_broadcast; /* bptc */
990 u64 tx_discards; /* tdpc */
991 u64 tx_errors; /* tepc */
992};
993
994#define ICE_MAX_UP 8
995
996/* Statistics collected by the MAC */
997struct ice_hw_port_stats {
998 /* eth stats collected by the port */
999 struct ice_eth_stats eth;
1000 /* additional port specific stats */
1001 u64 tx_dropped_link_down; /* tdold */
1002 u64 crc_errors; /* crcerrs */
1003 u64 illegal_bytes; /* illerrc */
1004 u64 error_bytes; /* errbc */
1005 u64 mac_local_faults; /* mlfc */
1006 u64 mac_remote_faults; /* mrfc */
1007 u64 link_xon_rx; /* lxonrxc */
1008 u64 link_xoff_rx; /* lxoffrxc */
1009 u64 link_xon_tx; /* lxontxc */
1010 u64 link_xoff_tx; /* lxofftxc */
1011 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1012 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1013 u64 priority_xon_tx[8]; /* pxontxc[8] */
1014 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1015 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1016 u64 rx_size_64; /* prc64 */
1017 u64 rx_size_127; /* prc127 */
1018 u64 rx_size_255; /* prc255 */
1019 u64 rx_size_511; /* prc511 */
1020 u64 rx_size_1023; /* prc1023 */
1021 u64 rx_size_1522; /* prc1522 */
1022 u64 rx_size_big; /* prc9522 */
1023 u64 rx_undersize; /* ruc */
1024 u64 rx_fragments; /* rfc */
1025 u64 rx_oversize; /* roc */
1026 u64 rx_jabber; /* rjc */
1027 u64 tx_size_64; /* ptc64 */
1028 u64 tx_size_127; /* ptc127 */
1029 u64 tx_size_255; /* ptc255 */
1030 u64 tx_size_511; /* ptc511 */
1031 u64 tx_size_1023; /* ptc1023 */
1032 u64 tx_size_1522; /* ptc1522 */
1033 u64 tx_size_big; /* ptc9522 */
1034 /* flow director stats */
1035 u32 fd_sb_status;
1036 u64 fd_sb_match;
1037};
1038
1039enum ice_sw_fwd_act_type {
1040 ICE_FWD_TO_VSI = 0,
1041 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1042 ICE_FWD_TO_Q,
1043 ICE_FWD_TO_QGRP,
1044 ICE_DROP_PACKET,
1045 ICE_MIRROR_PACKET,
1046 ICE_NOP,
1047 ICE_INVAL_ACT
1048};
1049
1050struct ice_aq_get_set_rss_lut_params {
1051 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
1052 enum ice_lut_size lut_size; /* size of the LUT buffer */
1053 enum ice_lut_type lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1054 u16 vsi_handle; /* software VSI handle */
1055 u8 global_lut_id; /* only valid when lut_type is global */
1056};
1057
1058/* Checksum and Shadow RAM pointers */
1059#define ICE_SR_NVM_CTRL_WORD 0x00
1060#define ICE_SR_BOOT_CFG_PTR 0x132
1061#define ICE_SR_NVM_WOL_CFG 0x19
1062#define ICE_NVM_OROM_VER_OFF 0x02
1063#define ICE_SR_PBA_BLOCK_PTR 0x16
1064#define ICE_SR_NVM_DEV_STARTER_VER 0x18
1065#define ICE_SR_NVM_EETRACK_LO 0x2D
1066#define ICE_SR_NVM_EETRACK_HI 0x2E
1067#define ICE_NVM_VER_LO_SHIFT 0
1068#define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1069#define ICE_NVM_VER_HI_SHIFT 12
1070#define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1071#define ICE_OROM_VER_PATCH_SHIFT 0
1072#define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1073#define ICE_OROM_VER_BUILD_SHIFT 8
1074#define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1075#define ICE_OROM_VER_SHIFT 24
1076#define ICE_OROM_VER_MASK (0xffU << ICE_OROM_VER_SHIFT)
1077#define ICE_SR_PFA_PTR 0x40
1078#define ICE_SR_1ST_NVM_BANK_PTR 0x42
1079#define ICE_SR_NVM_BANK_SIZE 0x43
1080#define ICE_SR_1ST_OROM_BANK_PTR 0x44
1081#define ICE_SR_OROM_BANK_SIZE 0x45
1082#define ICE_SR_NETLIST_BANK_PTR 0x46
1083#define ICE_SR_NETLIST_BANK_SIZE 0x47
1084#define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1085
1086/* CSS Header words */
1087#define ICE_NVM_CSS_SREV_L 0x14
1088#define ICE_NVM_CSS_SREV_H 0x15
1089
1090/* Length of CSS header section in words */
1091#define ICE_CSS_HEADER_LENGTH 330
1092
1093/* Offset of Shadow RAM copy in the NVM bank area. */
1094#define ICE_NVM_SR_COPY_WORD_OFFSET roundup(ICE_CSS_HEADER_LENGTH, 32)
1095
1096/* Size in bytes of Option ROM trailer */
1097#define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH)
1098
1099/* The Link Topology Netlist section is stored as a series of words. It is
1100 * stored in the NVM as a TLV, with the first two words containing the type
1101 * and length.
1102 */
1103#define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B
1104#define ICE_NETLIST_TYPE_OFFSET 0x0000
1105#define ICE_NETLIST_LEN_OFFSET 0x0001
1106
1107/* The Link Topology section follows the TLV header. When reading the netlist
1108 * using ice_read_netlist_module, we need to account for the 2-word TLV
1109 * header.
1110 */
1111#define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2)
1112
1113#define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1114#define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1115
1116#define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0)
1117
1118/* The Netlist ID Block is located after all of the Link Topology nodes. */
1119#define ICE_NETLIST_ID_BLK_SIZE 0x30
1120#define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1121
1122/* netlist ID block field offsets (word offsets) */
1123#define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02
1124#define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03
1125#define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04
1126#define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05
1127#define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06
1128#define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07
1129#define ICE_NETLIST_ID_BLK_REV_LOW 0x08
1130#define ICE_NETLIST_ID_BLK_REV_HIGH 0x09
1131#define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n))
1132#define ICE_NETLIST_ID_BLK_CUST_VER 0x2F
1133
1134/* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */
1135#define ICE_SR_CTRL_WORD_1_S 0x06
1136#define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1137#define ICE_SR_CTRL_WORD_VALID 0x1
1138#define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
1139#define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
1140#define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
1141
1142#define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
1143
1144/* Link override related */
1145#define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1146#define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1147#define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1148#define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1149#define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1150#define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1151#define ICE_FW_API_LINK_OVERRIDE_MIN 5
1152#define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1153
1154#define ICE_SR_WORDS_IN_1KB 512
1155
1156/* AQ API version for LLDP_FILTER_CONTROL */
1157#define ICE_FW_API_LLDP_FLTR_MAJ 1
1158#define ICE_FW_API_LLDP_FLTR_MIN 7
1159#define ICE_FW_API_LLDP_FLTR_PATCH 1
1160
1161/* AQ API version for report default configuration */
1162#define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
1163#define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
1164#define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
1165
1166#endif /* _ICE_TYPE_H_ */
1167

source code of linux/drivers/net/ethernet/intel/ice/ice_type.h