1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/mlx5/port.h>
34#include "mlx5_core.h"
35
36/* calling with verbose false will not print error to log */
37int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
38 void *data_out, int size_out, u16 reg_id, int arg,
39 int write, bool verbose)
40{
41 int outlen = MLX5_ST_SZ_BYTES(access_register_out) + size_out;
42 int inlen = MLX5_ST_SZ_BYTES(access_register_in) + size_in;
43 int err = -ENOMEM;
44 u32 *out = NULL;
45 u32 *in = NULL;
46 void *data;
47
48 in = kvzalloc(size: inlen, GFP_KERNEL);
49 out = kvzalloc(size: outlen, GFP_KERNEL);
50 if (!in || !out)
51 goto out;
52
53 data = MLX5_ADDR_OF(access_register_in, in, register_data);
54 memcpy(data, data_in, size_in);
55
56 MLX5_SET(access_register_in, in, opcode, MLX5_CMD_OP_ACCESS_REG);
57 MLX5_SET(access_register_in, in, op_mod, !write);
58 MLX5_SET(access_register_in, in, argument, arg);
59 MLX5_SET(access_register_in, in, register_id, reg_id);
60
61 err = mlx5_cmd_do(dev, in, in_size: inlen, out, out_size: outlen);
62 if (verbose)
63 err = mlx5_cmd_check(dev, err, in, out);
64 if (err)
65 goto out;
66
67 data = MLX5_ADDR_OF(access_register_out, out, register_data);
68 memcpy(data_out, data, size_out);
69
70out:
71 kvfree(addr: out);
72 kvfree(addr: in);
73 return err;
74}
75EXPORT_SYMBOL_GPL(mlx5_access_reg);
76
77int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
78 int size_in, void *data_out, int size_out,
79 u16 reg_id, int arg, int write)
80{
81 return mlx5_access_reg(dev, data_in, size_in, data_out, size_out,
82 reg_id, arg, write, true);
83}
84EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
85
86int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
87 u8 access_reg_group)
88{
89 u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0};
90 int sz = MLX5_ST_SZ_BYTES(pcam_reg);
91
92 MLX5_SET(pcam_reg, in, feature_group, feature_group);
93 MLX5_SET(pcam_reg, in, access_reg_group, access_reg_group);
94
95 return mlx5_core_access_reg(dev, in, sz, pcam, sz, MLX5_REG_PCAM, 0, 0);
96}
97
98int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group,
99 u8 access_reg_group)
100{
101 u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0};
102 int sz = MLX5_ST_SZ_BYTES(mcam_reg);
103
104 MLX5_SET(mcam_reg, in, feature_group, feature_group);
105 MLX5_SET(mcam_reg, in, access_reg_group, access_reg_group);
106
107 return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0);
108}
109
110int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
111 u8 feature_group, u8 access_reg_group)
112{
113 u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {};
114 int sz = MLX5_ST_SZ_BYTES(qcam_reg);
115
116 MLX5_SET(qcam_reg, in, feature_group, feature_group);
117 MLX5_SET(qcam_reg, in, access_reg_group, access_reg_group);
118
119 return mlx5_core_access_reg(mdev, in, sz, qcam, sz, MLX5_REG_QCAM, 0, 0);
120}
121
122struct mlx5_reg_pcap {
123 u8 rsvd0;
124 u8 port_num;
125 u8 rsvd1[2];
126 __be32 caps_127_96;
127 __be32 caps_95_64;
128 __be32 caps_63_32;
129 __be32 caps_31_0;
130};
131
132int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
133{
134 struct mlx5_reg_pcap in;
135 struct mlx5_reg_pcap out;
136
137 memset(&in, 0, sizeof(in));
138 in.caps_127_96 = cpu_to_be32(caps);
139 in.port_num = port_num;
140
141 return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
142 sizeof(out), MLX5_REG_PCAP, 0, 1);
143}
144EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
145
146int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
147 int ptys_size, int proto_mask, u8 local_port)
148{
149 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
150
151 MLX5_SET(ptys_reg, in, local_port, local_port);
152 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
153 return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
154 ptys_size, MLX5_REG_PTYS, 0, 0);
155}
156EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
157
158int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration)
159{
160 u32 in[MLX5_ST_SZ_DW(mlcr_reg)] = {0};
161 u32 out[MLX5_ST_SZ_DW(mlcr_reg)];
162
163 MLX5_SET(mlcr_reg, in, local_port, 1);
164 MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration);
165 return mlx5_core_access_reg(dev, in, sizeof(in), out,
166 sizeof(out), MLX5_REG_MLCR, 0, 1);
167}
168
169int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper,
170 u16 *proto_oper, u8 local_port)
171{
172 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
173 int err;
174
175 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB,
176 local_port);
177 if (err)
178 return err;
179
180 *link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
181 *proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
182
183 return 0;
184}
185EXPORT_SYMBOL(mlx5_query_ib_port_oper);
186
187/* This function should be used after setting a port register only */
188void mlx5_toggle_port_link(struct mlx5_core_dev *dev)
189{
190 enum mlx5_port_status ps;
191
192 mlx5_query_port_admin_status(dev, status: &ps);
193 mlx5_set_port_admin_status(dev, status: MLX5_PORT_DOWN);
194 if (ps == MLX5_PORT_UP)
195 mlx5_set_port_admin_status(dev, status: MLX5_PORT_UP);
196}
197EXPORT_SYMBOL_GPL(mlx5_toggle_port_link);
198
199int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
200 enum mlx5_port_status status)
201{
202 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
203 u32 out[MLX5_ST_SZ_DW(paos_reg)];
204
205 MLX5_SET(paos_reg, in, local_port, 1);
206 MLX5_SET(paos_reg, in, admin_status, status);
207 MLX5_SET(paos_reg, in, ase, 1);
208 return mlx5_core_access_reg(dev, in, sizeof(in), out,
209 sizeof(out), MLX5_REG_PAOS, 0, 1);
210}
211EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
212
213int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
214 enum mlx5_port_status *status)
215{
216 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
217 u32 out[MLX5_ST_SZ_DW(paos_reg)];
218 int err;
219
220 MLX5_SET(paos_reg, in, local_port, 1);
221 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
222 sizeof(out), MLX5_REG_PAOS, 0, 0);
223 if (err)
224 return err;
225 *status = MLX5_GET(paos_reg, out, admin_status);
226 return 0;
227}
228EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
229
230static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, u16 *admin_mtu,
231 u16 *max_mtu, u16 *oper_mtu, u8 port)
232{
233 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
234 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
235
236 MLX5_SET(pmtu_reg, in, local_port, port);
237 mlx5_core_access_reg(dev, in, sizeof(in), out,
238 sizeof(out), MLX5_REG_PMTU, 0, 0);
239
240 if (max_mtu)
241 *max_mtu = MLX5_GET(pmtu_reg, out, max_mtu);
242 if (oper_mtu)
243 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
244 if (admin_mtu)
245 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
246}
247
248int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port)
249{
250 u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
251 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
252
253 MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
254 MLX5_SET(pmtu_reg, in, local_port, port);
255 return mlx5_core_access_reg(dev, in, sizeof(in), out,
256 sizeof(out), MLX5_REG_PMTU, 0, 1);
257}
258EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
259
260void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu,
261 u8 port)
262{
263 mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
264}
265EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
266
267void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
268 u8 port)
269{
270 mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
271}
272EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
273
274int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num)
275{
276 u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {0};
277 u32 out[MLX5_ST_SZ_DW(pmlp_reg)];
278 int err;
279
280 MLX5_SET(pmlp_reg, in, local_port, 1);
281 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
282 MLX5_REG_PMLP, 0, 0);
283 if (err)
284 return err;
285
286 *module_num = MLX5_GET(lane_2_module_mapping,
287 MLX5_ADDR_OF(pmlp_reg, out, lane0_module_mapping),
288 module);
289
290 return 0;
291}
292
293static int mlx5_query_module_id(struct mlx5_core_dev *dev, int module_num,
294 u8 *module_id)
295{
296 u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {};
297 u32 out[MLX5_ST_SZ_DW(mcia_reg)];
298 int err, status;
299 u8 *ptr;
300
301 MLX5_SET(mcia_reg, in, i2c_device_address, MLX5_I2C_ADDR_LOW);
302 MLX5_SET(mcia_reg, in, module, module_num);
303 MLX5_SET(mcia_reg, in, device_address, 0);
304 MLX5_SET(mcia_reg, in, page_number, 0);
305 MLX5_SET(mcia_reg, in, size, 1);
306 MLX5_SET(mcia_reg, in, l, 0);
307
308 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
309 sizeof(out), MLX5_REG_MCIA, 0, 0);
310 if (err)
311 return err;
312
313 status = MLX5_GET(mcia_reg, out, status);
314 if (status) {
315 mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
316 status);
317 return -EIO;
318 }
319 ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
320
321 *module_id = ptr[0];
322
323 return 0;
324}
325
326static int mlx5_qsfp_eeprom_page(u16 offset)
327{
328 if (offset < MLX5_EEPROM_PAGE_LENGTH)
329 /* Addresses between 0-255 - page 00 */
330 return 0;
331
332 /* Addresses between 256 - 639 belongs to pages 01, 02 and 03
333 * For example, offset = 400 belongs to page 02:
334 * 1 + ((400 - 256)/128) = 2
335 */
336 return 1 + ((offset - MLX5_EEPROM_PAGE_LENGTH) /
337 MLX5_EEPROM_HIGH_PAGE_LENGTH);
338}
339
340static int mlx5_qsfp_eeprom_high_page_offset(int page_num)
341{
342 if (!page_num) /* Page 0 always start from low page */
343 return 0;
344
345 /* High page */
346 return page_num * MLX5_EEPROM_HIGH_PAGE_LENGTH;
347}
348
349static void mlx5_qsfp_eeprom_params_set(u16 *i2c_addr, int *page_num, u16 *offset)
350{
351 *i2c_addr = MLX5_I2C_ADDR_LOW;
352 *page_num = mlx5_qsfp_eeprom_page(offset: *offset);
353 *offset -= mlx5_qsfp_eeprom_high_page_offset(page_num: *page_num);
354}
355
356static void mlx5_sfp_eeprom_params_set(u16 *i2c_addr, int *page_num, u16 *offset)
357{
358 *i2c_addr = MLX5_I2C_ADDR_LOW;
359 *page_num = 0;
360
361 if (*offset < MLX5_EEPROM_PAGE_LENGTH)
362 return;
363
364 *i2c_addr = MLX5_I2C_ADDR_HIGH;
365 *offset -= MLX5_EEPROM_PAGE_LENGTH;
366}
367
368static int mlx5_mcia_max_bytes(struct mlx5_core_dev *dev)
369{
370 /* mcia supports either 12 dwords or 32 dwords */
371 return (MLX5_CAP_MCAM_FEATURE(dev, mcia_32dwords) ? 32 : 12) * sizeof(u32);
372}
373
374static int mlx5_query_mcia(struct mlx5_core_dev *dev,
375 struct mlx5_module_eeprom_query_params *params, u8 *data)
376{
377 u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {};
378 u32 out[MLX5_ST_SZ_DW(mcia_reg)];
379 int status, err;
380 void *ptr;
381 u16 size;
382
383 size = min_t(int, params->size, mlx5_mcia_max_bytes(dev));
384
385 MLX5_SET(mcia_reg, in, l, 0);
386 MLX5_SET(mcia_reg, in, size, size);
387 MLX5_SET(mcia_reg, in, module, params->module_number);
388 MLX5_SET(mcia_reg, in, device_address, params->offset);
389 MLX5_SET(mcia_reg, in, page_number, params->page);
390 MLX5_SET(mcia_reg, in, i2c_device_address, params->i2c_address);
391
392 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
393 sizeof(out), MLX5_REG_MCIA, 0, 0);
394 if (err)
395 return err;
396
397 status = MLX5_GET(mcia_reg, out, status);
398 if (status) {
399 mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
400 status);
401 return -EIO;
402 }
403
404 ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
405 memcpy(data, ptr, size);
406
407 return size;
408}
409
410int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
411 u16 offset, u16 size, u8 *data)
412{
413 struct mlx5_module_eeprom_query_params query = {0};
414 u8 module_id;
415 int err;
416
417 err = mlx5_query_module_num(dev, module_num: &query.module_number);
418 if (err)
419 return err;
420
421 err = mlx5_query_module_id(dev, module_num: query.module_number, module_id: &module_id);
422 if (err)
423 return err;
424
425 switch (module_id) {
426 case MLX5_MODULE_ID_SFP:
427 mlx5_sfp_eeprom_params_set(i2c_addr: &query.i2c_address, page_num: &query.page, offset: &offset);
428 break;
429 case MLX5_MODULE_ID_QSFP:
430 case MLX5_MODULE_ID_QSFP_PLUS:
431 case MLX5_MODULE_ID_QSFP28:
432 mlx5_qsfp_eeprom_params_set(i2c_addr: &query.i2c_address, page_num: &query.page, offset: &offset);
433 break;
434 default:
435 mlx5_core_err(dev, "Module ID not recognized: 0x%x\n", module_id);
436 return -EINVAL;
437 }
438
439 if (offset + size > MLX5_EEPROM_PAGE_LENGTH)
440 /* Cross pages read, read until offset 256 in low page */
441 size = MLX5_EEPROM_PAGE_LENGTH - offset;
442
443 query.size = size;
444 query.offset = offset;
445
446 return mlx5_query_mcia(dev, params: &query, data);
447}
448EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom);
449
450int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev,
451 struct mlx5_module_eeprom_query_params *params,
452 u8 *data)
453{
454 int err;
455
456 err = mlx5_query_module_num(dev, module_num: &params->module_number);
457 if (err)
458 return err;
459
460 if (params->i2c_address != MLX5_I2C_ADDR_HIGH &&
461 params->i2c_address != MLX5_I2C_ADDR_LOW) {
462 mlx5_core_err(dev, "I2C address not recognized: 0x%x\n", params->i2c_address);
463 return -EINVAL;
464 }
465
466 return mlx5_query_mcia(dev, params, data);
467}
468EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom_by_page);
469
470static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
471 int pvlc_size, u8 local_port)
472{
473 u32 in[MLX5_ST_SZ_DW(pvlc_reg)] = {0};
474
475 MLX5_SET(pvlc_reg, in, local_port, local_port);
476 return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
477 pvlc_size, MLX5_REG_PVLC, 0, 0);
478}
479
480int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
481 u8 *vl_hw_cap, u8 local_port)
482{
483 u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
484 int err;
485
486 err = mlx5_query_port_pvlc(dev, pvlc: out, pvlc_size: sizeof(out), local_port);
487 if (err)
488 return err;
489
490 *vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
491
492 return 0;
493}
494EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
495
496static int mlx5_query_pfcc_reg(struct mlx5_core_dev *dev, u32 *out,
497 u32 out_size)
498{
499 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
500
501 MLX5_SET(pfcc_reg, in, local_port, 1);
502
503 return mlx5_core_access_reg(dev, in, sizeof(in), out,
504 out_size, MLX5_REG_PFCC, 0, 0);
505}
506
507int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
508{
509 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
510 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
511
512 MLX5_SET(pfcc_reg, in, local_port, 1);
513 MLX5_SET(pfcc_reg, in, pptx, tx_pause);
514 MLX5_SET(pfcc_reg, in, pprx, rx_pause);
515
516 return mlx5_core_access_reg(dev, in, sizeof(in), out,
517 sizeof(out), MLX5_REG_PFCC, 0, 1);
518}
519EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
520
521int mlx5_query_port_pause(struct mlx5_core_dev *dev,
522 u32 *rx_pause, u32 *tx_pause)
523{
524 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
525 int err;
526
527 err = mlx5_query_pfcc_reg(dev, out, out_size: sizeof(out));
528 if (err)
529 return err;
530
531 if (rx_pause)
532 *rx_pause = MLX5_GET(pfcc_reg, out, pprx);
533
534 if (tx_pause)
535 *tx_pause = MLX5_GET(pfcc_reg, out, pptx);
536
537 return 0;
538}
539EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
540
541int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
542 u16 stall_critical_watermark,
543 u16 stall_minor_watermark)
544{
545 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
546 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
547
548 MLX5_SET(pfcc_reg, in, local_port, 1);
549 MLX5_SET(pfcc_reg, in, pptx_mask_n, 1);
550 MLX5_SET(pfcc_reg, in, pprx_mask_n, 1);
551 MLX5_SET(pfcc_reg, in, ppan_mask_n, 1);
552 MLX5_SET(pfcc_reg, in, critical_stall_mask, 1);
553 MLX5_SET(pfcc_reg, in, minor_stall_mask, 1);
554 MLX5_SET(pfcc_reg, in, device_stall_critical_watermark,
555 stall_critical_watermark);
556 MLX5_SET(pfcc_reg, in, device_stall_minor_watermark, stall_minor_watermark);
557
558 return mlx5_core_access_reg(dev, in, sizeof(in), out,
559 sizeof(out), MLX5_REG_PFCC, 0, 1);
560}
561
562int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
563 u16 *stall_critical_watermark,
564 u16 *stall_minor_watermark)
565{
566 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
567 int err;
568
569 err = mlx5_query_pfcc_reg(dev, out, out_size: sizeof(out));
570 if (err)
571 return err;
572
573 if (stall_critical_watermark)
574 *stall_critical_watermark = MLX5_GET(pfcc_reg, out,
575 device_stall_critical_watermark);
576
577 if (stall_minor_watermark)
578 *stall_minor_watermark = MLX5_GET(pfcc_reg, out,
579 device_stall_minor_watermark);
580
581 return 0;
582}
583
584int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
585{
586 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
587 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
588
589 MLX5_SET(pfcc_reg, in, local_port, 1);
590 MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
591 MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
592 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
593 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
594
595 return mlx5_core_access_reg(dev, in, sizeof(in), out,
596 sizeof(out), MLX5_REG_PFCC, 0, 1);
597}
598EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
599
600int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
601{
602 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
603 int err;
604
605 err = mlx5_query_pfcc_reg(dev, out, out_size: sizeof(out));
606 if (err)
607 return err;
608
609 if (pfc_en_tx)
610 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
611
612 if (pfc_en_rx)
613 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
614
615 return 0;
616}
617EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
618
619int mlx5_max_tc(struct mlx5_core_dev *mdev)
620{
621 u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
622
623 return num_tc - 1;
624}
625
626int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out)
627{
628 u32 in[MLX5_ST_SZ_DW(dcbx_param)] = {0};
629
630 MLX5_SET(dcbx_param, in, port_number, 1);
631
632 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
633 sizeof(in), MLX5_REG_DCBX_PARAM, 0, 0);
634}
635
636int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in)
637{
638 u32 out[MLX5_ST_SZ_DW(dcbx_param)];
639
640 MLX5_SET(dcbx_param, in, port_number, 1);
641
642 return mlx5_core_access_reg(mdev, in, sizeof(out), out,
643 sizeof(out), MLX5_REG_DCBX_PARAM, 0, 1);
644}
645
646int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
647{
648 u32 in[MLX5_ST_SZ_DW(qtct_reg)] = {0};
649 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
650 int err;
651 int i;
652
653 for (i = 0; i < 8; i++) {
654 if (prio_tc[i] > mlx5_max_tc(mdev))
655 return -EINVAL;
656
657 MLX5_SET(qtct_reg, in, prio, i);
658 MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
659
660 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
661 sizeof(out), MLX5_REG_QTCT, 0, 1);
662 if (err)
663 return err;
664 }
665
666 return 0;
667}
668EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
669
670int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
671 u8 prio, u8 *tc)
672{
673 u32 in[MLX5_ST_SZ_DW(qtct_reg)];
674 u32 out[MLX5_ST_SZ_DW(qtct_reg)];
675 int err;
676
677 memset(in, 0, sizeof(in));
678 memset(out, 0, sizeof(out));
679
680 MLX5_SET(qtct_reg, in, port_number, 1);
681 MLX5_SET(qtct_reg, in, prio, prio);
682
683 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
684 sizeof(out), MLX5_REG_QTCT, 0, 0);
685 if (!err)
686 *tc = MLX5_GET(qtct_reg, out, tclass);
687
688 return err;
689}
690EXPORT_SYMBOL_GPL(mlx5_query_port_prio_tc);
691
692static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
693 int inlen)
694{
695 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
696
697 if (!MLX5_CAP_GEN(mdev, ets))
698 return -EOPNOTSUPP;
699
700 return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
701 MLX5_REG_QETCR, 0, 1);
702}
703
704static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out,
705 int outlen)
706{
707 u32 in[MLX5_ST_SZ_DW(qetc_reg)];
708
709 if (!MLX5_CAP_GEN(mdev, ets))
710 return -EOPNOTSUPP;
711
712 memset(in, 0, sizeof(in));
713 return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
714 MLX5_REG_QETCR, 0, 0);
715}
716
717int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
718{
719 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
720 int i;
721
722 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
723 MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
724 MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
725 }
726
727 return mlx5_set_port_qetcr_reg(mdev, in, inlen: sizeof(in));
728}
729EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
730
731int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
732 u8 tc, u8 *tc_group)
733{
734 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
735 void *ets_tcn_conf;
736 int err;
737
738 err = mlx5_query_port_qetcr_reg(mdev, out, outlen: sizeof(out));
739 if (err)
740 return err;
741
742 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
743 tc_configuration[tc]);
744
745 *tc_group = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
746 group);
747
748 return 0;
749}
750EXPORT_SYMBOL_GPL(mlx5_query_port_tc_group);
751
752int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
753{
754 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
755 int i;
756
757 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
758 MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
759 MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
760 }
761
762 return mlx5_set_port_qetcr_reg(mdev, in, inlen: sizeof(in));
763}
764EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
765
766int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
767 u8 tc, u8 *bw_pct)
768{
769 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
770 void *ets_tcn_conf;
771 int err;
772
773 err = mlx5_query_port_qetcr_reg(mdev, out, outlen: sizeof(out));
774 if (err)
775 return err;
776
777 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
778 tc_configuration[tc]);
779
780 *bw_pct = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
781 bw_allocation);
782
783 return 0;
784}
785EXPORT_SYMBOL_GPL(mlx5_query_port_tc_bw_alloc);
786
787int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
788 u8 *max_bw_value,
789 u8 *max_bw_units)
790{
791 u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
792 void *ets_tcn_conf;
793 int i;
794
795 MLX5_SET(qetc_reg, in, port_number, 1);
796
797 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
798 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
799
800 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
801 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
802 max_bw_units[i]);
803 MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
804 max_bw_value[i]);
805 }
806
807 return mlx5_set_port_qetcr_reg(mdev, in, inlen: sizeof(in));
808}
809EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);
810
811int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
812 u8 *max_bw_value,
813 u8 *max_bw_units)
814{
815 u32 out[MLX5_ST_SZ_DW(qetc_reg)];
816 void *ets_tcn_conf;
817 int err;
818 int i;
819
820 err = mlx5_query_port_qetcr_reg(mdev, out, outlen: sizeof(out));
821 if (err)
822 return err;
823
824 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
825 ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);
826
827 max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
828 max_bw_value);
829 max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
830 max_bw_units);
831 }
832
833 return 0;
834}
835EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);
836
837int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
838{
839 u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)] = {};
840
841 MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
842 MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
843 MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
844 return mlx5_cmd_exec_in(mdev, set_wol_rol, in);
845}
846EXPORT_SYMBOL_GPL(mlx5_set_port_wol);
847
848int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode)
849{
850 u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)] = {};
851 u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)] = {};
852 int err;
853
854 MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
855 err = mlx5_cmd_exec_inout(mdev, query_wol_rol, in, out);
856 if (!err)
857 *wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
858
859 return err;
860}
861EXPORT_SYMBOL_GPL(mlx5_query_port_wol);
862
863int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen)
864{
865 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
866
867 MLX5_SET(pcmr_reg, in, local_port, 1);
868 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
869 outlen, MLX5_REG_PCMR, 0, 0);
870}
871
872int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen)
873{
874 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
875
876 return mlx5_core_access_reg(mdev, in, inlen, out,
877 sizeof(out), MLX5_REG_PCMR, 0, 1);
878}
879
880int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable)
881{
882 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
883 int err;
884
885 err = mlx5_query_ports_check(mdev, out: in, outlen: sizeof(in));
886 if (err)
887 return err;
888 MLX5_SET(pcmr_reg, in, local_port, 1);
889 MLX5_SET(pcmr_reg, in, fcs_chk, enable);
890 return mlx5_set_ports_check(mdev, in, inlen: sizeof(in));
891}
892
893void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
894 bool *enabled)
895{
896 u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
897 /* Default values for FW which do not support MLX5_REG_PCMR */
898 *supported = false;
899 *enabled = true;
900
901 if (!MLX5_CAP_GEN(mdev, ports_check))
902 return;
903
904 if (mlx5_query_ports_check(mdev, out, outlen: sizeof(out)))
905 return;
906
907 *supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap));
908 *enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk));
909}
910
911int mlx5_query_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
912{
913 u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
914
915 return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps,
916 mtpps_size, MLX5_REG_MTPPS, 0, 0);
917}
918
919int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
920{
921 u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
922
923 return mlx5_core_access_reg(mdev, mtpps, mtpps_size, out,
924 sizeof(out), MLX5_REG_MTPPS, 0, 1);
925}
926
927int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode)
928{
929 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
930 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
931 int err = 0;
932
933 MLX5_SET(mtppse_reg, in, pin, pin);
934
935 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
936 sizeof(out), MLX5_REG_MTPPSE, 0, 0);
937 if (err)
938 return err;
939
940 *arm = MLX5_GET(mtppse_reg, in, event_arm);
941 *mode = MLX5_GET(mtppse_reg, in, event_generation_mode);
942
943 return err;
944}
945
946int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode)
947{
948 u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
949 u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
950
951 MLX5_SET(mtppse_reg, in, pin, pin);
952 MLX5_SET(mtppse_reg, in, event_arm, arm);
953 MLX5_SET(mtppse_reg, in, event_generation_mode, mode);
954
955 return mlx5_core_access_reg(mdev, in, sizeof(in), out,
956 sizeof(out), MLX5_REG_MTPPSE, 0, 1);
957}
958
959int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state)
960{
961 u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
962 u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
963 int err;
964
965 MLX5_SET(qpts_reg, in, local_port, 1);
966 MLX5_SET(qpts_reg, in, trust_state, trust_state);
967
968 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
969 sizeof(out), MLX5_REG_QPTS, 0, 1);
970 return err;
971}
972
973int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state)
974{
975 u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
976 u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
977 int err;
978
979 MLX5_SET(qpts_reg, in, local_port, 1);
980
981 err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
982 sizeof(out), MLX5_REG_QPTS, 0, 0);
983 if (!err)
984 *trust_state = MLX5_GET(qpts_reg, out, trust_state);
985
986 return err;
987}
988
989int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio)
990{
991 int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
992 void *qpdpm_dscp;
993 void *out;
994 void *in;
995 int err;
996
997 in = kzalloc(size: sz, GFP_KERNEL);
998 out = kzalloc(size: sz, GFP_KERNEL);
999 if (!in || !out) {
1000 err = -ENOMEM;
1001 goto out;
1002 }
1003
1004 MLX5_SET(qpdpm_reg, in, local_port, 1);
1005 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
1006 if (err)
1007 goto out;
1008
1009 memcpy(in, out, sz);
1010 MLX5_SET(qpdpm_reg, in, local_port, 1);
1011
1012 /* Update the corresponding dscp entry */
1013 qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, in, dscp[dscp]);
1014 MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, prio, prio);
1015 MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, e, 1);
1016 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 1);
1017
1018out:
1019 kfree(objp: in);
1020 kfree(objp: out);
1021 return err;
1022}
1023
1024/* dscp2prio[i]: priority that dscp i mapped to */
1025#define MLX5E_SUPPORTED_DSCP 64
1026int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio)
1027{
1028 int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
1029 void *qpdpm_dscp;
1030 void *out;
1031 void *in;
1032 int err;
1033 int i;
1034
1035 in = kzalloc(size: sz, GFP_KERNEL);
1036 out = kzalloc(size: sz, GFP_KERNEL);
1037 if (!in || !out) {
1038 err = -ENOMEM;
1039 goto out;
1040 }
1041
1042 MLX5_SET(qpdpm_reg, in, local_port, 1);
1043 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
1044 if (err)
1045 goto out;
1046
1047 for (i = 0; i < (MLX5E_SUPPORTED_DSCP); i++) {
1048 qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, out, dscp[i]);
1049 dscp2prio[i] = MLX5_GET16(qpdpm_dscp_reg, qpdpm_dscp, prio);
1050 }
1051
1052out:
1053 kfree(objp: in);
1054 kfree(objp: out);
1055 return err;
1056}
1057
1058/* speed in units of 1Mb */
1059static const u32 mlx5e_link_speed[MLX5E_LINK_MODES_NUMBER] = {
1060 [MLX5E_1000BASE_CX_SGMII] = 1000,
1061 [MLX5E_1000BASE_KX] = 1000,
1062 [MLX5E_10GBASE_CX4] = 10000,
1063 [MLX5E_10GBASE_KX4] = 10000,
1064 [MLX5E_10GBASE_KR] = 10000,
1065 [MLX5E_20GBASE_KR2] = 20000,
1066 [MLX5E_40GBASE_CR4] = 40000,
1067 [MLX5E_40GBASE_KR4] = 40000,
1068 [MLX5E_56GBASE_R4] = 56000,
1069 [MLX5E_10GBASE_CR] = 10000,
1070 [MLX5E_10GBASE_SR] = 10000,
1071 [MLX5E_10GBASE_ER] = 10000,
1072 [MLX5E_40GBASE_SR4] = 40000,
1073 [MLX5E_40GBASE_LR4] = 40000,
1074 [MLX5E_50GBASE_SR2] = 50000,
1075 [MLX5E_100GBASE_CR4] = 100000,
1076 [MLX5E_100GBASE_SR4] = 100000,
1077 [MLX5E_100GBASE_KR4] = 100000,
1078 [MLX5E_100GBASE_LR4] = 100000,
1079 [MLX5E_100BASE_TX] = 100,
1080 [MLX5E_1000BASE_T] = 1000,
1081 [MLX5E_10GBASE_T] = 10000,
1082 [MLX5E_25GBASE_CR] = 25000,
1083 [MLX5E_25GBASE_KR] = 25000,
1084 [MLX5E_25GBASE_SR] = 25000,
1085 [MLX5E_50GBASE_CR2] = 50000,
1086 [MLX5E_50GBASE_KR2] = 50000,
1087};
1088
1089static const u32 mlx5e_ext_link_speed[MLX5E_EXT_LINK_MODES_NUMBER] = {
1090 [MLX5E_SGMII_100M] = 100,
1091 [MLX5E_1000BASE_X_SGMII] = 1000,
1092 [MLX5E_5GBASE_R] = 5000,
1093 [MLX5E_10GBASE_XFI_XAUI_1] = 10000,
1094 [MLX5E_40GBASE_XLAUI_4_XLPPI_4] = 40000,
1095 [MLX5E_25GAUI_1_25GBASE_CR_KR] = 25000,
1096 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2] = 50000,
1097 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR] = 50000,
1098 [MLX5E_CAUI_4_100GBASE_CR4_KR4] = 100000,
1099 [MLX5E_100GAUI_2_100GBASE_CR2_KR2] = 100000,
1100 [MLX5E_200GAUI_4_200GBASE_CR4_KR4] = 200000,
1101 [MLX5E_400GAUI_8_400GBASE_CR8] = 400000,
1102 [MLX5E_100GAUI_1_100GBASE_CR_KR] = 100000,
1103 [MLX5E_200GAUI_2_200GBASE_CR2_KR2] = 200000,
1104 [MLX5E_400GAUI_4_400GBASE_CR4_KR4] = 400000,
1105 [MLX5E_800GAUI_8_800GBASE_CR8_KR8] = 800000,
1106};
1107
1108int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext,
1109 struct mlx5_port_eth_proto *eproto)
1110{
1111 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
1112 int err;
1113
1114 if (!eproto)
1115 return -EINVAL;
1116
1117 err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_EN, port);
1118 if (err)
1119 return err;
1120
1121 eproto->cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
1122 eth_proto_capability);
1123 eproto->admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_admin);
1124 eproto->oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
1125 return 0;
1126}
1127
1128bool mlx5_ptys_ext_supported(struct mlx5_core_dev *mdev)
1129{
1130 struct mlx5_port_eth_proto eproto;
1131 int err;
1132
1133 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet))
1134 return true;
1135
1136 err = mlx5_port_query_eth_proto(dev: mdev, port: 1, ext: true, eproto: &eproto);
1137 if (err)
1138 return false;
1139
1140 return !!eproto.cap;
1141}
1142
1143static void mlx5e_port_get_speed_arr(struct mlx5_core_dev *mdev,
1144 const u32 **arr, u32 *size,
1145 bool force_legacy)
1146{
1147 bool ext = force_legacy ? false : mlx5_ptys_ext_supported(mdev);
1148
1149 *size = ext ? ARRAY_SIZE(mlx5e_ext_link_speed) :
1150 ARRAY_SIZE(mlx5e_link_speed);
1151 *arr = ext ? mlx5e_ext_link_speed : mlx5e_link_speed;
1152}
1153
1154u32 mlx5_port_ptys2speed(struct mlx5_core_dev *mdev, u32 eth_proto_oper,
1155 bool force_legacy)
1156{
1157 unsigned long temp = eth_proto_oper;
1158 const u32 *table;
1159 u32 speed = 0;
1160 u32 max_size;
1161 int i;
1162
1163 mlx5e_port_get_speed_arr(mdev, arr: &table, size: &max_size, force_legacy);
1164 i = find_first_bit(addr: &temp, size: max_size);
1165 if (i < max_size)
1166 speed = table[i];
1167 return speed;
1168}
1169
1170u32 mlx5_port_speed2linkmodes(struct mlx5_core_dev *mdev, u32 speed,
1171 bool force_legacy)
1172{
1173 u32 link_modes = 0;
1174 const u32 *table;
1175 u32 max_size;
1176 int i;
1177
1178 mlx5e_port_get_speed_arr(mdev, arr: &table, size: &max_size, force_legacy);
1179 for (i = 0; i < max_size; ++i) {
1180 if (table[i] == speed)
1181 link_modes |= MLX5E_PROT_MASK(i);
1182 }
1183 return link_modes;
1184}
1185
1186int mlx5_port_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
1187{
1188 struct mlx5_port_eth_proto eproto;
1189 u32 max_speed = 0;
1190 const u32 *table;
1191 u32 max_size;
1192 bool ext;
1193 int err;
1194 int i;
1195
1196 ext = mlx5_ptys_ext_supported(mdev);
1197 err = mlx5_port_query_eth_proto(dev: mdev, port: 1, ext, eproto: &eproto);
1198 if (err)
1199 return err;
1200
1201 mlx5e_port_get_speed_arr(mdev, arr: &table, size: &max_size, force_legacy: false);
1202 for (i = 0; i < max_size; ++i)
1203 if (eproto.cap & MLX5E_PROT_MASK(i))
1204 max_speed = max(max_speed, table[i]);
1205
1206 *speed = max_speed;
1207 return 0;
1208}
1209
1210int mlx5_query_mpir_reg(struct mlx5_core_dev *dev, u32 *mpir)
1211{
1212 u32 in[MLX5_ST_SZ_DW(mpir_reg)] = {};
1213 int sz = MLX5_ST_SZ_BYTES(mpir_reg);
1214
1215 MLX5_SET(mpir_reg, in, local_port, 1);
1216
1217 return mlx5_core_access_reg(dev, in, sz, mpir, sz, MLX5_REG_MPIR, 0, 0);
1218}
1219

source code of linux/drivers/net/ethernet/mellanox/mlx5/core/port.c