1 | /* |
2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
3 | * |
4 | * This software is available to you under a choice of one of two |
5 | * licenses. You may choose to be licensed under the terms of the GNU |
6 | * General Public License (GPL) Version 2, available from the file |
7 | * COPYING in the main directory of this source tree, or the |
8 | * OpenIB.org BSD license below: |
9 | * |
10 | * Redistribution and use in source and binary forms, with or |
11 | * without modification, are permitted provided that the following |
12 | * conditions are met: |
13 | * |
14 | * - Redistributions of source code must retain the above |
15 | * copyright notice, this list of conditions and the following |
16 | * disclaimer. |
17 | * |
18 | * - Redistributions in binary form must reproduce the above |
19 | * copyright notice, this list of conditions and the following |
20 | * disclaimer in the documentation and/or other materials |
21 | * provided with the distribution. |
22 | * |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
30 | * SOFTWARE. |
31 | */ |
32 | |
33 | #ifndef MLX5_DEVICE_H |
34 | #define MLX5_DEVICE_H |
35 | |
36 | #include <linux/types.h> |
37 | #include <rdma/ib_verbs.h> |
38 | #include <linux/mlx5/mlx5_ifc.h> |
39 | #include <linux/bitfield.h> |
40 | |
41 | #if defined(__LITTLE_ENDIAN) |
42 | #define MLX5_SET_HOST_ENDIANNESS 0 |
43 | #elif defined(__BIG_ENDIAN) |
44 | #define MLX5_SET_HOST_ENDIANNESS 0x80 |
45 | #else |
46 | #error Host endianness not defined |
47 | #endif |
48 | |
49 | /* helper macros */ |
50 | #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) |
51 | #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) |
52 | #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld)) |
53 | #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) |
54 | #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) |
55 | #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) |
56 | #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf)) |
57 | #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) |
58 | #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) |
59 | #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) |
60 | #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) |
61 | #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld)) |
62 | #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) |
63 | |
64 | #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) |
65 | #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) |
66 | #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) |
67 | #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) |
68 | #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) |
69 | #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) |
70 | #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) |
71 | #define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld))) |
72 | |
73 | /* insert a value to a struct */ |
74 | #define MLX5_SET(typ, p, fld, v) do { \ |
75 | u32 _v = v; \ |
76 | BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ |
77 | *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ |
78 | cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ |
79 | (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \ |
80 | << __mlx5_dw_bit_off(typ, fld))); \ |
81 | } while (0) |
82 | |
83 | #define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \ |
84 | BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \ |
85 | MLX5_SET(typ, p, fld[idx], v); \ |
86 | } while (0) |
87 | |
88 | #define MLX5_SET_TO_ONES(typ, p, fld) do { \ |
89 | BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ |
90 | *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ |
91 | cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ |
92 | (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ |
93 | << __mlx5_dw_bit_off(typ, fld))); \ |
94 | } while (0) |
95 | |
96 | #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ |
97 | __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ |
98 | __mlx5_mask(typ, fld)) |
99 | |
100 | #define MLX5_GET_PR(typ, p, fld) ({ \ |
101 | u32 ___t = MLX5_GET(typ, p, fld); \ |
102 | pr_debug(#fld " = 0x%x\n", ___t); \ |
103 | ___t; \ |
104 | }) |
105 | |
106 | #define __MLX5_SET64(typ, p, fld, v) do { \ |
107 | BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ |
108 | *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ |
109 | } while (0) |
110 | |
111 | #define MLX5_SET64(typ, p, fld, v) do { \ |
112 | BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ |
113 | __MLX5_SET64(typ, p, fld, v); \ |
114 | } while (0) |
115 | |
116 | #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \ |
117 | BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ |
118 | __MLX5_SET64(typ, p, fld[idx], v); \ |
119 | } while (0) |
120 | |
121 | #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) |
122 | |
123 | #define MLX5_GET64_PR(typ, p, fld) ({ \ |
124 | u64 ___t = MLX5_GET64(typ, p, fld); \ |
125 | pr_debug(#fld " = 0x%llx\n", ___t); \ |
126 | ___t; \ |
127 | }) |
128 | |
129 | #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\ |
130 | __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ |
131 | __mlx5_mask16(typ, fld)) |
132 | |
133 | #define MLX5_SET16(typ, p, fld, v) do { \ |
134 | u16 _v = v; \ |
135 | BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \ |
136 | *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \ |
137 | cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \ |
138 | (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \ |
139 | << __mlx5_16_bit_off(typ, fld))); \ |
140 | } while (0) |
141 | |
142 | /* Big endian getters */ |
143 | #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\ |
144 | __mlx5_64_off(typ, fld))) |
145 | |
146 | #define MLX5_GET_BE(type_t, typ, p, fld) ({ \ |
147 | type_t tmp; \ |
148 | switch (sizeof(tmp)) { \ |
149 | case sizeof(u8): \ |
150 | tmp = (__force type_t)MLX5_GET(typ, p, fld); \ |
151 | break; \ |
152 | case sizeof(u16): \ |
153 | tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \ |
154 | break; \ |
155 | case sizeof(u32): \ |
156 | tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \ |
157 | break; \ |
158 | case sizeof(u64): \ |
159 | tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \ |
160 | break; \ |
161 | } \ |
162 | tmp; \ |
163 | }) |
164 | |
165 | enum mlx5_inline_modes { |
166 | MLX5_INLINE_MODE_NONE, |
167 | MLX5_INLINE_MODE_L2, |
168 | MLX5_INLINE_MODE_IP, |
169 | MLX5_INLINE_MODE_TCP_UDP, |
170 | }; |
171 | |
172 | enum { |
173 | MLX5_MAX_COMMANDS = 32, |
174 | MLX5_CMD_DATA_BLOCK_SIZE = 512, |
175 | MLX5_PCI_CMD_XPORT = 7, |
176 | MLX5_MKEY_BSF_OCTO_SIZE = 4, |
177 | MLX5_MAX_PSVS = 4, |
178 | }; |
179 | |
180 | enum { |
181 | MLX5_EXTENDED_UD_AV = 0x80000000, |
182 | }; |
183 | |
184 | enum { |
185 | MLX5_CQ_STATE_ARMED = 9, |
186 | MLX5_CQ_STATE_ALWAYS_ARMED = 0xb, |
187 | MLX5_CQ_STATE_FIRED = 0xa, |
188 | }; |
189 | |
190 | enum { |
191 | MLX5_STAT_RATE_OFFSET = 5, |
192 | }; |
193 | |
194 | enum { |
195 | MLX5_INLINE_SEG = 0x80000000, |
196 | }; |
197 | |
198 | enum { |
199 | MLX5_HW_START_PADDING = MLX5_INLINE_SEG, |
200 | }; |
201 | |
202 | enum { |
203 | MLX5_MIN_PKEY_TABLE_SIZE = 128, |
204 | MLX5_MAX_LOG_PKEY_TABLE = 5, |
205 | }; |
206 | |
207 | enum { |
208 | MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 |
209 | }; |
210 | |
211 | enum { |
212 | MLX5_PFAULT_SUBTYPE_WQE = 0, |
213 | MLX5_PFAULT_SUBTYPE_RDMA = 1, |
214 | }; |
215 | |
216 | enum wqe_page_fault_type { |
217 | MLX5_WQE_PF_TYPE_RMP = 0, |
218 | MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1, |
219 | MLX5_WQE_PF_TYPE_RESP = 2, |
220 | MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3, |
221 | }; |
222 | |
223 | enum { |
224 | MLX5_PERM_LOCAL_READ = 1 << 2, |
225 | MLX5_PERM_LOCAL_WRITE = 1 << 3, |
226 | MLX5_PERM_REMOTE_READ = 1 << 4, |
227 | MLX5_PERM_REMOTE_WRITE = 1 << 5, |
228 | MLX5_PERM_ATOMIC = 1 << 6, |
229 | MLX5_PERM_UMR_EN = 1 << 7, |
230 | }; |
231 | |
232 | enum { |
233 | MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, |
234 | MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, |
235 | MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, |
236 | MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, |
237 | MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, |
238 | }; |
239 | |
240 | enum { |
241 | MLX5_EN_RD = (u64)1, |
242 | MLX5_EN_WR = (u64)2 |
243 | }; |
244 | |
245 | enum { |
246 | MLX5_ADAPTER_PAGE_SHIFT = 12, |
247 | MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, |
248 | }; |
249 | |
250 | enum { |
251 | MLX5_BFREGS_PER_UAR = 4, |
252 | MLX5_MAX_UARS = 1 << 8, |
253 | MLX5_NON_FP_BFREGS_PER_UAR = 2, |
254 | MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR - |
255 | MLX5_NON_FP_BFREGS_PER_UAR, |
256 | MLX5_MAX_BFREGS = MLX5_MAX_UARS * |
257 | MLX5_NON_FP_BFREGS_PER_UAR, |
258 | MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE, |
259 | MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE, |
260 | MLX5_MIN_DYN_BFREGS = 512, |
261 | MLX5_MAX_DYN_BFREGS = 1024, |
262 | }; |
263 | |
264 | enum { |
265 | MLX5_MKEY_MASK_LEN = 1ull << 0, |
266 | MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, |
267 | MLX5_MKEY_MASK_START_ADDR = 1ull << 6, |
268 | MLX5_MKEY_MASK_PD = 1ull << 7, |
269 | MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, |
270 | MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, |
271 | MLX5_MKEY_MASK_BSF_EN = 1ull << 12, |
272 | MLX5_MKEY_MASK_KEY = 1ull << 13, |
273 | MLX5_MKEY_MASK_QPN = 1ull << 14, |
274 | MLX5_MKEY_MASK_LR = 1ull << 17, |
275 | MLX5_MKEY_MASK_LW = 1ull << 18, |
276 | MLX5_MKEY_MASK_RR = 1ull << 19, |
277 | MLX5_MKEY_MASK_RW = 1ull << 20, |
278 | MLX5_MKEY_MASK_A = 1ull << 21, |
279 | MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, |
280 | MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE = 1ull << 25, |
281 | MLX5_MKEY_MASK_FREE = 1ull << 29, |
282 | MLX5_MKEY_MASK_RELAXED_ORDERING_READ = 1ull << 47, |
283 | }; |
284 | |
285 | enum { |
286 | MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), |
287 | |
288 | MLX5_UMR_CHECK_NOT_FREE = (1 << 5), |
289 | MLX5_UMR_CHECK_FREE = (2 << 5), |
290 | |
291 | MLX5_UMR_INLINE = (1 << 7), |
292 | }; |
293 | |
294 | #define MLX5_UMR_FLEX_ALIGNMENT 0x40 |
295 | #define MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_mtt)) |
296 | #define MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_klm)) |
297 | |
298 | #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8) |
299 | |
300 | enum { |
301 | MLX5_EVENT_QUEUE_TYPE_QP = 0, |
302 | MLX5_EVENT_QUEUE_TYPE_RQ = 1, |
303 | MLX5_EVENT_QUEUE_TYPE_SQ = 2, |
304 | MLX5_EVENT_QUEUE_TYPE_DCT = 6, |
305 | }; |
306 | |
307 | /* mlx5 components can subscribe to any one of these events via |
308 | * mlx5_eq_notifier_register API. |
309 | */ |
310 | enum mlx5_event { |
311 | /* Special value to subscribe to any event */ |
312 | MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0, |
313 | /* HW events enum start: comp events are not subscribable */ |
314 | MLX5_EVENT_TYPE_COMP = 0x0, |
315 | /* HW Async events enum start: subscribable events */ |
316 | MLX5_EVENT_TYPE_PATH_MIG = 0x01, |
317 | MLX5_EVENT_TYPE_COMM_EST = 0x02, |
318 | MLX5_EVENT_TYPE_SQ_DRAINED = 0x03, |
319 | MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, |
320 | MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, |
321 | |
322 | MLX5_EVENT_TYPE_CQ_ERROR = 0x04, |
323 | MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, |
324 | MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07, |
325 | MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, |
326 | MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, |
327 | MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, |
328 | MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, |
329 | |
330 | MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08, |
331 | MLX5_EVENT_TYPE_PORT_CHANGE = 0x09, |
332 | MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, |
333 | MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16, |
334 | MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, |
335 | MLX5_EVENT_TYPE_XRQ_ERROR = 0x18, |
336 | MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, |
337 | MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22, |
338 | MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24, |
339 | MLX5_EVENT_TYPE_PPS_EVENT = 0x25, |
340 | |
341 | MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, |
342 | MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, |
343 | |
344 | MLX5_EVENT_TYPE_CMD = 0x0a, |
345 | MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, |
346 | |
347 | MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, |
348 | MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, |
349 | |
350 | MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe, |
351 | MLX5_EVENT_TYPE_VHCA_STATE_CHANGE = 0xf, |
352 | |
353 | MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, |
354 | MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, |
355 | |
356 | MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, |
357 | MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, |
358 | |
359 | MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26, |
360 | |
361 | MLX5_EVENT_TYPE_MAX = 0x100, |
362 | }; |
363 | |
364 | enum mlx5_driver_event { |
365 | MLX5_DRIVER_EVENT_TYPE_TRAP = 0, |
366 | MLX5_DRIVER_EVENT_UPLINK_NETDEV, |
367 | MLX5_DRIVER_EVENT_MACSEC_SA_ADDED, |
368 | MLX5_DRIVER_EVENT_MACSEC_SA_DELETED, |
369 | MLX5_DRIVER_EVENT_SF_PEER_DEVLINK, |
370 | MLX5_DRIVER_EVENT_AFFILIATION_DONE, |
371 | MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, |
372 | }; |
373 | |
374 | enum { |
375 | MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0, |
376 | MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1, |
377 | MLX5_TRACER_SUBTYPE_STRINGS_DB_UPDATE = 0x2, |
378 | }; |
379 | |
380 | enum { |
381 | MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1, |
382 | MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5, |
383 | MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT = 0x7, |
384 | MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 0x8, |
385 | }; |
386 | |
387 | enum { |
388 | MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, |
389 | MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, |
390 | MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, |
391 | MLX5_PORT_CHANGE_SUBTYPE_LID = 6, |
392 | MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, |
393 | MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, |
394 | MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, |
395 | }; |
396 | |
397 | enum { |
398 | MLX5_ROCE_VERSION_1 = 0, |
399 | MLX5_ROCE_VERSION_2 = 2, |
400 | }; |
401 | |
402 | enum { |
403 | MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, |
404 | MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, |
405 | }; |
406 | |
407 | enum { |
408 | MLX5_ROCE_L3_TYPE_IPV4 = 0, |
409 | MLX5_ROCE_L3_TYPE_IPV6 = 1, |
410 | }; |
411 | |
412 | enum { |
413 | MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, |
414 | MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, |
415 | }; |
416 | |
417 | enum { |
418 | MLX5_OPCODE_NOP = 0x00, |
419 | MLX5_OPCODE_SEND_INVAL = 0x01, |
420 | MLX5_OPCODE_RDMA_WRITE = 0x08, |
421 | MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, |
422 | MLX5_OPCODE_SEND = 0x0a, |
423 | MLX5_OPCODE_SEND_IMM = 0x0b, |
424 | MLX5_OPCODE_LSO = 0x0e, |
425 | MLX5_OPCODE_RDMA_READ = 0x10, |
426 | MLX5_OPCODE_ATOMIC_CS = 0x11, |
427 | MLX5_OPCODE_ATOMIC_FA = 0x12, |
428 | MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, |
429 | MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, |
430 | MLX5_OPCODE_BIND_MW = 0x18, |
431 | MLX5_OPCODE_CONFIG_CMD = 0x1f, |
432 | MLX5_OPCODE_ENHANCED_MPSW = 0x29, |
433 | |
434 | MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, |
435 | MLX5_RECV_OPCODE_SEND = 0x01, |
436 | MLX5_RECV_OPCODE_SEND_IMM = 0x02, |
437 | MLX5_RECV_OPCODE_SEND_INVAL = 0x03, |
438 | |
439 | MLX5_CQE_OPCODE_ERROR = 0x1e, |
440 | MLX5_CQE_OPCODE_RESIZE = 0x16, |
441 | |
442 | MLX5_OPCODE_SET_PSV = 0x20, |
443 | MLX5_OPCODE_GET_PSV = 0x21, |
444 | MLX5_OPCODE_CHECK_PSV = 0x22, |
445 | MLX5_OPCODE_DUMP = 0x23, |
446 | MLX5_OPCODE_RGET_PSV = 0x26, |
447 | MLX5_OPCODE_RCHECK_PSV = 0x27, |
448 | |
449 | MLX5_OPCODE_UMR = 0x25, |
450 | |
451 | MLX5_OPCODE_FLOW_TBL_ACCESS = 0x2c, |
452 | |
453 | MLX5_OPCODE_ACCESS_ASO = 0x2d, |
454 | }; |
455 | |
456 | enum { |
457 | MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1, |
458 | MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2, |
459 | }; |
460 | |
461 | enum { |
462 | MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1, |
463 | MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2, |
464 | }; |
465 | |
466 | struct mlx5_wqe_tls_static_params_seg { |
467 | u8 ctx[MLX5_ST_SZ_BYTES(tls_static_params)]; |
468 | }; |
469 | |
470 | struct mlx5_wqe_tls_progress_params_seg { |
471 | __be32 tis_tir_num; |
472 | u8 ctx[MLX5_ST_SZ_BYTES(tls_progress_params)]; |
473 | }; |
474 | |
475 | enum { |
476 | MLX5_SET_PORT_RESET_QKEY = 0, |
477 | MLX5_SET_PORT_GUID0 = 16, |
478 | MLX5_SET_PORT_NODE_GUID = 17, |
479 | MLX5_SET_PORT_SYS_GUID = 18, |
480 | MLX5_SET_PORT_GID_TABLE = 19, |
481 | MLX5_SET_PORT_PKEY_TABLE = 20, |
482 | }; |
483 | |
484 | enum { |
485 | MLX5_BW_NO_LIMIT = 0, |
486 | MLX5_100_MBPS_UNIT = 3, |
487 | MLX5_GBPS_UNIT = 4, |
488 | }; |
489 | |
490 | enum { |
491 | MLX5_MAX_PAGE_SHIFT = 31 |
492 | }; |
493 | |
494 | enum { |
495 | /* |
496 | * Max wqe size for rdma read is 512 bytes, so this |
497 | * limits our max_sge_rd as the wqe needs to fit: |
498 | * - ctrl segment (16 bytes) |
499 | * - rdma segment (16 bytes) |
500 | * - scatter elements (16 bytes each) |
501 | */ |
502 | MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 |
503 | }; |
504 | |
505 | enum mlx5_odp_transport_cap_bits { |
506 | MLX5_ODP_SUPPORT_SEND = 1 << 31, |
507 | MLX5_ODP_SUPPORT_RECV = 1 << 30, |
508 | MLX5_ODP_SUPPORT_WRITE = 1 << 29, |
509 | MLX5_ODP_SUPPORT_READ = 1 << 28, |
510 | }; |
511 | |
512 | struct mlx5_odp_caps { |
513 | char reserved[0x10]; |
514 | struct { |
515 | __be32 rc_odp_caps; |
516 | __be32 uc_odp_caps; |
517 | __be32 ud_odp_caps; |
518 | } per_transport_caps; |
519 | char reserved2[0xe4]; |
520 | }; |
521 | |
522 | struct mlx5_cmd_layout { |
523 | u8 type; |
524 | u8 rsvd0[3]; |
525 | __be32 inlen; |
526 | __be64 in_ptr; |
527 | __be32 in[4]; |
528 | __be32 out[4]; |
529 | __be64 out_ptr; |
530 | __be32 outlen; |
531 | u8 token; |
532 | u8 sig; |
533 | u8 rsvd1; |
534 | u8 status_own; |
535 | }; |
536 | |
537 | enum mlx5_rfr_severity_bit_offsets { |
538 | MLX5_RFR_BIT_OFFSET = 0x7, |
539 | }; |
540 | |
541 | struct health_buffer { |
542 | __be32 assert_var[6]; |
543 | __be32 rsvd0[2]; |
544 | __be32 assert_exit_ptr; |
545 | __be32 assert_callra; |
546 | __be32 rsvd1[1]; |
547 | __be32 time; |
548 | __be32 fw_ver; |
549 | __be32 hw_id; |
550 | u8 rfr_severity; |
551 | u8 rsvd2[3]; |
552 | u8 irisc_index; |
553 | u8 synd; |
554 | __be16 ext_synd; |
555 | }; |
556 | |
557 | enum mlx5_initializing_bit_offsets { |
558 | MLX5_FW_RESET_SUPPORTED_OFFSET = 30, |
559 | }; |
560 | |
561 | enum mlx5_cmd_addr_l_sz_offset { |
562 | MLX5_NIC_IFC_OFFSET = 8, |
563 | }; |
564 | |
565 | struct mlx5_init_seg { |
566 | __be32 fw_rev; |
567 | __be32 cmdif_rev_fw_sub; |
568 | __be32 rsvd0[2]; |
569 | __be32 cmdq_addr_h; |
570 | __be32 cmdq_addr_l_sz; |
571 | __be32 cmd_dbell; |
572 | __be32 rsvd1[120]; |
573 | __be32 initializing; |
574 | struct health_buffer health; |
575 | __be32 rsvd2[878]; |
576 | __be32 cmd_exec_to; |
577 | __be32 cmd_q_init_to; |
578 | __be32 internal_timer_h; |
579 | __be32 internal_timer_l; |
580 | __be32 rsvd3[2]; |
581 | __be32 health_counter; |
582 | __be32 rsvd4[11]; |
583 | __be32 real_time_h; |
584 | __be32 real_time_l; |
585 | __be32 rsvd5[1006]; |
586 | __be64 ieee1588_clk; |
587 | __be32 ieee1588_clk_type; |
588 | __be32 clr_intx; |
589 | }; |
590 | |
591 | struct mlx5_eqe_comp { |
592 | __be32 reserved[6]; |
593 | __be32 cqn; |
594 | }; |
595 | |
596 | struct mlx5_eqe_qp_srq { |
597 | __be32 reserved1[5]; |
598 | u8 type; |
599 | u8 reserved2[3]; |
600 | __be32 qp_srq_n; |
601 | }; |
602 | |
603 | struct mlx5_eqe_cq_err { |
604 | __be32 cqn; |
605 | u8 reserved1[7]; |
606 | u8 syndrome; |
607 | }; |
608 | |
609 | struct mlx5_eqe_xrq_err { |
610 | __be32 reserved1[5]; |
611 | __be32 type_xrqn; |
612 | __be32 reserved2; |
613 | }; |
614 | |
615 | struct mlx5_eqe_port_state { |
616 | u8 reserved0[8]; |
617 | u8 port; |
618 | }; |
619 | |
620 | struct mlx5_eqe_gpio { |
621 | __be32 reserved0[2]; |
622 | __be64 gpio_event; |
623 | }; |
624 | |
625 | struct mlx5_eqe_congestion { |
626 | u8 type; |
627 | u8 rsvd0; |
628 | u8 congestion_level; |
629 | }; |
630 | |
631 | struct mlx5_eqe_stall_vl { |
632 | u8 rsvd0[3]; |
633 | u8 port_vl; |
634 | }; |
635 | |
636 | struct mlx5_eqe_cmd { |
637 | __be32 vector; |
638 | __be32 rsvd[6]; |
639 | }; |
640 | |
641 | struct mlx5_eqe_page_req { |
642 | __be16 ec_function; |
643 | __be16 func_id; |
644 | __be32 num_pages; |
645 | __be32 rsvd1[5]; |
646 | }; |
647 | |
648 | struct mlx5_eqe_page_fault { |
649 | __be32 bytes_committed; |
650 | union { |
651 | struct { |
652 | u16 reserved1; |
653 | __be16 wqe_index; |
654 | u16 reserved2; |
655 | __be16 packet_length; |
656 | __be32 token; |
657 | u8 reserved4[8]; |
658 | __be32 pftype_wq; |
659 | } __packed wqe; |
660 | struct { |
661 | __be32 r_key; |
662 | u16 reserved1; |
663 | __be16 packet_length; |
664 | __be32 rdma_op_len; |
665 | __be64 rdma_va; |
666 | __be32 pftype_token; |
667 | } __packed rdma; |
668 | } __packed; |
669 | } __packed; |
670 | |
671 | struct mlx5_eqe_vport_change { |
672 | u8 rsvd0[2]; |
673 | __be16 vport_num; |
674 | __be32 rsvd1[6]; |
675 | } __packed; |
676 | |
677 | struct mlx5_eqe_port_module { |
678 | u8 reserved_at_0[1]; |
679 | u8 module; |
680 | u8 reserved_at_2[1]; |
681 | u8 module_status; |
682 | u8 reserved_at_4[2]; |
683 | u8 error_type; |
684 | } __packed; |
685 | |
686 | struct mlx5_eqe_pps { |
687 | u8 rsvd0[3]; |
688 | u8 pin; |
689 | u8 rsvd1[4]; |
690 | union { |
691 | struct { |
692 | __be32 time_sec; |
693 | __be32 time_nsec; |
694 | }; |
695 | struct { |
696 | __be64 time_stamp; |
697 | }; |
698 | }; |
699 | u8 rsvd2[12]; |
700 | } __packed; |
701 | |
702 | struct mlx5_eqe_dct { |
703 | __be32 reserved[6]; |
704 | __be32 dctn; |
705 | }; |
706 | |
707 | struct mlx5_eqe_temp_warning { |
708 | __be64 sensor_warning_msb; |
709 | __be64 sensor_warning_lsb; |
710 | } __packed; |
711 | |
712 | struct mlx5_eqe_obj_change { |
713 | u8 rsvd0[2]; |
714 | __be16 obj_type; |
715 | __be32 obj_id; |
716 | } __packed; |
717 | |
718 | #define SYNC_RST_STATE_MASK 0xf |
719 | |
720 | enum sync_rst_state_type { |
721 | MLX5_SYNC_RST_STATE_RESET_REQUEST = 0x0, |
722 | MLX5_SYNC_RST_STATE_RESET_NOW = 0x1, |
723 | MLX5_SYNC_RST_STATE_RESET_ABORT = 0x2, |
724 | MLX5_SYNC_RST_STATE_RESET_UNLOAD = 0x3, |
725 | }; |
726 | |
727 | struct mlx5_eqe_sync_fw_update { |
728 | u8 reserved_at_0[3]; |
729 | u8 sync_rst_state; |
730 | }; |
731 | |
732 | struct mlx5_eqe_vhca_state { |
733 | __be16 ec_function; |
734 | __be16 function_id; |
735 | } __packed; |
736 | |
737 | union ev_data { |
738 | __be32 raw[7]; |
739 | struct mlx5_eqe_cmd cmd; |
740 | struct mlx5_eqe_comp comp; |
741 | struct mlx5_eqe_qp_srq qp_srq; |
742 | struct mlx5_eqe_cq_err cq_err; |
743 | struct mlx5_eqe_port_state port; |
744 | struct mlx5_eqe_gpio gpio; |
745 | struct mlx5_eqe_congestion cong; |
746 | struct mlx5_eqe_stall_vl stall_vl; |
747 | struct mlx5_eqe_page_req req_pages; |
748 | struct mlx5_eqe_page_fault page_fault; |
749 | struct mlx5_eqe_vport_change vport_change; |
750 | struct mlx5_eqe_port_module port_module; |
751 | struct mlx5_eqe_pps pps; |
752 | struct mlx5_eqe_dct dct; |
753 | struct mlx5_eqe_temp_warning temp_warning; |
754 | struct mlx5_eqe_xrq_err xrq_err; |
755 | struct mlx5_eqe_sync_fw_update sync_fw_update; |
756 | struct mlx5_eqe_vhca_state vhca_state; |
757 | struct mlx5_eqe_obj_change obj_change; |
758 | } __packed; |
759 | |
760 | struct mlx5_eqe { |
761 | u8 rsvd0; |
762 | u8 type; |
763 | u8 rsvd1; |
764 | u8 sub_type; |
765 | __be32 rsvd2[7]; |
766 | union ev_data data; |
767 | __be16 rsvd3; |
768 | u8 signature; |
769 | u8 owner; |
770 | } __packed; |
771 | |
772 | struct mlx5_cmd_prot_block { |
773 | u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; |
774 | u8 rsvd0[48]; |
775 | __be64 next; |
776 | __be32 block_num; |
777 | u8 rsvd1; |
778 | u8 token; |
779 | u8 ctrl_sig; |
780 | u8 sig; |
781 | }; |
782 | |
783 | enum { |
784 | MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, |
785 | }; |
786 | |
787 | struct mlx5_err_cqe { |
788 | u8 rsvd0[32]; |
789 | __be32 srqn; |
790 | u8 rsvd1[18]; |
791 | u8 vendor_err_synd; |
792 | u8 syndrome; |
793 | __be32 s_wqe_opcode_qpn; |
794 | __be16 wqe_counter; |
795 | u8 signature; |
796 | u8 op_own; |
797 | }; |
798 | |
799 | struct mlx5_cqe64 { |
800 | u8 tls_outer_l3_tunneled; |
801 | u8 rsvd0; |
802 | __be16 wqe_id; |
803 | union { |
804 | struct { |
805 | u8 tcppsh_abort_dupack; |
806 | u8 min_ttl; |
807 | __be16 tcp_win; |
808 | __be32 ack_seq_num; |
809 | } lro; |
810 | struct { |
811 | u8 reserved0:1; |
812 | u8 match:1; |
813 | u8 flush:1; |
814 | u8 reserved3:5; |
815 | u8 ; |
816 | __be16 ; |
817 | __be32 data_offset; |
818 | } shampo; |
819 | }; |
820 | __be32 ; |
821 | u8 ; |
822 | u8 ml_path; |
823 | u8 rsvd20[2]; |
824 | __be16 check_sum; |
825 | __be16 slid; |
826 | __be32 flags_rqpn; |
827 | u8 hds_ip_ext; |
828 | u8 l4_l3_hdr_type; |
829 | __be16 vlan_info; |
830 | __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ |
831 | union { |
832 | __be32 immediate; |
833 | __be32 inval_rkey; |
834 | __be32 pkey; |
835 | __be32 ft_metadata; |
836 | }; |
837 | u8 rsvd40[4]; |
838 | __be32 byte_cnt; |
839 | __be32 timestamp_h; |
840 | __be32 timestamp_l; |
841 | __be32 sop_drop_qpn; |
842 | __be16 wqe_counter; |
843 | union { |
844 | u8 signature; |
845 | u8 validity_iteration_count; |
846 | }; |
847 | u8 op_own; |
848 | }; |
849 | |
850 | struct mlx5_mini_cqe8 { |
851 | union { |
852 | __be32 rx_hash_result; |
853 | struct { |
854 | __be16 checksum; |
855 | __be16 stridx; |
856 | }; |
857 | struct { |
858 | __be16 wqe_counter; |
859 | u8 s_wqe_opcode; |
860 | u8 reserved; |
861 | } s_wqe_info; |
862 | }; |
863 | __be32 byte_cnt; |
864 | }; |
865 | |
866 | enum { |
867 | MLX5_NO_INLINE_DATA, |
868 | MLX5_INLINE_DATA32_SEG, |
869 | MLX5_INLINE_DATA64_SEG, |
870 | MLX5_COMPRESSED, |
871 | }; |
872 | |
873 | enum { |
874 | MLX5_CQE_FORMAT_CSUM = 0x1, |
875 | MLX5_CQE_FORMAT_CSUM_STRIDX = 0x3, |
876 | }; |
877 | |
878 | enum { |
879 | MLX5_CQE_COMPRESS_LAYOUT_BASIC = 0, |
880 | MLX5_CQE_COMPRESS_LAYOUT_ENHANCED = 1, |
881 | }; |
882 | |
883 | #define MLX5_MINI_CQE_ARRAY_SIZE 8 |
884 | |
885 | static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe) |
886 | { |
887 | return (cqe->op_own >> 2) & 0x3; |
888 | } |
889 | |
890 | static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe) |
891 | { |
892 | return cqe->op_own >> 4; |
893 | } |
894 | |
895 | static inline u8 get_cqe_enhanced_num_mini_cqes(struct mlx5_cqe64 *cqe) |
896 | { |
897 | /* num_of_mini_cqes is zero based */ |
898 | return get_cqe_opcode(cqe) + 1; |
899 | } |
900 | |
901 | static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) |
902 | { |
903 | return (cqe->lro.tcppsh_abort_dupack >> 6) & 1; |
904 | } |
905 | |
906 | static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) |
907 | { |
908 | return (cqe->l4_l3_hdr_type >> 4) & 0x7; |
909 | } |
910 | |
911 | static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) |
912 | { |
913 | return cqe->tls_outer_l3_tunneled & 0x1; |
914 | } |
915 | |
916 | static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe) |
917 | { |
918 | return (cqe->tls_outer_l3_tunneled >> 3) & 0x3; |
919 | } |
920 | |
921 | static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) |
922 | { |
923 | return cqe->l4_l3_hdr_type & 0x1; |
924 | } |
925 | |
926 | static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe) |
927 | { |
928 | u32 hi, lo; |
929 | |
930 | hi = be32_to_cpu(cqe->timestamp_h); |
931 | lo = be32_to_cpu(cqe->timestamp_l); |
932 | |
933 | return (u64)lo | ((u64)hi << 32); |
934 | } |
935 | |
936 | static inline u16 get_cqe_flow_tag(struct mlx5_cqe64 *cqe) |
937 | { |
938 | return be32_to_cpu(cqe->sop_drop_qpn) & 0xFFF; |
939 | } |
940 | |
941 | #define MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE 3 |
942 | #define MLX5_MPWQE_LOG_NUM_STRIDES_BASE 9 |
943 | #define MLX5_MPWQE_LOG_NUM_STRIDES_MAX 16 |
944 | #define MLX5_MPWQE_LOG_STRIDE_SZ_BASE 6 |
945 | #define MLX5_MPWQE_LOG_STRIDE_SZ_MAX 13 |
946 | |
947 | struct mpwrq_cqe_bc { |
948 | __be16 filler_consumed_strides; |
949 | __be16 byte_cnt; |
950 | }; |
951 | |
952 | static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe) |
953 | { |
954 | struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; |
955 | |
956 | return be16_to_cpu(bc->byte_cnt); |
957 | } |
958 | |
959 | static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc) |
960 | { |
961 | return 0x7fff & be16_to_cpu(bc->filler_consumed_strides); |
962 | } |
963 | |
964 | static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe) |
965 | { |
966 | struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; |
967 | |
968 | return mpwrq_get_cqe_bc_consumed_strides(bc); |
969 | } |
970 | |
971 | static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe) |
972 | { |
973 | struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt; |
974 | |
975 | return 0x8000 & be16_to_cpu(bc->filler_consumed_strides); |
976 | } |
977 | |
978 | static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe) |
979 | { |
980 | return be16_to_cpu(cqe->wqe_counter); |
981 | } |
982 | |
983 | enum { |
984 | CQE_L4_HDR_TYPE_NONE = 0x0, |
985 | CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, |
986 | CQE_L4_HDR_TYPE_UDP = 0x2, |
987 | CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, |
988 | CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, |
989 | }; |
990 | |
991 | enum { |
992 | = GENMASK(3, 2), |
993 | /* cqe->rss_hash_type[3:2] - IP destination selected for hash |
994 | * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved) |
995 | */ |
996 | = 0x0, |
997 | = 0x1, |
998 | = 0x2, |
999 | = 0x3, |
1000 | |
1001 | = GENMASK(7, 6), |
1002 | /* cqe->rss_hash_type[7:6] - L4 destination selected for hash |
1003 | * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI |
1004 | */ |
1005 | = 0x0, |
1006 | = 0x1, |
1007 | = 0x2, |
1008 | = 0x3, |
1009 | }; |
1010 | |
1011 | enum { |
1012 | = 0x0, |
1013 | = 0x1, |
1014 | = 0x2, |
1015 | }; |
1016 | |
1017 | enum { |
1018 | CQE_L2_OK = 1 << 0, |
1019 | CQE_L3_OK = 1 << 1, |
1020 | CQE_L4_OK = 1 << 2, |
1021 | }; |
1022 | |
1023 | enum { |
1024 | CQE_TLS_OFFLOAD_NOT_DECRYPTED = 0x0, |
1025 | CQE_TLS_OFFLOAD_DECRYPTED = 0x1, |
1026 | CQE_TLS_OFFLOAD_RESYNC = 0x2, |
1027 | CQE_TLS_OFFLOAD_ERROR = 0x3, |
1028 | }; |
1029 | |
1030 | struct mlx5_sig_err_cqe { |
1031 | u8 rsvd0[16]; |
1032 | __be32 expected_trans_sig; |
1033 | __be32 actual_trans_sig; |
1034 | __be32 expected_reftag; |
1035 | __be32 actual_reftag; |
1036 | __be16 syndrome; |
1037 | u8 rsvd22[2]; |
1038 | __be32 mkey; |
1039 | __be64 err_offset; |
1040 | u8 rsvd30[8]; |
1041 | __be32 qpn; |
1042 | u8 rsvd38[2]; |
1043 | u8 signature; |
1044 | u8 op_own; |
1045 | }; |
1046 | |
1047 | struct mlx5_wqe_srq_next_seg { |
1048 | u8 rsvd0[2]; |
1049 | __be16 next_wqe_index; |
1050 | u8 signature; |
1051 | u8 rsvd1[11]; |
1052 | }; |
1053 | |
1054 | union mlx5_ext_cqe { |
1055 | struct ib_grh grh; |
1056 | u8 inl[64]; |
1057 | }; |
1058 | |
1059 | struct mlx5_cqe128 { |
1060 | union mlx5_ext_cqe inl_grh; |
1061 | struct mlx5_cqe64 cqe64; |
1062 | }; |
1063 | |
1064 | enum { |
1065 | MLX5_MKEY_STATUS_FREE = 1 << 6, |
1066 | }; |
1067 | |
1068 | enum { |
1069 | MLX5_MKEY_REMOTE_INVAL = 1 << 24, |
1070 | MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, |
1071 | MLX5_MKEY_BSF_EN = 1 << 30, |
1072 | }; |
1073 | |
1074 | struct mlx5_mkey_seg { |
1075 | /* This is a two bit field occupying bits 31-30. |
1076 | * bit 31 is always 0, |
1077 | * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have translation |
1078 | */ |
1079 | u8 status; |
1080 | u8 pcie_control; |
1081 | u8 flags; |
1082 | u8 version; |
1083 | __be32 qpn_mkey7_0; |
1084 | u8 rsvd1[4]; |
1085 | __be32 flags_pd; |
1086 | __be64 start_addr; |
1087 | __be64 len; |
1088 | __be32 bsfs_octo_size; |
1089 | u8 rsvd2[16]; |
1090 | __be32 xlt_oct_size; |
1091 | u8 rsvd3[3]; |
1092 | u8 log2_page_size; |
1093 | u8 rsvd4[4]; |
1094 | }; |
1095 | |
1096 | #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) |
1097 | |
1098 | enum { |
1099 | MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 |
1100 | }; |
1101 | |
1102 | enum { |
1103 | VPORT_STATE_DOWN = 0x0, |
1104 | VPORT_STATE_UP = 0x1, |
1105 | }; |
1106 | |
1107 | enum { |
1108 | MLX5_VPORT_ADMIN_STATE_DOWN = 0x0, |
1109 | MLX5_VPORT_ADMIN_STATE_UP = 0x1, |
1110 | MLX5_VPORT_ADMIN_STATE_AUTO = 0x2, |
1111 | }; |
1112 | |
1113 | enum { |
1114 | MLX5_VPORT_CVLAN_INSERT_WHEN_NO_CVLAN = 0x1, |
1115 | MLX5_VPORT_CVLAN_INSERT_ALWAYS = 0x3, |
1116 | }; |
1117 | |
1118 | enum { |
1119 | MLX5_L3_PROT_TYPE_IPV4 = 0, |
1120 | MLX5_L3_PROT_TYPE_IPV6 = 1, |
1121 | }; |
1122 | |
1123 | enum { |
1124 | MLX5_L4_PROT_TYPE_TCP = 0, |
1125 | MLX5_L4_PROT_TYPE_UDP = 1, |
1126 | }; |
1127 | |
1128 | enum { |
1129 | MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, |
1130 | MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, |
1131 | MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, |
1132 | MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, |
1133 | MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, |
1134 | }; |
1135 | |
1136 | enum { |
1137 | = 1 << 0, |
1138 | MLX5_MATCH_MISC_PARAMETERS = 1 << 1, |
1139 | = 1 << 2, |
1140 | MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3, |
1141 | MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4, |
1142 | MLX5_MATCH_MISC_PARAMETERS_4 = 1 << 5, |
1143 | MLX5_MATCH_MISC_PARAMETERS_5 = 1 << 6, |
1144 | }; |
1145 | |
1146 | enum { |
1147 | MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, |
1148 | MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, |
1149 | }; |
1150 | |
1151 | enum { |
1152 | MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0, |
1153 | MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1, |
1154 | MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2, |
1155 | }; |
1156 | |
1157 | enum mlx5_list_type { |
1158 | MLX5_NVPRT_LIST_TYPE_UC = 0x0, |
1159 | MLX5_NVPRT_LIST_TYPE_MC = 0x1, |
1160 | MLX5_NVPRT_LIST_TYPE_VLAN = 0x2, |
1161 | }; |
1162 | |
1163 | enum { |
1164 | MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, |
1165 | MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1, |
1166 | }; |
1167 | |
1168 | enum mlx5_wol_mode { |
1169 | MLX5_WOL_DISABLE = 0, |
1170 | MLX5_WOL_SECURED_MAGIC = 1 << 1, |
1171 | MLX5_WOL_MAGIC = 1 << 2, |
1172 | MLX5_WOL_ARP = 1 << 3, |
1173 | MLX5_WOL_BROADCAST = 1 << 4, |
1174 | MLX5_WOL_MULTICAST = 1 << 5, |
1175 | MLX5_WOL_UNICAST = 1 << 6, |
1176 | MLX5_WOL_PHY_ACTIVITY = 1 << 7, |
1177 | }; |
1178 | |
1179 | enum mlx5_mpls_supported_fields { |
1180 | MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0, |
1181 | MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1, |
1182 | MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2, |
1183 | MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3 |
1184 | }; |
1185 | |
1186 | enum mlx5_flex_parser_protos { |
1187 | MLX5_FLEX_PROTO_GENEVE = 1 << 3, |
1188 | MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4, |
1189 | MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5, |
1190 | MLX5_FLEX_PROTO_ICMP = 1 << 8, |
1191 | MLX5_FLEX_PROTO_ICMPV6 = 1 << 9, |
1192 | }; |
1193 | |
1194 | /* MLX5 DEV CAPs */ |
1195 | |
1196 | /* TODO: EAT.ME */ |
1197 | enum mlx5_cap_mode { |
1198 | HCA_CAP_OPMOD_GET_MAX = 0, |
1199 | HCA_CAP_OPMOD_GET_CUR = 1, |
1200 | }; |
1201 | |
1202 | /* Any new cap addition must update mlx5_hca_caps_alloc() to allocate |
1203 | * capability memory. |
1204 | */ |
1205 | enum mlx5_cap_type { |
1206 | MLX5_CAP_GENERAL = 0, |
1207 | MLX5_CAP_ETHERNET_OFFLOADS, |
1208 | MLX5_CAP_ODP, |
1209 | MLX5_CAP_ATOMIC, |
1210 | MLX5_CAP_ROCE, |
1211 | MLX5_CAP_IPOIB_OFFLOADS, |
1212 | MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, |
1213 | MLX5_CAP_FLOW_TABLE, |
1214 | MLX5_CAP_ESWITCH_FLOW_TABLE, |
1215 | MLX5_CAP_ESWITCH, |
1216 | MLX5_CAP_QOS = 0xc, |
1217 | MLX5_CAP_DEBUG, |
1218 | MLX5_CAP_RESERVED_14, |
1219 | MLX5_CAP_DEV_MEM, |
1220 | MLX5_CAP_RESERVED_16, |
1221 | MLX5_CAP_TLS, |
1222 | MLX5_CAP_VDPA_EMULATION = 0x13, |
1223 | MLX5_CAP_DEV_EVENT = 0x14, |
1224 | MLX5_CAP_IPSEC, |
1225 | MLX5_CAP_CRYPTO = 0x1a, |
1226 | MLX5_CAP_MACSEC = 0x1f, |
1227 | MLX5_CAP_GENERAL_2 = 0x20, |
1228 | MLX5_CAP_PORT_SELECTION = 0x25, |
1229 | MLX5_CAP_ADV_VIRTUALIZATION = 0x26, |
1230 | /* NUM OF CAP Types */ |
1231 | MLX5_CAP_NUM |
1232 | }; |
1233 | |
1234 | enum mlx5_pcam_reg_groups { |
1235 | MLX5_PCAM_REGS_5000_TO_507F = 0x0, |
1236 | }; |
1237 | |
1238 | enum mlx5_pcam_feature_groups { |
1239 | MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0, |
1240 | }; |
1241 | |
1242 | enum mlx5_mcam_reg_groups { |
1243 | MLX5_MCAM_REGS_FIRST_128 = 0x0, |
1244 | MLX5_MCAM_REGS_0x9100_0x917F = 0x2, |
1245 | MLX5_MCAM_REGS_NUM = 0x3, |
1246 | }; |
1247 | |
1248 | enum mlx5_mcam_feature_groups { |
1249 | MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0, |
1250 | }; |
1251 | |
1252 | enum mlx5_qcam_reg_groups { |
1253 | MLX5_QCAM_REGS_FIRST_128 = 0x0, |
1254 | }; |
1255 | |
1256 | enum mlx5_qcam_feature_groups { |
1257 | MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0, |
1258 | }; |
1259 | |
1260 | /* GET Dev Caps macros */ |
1261 | #define MLX5_CAP_GEN(mdev, cap) \ |
1262 | MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap) |
1263 | |
1264 | #define MLX5_CAP_GEN_64(mdev, cap) \ |
1265 | MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap) |
1266 | |
1267 | #define MLX5_CAP_GEN_MAX(mdev, cap) \ |
1268 | MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap) |
1269 | |
1270 | #define MLX5_CAP_GEN_2(mdev, cap) \ |
1271 | MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap) |
1272 | |
1273 | #define MLX5_CAP_GEN_2_64(mdev, cap) \ |
1274 | MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap) |
1275 | |
1276 | #define MLX5_CAP_GEN_2_MAX(mdev, cap) \ |
1277 | MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap) |
1278 | |
1279 | #define MLX5_CAP_ETH(mdev, cap) \ |
1280 | MLX5_GET(per_protocol_networking_offload_caps,\ |
1281 | mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap) |
1282 | |
1283 | #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \ |
1284 | MLX5_GET(per_protocol_networking_offload_caps,\ |
1285 | mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap) |
1286 | |
1287 | #define MLX5_CAP_ROCE(mdev, cap) \ |
1288 | MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap) |
1289 | |
1290 | #define MLX5_CAP_ROCE_MAX(mdev, cap) \ |
1291 | MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap) |
1292 | |
1293 | #define MLX5_CAP_ATOMIC(mdev, cap) \ |
1294 | MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap) |
1295 | |
1296 | #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ |
1297 | MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap) |
1298 | |
1299 | #define MLX5_CAP_FLOWTABLE(mdev, cap) \ |
1300 | MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap) |
1301 | |
1302 | #define MLX5_CAP64_FLOWTABLE(mdev, cap) \ |
1303 | MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap) |
1304 | |
1305 | #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \ |
1306 | MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap) |
1307 | |
1308 | #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \ |
1309 | MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap) |
1310 | |
1311 | #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \ |
1312 | MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap) |
1313 | |
1314 | #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \ |
1315 | MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap) |
1316 | |
1317 | #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \ |
1318 | MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap) |
1319 | |
1320 | #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \ |
1321 | MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap) |
1322 | |
1323 | #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ |
1324 | MLX5_GET(flow_table_eswitch_cap, \ |
1325 | mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap) |
1326 | |
1327 | #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ |
1328 | MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) |
1329 | |
1330 | #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ |
1331 | MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) |
1332 | |
1333 | #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ |
1334 | MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) |
1335 | |
1336 | #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \ |
1337 | MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap) |
1338 | |
1339 | #define MLX5_CAP_ESW(mdev, cap) \ |
1340 | MLX5_GET(e_switch_cap, \ |
1341 | mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap) |
1342 | |
1343 | #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \ |
1344 | MLX5_GET64(flow_table_eswitch_cap, \ |
1345 | (mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap) |
1346 | |
1347 | #define MLX5_CAP_PORT_SELECTION(mdev, cap) \ |
1348 | MLX5_GET(port_selection_cap, \ |
1349 | mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap) |
1350 | |
1351 | #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \ |
1352 | MLX5_GET(port_selection_cap, \ |
1353 | mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap) |
1354 | |
1355 | #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \ |
1356 | MLX5_GET(adv_virtualization_cap, \ |
1357 | mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap) |
1358 | |
1359 | #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \ |
1360 | MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap) |
1361 | |
1362 | #define MLX5_CAP_ODP(mdev, cap)\ |
1363 | MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap) |
1364 | |
1365 | #define MLX5_CAP_ODP_MAX(mdev, cap)\ |
1366 | MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap) |
1367 | |
1368 | #define MLX5_CAP_QOS(mdev, cap)\ |
1369 | MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap) |
1370 | |
1371 | #define MLX5_CAP_DEBUG(mdev, cap)\ |
1372 | MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap) |
1373 | |
1374 | #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \ |
1375 | MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld) |
1376 | |
1377 | #define MLX5_CAP_PCAM_REG(mdev, reg) \ |
1378 | MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg) |
1379 | |
1380 | #define MLX5_CAP_MCAM_REG(mdev, reg) \ |
1381 | MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \ |
1382 | mng_access_reg_cap_mask.access_regs.reg) |
1383 | |
1384 | #define MLX5_CAP_MCAM_REG2(mdev, reg) \ |
1385 | MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \ |
1386 | mng_access_reg_cap_mask.access_regs2.reg) |
1387 | |
1388 | #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ |
1389 | MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) |
1390 | |
1391 | #define MLX5_CAP_QCAM_REG(mdev, fld) \ |
1392 | MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld) |
1393 | |
1394 | #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \ |
1395 | MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld) |
1396 | |
1397 | #define MLX5_CAP_FPGA(mdev, cap) \ |
1398 | MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap) |
1399 | |
1400 | #define MLX5_CAP64_FPGA(mdev, cap) \ |
1401 | MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap) |
1402 | |
1403 | #define MLX5_CAP_DEV_MEM(mdev, cap)\ |
1404 | MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap) |
1405 | |
1406 | #define MLX5_CAP64_DEV_MEM(mdev, cap)\ |
1407 | MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap) |
1408 | |
1409 | #define MLX5_CAP_TLS(mdev, cap) \ |
1410 | MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap) |
1411 | |
1412 | #define MLX5_CAP_DEV_EVENT(mdev, cap)\ |
1413 | MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap) |
1414 | |
1415 | #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\ |
1416 | MLX5_GET(virtio_emulation_cap, \ |
1417 | (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap) |
1418 | |
1419 | #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\ |
1420 | MLX5_GET64(virtio_emulation_cap, \ |
1421 | (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap) |
1422 | |
1423 | #define MLX5_CAP_IPSEC(mdev, cap)\ |
1424 | MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap) |
1425 | |
1426 | #define MLX5_CAP_CRYPTO(mdev, cap)\ |
1427 | MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap) |
1428 | |
1429 | #define MLX5_CAP_MACSEC(mdev, cap)\ |
1430 | MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap) |
1431 | |
1432 | enum { |
1433 | MLX5_CMD_STAT_OK = 0x0, |
1434 | MLX5_CMD_STAT_INT_ERR = 0x1, |
1435 | MLX5_CMD_STAT_BAD_OP_ERR = 0x2, |
1436 | MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, |
1437 | MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, |
1438 | MLX5_CMD_STAT_BAD_RES_ERR = 0x5, |
1439 | MLX5_CMD_STAT_RES_BUSY = 0x6, |
1440 | MLX5_CMD_STAT_LIM_ERR = 0x8, |
1441 | MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, |
1442 | MLX5_CMD_STAT_IX_ERR = 0xa, |
1443 | MLX5_CMD_STAT_NO_RES_ERR = 0xf, |
1444 | MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, |
1445 | MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, |
1446 | MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, |
1447 | MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, |
1448 | MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, |
1449 | }; |
1450 | |
1451 | enum { |
1452 | MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, |
1453 | MLX5_RFC_2863_COUNTERS_GROUP = 0x1, |
1454 | MLX5_RFC_2819_COUNTERS_GROUP = 0x2, |
1455 | MLX5_RFC_3635_COUNTERS_GROUP = 0x3, |
1456 | MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, |
1457 | MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, |
1458 | MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, |
1459 | MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, |
1460 | MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13, |
1461 | MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16, |
1462 | MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, |
1463 | }; |
1464 | |
1465 | enum { |
1466 | MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, |
1467 | }; |
1468 | |
1469 | static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) |
1470 | { |
1471 | if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) |
1472 | return 0; |
1473 | return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; |
1474 | } |
1475 | |
1476 | #define MLX5_RDMA_RX_NUM_COUNTERS_PRIOS 2 |
1477 | #define MLX5_RDMA_TX_NUM_COUNTERS_PRIOS 1 |
1478 | #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16 |
1479 | #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16 |
1480 | #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1 |
1481 | #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\ |
1482 | MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\ |
1483 | MLX5_BY_PASS_NUM_MULTICAST_PRIOS) |
1484 | |
1485 | #endif /* MLX5_DEVICE_H */ |
1486 | |