1/*
2 * Qualcomm Atheros IPQ806x GMAC glue layer
3 *
4 * Copyright (C) 2015 The Linux Foundation
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19#include <linux/device.h>
20#include <linux/platform_device.h>
21#include <linux/phy.h>
22#include <linux/regmap.h>
23#include <linux/clk.h>
24#include <linux/reset.h>
25#include <linux/of_net.h>
26#include <linux/mfd/syscon.h>
27#include <linux/stmmac.h>
28#include <linux/of_mdio.h>
29#include <linux/module.h>
30#include <linux/sys_soc.h>
31#include <linux/bitfield.h>
32
33#include "stmmac_platform.h"
34
35#define NSS_COMMON_CLK_GATE 0x8
36#define NSS_COMMON_CLK_GATE_PTP_EN(x) BIT(0x10 + x)
37#define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x) BIT(0x9 + (x * 2))
38#define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x) BIT(0x8 + (x * 2))
39#define NSS_COMMON_CLK_GATE_GMII_RX_EN(x) BIT(0x4 + x)
40#define NSS_COMMON_CLK_GATE_GMII_TX_EN(x) BIT(0x0 + x)
41
42#define NSS_COMMON_CLK_DIV0 0xC
43#define NSS_COMMON_CLK_DIV_OFFSET(x) (x * 8)
44#define NSS_COMMON_CLK_DIV_MASK 0x7f
45
46#define NSS_COMMON_CLK_SRC_CTRL 0x14
47#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (x)
48/* Mode is coded on 1 bit but is different depending on the MAC ID:
49 * MAC0: QSGMII=0 RGMII=1
50 * MAC1: QSGMII=0 SGMII=0 RGMII=1
51 * MAC2 & MAC3: QSGMII=0 SGMII=1
52 */
53#define NSS_COMMON_CLK_SRC_CTRL_RGMII(x) 1
54#define NSS_COMMON_CLK_SRC_CTRL_SGMII(x) ((x >= 2) ? 1 : 0)
55
56#define NSS_COMMON_GMAC_CTL(x) (0x30 + (x * 4))
57#define NSS_COMMON_GMAC_CTL_CSYS_REQ BIT(19)
58#define NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL BIT(16)
59#define NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET 8
60#define NSS_COMMON_GMAC_CTL_IFG_OFFSET 0
61
62#define NSS_COMMON_CLK_DIV_RGMII_1000 1
63#define NSS_COMMON_CLK_DIV_RGMII_100 9
64#define NSS_COMMON_CLK_DIV_RGMII_10 99
65#define NSS_COMMON_CLK_DIV_SGMII_1000 0
66#define NSS_COMMON_CLK_DIV_SGMII_100 4
67#define NSS_COMMON_CLK_DIV_SGMII_10 49
68
69#define QSGMII_PCS_ALL_CH_CTL 0x80
70#define QSGMII_PCS_CH_SPEED_FORCE BIT(1)
71#define QSGMII_PCS_CH_SPEED_10 0x0
72#define QSGMII_PCS_CH_SPEED_100 BIT(2)
73#define QSGMII_PCS_CH_SPEED_1000 BIT(3)
74#define QSGMII_PCS_CH_SPEED_MASK (QSGMII_PCS_CH_SPEED_FORCE | \
75 QSGMII_PCS_CH_SPEED_10 | \
76 QSGMII_PCS_CH_SPEED_100 | \
77 QSGMII_PCS_CH_SPEED_1000)
78#define QSGMII_PCS_CH_SPEED_SHIFT(x) ((x) * 4)
79
80#define QSGMII_PCS_CAL_LCKDT_CTL 0x120
81#define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19)
82
83/* Only GMAC1/2/3 support SGMII and their CTL register are not contiguous */
84#define QSGMII_PHY_SGMII_CTL(x) ((x == 1) ? 0x134 : \
85 (0x13c + (4 * (x - 2))))
86#define QSGMII_PHY_CDR_EN BIT(0)
87#define QSGMII_PHY_RX_FRONT_EN BIT(1)
88#define QSGMII_PHY_RX_SIGNAL_DETECT_EN BIT(2)
89#define QSGMII_PHY_TX_DRIVER_EN BIT(3)
90#define QSGMII_PHY_QSGMII_EN BIT(7)
91#define QSGMII_PHY_DEEMPHASIS_LVL_MASK GENMASK(11, 10)
92#define QSGMII_PHY_DEEMPHASIS_LVL(x) FIELD_PREP(QSGMII_PHY_DEEMPHASIS_LVL_MASK, (x))
93#define QSGMII_PHY_PHASE_LOOP_GAIN_MASK GENMASK(14, 12)
94#define QSGMII_PHY_PHASE_LOOP_GAIN(x) FIELD_PREP(QSGMII_PHY_PHASE_LOOP_GAIN_MASK, (x))
95#define QSGMII_PHY_RX_DC_BIAS_MASK GENMASK(19, 18)
96#define QSGMII_PHY_RX_DC_BIAS(x) FIELD_PREP(QSGMII_PHY_RX_DC_BIAS_MASK, (x))
97#define QSGMII_PHY_RX_INPUT_EQU_MASK GENMASK(21, 20)
98#define QSGMII_PHY_RX_INPUT_EQU(x) FIELD_PREP(QSGMII_PHY_RX_INPUT_EQU_MASK, (x))
99#define QSGMII_PHY_CDR_PI_SLEW_MASK GENMASK(23, 22)
100#define QSGMII_PHY_CDR_PI_SLEW(x) FIELD_PREP(QSGMII_PHY_CDR_PI_SLEW_MASK, (x))
101#define QSGMII_PHY_TX_SLEW_MASK GENMASK(27, 26)
102#define QSGMII_PHY_TX_SLEW(x) FIELD_PREP(QSGMII_PHY_TX_SLEW_MASK, (x))
103#define QSGMII_PHY_TX_DRV_AMP_MASK GENMASK(31, 28)
104#define QSGMII_PHY_TX_DRV_AMP(x) FIELD_PREP(QSGMII_PHY_TX_DRV_AMP_MASK, (x))
105
106struct ipq806x_gmac {
107 struct platform_device *pdev;
108 struct regmap *nss_common;
109 struct regmap *qsgmii_csr;
110 uint32_t id;
111 struct clk *core_clk;
112 phy_interface_t phy_mode;
113};
114
115static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, unsigned int speed)
116{
117 struct device *dev = &gmac->pdev->dev;
118 int div;
119
120 switch (speed) {
121 case SPEED_1000:
122 div = NSS_COMMON_CLK_DIV_SGMII_1000;
123 break;
124
125 case SPEED_100:
126 div = NSS_COMMON_CLK_DIV_SGMII_100;
127 break;
128
129 case SPEED_10:
130 div = NSS_COMMON_CLK_DIV_SGMII_10;
131 break;
132
133 default:
134 dev_err(dev, "Speed %dMbps not supported in SGMII\n", speed);
135 return -EINVAL;
136 }
137
138 return div;
139}
140
141static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, unsigned int speed)
142{
143 struct device *dev = &gmac->pdev->dev;
144 int div;
145
146 switch (speed) {
147 case SPEED_1000:
148 div = NSS_COMMON_CLK_DIV_RGMII_1000;
149 break;
150
151 case SPEED_100:
152 div = NSS_COMMON_CLK_DIV_RGMII_100;
153 break;
154
155 case SPEED_10:
156 div = NSS_COMMON_CLK_DIV_RGMII_10;
157 break;
158
159 default:
160 dev_err(dev, "Speed %dMbps not supported in RGMII\n", speed);
161 return -EINVAL;
162 }
163
164 return div;
165}
166
167static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, unsigned int speed)
168{
169 uint32_t clk_bits, val;
170 int div;
171
172 switch (gmac->phy_mode) {
173 case PHY_INTERFACE_MODE_RGMII:
174 div = get_clk_div_rgmii(gmac, speed);
175 clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
176 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
177 break;
178
179 case PHY_INTERFACE_MODE_SGMII:
180 div = get_clk_div_sgmii(gmac, speed);
181 clk_bits = NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) |
182 NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id);
183 break;
184
185 default:
186 dev_err(&gmac->pdev->dev, "Unsupported PHY mode: \"%s\"\n",
187 phy_modes(gmac->phy_mode));
188 return -EINVAL;
189 }
190
191 /* Disable the clocks */
192 regmap_read(map: gmac->nss_common, NSS_COMMON_CLK_GATE, val: &val);
193 val &= ~clk_bits;
194 regmap_write(map: gmac->nss_common, NSS_COMMON_CLK_GATE, val);
195
196 /* Set the divider */
197 regmap_read(map: gmac->nss_common, NSS_COMMON_CLK_DIV0, val: &val);
198 val &= ~(NSS_COMMON_CLK_DIV_MASK
199 << NSS_COMMON_CLK_DIV_OFFSET(gmac->id));
200 val |= div << NSS_COMMON_CLK_DIV_OFFSET(gmac->id);
201 regmap_write(map: gmac->nss_common, NSS_COMMON_CLK_DIV0, val);
202
203 /* Enable the clock back */
204 regmap_read(map: gmac->nss_common, NSS_COMMON_CLK_GATE, val: &val);
205 val |= clk_bits;
206 regmap_write(map: gmac->nss_common, NSS_COMMON_CLK_GATE, val);
207
208 return 0;
209}
210
211static int ipq806x_gmac_of_parse(struct ipq806x_gmac *gmac)
212{
213 struct device *dev = &gmac->pdev->dev;
214 int ret;
215
216 ret = of_get_phy_mode(np: dev->of_node, interface: &gmac->phy_mode);
217 if (ret) {
218 dev_err(dev, "missing phy mode property\n");
219 return -EINVAL;
220 }
221
222 if (of_property_read_u32(np: dev->of_node, propname: "qcom,id", out_value: &gmac->id) < 0) {
223 dev_err(dev, "missing qcom id property\n");
224 return -EINVAL;
225 }
226
227 /* The GMACs are called 1 to 4 in the documentation, but to simplify the
228 * code and keep it consistent with the Linux convention, we'll number
229 * them from 0 to 3 here.
230 */
231 if (gmac->id > 3) {
232 dev_err(dev, "invalid gmac id\n");
233 return -EINVAL;
234 }
235
236 gmac->core_clk = devm_clk_get(dev, id: "stmmaceth");
237 if (IS_ERR(ptr: gmac->core_clk)) {
238 dev_err(dev, "missing stmmaceth clk property\n");
239 return PTR_ERR(ptr: gmac->core_clk);
240 }
241 clk_set_rate(clk: gmac->core_clk, rate: 266000000);
242
243 /* Setup the register map for the nss common registers */
244 gmac->nss_common = syscon_regmap_lookup_by_phandle(np: dev->of_node,
245 property: "qcom,nss-common");
246 if (IS_ERR(ptr: gmac->nss_common)) {
247 dev_err(dev, "missing nss-common node\n");
248 return PTR_ERR(ptr: gmac->nss_common);
249 }
250
251 /* Setup the register map for the qsgmii csr registers */
252 gmac->qsgmii_csr = syscon_regmap_lookup_by_phandle(np: dev->of_node,
253 property: "qcom,qsgmii-csr");
254 if (IS_ERR(ptr: gmac->qsgmii_csr))
255 dev_err(dev, "missing qsgmii-csr node\n");
256
257 return PTR_ERR_OR_ZERO(ptr: gmac->qsgmii_csr);
258}
259
260static void ipq806x_gmac_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode)
261{
262 struct ipq806x_gmac *gmac = priv;
263
264 ipq806x_gmac_set_speed(gmac, speed);
265}
266
267static int
268ipq806x_gmac_configure_qsgmii_pcs_speed(struct ipq806x_gmac *gmac)
269{
270 struct platform_device *pdev = gmac->pdev;
271 struct device *dev = &pdev->dev;
272 struct device_node *dn;
273 int link_speed;
274 int val = 0;
275 int ret;
276
277 /* Some bootloader may apply wrong configuration and cause
278 * not functioning port. If fixed link is not set,
279 * reset the force speed bit.
280 */
281 if (!of_phy_is_fixed_link(np: pdev->dev.of_node))
282 goto write;
283
284 dn = of_get_child_by_name(node: pdev->dev.of_node, name: "fixed-link");
285 ret = of_property_read_u32(np: dn, propname: "speed", out_value: &link_speed);
286 of_node_put(node: dn);
287 if (ret) {
288 dev_err(dev, "found fixed-link node with no speed");
289 return ret;
290 }
291
292 val = QSGMII_PCS_CH_SPEED_FORCE;
293
294 switch (link_speed) {
295 case SPEED_1000:
296 val |= QSGMII_PCS_CH_SPEED_1000;
297 break;
298 case SPEED_100:
299 val |= QSGMII_PCS_CH_SPEED_100;
300 break;
301 case SPEED_10:
302 val |= QSGMII_PCS_CH_SPEED_10;
303 break;
304 }
305
306write:
307 regmap_update_bits(map: gmac->qsgmii_csr, QSGMII_PCS_ALL_CH_CTL,
308 QSGMII_PCS_CH_SPEED_MASK <<
309 QSGMII_PCS_CH_SPEED_SHIFT(gmac->id),
310 val: val <<
311 QSGMII_PCS_CH_SPEED_SHIFT(gmac->id));
312
313 return 0;
314}
315
316static const struct soc_device_attribute ipq806x_gmac_soc_v1[] = {
317 {
318 .revision = "1.*",
319 },
320 {
321 /* sentinel */
322 }
323};
324
325static int
326ipq806x_gmac_configure_qsgmii_params(struct ipq806x_gmac *gmac)
327{
328 struct platform_device *pdev = gmac->pdev;
329 const struct soc_device_attribute *soc;
330 struct device *dev = &pdev->dev;
331 u32 qsgmii_param;
332
333 switch (gmac->id) {
334 case 1:
335 soc = soc_device_match(matches: ipq806x_gmac_soc_v1);
336
337 if (soc)
338 qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xc) |
339 QSGMII_PHY_TX_SLEW(0x2) |
340 QSGMII_PHY_DEEMPHASIS_LVL(0x2);
341 else
342 qsgmii_param = QSGMII_PHY_TX_DRV_AMP(0xd) |
343 QSGMII_PHY_TX_SLEW(0x0) |
344 QSGMII_PHY_DEEMPHASIS_LVL(0x0);
345
346 qsgmii_param |= QSGMII_PHY_RX_DC_BIAS(0x2);
347 break;
348 case 2:
349 case 3:
350 qsgmii_param = QSGMII_PHY_RX_DC_BIAS(0x3) |
351 QSGMII_PHY_TX_DRV_AMP(0xc);
352 break;
353 default: /* gmac 0 can't be set in SGMII mode */
354 dev_err(dev, "gmac id %d can't be in SGMII mode", gmac->id);
355 return -EINVAL;
356 }
357
358 /* Common params across all gmac id */
359 qsgmii_param |= QSGMII_PHY_CDR_EN |
360 QSGMII_PHY_RX_FRONT_EN |
361 QSGMII_PHY_RX_SIGNAL_DETECT_EN |
362 QSGMII_PHY_TX_DRIVER_EN |
363 QSGMII_PHY_QSGMII_EN |
364 QSGMII_PHY_PHASE_LOOP_GAIN(0x4) |
365 QSGMII_PHY_RX_INPUT_EQU(0x1) |
366 QSGMII_PHY_CDR_PI_SLEW(0x2);
367
368 regmap_write(map: gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id),
369 val: qsgmii_param);
370
371 return 0;
372}
373
374static int ipq806x_gmac_probe(struct platform_device *pdev)
375{
376 struct plat_stmmacenet_data *plat_dat;
377 struct stmmac_resources stmmac_res;
378 struct device *dev = &pdev->dev;
379 struct ipq806x_gmac *gmac;
380 int val;
381 int err;
382
383 val = stmmac_get_platform_resources(pdev, stmmac_res: &stmmac_res);
384 if (val)
385 return val;
386
387 plat_dat = devm_stmmac_probe_config_dt(pdev, mac: stmmac_res.mac);
388 if (IS_ERR(ptr: plat_dat))
389 return PTR_ERR(ptr: plat_dat);
390
391 gmac = devm_kzalloc(dev, size: sizeof(*gmac), GFP_KERNEL);
392 if (!gmac)
393 return -ENOMEM;
394
395 gmac->pdev = pdev;
396
397 err = ipq806x_gmac_of_parse(gmac);
398 if (err) {
399 dev_err(dev, "device tree parsing error\n");
400 return err;
401 }
402
403 regmap_write(map: gmac->qsgmii_csr, QSGMII_PCS_CAL_LCKDT_CTL,
404 QSGMII_PCS_CAL_LCKDT_CTL_RST);
405
406 /* Inter frame gap is set to 12 */
407 val = 12 << NSS_COMMON_GMAC_CTL_IFG_OFFSET |
408 12 << NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET;
409 /* We also initiate an AXI low power exit request */
410 val |= NSS_COMMON_GMAC_CTL_CSYS_REQ;
411 switch (gmac->phy_mode) {
412 case PHY_INTERFACE_MODE_RGMII:
413 val |= NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
414 break;
415 case PHY_INTERFACE_MODE_SGMII:
416 val &= ~NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
417 break;
418 default:
419 goto err_unsupported_phy;
420 }
421 regmap_write(map: gmac->nss_common, NSS_COMMON_GMAC_CTL(gmac->id), val);
422
423 /* Configure the clock src according to the mode */
424 regmap_read(map: gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val: &val);
425 val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id));
426 switch (gmac->phy_mode) {
427 case PHY_INTERFACE_MODE_RGMII:
428 val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) <<
429 NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
430 break;
431 case PHY_INTERFACE_MODE_SGMII:
432 val |= NSS_COMMON_CLK_SRC_CTRL_SGMII(gmac->id) <<
433 NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
434 break;
435 default:
436 goto err_unsupported_phy;
437 }
438 regmap_write(map: gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val);
439
440 /* Enable PTP clock */
441 regmap_read(map: gmac->nss_common, NSS_COMMON_CLK_GATE, val: &val);
442 val |= NSS_COMMON_CLK_GATE_PTP_EN(gmac->id);
443 switch (gmac->phy_mode) {
444 case PHY_INTERFACE_MODE_RGMII:
445 val |= NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
446 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
447 break;
448 case PHY_INTERFACE_MODE_SGMII:
449 val |= NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) |
450 NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id);
451 break;
452 default:
453 goto err_unsupported_phy;
454 }
455 regmap_write(map: gmac->nss_common, NSS_COMMON_CLK_GATE, val);
456
457 if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) {
458 err = ipq806x_gmac_configure_qsgmii_params(gmac);
459 if (err)
460 return err;
461
462 err = ipq806x_gmac_configure_qsgmii_pcs_speed(gmac);
463 if (err)
464 return err;
465 }
466
467 plat_dat->has_gmac = true;
468 plat_dat->bsp_priv = gmac;
469 plat_dat->fix_mac_speed = ipq806x_gmac_fix_mac_speed;
470 plat_dat->multicast_filter_bins = 0;
471 plat_dat->tx_fifo_size = 8192;
472 plat_dat->rx_fifo_size = 8192;
473
474 return stmmac_dvr_probe(device: &pdev->dev, plat_dat, res: &stmmac_res);
475
476err_unsupported_phy:
477 dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n",
478 phy_modes(gmac->phy_mode));
479 return -EINVAL;
480}
481
482static const struct of_device_id ipq806x_gmac_dwmac_match[] = {
483 { .compatible = "qcom,ipq806x-gmac" },
484 { }
485};
486MODULE_DEVICE_TABLE(of, ipq806x_gmac_dwmac_match);
487
488static struct platform_driver ipq806x_gmac_dwmac_driver = {
489 .probe = ipq806x_gmac_probe,
490 .remove_new = stmmac_pltfr_remove,
491 .driver = {
492 .name = "ipq806x-gmac-dwmac",
493 .pm = &stmmac_pltfr_pm_ops,
494 .of_match_table = ipq806x_gmac_dwmac_match,
495 },
496};
497module_platform_driver(ipq806x_gmac_dwmac_driver);
498
499MODULE_AUTHOR("Mathieu Olivari <mathieu@codeaurora.org>");
500MODULE_DESCRIPTION("Qualcomm Atheros IPQ806x DWMAC specific glue layer");
501MODULE_LICENSE("Dual BSD/GPL");
502

source code of linux/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c