1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /** |
3 | * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer |
4 | * |
5 | * Copyright (C) 2014 Chen-Zhi (Roger Chen) |
6 | * |
7 | * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com> |
8 | */ |
9 | |
10 | #include <linux/stmmac.h> |
11 | #include <linux/bitops.h> |
12 | #include <linux/clk.h> |
13 | #include <linux/phy.h> |
14 | #include <linux/of_net.h> |
15 | #include <linux/gpio.h> |
16 | #include <linux/module.h> |
17 | #include <linux/of.h> |
18 | #include <linux/of_gpio.h> |
19 | #include <linux/platform_device.h> |
20 | #include <linux/regulator/consumer.h> |
21 | #include <linux/delay.h> |
22 | #include <linux/mfd/syscon.h> |
23 | #include <linux/regmap.h> |
24 | #include <linux/pm_runtime.h> |
25 | |
26 | #include "stmmac_platform.h" |
27 | |
28 | struct rk_priv_data; |
29 | struct rk_gmac_ops { |
30 | void (*set_to_rgmii)(struct rk_priv_data *bsp_priv, |
31 | int tx_delay, int rx_delay); |
32 | void (*set_to_rmii)(struct rk_priv_data *bsp_priv); |
33 | void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed); |
34 | void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed); |
35 | void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, |
36 | bool enable); |
37 | void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); |
38 | bool regs_valid; |
39 | u32 regs[]; |
40 | }; |
41 | |
42 | static const char * const rk_clocks[] = { |
43 | "aclk_mac" , "pclk_mac" , "mac_clk_tx" , "clk_mac_speed" , |
44 | }; |
45 | |
46 | static const char * const rk_rmii_clocks[] = { |
47 | "mac_clk_rx" , "clk_mac_ref" , "clk_mac_refout" , |
48 | }; |
49 | |
50 | enum rk_clocks_index { |
51 | RK_ACLK_MAC = 0, |
52 | RK_PCLK_MAC, |
53 | RK_MAC_CLK_TX, |
54 | RK_CLK_MAC_SPEED, |
55 | RK_MAC_CLK_RX, |
56 | RK_CLK_MAC_REF, |
57 | RK_CLK_MAC_REFOUT, |
58 | }; |
59 | |
60 | struct rk_priv_data { |
61 | struct platform_device *pdev; |
62 | phy_interface_t phy_iface; |
63 | int id; |
64 | struct regulator *regulator; |
65 | bool suspended; |
66 | const struct rk_gmac_ops *ops; |
67 | |
68 | bool clk_enabled; |
69 | bool clock_input; |
70 | bool integrated_phy; |
71 | |
72 | struct clk_bulk_data *clks; |
73 | int num_clks; |
74 | struct clk *clk_mac; |
75 | struct clk *clk_phy; |
76 | |
77 | struct reset_control *phy_reset; |
78 | |
79 | int tx_delay; |
80 | int rx_delay; |
81 | |
82 | struct regmap *grf; |
83 | struct regmap *php_grf; |
84 | }; |
85 | |
86 | #define HIWORD_UPDATE(val, mask, shift) \ |
87 | ((val) << (shift) | (mask) << ((shift) + 16)) |
88 | |
89 | #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16)) |
90 | #define GRF_CLR_BIT(nr) (BIT(nr+16)) |
91 | |
92 | #define DELAY_ENABLE(soc, tx, rx) \ |
93 | (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ |
94 | ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) |
95 | |
96 | #define PX30_GRF_GMAC_CON1 0x0904 |
97 | |
98 | /* PX30_GRF_GMAC_CON1 */ |
99 | #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ |
100 | GRF_BIT(6)) |
101 | #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2) |
102 | #define PX30_GMAC_SPEED_100M GRF_BIT(2) |
103 | |
104 | static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) |
105 | { |
106 | struct device *dev = &bsp_priv->pdev->dev; |
107 | |
108 | if (IS_ERR(ptr: bsp_priv->grf)) { |
109 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
110 | return; |
111 | } |
112 | |
113 | regmap_write(map: bsp_priv->grf, PX30_GRF_GMAC_CON1, |
114 | PX30_GMAC_PHY_INTF_SEL_RMII); |
115 | } |
116 | |
117 | static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
118 | { |
119 | struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; |
120 | struct device *dev = &bsp_priv->pdev->dev; |
121 | int ret; |
122 | |
123 | if (!clk_mac_speed) { |
124 | dev_err(dev, "%s: Missing clk_mac_speed clock\n" , __func__); |
125 | return; |
126 | } |
127 | |
128 | if (speed == 10) { |
129 | regmap_write(map: bsp_priv->grf, PX30_GRF_GMAC_CON1, |
130 | PX30_GMAC_SPEED_10M); |
131 | |
132 | ret = clk_set_rate(clk: clk_mac_speed, rate: 2500000); |
133 | if (ret) |
134 | dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n" , |
135 | __func__, ret); |
136 | } else if (speed == 100) { |
137 | regmap_write(map: bsp_priv->grf, PX30_GRF_GMAC_CON1, |
138 | PX30_GMAC_SPEED_100M); |
139 | |
140 | ret = clk_set_rate(clk: clk_mac_speed, rate: 25000000); |
141 | if (ret) |
142 | dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n" , |
143 | __func__, ret); |
144 | |
145 | } else { |
146 | dev_err(dev, "unknown speed value for RMII! speed=%d" , speed); |
147 | } |
148 | } |
149 | |
150 | static const struct rk_gmac_ops px30_ops = { |
151 | .set_to_rmii = px30_set_to_rmii, |
152 | .set_rmii_speed = px30_set_rmii_speed, |
153 | }; |
154 | |
155 | #define RK3128_GRF_MAC_CON0 0x0168 |
156 | #define RK3128_GRF_MAC_CON1 0x016c |
157 | |
158 | /* RK3128_GRF_MAC_CON0 */ |
159 | #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) |
160 | #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) |
161 | #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) |
162 | #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) |
163 | #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) |
164 | #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) |
165 | |
166 | /* RK3128_GRF_MAC_CON1 */ |
167 | #define RK3128_GMAC_PHY_INTF_SEL_RGMII \ |
168 | (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8)) |
169 | #define RK3128_GMAC_PHY_INTF_SEL_RMII \ |
170 | (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8)) |
171 | #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9) |
172 | #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) |
173 | #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10) |
174 | #define RK3128_GMAC_SPEED_100M GRF_BIT(10) |
175 | #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11) |
176 | #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) |
177 | #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) |
178 | #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) |
179 | #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) |
180 | #define RK3128_GMAC_RMII_MODE GRF_BIT(14) |
181 | #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) |
182 | |
183 | static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, |
184 | int tx_delay, int rx_delay) |
185 | { |
186 | struct device *dev = &bsp_priv->pdev->dev; |
187 | |
188 | if (IS_ERR(ptr: bsp_priv->grf)) { |
189 | dev_err(dev, "Missing rockchip,grf property\n" ); |
190 | return; |
191 | } |
192 | |
193 | regmap_write(map: bsp_priv->grf, RK3128_GRF_MAC_CON1, |
194 | RK3128_GMAC_PHY_INTF_SEL_RGMII | |
195 | RK3128_GMAC_RMII_MODE_CLR); |
196 | regmap_write(map: bsp_priv->grf, RK3128_GRF_MAC_CON0, |
197 | DELAY_ENABLE(RK3128, tx_delay, rx_delay) | |
198 | RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) | |
199 | RK3128_GMAC_CLK_TX_DL_CFG(tx_delay)); |
200 | } |
201 | |
202 | static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) |
203 | { |
204 | struct device *dev = &bsp_priv->pdev->dev; |
205 | |
206 | if (IS_ERR(ptr: bsp_priv->grf)) { |
207 | dev_err(dev, "Missing rockchip,grf property\n" ); |
208 | return; |
209 | } |
210 | |
211 | regmap_write(map: bsp_priv->grf, RK3128_GRF_MAC_CON1, |
212 | RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE); |
213 | } |
214 | |
215 | static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) |
216 | { |
217 | struct device *dev = &bsp_priv->pdev->dev; |
218 | |
219 | if (IS_ERR(ptr: bsp_priv->grf)) { |
220 | dev_err(dev, "Missing rockchip,grf property\n" ); |
221 | return; |
222 | } |
223 | |
224 | if (speed == 10) |
225 | regmap_write(map: bsp_priv->grf, RK3128_GRF_MAC_CON1, |
226 | RK3128_GMAC_CLK_2_5M); |
227 | else if (speed == 100) |
228 | regmap_write(map: bsp_priv->grf, RK3128_GRF_MAC_CON1, |
229 | RK3128_GMAC_CLK_25M); |
230 | else if (speed == 1000) |
231 | regmap_write(map: bsp_priv->grf, RK3128_GRF_MAC_CON1, |
232 | RK3128_GMAC_CLK_125M); |
233 | else |
234 | dev_err(dev, "unknown speed value for RGMII! speed=%d" , speed); |
235 | } |
236 | |
237 | static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
238 | { |
239 | struct device *dev = &bsp_priv->pdev->dev; |
240 | |
241 | if (IS_ERR(ptr: bsp_priv->grf)) { |
242 | dev_err(dev, "Missing rockchip,grf property\n" ); |
243 | return; |
244 | } |
245 | |
246 | if (speed == 10) { |
247 | regmap_write(map: bsp_priv->grf, RK3128_GRF_MAC_CON1, |
248 | RK3128_GMAC_RMII_CLK_2_5M | |
249 | RK3128_GMAC_SPEED_10M); |
250 | } else if (speed == 100) { |
251 | regmap_write(map: bsp_priv->grf, RK3128_GRF_MAC_CON1, |
252 | RK3128_GMAC_RMII_CLK_25M | |
253 | RK3128_GMAC_SPEED_100M); |
254 | } else { |
255 | dev_err(dev, "unknown speed value for RMII! speed=%d" , speed); |
256 | } |
257 | } |
258 | |
259 | static const struct rk_gmac_ops rk3128_ops = { |
260 | .set_to_rgmii = rk3128_set_to_rgmii, |
261 | .set_to_rmii = rk3128_set_to_rmii, |
262 | .set_rgmii_speed = rk3128_set_rgmii_speed, |
263 | .set_rmii_speed = rk3128_set_rmii_speed, |
264 | }; |
265 | |
266 | #define RK3228_GRF_MAC_CON0 0x0900 |
267 | #define RK3228_GRF_MAC_CON1 0x0904 |
268 | |
269 | #define RK3228_GRF_CON_MUX 0x50 |
270 | |
271 | /* RK3228_GRF_MAC_CON0 */ |
272 | #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) |
273 | #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) |
274 | |
275 | /* RK3228_GRF_MAC_CON1 */ |
276 | #define RK3228_GMAC_PHY_INTF_SEL_RGMII \ |
277 | (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) |
278 | #define RK3228_GMAC_PHY_INTF_SEL_RMII \ |
279 | (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) |
280 | #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3) |
281 | #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) |
282 | #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2) |
283 | #define RK3228_GMAC_SPEED_100M GRF_BIT(2) |
284 | #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7) |
285 | #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) |
286 | #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9)) |
287 | #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9)) |
288 | #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9)) |
289 | #define RK3228_GMAC_RMII_MODE GRF_BIT(10) |
290 | #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10) |
291 | #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) |
292 | #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) |
293 | #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) |
294 | #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) |
295 | |
296 | /* RK3228_GRF_COM_MUX */ |
297 | #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15) |
298 | |
299 | static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv, |
300 | int tx_delay, int rx_delay) |
301 | { |
302 | struct device *dev = &bsp_priv->pdev->dev; |
303 | |
304 | if (IS_ERR(ptr: bsp_priv->grf)) { |
305 | dev_err(dev, "Missing rockchip,grf property\n" ); |
306 | return; |
307 | } |
308 | |
309 | regmap_write(map: bsp_priv->grf, RK3228_GRF_MAC_CON1, |
310 | RK3228_GMAC_PHY_INTF_SEL_RGMII | |
311 | RK3228_GMAC_RMII_MODE_CLR | |
312 | DELAY_ENABLE(RK3228, tx_delay, rx_delay)); |
313 | |
314 | regmap_write(map: bsp_priv->grf, RK3228_GRF_MAC_CON0, |
315 | RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) | |
316 | RK3228_GMAC_CLK_TX_DL_CFG(tx_delay)); |
317 | } |
318 | |
319 | static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv) |
320 | { |
321 | struct device *dev = &bsp_priv->pdev->dev; |
322 | |
323 | if (IS_ERR(ptr: bsp_priv->grf)) { |
324 | dev_err(dev, "Missing rockchip,grf property\n" ); |
325 | return; |
326 | } |
327 | |
328 | regmap_write(map: bsp_priv->grf, RK3228_GRF_MAC_CON1, |
329 | RK3228_GMAC_PHY_INTF_SEL_RMII | |
330 | RK3228_GMAC_RMII_MODE); |
331 | |
332 | /* set MAC to RMII mode */ |
333 | regmap_write(map: bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11)); |
334 | } |
335 | |
336 | static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) |
337 | { |
338 | struct device *dev = &bsp_priv->pdev->dev; |
339 | |
340 | if (IS_ERR(ptr: bsp_priv->grf)) { |
341 | dev_err(dev, "Missing rockchip,grf property\n" ); |
342 | return; |
343 | } |
344 | |
345 | if (speed == 10) |
346 | regmap_write(map: bsp_priv->grf, RK3228_GRF_MAC_CON1, |
347 | RK3228_GMAC_CLK_2_5M); |
348 | else if (speed == 100) |
349 | regmap_write(map: bsp_priv->grf, RK3228_GRF_MAC_CON1, |
350 | RK3228_GMAC_CLK_25M); |
351 | else if (speed == 1000) |
352 | regmap_write(map: bsp_priv->grf, RK3228_GRF_MAC_CON1, |
353 | RK3228_GMAC_CLK_125M); |
354 | else |
355 | dev_err(dev, "unknown speed value for RGMII! speed=%d" , speed); |
356 | } |
357 | |
358 | static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
359 | { |
360 | struct device *dev = &bsp_priv->pdev->dev; |
361 | |
362 | if (IS_ERR(ptr: bsp_priv->grf)) { |
363 | dev_err(dev, "Missing rockchip,grf property\n" ); |
364 | return; |
365 | } |
366 | |
367 | if (speed == 10) |
368 | regmap_write(map: bsp_priv->grf, RK3228_GRF_MAC_CON1, |
369 | RK3228_GMAC_RMII_CLK_2_5M | |
370 | RK3228_GMAC_SPEED_10M); |
371 | else if (speed == 100) |
372 | regmap_write(map: bsp_priv->grf, RK3228_GRF_MAC_CON1, |
373 | RK3228_GMAC_RMII_CLK_25M | |
374 | RK3228_GMAC_SPEED_100M); |
375 | else |
376 | dev_err(dev, "unknown speed value for RMII! speed=%d" , speed); |
377 | } |
378 | |
379 | static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv) |
380 | { |
381 | regmap_write(map: priv->grf, RK3228_GRF_CON_MUX, |
382 | RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); |
383 | } |
384 | |
385 | static const struct rk_gmac_ops rk3228_ops = { |
386 | .set_to_rgmii = rk3228_set_to_rgmii, |
387 | .set_to_rmii = rk3228_set_to_rmii, |
388 | .set_rgmii_speed = rk3228_set_rgmii_speed, |
389 | .set_rmii_speed = rk3228_set_rmii_speed, |
390 | .integrated_phy_powerup = rk3228_integrated_phy_powerup, |
391 | }; |
392 | |
393 | #define RK3288_GRF_SOC_CON1 0x0248 |
394 | #define RK3288_GRF_SOC_CON3 0x0250 |
395 | |
396 | /*RK3288_GRF_SOC_CON1*/ |
397 | #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \ |
398 | GRF_CLR_BIT(8)) |
399 | #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \ |
400 | GRF_BIT(8)) |
401 | #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9) |
402 | #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9) |
403 | #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10) |
404 | #define RK3288_GMAC_SPEED_100M GRF_BIT(10) |
405 | #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11) |
406 | #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11) |
407 | #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13)) |
408 | #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13)) |
409 | #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13)) |
410 | #define RK3288_GMAC_RMII_MODE GRF_BIT(14) |
411 | #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14) |
412 | |
413 | /*RK3288_GRF_SOC_CON3*/ |
414 | #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) |
415 | #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) |
416 | #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) |
417 | #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) |
418 | #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) |
419 | #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) |
420 | |
421 | static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, |
422 | int tx_delay, int rx_delay) |
423 | { |
424 | struct device *dev = &bsp_priv->pdev->dev; |
425 | |
426 | if (IS_ERR(ptr: bsp_priv->grf)) { |
427 | dev_err(dev, "Missing rockchip,grf property\n" ); |
428 | return; |
429 | } |
430 | |
431 | regmap_write(map: bsp_priv->grf, RK3288_GRF_SOC_CON1, |
432 | RK3288_GMAC_PHY_INTF_SEL_RGMII | |
433 | RK3288_GMAC_RMII_MODE_CLR); |
434 | regmap_write(map: bsp_priv->grf, RK3288_GRF_SOC_CON3, |
435 | DELAY_ENABLE(RK3288, tx_delay, rx_delay) | |
436 | RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) | |
437 | RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); |
438 | } |
439 | |
440 | static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) |
441 | { |
442 | struct device *dev = &bsp_priv->pdev->dev; |
443 | |
444 | if (IS_ERR(ptr: bsp_priv->grf)) { |
445 | dev_err(dev, "Missing rockchip,grf property\n" ); |
446 | return; |
447 | } |
448 | |
449 | regmap_write(map: bsp_priv->grf, RK3288_GRF_SOC_CON1, |
450 | RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE); |
451 | } |
452 | |
453 | static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) |
454 | { |
455 | struct device *dev = &bsp_priv->pdev->dev; |
456 | |
457 | if (IS_ERR(ptr: bsp_priv->grf)) { |
458 | dev_err(dev, "Missing rockchip,grf property\n" ); |
459 | return; |
460 | } |
461 | |
462 | if (speed == 10) |
463 | regmap_write(map: bsp_priv->grf, RK3288_GRF_SOC_CON1, |
464 | RK3288_GMAC_CLK_2_5M); |
465 | else if (speed == 100) |
466 | regmap_write(map: bsp_priv->grf, RK3288_GRF_SOC_CON1, |
467 | RK3288_GMAC_CLK_25M); |
468 | else if (speed == 1000) |
469 | regmap_write(map: bsp_priv->grf, RK3288_GRF_SOC_CON1, |
470 | RK3288_GMAC_CLK_125M); |
471 | else |
472 | dev_err(dev, "unknown speed value for RGMII! speed=%d" , speed); |
473 | } |
474 | |
475 | static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
476 | { |
477 | struct device *dev = &bsp_priv->pdev->dev; |
478 | |
479 | if (IS_ERR(ptr: bsp_priv->grf)) { |
480 | dev_err(dev, "Missing rockchip,grf property\n" ); |
481 | return; |
482 | } |
483 | |
484 | if (speed == 10) { |
485 | regmap_write(map: bsp_priv->grf, RK3288_GRF_SOC_CON1, |
486 | RK3288_GMAC_RMII_CLK_2_5M | |
487 | RK3288_GMAC_SPEED_10M); |
488 | } else if (speed == 100) { |
489 | regmap_write(map: bsp_priv->grf, RK3288_GRF_SOC_CON1, |
490 | RK3288_GMAC_RMII_CLK_25M | |
491 | RK3288_GMAC_SPEED_100M); |
492 | } else { |
493 | dev_err(dev, "unknown speed value for RMII! speed=%d" , speed); |
494 | } |
495 | } |
496 | |
497 | static const struct rk_gmac_ops rk3288_ops = { |
498 | .set_to_rgmii = rk3288_set_to_rgmii, |
499 | .set_to_rmii = rk3288_set_to_rmii, |
500 | .set_rgmii_speed = rk3288_set_rgmii_speed, |
501 | .set_rmii_speed = rk3288_set_rmii_speed, |
502 | }; |
503 | |
504 | #define RK3308_GRF_MAC_CON0 0x04a0 |
505 | |
506 | /* RK3308_GRF_MAC_CON0 */ |
507 | #define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \ |
508 | GRF_BIT(4)) |
509 | #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3) |
510 | #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) |
511 | #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0) |
512 | #define RK3308_GMAC_SPEED_100M GRF_BIT(0) |
513 | |
514 | static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) |
515 | { |
516 | struct device *dev = &bsp_priv->pdev->dev; |
517 | |
518 | if (IS_ERR(ptr: bsp_priv->grf)) { |
519 | dev_err(dev, "Missing rockchip,grf property\n" ); |
520 | return; |
521 | } |
522 | |
523 | regmap_write(map: bsp_priv->grf, RK3308_GRF_MAC_CON0, |
524 | RK3308_GMAC_PHY_INTF_SEL_RMII); |
525 | } |
526 | |
527 | static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
528 | { |
529 | struct device *dev = &bsp_priv->pdev->dev; |
530 | |
531 | if (IS_ERR(ptr: bsp_priv->grf)) { |
532 | dev_err(dev, "Missing rockchip,grf property\n" ); |
533 | return; |
534 | } |
535 | |
536 | if (speed == 10) { |
537 | regmap_write(map: bsp_priv->grf, RK3308_GRF_MAC_CON0, |
538 | RK3308_GMAC_SPEED_10M); |
539 | } else if (speed == 100) { |
540 | regmap_write(map: bsp_priv->grf, RK3308_GRF_MAC_CON0, |
541 | RK3308_GMAC_SPEED_100M); |
542 | } else { |
543 | dev_err(dev, "unknown speed value for RMII! speed=%d" , speed); |
544 | } |
545 | } |
546 | |
547 | static const struct rk_gmac_ops rk3308_ops = { |
548 | .set_to_rmii = rk3308_set_to_rmii, |
549 | .set_rmii_speed = rk3308_set_rmii_speed, |
550 | }; |
551 | |
552 | #define RK3328_GRF_MAC_CON0 0x0900 |
553 | #define RK3328_GRF_MAC_CON1 0x0904 |
554 | #define RK3328_GRF_MAC_CON2 0x0908 |
555 | #define RK3328_GRF_MACPHY_CON1 0xb04 |
556 | |
557 | /* RK3328_GRF_MAC_CON0 */ |
558 | #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7) |
559 | #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) |
560 | |
561 | /* RK3328_GRF_MAC_CON1 */ |
562 | #define RK3328_GMAC_PHY_INTF_SEL_RGMII \ |
563 | (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) |
564 | #define RK3328_GMAC_PHY_INTF_SEL_RMII \ |
565 | (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) |
566 | #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3) |
567 | #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) |
568 | #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2) |
569 | #define RK3328_GMAC_SPEED_100M GRF_BIT(2) |
570 | #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7) |
571 | #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) |
572 | #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12)) |
573 | #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12)) |
574 | #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12)) |
575 | #define RK3328_GMAC_RMII_MODE GRF_BIT(9) |
576 | #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) |
577 | #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) |
578 | #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) |
579 | #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) |
580 | #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0) |
581 | |
582 | /* RK3328_GRF_MACPHY_CON1 */ |
583 | #define RK3328_MACPHY_RMII_MODE GRF_BIT(9) |
584 | |
585 | static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, |
586 | int tx_delay, int rx_delay) |
587 | { |
588 | struct device *dev = &bsp_priv->pdev->dev; |
589 | |
590 | if (IS_ERR(ptr: bsp_priv->grf)) { |
591 | dev_err(dev, "Missing rockchip,grf property\n" ); |
592 | return; |
593 | } |
594 | |
595 | regmap_write(map: bsp_priv->grf, RK3328_GRF_MAC_CON1, |
596 | RK3328_GMAC_PHY_INTF_SEL_RGMII | |
597 | RK3328_GMAC_RMII_MODE_CLR | |
598 | RK3328_GMAC_RXCLK_DLY_ENABLE | |
599 | RK3328_GMAC_TXCLK_DLY_ENABLE); |
600 | |
601 | regmap_write(map: bsp_priv->grf, RK3328_GRF_MAC_CON0, |
602 | RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) | |
603 | RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); |
604 | } |
605 | |
606 | static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) |
607 | { |
608 | struct device *dev = &bsp_priv->pdev->dev; |
609 | unsigned int reg; |
610 | |
611 | if (IS_ERR(ptr: bsp_priv->grf)) { |
612 | dev_err(dev, "Missing rockchip,grf property\n" ); |
613 | return; |
614 | } |
615 | |
616 | reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : |
617 | RK3328_GRF_MAC_CON1; |
618 | |
619 | regmap_write(map: bsp_priv->grf, reg, |
620 | RK3328_GMAC_PHY_INTF_SEL_RMII | |
621 | RK3328_GMAC_RMII_MODE); |
622 | } |
623 | |
624 | static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) |
625 | { |
626 | struct device *dev = &bsp_priv->pdev->dev; |
627 | |
628 | if (IS_ERR(ptr: bsp_priv->grf)) { |
629 | dev_err(dev, "Missing rockchip,grf property\n" ); |
630 | return; |
631 | } |
632 | |
633 | if (speed == 10) |
634 | regmap_write(map: bsp_priv->grf, RK3328_GRF_MAC_CON1, |
635 | RK3328_GMAC_CLK_2_5M); |
636 | else if (speed == 100) |
637 | regmap_write(map: bsp_priv->grf, RK3328_GRF_MAC_CON1, |
638 | RK3328_GMAC_CLK_25M); |
639 | else if (speed == 1000) |
640 | regmap_write(map: bsp_priv->grf, RK3328_GRF_MAC_CON1, |
641 | RK3328_GMAC_CLK_125M); |
642 | else |
643 | dev_err(dev, "unknown speed value for RGMII! speed=%d" , speed); |
644 | } |
645 | |
646 | static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
647 | { |
648 | struct device *dev = &bsp_priv->pdev->dev; |
649 | unsigned int reg; |
650 | |
651 | if (IS_ERR(ptr: bsp_priv->grf)) { |
652 | dev_err(dev, "Missing rockchip,grf property\n" ); |
653 | return; |
654 | } |
655 | |
656 | reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 : |
657 | RK3328_GRF_MAC_CON1; |
658 | |
659 | if (speed == 10) |
660 | regmap_write(map: bsp_priv->grf, reg, |
661 | RK3328_GMAC_RMII_CLK_2_5M | |
662 | RK3328_GMAC_SPEED_10M); |
663 | else if (speed == 100) |
664 | regmap_write(map: bsp_priv->grf, reg, |
665 | RK3328_GMAC_RMII_CLK_25M | |
666 | RK3328_GMAC_SPEED_100M); |
667 | else |
668 | dev_err(dev, "unknown speed value for RMII! speed=%d" , speed); |
669 | } |
670 | |
671 | static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) |
672 | { |
673 | regmap_write(map: priv->grf, RK3328_GRF_MACPHY_CON1, |
674 | RK3328_MACPHY_RMII_MODE); |
675 | } |
676 | |
677 | static const struct rk_gmac_ops rk3328_ops = { |
678 | .set_to_rgmii = rk3328_set_to_rgmii, |
679 | .set_to_rmii = rk3328_set_to_rmii, |
680 | .set_rgmii_speed = rk3328_set_rgmii_speed, |
681 | .set_rmii_speed = rk3328_set_rmii_speed, |
682 | .integrated_phy_powerup = rk3328_integrated_phy_powerup, |
683 | }; |
684 | |
685 | #define RK3366_GRF_SOC_CON6 0x0418 |
686 | #define RK3366_GRF_SOC_CON7 0x041c |
687 | |
688 | /* RK3366_GRF_SOC_CON6 */ |
689 | #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ |
690 | GRF_CLR_BIT(11)) |
691 | #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ |
692 | GRF_BIT(11)) |
693 | #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8) |
694 | #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) |
695 | #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7) |
696 | #define RK3366_GMAC_SPEED_100M GRF_BIT(7) |
697 | #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3) |
698 | #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) |
699 | #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) |
700 | #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) |
701 | #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) |
702 | #define RK3366_GMAC_RMII_MODE GRF_BIT(6) |
703 | #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) |
704 | |
705 | /* RK3366_GRF_SOC_CON7 */ |
706 | #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) |
707 | #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) |
708 | #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) |
709 | #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) |
710 | #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) |
711 | #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) |
712 | |
713 | static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, |
714 | int tx_delay, int rx_delay) |
715 | { |
716 | struct device *dev = &bsp_priv->pdev->dev; |
717 | |
718 | if (IS_ERR(ptr: bsp_priv->grf)) { |
719 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
720 | return; |
721 | } |
722 | |
723 | regmap_write(map: bsp_priv->grf, RK3366_GRF_SOC_CON6, |
724 | RK3366_GMAC_PHY_INTF_SEL_RGMII | |
725 | RK3366_GMAC_RMII_MODE_CLR); |
726 | regmap_write(map: bsp_priv->grf, RK3366_GRF_SOC_CON7, |
727 | DELAY_ENABLE(RK3366, tx_delay, rx_delay) | |
728 | RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) | |
729 | RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); |
730 | } |
731 | |
732 | static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) |
733 | { |
734 | struct device *dev = &bsp_priv->pdev->dev; |
735 | |
736 | if (IS_ERR(ptr: bsp_priv->grf)) { |
737 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
738 | return; |
739 | } |
740 | |
741 | regmap_write(map: bsp_priv->grf, RK3366_GRF_SOC_CON6, |
742 | RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE); |
743 | } |
744 | |
745 | static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) |
746 | { |
747 | struct device *dev = &bsp_priv->pdev->dev; |
748 | |
749 | if (IS_ERR(ptr: bsp_priv->grf)) { |
750 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
751 | return; |
752 | } |
753 | |
754 | if (speed == 10) |
755 | regmap_write(map: bsp_priv->grf, RK3366_GRF_SOC_CON6, |
756 | RK3366_GMAC_CLK_2_5M); |
757 | else if (speed == 100) |
758 | regmap_write(map: bsp_priv->grf, RK3366_GRF_SOC_CON6, |
759 | RK3366_GMAC_CLK_25M); |
760 | else if (speed == 1000) |
761 | regmap_write(map: bsp_priv->grf, RK3366_GRF_SOC_CON6, |
762 | RK3366_GMAC_CLK_125M); |
763 | else |
764 | dev_err(dev, "unknown speed value for RGMII! speed=%d" , speed); |
765 | } |
766 | |
767 | static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
768 | { |
769 | struct device *dev = &bsp_priv->pdev->dev; |
770 | |
771 | if (IS_ERR(ptr: bsp_priv->grf)) { |
772 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
773 | return; |
774 | } |
775 | |
776 | if (speed == 10) { |
777 | regmap_write(map: bsp_priv->grf, RK3366_GRF_SOC_CON6, |
778 | RK3366_GMAC_RMII_CLK_2_5M | |
779 | RK3366_GMAC_SPEED_10M); |
780 | } else if (speed == 100) { |
781 | regmap_write(map: bsp_priv->grf, RK3366_GRF_SOC_CON6, |
782 | RK3366_GMAC_RMII_CLK_25M | |
783 | RK3366_GMAC_SPEED_100M); |
784 | } else { |
785 | dev_err(dev, "unknown speed value for RMII! speed=%d" , speed); |
786 | } |
787 | } |
788 | |
789 | static const struct rk_gmac_ops rk3366_ops = { |
790 | .set_to_rgmii = rk3366_set_to_rgmii, |
791 | .set_to_rmii = rk3366_set_to_rmii, |
792 | .set_rgmii_speed = rk3366_set_rgmii_speed, |
793 | .set_rmii_speed = rk3366_set_rmii_speed, |
794 | }; |
795 | |
796 | #define RK3368_GRF_SOC_CON15 0x043c |
797 | #define RK3368_GRF_SOC_CON16 0x0440 |
798 | |
799 | /* RK3368_GRF_SOC_CON15 */ |
800 | #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ |
801 | GRF_CLR_BIT(11)) |
802 | #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ |
803 | GRF_BIT(11)) |
804 | #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8) |
805 | #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) |
806 | #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7) |
807 | #define RK3368_GMAC_SPEED_100M GRF_BIT(7) |
808 | #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3) |
809 | #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) |
810 | #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) |
811 | #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) |
812 | #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) |
813 | #define RK3368_GMAC_RMII_MODE GRF_BIT(6) |
814 | #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) |
815 | |
816 | /* RK3368_GRF_SOC_CON16 */ |
817 | #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) |
818 | #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) |
819 | #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) |
820 | #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) |
821 | #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) |
822 | #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) |
823 | |
824 | static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, |
825 | int tx_delay, int rx_delay) |
826 | { |
827 | struct device *dev = &bsp_priv->pdev->dev; |
828 | |
829 | if (IS_ERR(ptr: bsp_priv->grf)) { |
830 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
831 | return; |
832 | } |
833 | |
834 | regmap_write(map: bsp_priv->grf, RK3368_GRF_SOC_CON15, |
835 | RK3368_GMAC_PHY_INTF_SEL_RGMII | |
836 | RK3368_GMAC_RMII_MODE_CLR); |
837 | regmap_write(map: bsp_priv->grf, RK3368_GRF_SOC_CON16, |
838 | DELAY_ENABLE(RK3368, tx_delay, rx_delay) | |
839 | RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) | |
840 | RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); |
841 | } |
842 | |
843 | static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) |
844 | { |
845 | struct device *dev = &bsp_priv->pdev->dev; |
846 | |
847 | if (IS_ERR(ptr: bsp_priv->grf)) { |
848 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
849 | return; |
850 | } |
851 | |
852 | regmap_write(map: bsp_priv->grf, RK3368_GRF_SOC_CON15, |
853 | RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE); |
854 | } |
855 | |
856 | static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) |
857 | { |
858 | struct device *dev = &bsp_priv->pdev->dev; |
859 | |
860 | if (IS_ERR(ptr: bsp_priv->grf)) { |
861 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
862 | return; |
863 | } |
864 | |
865 | if (speed == 10) |
866 | regmap_write(map: bsp_priv->grf, RK3368_GRF_SOC_CON15, |
867 | RK3368_GMAC_CLK_2_5M); |
868 | else if (speed == 100) |
869 | regmap_write(map: bsp_priv->grf, RK3368_GRF_SOC_CON15, |
870 | RK3368_GMAC_CLK_25M); |
871 | else if (speed == 1000) |
872 | regmap_write(map: bsp_priv->grf, RK3368_GRF_SOC_CON15, |
873 | RK3368_GMAC_CLK_125M); |
874 | else |
875 | dev_err(dev, "unknown speed value for RGMII! speed=%d" , speed); |
876 | } |
877 | |
878 | static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
879 | { |
880 | struct device *dev = &bsp_priv->pdev->dev; |
881 | |
882 | if (IS_ERR(ptr: bsp_priv->grf)) { |
883 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
884 | return; |
885 | } |
886 | |
887 | if (speed == 10) { |
888 | regmap_write(map: bsp_priv->grf, RK3368_GRF_SOC_CON15, |
889 | RK3368_GMAC_RMII_CLK_2_5M | |
890 | RK3368_GMAC_SPEED_10M); |
891 | } else if (speed == 100) { |
892 | regmap_write(map: bsp_priv->grf, RK3368_GRF_SOC_CON15, |
893 | RK3368_GMAC_RMII_CLK_25M | |
894 | RK3368_GMAC_SPEED_100M); |
895 | } else { |
896 | dev_err(dev, "unknown speed value for RMII! speed=%d" , speed); |
897 | } |
898 | } |
899 | |
900 | static const struct rk_gmac_ops rk3368_ops = { |
901 | .set_to_rgmii = rk3368_set_to_rgmii, |
902 | .set_to_rmii = rk3368_set_to_rmii, |
903 | .set_rgmii_speed = rk3368_set_rgmii_speed, |
904 | .set_rmii_speed = rk3368_set_rmii_speed, |
905 | }; |
906 | |
907 | #define RK3399_GRF_SOC_CON5 0xc214 |
908 | #define RK3399_GRF_SOC_CON6 0xc218 |
909 | |
910 | /* RK3399_GRF_SOC_CON5 */ |
911 | #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \ |
912 | GRF_CLR_BIT(11)) |
913 | #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \ |
914 | GRF_BIT(11)) |
915 | #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8) |
916 | #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8) |
917 | #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7) |
918 | #define RK3399_GMAC_SPEED_100M GRF_BIT(7) |
919 | #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3) |
920 | #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3) |
921 | #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5)) |
922 | #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5)) |
923 | #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5)) |
924 | #define RK3399_GMAC_RMII_MODE GRF_BIT(6) |
925 | #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6) |
926 | |
927 | /* RK3399_GRF_SOC_CON6 */ |
928 | #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7) |
929 | #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7) |
930 | #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) |
931 | #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) |
932 | #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) |
933 | #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) |
934 | |
935 | static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, |
936 | int tx_delay, int rx_delay) |
937 | { |
938 | struct device *dev = &bsp_priv->pdev->dev; |
939 | |
940 | if (IS_ERR(ptr: bsp_priv->grf)) { |
941 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
942 | return; |
943 | } |
944 | |
945 | regmap_write(map: bsp_priv->grf, RK3399_GRF_SOC_CON5, |
946 | RK3399_GMAC_PHY_INTF_SEL_RGMII | |
947 | RK3399_GMAC_RMII_MODE_CLR); |
948 | regmap_write(map: bsp_priv->grf, RK3399_GRF_SOC_CON6, |
949 | DELAY_ENABLE(RK3399, tx_delay, rx_delay) | |
950 | RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) | |
951 | RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); |
952 | } |
953 | |
954 | static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) |
955 | { |
956 | struct device *dev = &bsp_priv->pdev->dev; |
957 | |
958 | if (IS_ERR(ptr: bsp_priv->grf)) { |
959 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
960 | return; |
961 | } |
962 | |
963 | regmap_write(map: bsp_priv->grf, RK3399_GRF_SOC_CON5, |
964 | RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE); |
965 | } |
966 | |
967 | static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) |
968 | { |
969 | struct device *dev = &bsp_priv->pdev->dev; |
970 | |
971 | if (IS_ERR(ptr: bsp_priv->grf)) { |
972 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
973 | return; |
974 | } |
975 | |
976 | if (speed == 10) |
977 | regmap_write(map: bsp_priv->grf, RK3399_GRF_SOC_CON5, |
978 | RK3399_GMAC_CLK_2_5M); |
979 | else if (speed == 100) |
980 | regmap_write(map: bsp_priv->grf, RK3399_GRF_SOC_CON5, |
981 | RK3399_GMAC_CLK_25M); |
982 | else if (speed == 1000) |
983 | regmap_write(map: bsp_priv->grf, RK3399_GRF_SOC_CON5, |
984 | RK3399_GMAC_CLK_125M); |
985 | else |
986 | dev_err(dev, "unknown speed value for RGMII! speed=%d" , speed); |
987 | } |
988 | |
989 | static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
990 | { |
991 | struct device *dev = &bsp_priv->pdev->dev; |
992 | |
993 | if (IS_ERR(ptr: bsp_priv->grf)) { |
994 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
995 | return; |
996 | } |
997 | |
998 | if (speed == 10) { |
999 | regmap_write(map: bsp_priv->grf, RK3399_GRF_SOC_CON5, |
1000 | RK3399_GMAC_RMII_CLK_2_5M | |
1001 | RK3399_GMAC_SPEED_10M); |
1002 | } else if (speed == 100) { |
1003 | regmap_write(map: bsp_priv->grf, RK3399_GRF_SOC_CON5, |
1004 | RK3399_GMAC_RMII_CLK_25M | |
1005 | RK3399_GMAC_SPEED_100M); |
1006 | } else { |
1007 | dev_err(dev, "unknown speed value for RMII! speed=%d" , speed); |
1008 | } |
1009 | } |
1010 | |
1011 | static const struct rk_gmac_ops rk3399_ops = { |
1012 | .set_to_rgmii = rk3399_set_to_rgmii, |
1013 | .set_to_rmii = rk3399_set_to_rmii, |
1014 | .set_rgmii_speed = rk3399_set_rgmii_speed, |
1015 | .set_rmii_speed = rk3399_set_rmii_speed, |
1016 | }; |
1017 | |
1018 | #define RK3568_GRF_GMAC0_CON0 0x0380 |
1019 | #define RK3568_GRF_GMAC0_CON1 0x0384 |
1020 | #define RK3568_GRF_GMAC1_CON0 0x0388 |
1021 | #define RK3568_GRF_GMAC1_CON1 0x038c |
1022 | |
1023 | /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */ |
1024 | #define RK3568_GMAC_PHY_INTF_SEL_RGMII \ |
1025 | (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) |
1026 | #define RK3568_GMAC_PHY_INTF_SEL_RMII \ |
1027 | (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) |
1028 | #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3) |
1029 | #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) |
1030 | #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) |
1031 | #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) |
1032 | #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) |
1033 | #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) |
1034 | |
1035 | /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */ |
1036 | #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) |
1037 | #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) |
1038 | |
1039 | static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, |
1040 | int tx_delay, int rx_delay) |
1041 | { |
1042 | struct device *dev = &bsp_priv->pdev->dev; |
1043 | u32 con0, con1; |
1044 | |
1045 | if (IS_ERR(ptr: bsp_priv->grf)) { |
1046 | dev_err(dev, "Missing rockchip,grf property\n" ); |
1047 | return; |
1048 | } |
1049 | |
1050 | con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 : |
1051 | RK3568_GRF_GMAC0_CON0; |
1052 | con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : |
1053 | RK3568_GRF_GMAC0_CON1; |
1054 | |
1055 | regmap_write(map: bsp_priv->grf, reg: con0, |
1056 | RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) | |
1057 | RK3568_GMAC_CLK_TX_DL_CFG(tx_delay)); |
1058 | |
1059 | regmap_write(map: bsp_priv->grf, reg: con1, |
1060 | RK3568_GMAC_PHY_INTF_SEL_RGMII | |
1061 | RK3568_GMAC_RXCLK_DLY_ENABLE | |
1062 | RK3568_GMAC_TXCLK_DLY_ENABLE); |
1063 | } |
1064 | |
1065 | static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) |
1066 | { |
1067 | struct device *dev = &bsp_priv->pdev->dev; |
1068 | u32 con1; |
1069 | |
1070 | if (IS_ERR(ptr: bsp_priv->grf)) { |
1071 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
1072 | return; |
1073 | } |
1074 | |
1075 | con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 : |
1076 | RK3568_GRF_GMAC0_CON1; |
1077 | regmap_write(map: bsp_priv->grf, reg: con1, RK3568_GMAC_PHY_INTF_SEL_RMII); |
1078 | } |
1079 | |
1080 | static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) |
1081 | { |
1082 | struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; |
1083 | struct device *dev = &bsp_priv->pdev->dev; |
1084 | unsigned long rate; |
1085 | int ret; |
1086 | |
1087 | switch (speed) { |
1088 | case 10: |
1089 | rate = 2500000; |
1090 | break; |
1091 | case 100: |
1092 | rate = 25000000; |
1093 | break; |
1094 | case 1000: |
1095 | rate = 125000000; |
1096 | break; |
1097 | default: |
1098 | dev_err(dev, "unknown speed value for GMAC speed=%d" , speed); |
1099 | return; |
1100 | } |
1101 | |
1102 | ret = clk_set_rate(clk: clk_mac_speed, rate); |
1103 | if (ret) |
1104 | dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n" , |
1105 | __func__, rate, ret); |
1106 | } |
1107 | |
1108 | static const struct rk_gmac_ops rk3568_ops = { |
1109 | .set_to_rgmii = rk3568_set_to_rgmii, |
1110 | .set_to_rmii = rk3568_set_to_rmii, |
1111 | .set_rgmii_speed = rk3568_set_gmac_speed, |
1112 | .set_rmii_speed = rk3568_set_gmac_speed, |
1113 | .regs_valid = true, |
1114 | .regs = { |
1115 | 0xfe2a0000, /* gmac0 */ |
1116 | 0xfe010000, /* gmac1 */ |
1117 | 0x0, /* sentinel */ |
1118 | }, |
1119 | }; |
1120 | |
1121 | /* sys_grf */ |
1122 | #define RK3588_GRF_GMAC_CON7 0X031c |
1123 | #define RK3588_GRF_GMAC_CON8 0X0320 |
1124 | #define RK3588_GRF_GMAC_CON9 0X0324 |
1125 | |
1126 | #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3) |
1127 | #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3) |
1128 | #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2) |
1129 | #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2) |
1130 | |
1131 | #define RK3588_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) |
1132 | #define RK3588_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) |
1133 | |
1134 | /* php_grf */ |
1135 | #define RK3588_GRF_GMAC_CON0 0X0008 |
1136 | #define RK3588_GRF_CLK_CON1 0X0070 |
1137 | |
1138 | #define RK3588_GMAC_PHY_INTF_SEL_RGMII(id) \ |
1139 | (GRF_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_CLR_BIT(5 + (id) * 6)) |
1140 | #define RK3588_GMAC_PHY_INTF_SEL_RMII(id) \ |
1141 | (GRF_CLR_BIT(3 + (id) * 6) | GRF_CLR_BIT(4 + (id) * 6) | GRF_BIT(5 + (id) * 6)) |
1142 | |
1143 | #define RK3588_GMAC_CLK_RMII_MODE(id) GRF_BIT(5 * (id)) |
1144 | #define RK3588_GMAC_CLK_RGMII_MODE(id) GRF_CLR_BIT(5 * (id)) |
1145 | |
1146 | #define RK3588_GMAC_CLK_SELET_CRU(id) GRF_BIT(5 * (id) + 4) |
1147 | #define RK3588_GMAC_CLK_SELET_IO(id) GRF_CLR_BIT(5 * (id) + 4) |
1148 | |
1149 | #define RK3588_GMA_CLK_RMII_DIV2(id) GRF_BIT(5 * (id) + 2) |
1150 | #define RK3588_GMA_CLK_RMII_DIV20(id) GRF_CLR_BIT(5 * (id) + 2) |
1151 | |
1152 | #define RK3588_GMAC_CLK_RGMII_DIV1(id) \ |
1153 | (GRF_CLR_BIT(5 * (id) + 2) | GRF_CLR_BIT(5 * (id) + 3)) |
1154 | #define RK3588_GMAC_CLK_RGMII_DIV5(id) \ |
1155 | (GRF_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) |
1156 | #define RK3588_GMAC_CLK_RGMII_DIV50(id) \ |
1157 | (GRF_CLR_BIT(5 * (id) + 2) | GRF_BIT(5 * (id) + 3)) |
1158 | |
1159 | #define RK3588_GMAC_CLK_RMII_GATE(id) GRF_BIT(5 * (id) + 1) |
1160 | #define RK3588_GMAC_CLK_RMII_NOGATE(id) GRF_CLR_BIT(5 * (id) + 1) |
1161 | |
1162 | static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv, |
1163 | int tx_delay, int rx_delay) |
1164 | { |
1165 | struct device *dev = &bsp_priv->pdev->dev; |
1166 | u32 offset_con, id = bsp_priv->id; |
1167 | |
1168 | if (IS_ERR(ptr: bsp_priv->grf) || IS_ERR(ptr: bsp_priv->php_grf)) { |
1169 | dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n" ); |
1170 | return; |
1171 | } |
1172 | |
1173 | offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 : |
1174 | RK3588_GRF_GMAC_CON8; |
1175 | |
1176 | regmap_write(map: bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, |
1177 | RK3588_GMAC_PHY_INTF_SEL_RGMII(id)); |
1178 | |
1179 | regmap_write(map: bsp_priv->php_grf, RK3588_GRF_CLK_CON1, |
1180 | RK3588_GMAC_CLK_RGMII_MODE(id)); |
1181 | |
1182 | regmap_write(map: bsp_priv->grf, RK3588_GRF_GMAC_CON7, |
1183 | RK3588_GMAC_RXCLK_DLY_ENABLE(id) | |
1184 | RK3588_GMAC_TXCLK_DLY_ENABLE(id)); |
1185 | |
1186 | regmap_write(map: bsp_priv->grf, reg: offset_con, |
1187 | RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) | |
1188 | RK3588_GMAC_CLK_TX_DL_CFG(tx_delay)); |
1189 | } |
1190 | |
1191 | static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv) |
1192 | { |
1193 | struct device *dev = &bsp_priv->pdev->dev; |
1194 | |
1195 | if (IS_ERR(ptr: bsp_priv->php_grf)) { |
1196 | dev_err(dev, "%s: Missing rockchip,php_grf property\n" , __func__); |
1197 | return; |
1198 | } |
1199 | |
1200 | regmap_write(map: bsp_priv->php_grf, RK3588_GRF_GMAC_CON0, |
1201 | RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id)); |
1202 | |
1203 | regmap_write(map: bsp_priv->php_grf, RK3588_GRF_CLK_CON1, |
1204 | RK3588_GMAC_CLK_RMII_MODE(bsp_priv->id)); |
1205 | } |
1206 | |
1207 | static void rk3588_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed) |
1208 | { |
1209 | struct device *dev = &bsp_priv->pdev->dev; |
1210 | unsigned int val = 0, id = bsp_priv->id; |
1211 | |
1212 | switch (speed) { |
1213 | case 10: |
1214 | if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) |
1215 | val = RK3588_GMA_CLK_RMII_DIV20(id); |
1216 | else |
1217 | val = RK3588_GMAC_CLK_RGMII_DIV50(id); |
1218 | break; |
1219 | case 100: |
1220 | if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) |
1221 | val = RK3588_GMA_CLK_RMII_DIV2(id); |
1222 | else |
1223 | val = RK3588_GMAC_CLK_RGMII_DIV5(id); |
1224 | break; |
1225 | case 1000: |
1226 | if (bsp_priv->phy_iface != PHY_INTERFACE_MODE_RMII) |
1227 | val = RK3588_GMAC_CLK_RGMII_DIV1(id); |
1228 | else |
1229 | goto err; |
1230 | break; |
1231 | default: |
1232 | goto err; |
1233 | } |
1234 | |
1235 | regmap_write(map: bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); |
1236 | |
1237 | return; |
1238 | err: |
1239 | dev_err(dev, "unknown speed value for GMAC speed=%d" , speed); |
1240 | } |
1241 | |
1242 | static void rk3588_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, |
1243 | bool enable) |
1244 | { |
1245 | unsigned int val = input ? RK3588_GMAC_CLK_SELET_IO(bsp_priv->id) : |
1246 | RK3588_GMAC_CLK_SELET_CRU(bsp_priv->id); |
1247 | |
1248 | val |= enable ? RK3588_GMAC_CLK_RMII_NOGATE(bsp_priv->id) : |
1249 | RK3588_GMAC_CLK_RMII_GATE(bsp_priv->id); |
1250 | |
1251 | regmap_write(map: bsp_priv->php_grf, RK3588_GRF_CLK_CON1, val); |
1252 | } |
1253 | |
1254 | static const struct rk_gmac_ops rk3588_ops = { |
1255 | .set_to_rgmii = rk3588_set_to_rgmii, |
1256 | .set_to_rmii = rk3588_set_to_rmii, |
1257 | .set_rgmii_speed = rk3588_set_gmac_speed, |
1258 | .set_rmii_speed = rk3588_set_gmac_speed, |
1259 | .set_clock_selection = rk3588_set_clock_selection, |
1260 | .regs_valid = true, |
1261 | .regs = { |
1262 | 0xfe1b0000, /* gmac0 */ |
1263 | 0xfe1c0000, /* gmac1 */ |
1264 | 0x0, /* sentinel */ |
1265 | }, |
1266 | }; |
1267 | |
1268 | #define RV1108_GRF_GMAC_CON0 0X0900 |
1269 | |
1270 | /* RV1108_GRF_GMAC_CON0 */ |
1271 | #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \ |
1272 | GRF_BIT(6)) |
1273 | #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) |
1274 | #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) |
1275 | #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2) |
1276 | #define RV1108_GMAC_SPEED_100M GRF_BIT(2) |
1277 | #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7) |
1278 | #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7) |
1279 | |
1280 | static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) |
1281 | { |
1282 | struct device *dev = &bsp_priv->pdev->dev; |
1283 | |
1284 | if (IS_ERR(ptr: bsp_priv->grf)) { |
1285 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
1286 | return; |
1287 | } |
1288 | |
1289 | regmap_write(map: bsp_priv->grf, RV1108_GRF_GMAC_CON0, |
1290 | RV1108_GMAC_PHY_INTF_SEL_RMII); |
1291 | } |
1292 | |
1293 | static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
1294 | { |
1295 | struct device *dev = &bsp_priv->pdev->dev; |
1296 | |
1297 | if (IS_ERR(ptr: bsp_priv->grf)) { |
1298 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
1299 | return; |
1300 | } |
1301 | |
1302 | if (speed == 10) { |
1303 | regmap_write(map: bsp_priv->grf, RV1108_GRF_GMAC_CON0, |
1304 | RV1108_GMAC_RMII_CLK_2_5M | |
1305 | RV1108_GMAC_SPEED_10M); |
1306 | } else if (speed == 100) { |
1307 | regmap_write(map: bsp_priv->grf, RV1108_GRF_GMAC_CON0, |
1308 | RV1108_GMAC_RMII_CLK_25M | |
1309 | RV1108_GMAC_SPEED_100M); |
1310 | } else { |
1311 | dev_err(dev, "unknown speed value for RMII! speed=%d" , speed); |
1312 | } |
1313 | } |
1314 | |
1315 | static const struct rk_gmac_ops rv1108_ops = { |
1316 | .set_to_rmii = rv1108_set_to_rmii, |
1317 | .set_rmii_speed = rv1108_set_rmii_speed, |
1318 | }; |
1319 | |
1320 | #define RV1126_GRF_GMAC_CON0 0X0070 |
1321 | #define RV1126_GRF_GMAC_CON1 0X0074 |
1322 | #define RV1126_GRF_GMAC_CON2 0X0078 |
1323 | |
1324 | /* RV1126_GRF_GMAC_CON0 */ |
1325 | #define RV1126_GMAC_PHY_INTF_SEL_RGMII \ |
1326 | (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6)) |
1327 | #define RV1126_GMAC_PHY_INTF_SEL_RMII \ |
1328 | (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6)) |
1329 | #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7) |
1330 | #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7) |
1331 | #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1) |
1332 | #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1) |
1333 | #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0) |
1334 | #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) |
1335 | #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3) |
1336 | #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3) |
1337 | #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2) |
1338 | #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2) |
1339 | |
1340 | /* RV1126_GRF_GMAC_CON1 */ |
1341 | #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) |
1342 | #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) |
1343 | /* RV1126_GRF_GMAC_CON2 */ |
1344 | #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8) |
1345 | #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0) |
1346 | |
1347 | static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv, |
1348 | int tx_delay, int rx_delay) |
1349 | { |
1350 | struct device *dev = &bsp_priv->pdev->dev; |
1351 | |
1352 | if (IS_ERR(ptr: bsp_priv->grf)) { |
1353 | dev_err(dev, "Missing rockchip,grf property\n" ); |
1354 | return; |
1355 | } |
1356 | |
1357 | regmap_write(map: bsp_priv->grf, RV1126_GRF_GMAC_CON0, |
1358 | RV1126_GMAC_PHY_INTF_SEL_RGMII | |
1359 | RV1126_GMAC_M0_RXCLK_DLY_ENABLE | |
1360 | RV1126_GMAC_M0_TXCLK_DLY_ENABLE | |
1361 | RV1126_GMAC_M1_RXCLK_DLY_ENABLE | |
1362 | RV1126_GMAC_M1_TXCLK_DLY_ENABLE); |
1363 | |
1364 | regmap_write(map: bsp_priv->grf, RV1126_GRF_GMAC_CON1, |
1365 | RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) | |
1366 | RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay)); |
1367 | |
1368 | regmap_write(map: bsp_priv->grf, RV1126_GRF_GMAC_CON2, |
1369 | RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) | |
1370 | RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay)); |
1371 | } |
1372 | |
1373 | static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) |
1374 | { |
1375 | struct device *dev = &bsp_priv->pdev->dev; |
1376 | |
1377 | if (IS_ERR(ptr: bsp_priv->grf)) { |
1378 | dev_err(dev, "%s: Missing rockchip,grf property\n" , __func__); |
1379 | return; |
1380 | } |
1381 | |
1382 | regmap_write(map: bsp_priv->grf, RV1126_GRF_GMAC_CON0, |
1383 | RV1126_GMAC_PHY_INTF_SEL_RMII); |
1384 | } |
1385 | |
1386 | static void rv1126_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed) |
1387 | { |
1388 | struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; |
1389 | struct device *dev = &bsp_priv->pdev->dev; |
1390 | unsigned long rate; |
1391 | int ret; |
1392 | |
1393 | switch (speed) { |
1394 | case 10: |
1395 | rate = 2500000; |
1396 | break; |
1397 | case 100: |
1398 | rate = 25000000; |
1399 | break; |
1400 | case 1000: |
1401 | rate = 125000000; |
1402 | break; |
1403 | default: |
1404 | dev_err(dev, "unknown speed value for RGMII speed=%d" , speed); |
1405 | return; |
1406 | } |
1407 | |
1408 | ret = clk_set_rate(clk: clk_mac_speed, rate); |
1409 | if (ret) |
1410 | dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n" , |
1411 | __func__, rate, ret); |
1412 | } |
1413 | |
1414 | static void rv1126_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) |
1415 | { |
1416 | struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk; |
1417 | struct device *dev = &bsp_priv->pdev->dev; |
1418 | unsigned long rate; |
1419 | int ret; |
1420 | |
1421 | switch (speed) { |
1422 | case 10: |
1423 | rate = 2500000; |
1424 | break; |
1425 | case 100: |
1426 | rate = 25000000; |
1427 | break; |
1428 | default: |
1429 | dev_err(dev, "unknown speed value for RGMII speed=%d" , speed); |
1430 | return; |
1431 | } |
1432 | |
1433 | ret = clk_set_rate(clk: clk_mac_speed, rate); |
1434 | if (ret) |
1435 | dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n" , |
1436 | __func__, rate, ret); |
1437 | } |
1438 | |
1439 | static const struct rk_gmac_ops rv1126_ops = { |
1440 | .set_to_rgmii = rv1126_set_to_rgmii, |
1441 | .set_to_rmii = rv1126_set_to_rmii, |
1442 | .set_rgmii_speed = rv1126_set_rgmii_speed, |
1443 | .set_rmii_speed = rv1126_set_rmii_speed, |
1444 | }; |
1445 | |
1446 | #define RK_GRF_MACPHY_CON0 0xb00 |
1447 | #define RK_GRF_MACPHY_CON1 0xb04 |
1448 | #define RK_GRF_MACPHY_CON2 0xb08 |
1449 | #define RK_GRF_MACPHY_CON3 0xb0c |
1450 | |
1451 | #define RK_MACPHY_ENABLE GRF_BIT(0) |
1452 | #define RK_MACPHY_DISABLE GRF_CLR_BIT(0) |
1453 | #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) |
1454 | #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) |
1455 | #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) |
1456 | #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) |
1457 | |
1458 | static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) |
1459 | { |
1460 | if (priv->ops->integrated_phy_powerup) |
1461 | priv->ops->integrated_phy_powerup(priv); |
1462 | |
1463 | regmap_write(map: priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); |
1464 | regmap_write(map: priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); |
1465 | |
1466 | regmap_write(map: priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); |
1467 | regmap_write(map: priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); |
1468 | |
1469 | if (priv->phy_reset) { |
1470 | /* PHY needs to be disabled before trying to reset it */ |
1471 | regmap_write(map: priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); |
1472 | if (priv->phy_reset) |
1473 | reset_control_assert(rstc: priv->phy_reset); |
1474 | usleep_range(min: 10, max: 20); |
1475 | if (priv->phy_reset) |
1476 | reset_control_deassert(rstc: priv->phy_reset); |
1477 | usleep_range(min: 10, max: 20); |
1478 | regmap_write(map: priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); |
1479 | msleep(msecs: 30); |
1480 | } |
1481 | } |
1482 | |
1483 | static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) |
1484 | { |
1485 | regmap_write(map: priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); |
1486 | if (priv->phy_reset) |
1487 | reset_control_assert(rstc: priv->phy_reset); |
1488 | } |
1489 | |
1490 | static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) |
1491 | { |
1492 | struct rk_priv_data *bsp_priv = plat->bsp_priv; |
1493 | struct device *dev = &bsp_priv->pdev->dev; |
1494 | int phy_iface = bsp_priv->phy_iface; |
1495 | int i, j, ret; |
1496 | |
1497 | bsp_priv->clk_enabled = false; |
1498 | |
1499 | bsp_priv->num_clks = ARRAY_SIZE(rk_clocks); |
1500 | if (phy_iface == PHY_INTERFACE_MODE_RMII) |
1501 | bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks); |
1502 | |
1503 | bsp_priv->clks = devm_kcalloc(dev, n: bsp_priv->num_clks, |
1504 | size: sizeof(*bsp_priv->clks), GFP_KERNEL); |
1505 | if (!bsp_priv->clks) |
1506 | return -ENOMEM; |
1507 | |
1508 | for (i = 0; i < ARRAY_SIZE(rk_clocks); i++) |
1509 | bsp_priv->clks[i].id = rk_clocks[i]; |
1510 | |
1511 | if (phy_iface == PHY_INTERFACE_MODE_RMII) { |
1512 | for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++) |
1513 | bsp_priv->clks[i++].id = rk_rmii_clocks[j]; |
1514 | } |
1515 | |
1516 | ret = devm_clk_bulk_get_optional(dev, num_clks: bsp_priv->num_clks, |
1517 | clks: bsp_priv->clks); |
1518 | if (ret) |
1519 | return dev_err_probe(dev, err: ret, fmt: "Failed to get clocks\n" ); |
1520 | |
1521 | /* "stmmaceth" will be enabled by the core */ |
1522 | bsp_priv->clk_mac = devm_clk_get(dev, id: "stmmaceth" ); |
1523 | ret = PTR_ERR_OR_ZERO(ptr: bsp_priv->clk_mac); |
1524 | if (ret) |
1525 | return dev_err_probe(dev, err: ret, fmt: "Cannot get stmmaceth clock\n" ); |
1526 | |
1527 | if (bsp_priv->clock_input) { |
1528 | dev_info(dev, "clock input from PHY\n" ); |
1529 | } else if (phy_iface == PHY_INTERFACE_MODE_RMII) { |
1530 | clk_set_rate(clk: bsp_priv->clk_mac, rate: 50000000); |
1531 | } |
1532 | |
1533 | if (plat->phy_node && bsp_priv->integrated_phy) { |
1534 | bsp_priv->clk_phy = of_clk_get(np: plat->phy_node, index: 0); |
1535 | ret = PTR_ERR_OR_ZERO(ptr: bsp_priv->clk_phy); |
1536 | if (ret) |
1537 | return dev_err_probe(dev, err: ret, fmt: "Cannot get PHY clock\n" ); |
1538 | clk_set_rate(clk: bsp_priv->clk_phy, rate: 50000000); |
1539 | } |
1540 | |
1541 | return 0; |
1542 | } |
1543 | |
1544 | static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable) |
1545 | { |
1546 | int ret; |
1547 | |
1548 | if (enable) { |
1549 | if (!bsp_priv->clk_enabled) { |
1550 | ret = clk_bulk_prepare_enable(num_clks: bsp_priv->num_clks, |
1551 | clks: bsp_priv->clks); |
1552 | if (ret) |
1553 | return ret; |
1554 | |
1555 | ret = clk_prepare_enable(clk: bsp_priv->clk_phy); |
1556 | if (ret) |
1557 | return ret; |
1558 | |
1559 | if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) |
1560 | bsp_priv->ops->set_clock_selection(bsp_priv, |
1561 | bsp_priv->clock_input, true); |
1562 | |
1563 | mdelay(5); |
1564 | bsp_priv->clk_enabled = true; |
1565 | } |
1566 | } else { |
1567 | if (bsp_priv->clk_enabled) { |
1568 | clk_bulk_disable_unprepare(num_clks: bsp_priv->num_clks, |
1569 | clks: bsp_priv->clks); |
1570 | clk_disable_unprepare(clk: bsp_priv->clk_phy); |
1571 | |
1572 | if (bsp_priv->ops && bsp_priv->ops->set_clock_selection) |
1573 | bsp_priv->ops->set_clock_selection(bsp_priv, |
1574 | bsp_priv->clock_input, false); |
1575 | |
1576 | bsp_priv->clk_enabled = false; |
1577 | } |
1578 | } |
1579 | |
1580 | return 0; |
1581 | } |
1582 | |
1583 | static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable) |
1584 | { |
1585 | struct regulator *ldo = bsp_priv->regulator; |
1586 | int ret; |
1587 | struct device *dev = &bsp_priv->pdev->dev; |
1588 | |
1589 | if (enable) { |
1590 | ret = regulator_enable(regulator: ldo); |
1591 | if (ret) |
1592 | dev_err(dev, "fail to enable phy-supply\n" ); |
1593 | } else { |
1594 | ret = regulator_disable(regulator: ldo); |
1595 | if (ret) |
1596 | dev_err(dev, "fail to disable phy-supply\n" ); |
1597 | } |
1598 | |
1599 | return 0; |
1600 | } |
1601 | |
1602 | static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev, |
1603 | struct plat_stmmacenet_data *plat, |
1604 | const struct rk_gmac_ops *ops) |
1605 | { |
1606 | struct rk_priv_data *bsp_priv; |
1607 | struct device *dev = &pdev->dev; |
1608 | struct resource *res; |
1609 | int ret; |
1610 | const char *strings = NULL; |
1611 | int value; |
1612 | |
1613 | bsp_priv = devm_kzalloc(dev, size: sizeof(*bsp_priv), GFP_KERNEL); |
1614 | if (!bsp_priv) |
1615 | return ERR_PTR(error: -ENOMEM); |
1616 | |
1617 | of_get_phy_mode(np: dev->of_node, interface: &bsp_priv->phy_iface); |
1618 | bsp_priv->ops = ops; |
1619 | |
1620 | /* Some SoCs have multiple MAC controllers, which need |
1621 | * to be distinguished. |
1622 | */ |
1623 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1624 | if (res && ops->regs_valid) { |
1625 | int i = 0; |
1626 | |
1627 | while (ops->regs[i]) { |
1628 | if (ops->regs[i] == res->start) { |
1629 | bsp_priv->id = i; |
1630 | break; |
1631 | } |
1632 | i++; |
1633 | } |
1634 | } |
1635 | |
1636 | bsp_priv->regulator = devm_regulator_get(dev, id: "phy" ); |
1637 | if (IS_ERR(ptr: bsp_priv->regulator)) { |
1638 | ret = PTR_ERR(ptr: bsp_priv->regulator); |
1639 | dev_err_probe(dev, err: ret, fmt: "failed to get phy regulator\n" ); |
1640 | return ERR_PTR(error: ret); |
1641 | } |
1642 | |
1643 | ret = of_property_read_string(np: dev->of_node, propname: "clock_in_out" , out_string: &strings); |
1644 | if (ret) { |
1645 | dev_err(dev, "Can not read property: clock_in_out.\n" ); |
1646 | bsp_priv->clock_input = true; |
1647 | } else { |
1648 | dev_info(dev, "clock input or output? (%s).\n" , |
1649 | strings); |
1650 | if (!strcmp(strings, "input" )) |
1651 | bsp_priv->clock_input = true; |
1652 | else |
1653 | bsp_priv->clock_input = false; |
1654 | } |
1655 | |
1656 | ret = of_property_read_u32(np: dev->of_node, propname: "tx_delay" , out_value: &value); |
1657 | if (ret) { |
1658 | bsp_priv->tx_delay = 0x30; |
1659 | dev_err(dev, "Can not read property: tx_delay." ); |
1660 | dev_err(dev, "set tx_delay to 0x%x\n" , |
1661 | bsp_priv->tx_delay); |
1662 | } else { |
1663 | dev_info(dev, "TX delay(0x%x).\n" , value); |
1664 | bsp_priv->tx_delay = value; |
1665 | } |
1666 | |
1667 | ret = of_property_read_u32(np: dev->of_node, propname: "rx_delay" , out_value: &value); |
1668 | if (ret) { |
1669 | bsp_priv->rx_delay = 0x10; |
1670 | dev_err(dev, "Can not read property: rx_delay." ); |
1671 | dev_err(dev, "set rx_delay to 0x%x\n" , |
1672 | bsp_priv->rx_delay); |
1673 | } else { |
1674 | dev_info(dev, "RX delay(0x%x).\n" , value); |
1675 | bsp_priv->rx_delay = value; |
1676 | } |
1677 | |
1678 | bsp_priv->grf = syscon_regmap_lookup_by_phandle(np: dev->of_node, |
1679 | property: "rockchip,grf" ); |
1680 | bsp_priv->php_grf = syscon_regmap_lookup_by_phandle(np: dev->of_node, |
1681 | property: "rockchip,php-grf" ); |
1682 | |
1683 | if (plat->phy_node) { |
1684 | bsp_priv->integrated_phy = of_property_read_bool(np: plat->phy_node, |
1685 | propname: "phy-is-integrated" ); |
1686 | if (bsp_priv->integrated_phy) { |
1687 | bsp_priv->phy_reset = of_reset_control_get(node: plat->phy_node, NULL); |
1688 | if (IS_ERR(ptr: bsp_priv->phy_reset)) { |
1689 | dev_err(&pdev->dev, "No PHY reset control found.\n" ); |
1690 | bsp_priv->phy_reset = NULL; |
1691 | } |
1692 | } |
1693 | } |
1694 | dev_info(dev, "integrated PHY? (%s).\n" , |
1695 | bsp_priv->integrated_phy ? "yes" : "no" ); |
1696 | |
1697 | bsp_priv->pdev = pdev; |
1698 | |
1699 | return bsp_priv; |
1700 | } |
1701 | |
1702 | static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv) |
1703 | { |
1704 | switch (bsp_priv->phy_iface) { |
1705 | case PHY_INTERFACE_MODE_RGMII: |
1706 | case PHY_INTERFACE_MODE_RGMII_ID: |
1707 | case PHY_INTERFACE_MODE_RGMII_RXID: |
1708 | case PHY_INTERFACE_MODE_RGMII_TXID: |
1709 | if (!bsp_priv->ops->set_to_rgmii) |
1710 | return -EINVAL; |
1711 | break; |
1712 | case PHY_INTERFACE_MODE_RMII: |
1713 | if (!bsp_priv->ops->set_to_rmii) |
1714 | return -EINVAL; |
1715 | break; |
1716 | default: |
1717 | dev_err(&bsp_priv->pdev->dev, |
1718 | "unsupported interface %d" , bsp_priv->phy_iface); |
1719 | } |
1720 | return 0; |
1721 | } |
1722 | |
1723 | static int rk_gmac_powerup(struct rk_priv_data *bsp_priv) |
1724 | { |
1725 | int ret; |
1726 | struct device *dev = &bsp_priv->pdev->dev; |
1727 | |
1728 | ret = rk_gmac_check_ops(bsp_priv); |
1729 | if (ret) |
1730 | return ret; |
1731 | |
1732 | ret = gmac_clk_enable(bsp_priv, enable: true); |
1733 | if (ret) |
1734 | return ret; |
1735 | |
1736 | /*rmii or rgmii*/ |
1737 | switch (bsp_priv->phy_iface) { |
1738 | case PHY_INTERFACE_MODE_RGMII: |
1739 | dev_info(dev, "init for RGMII\n" ); |
1740 | bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, |
1741 | bsp_priv->rx_delay); |
1742 | break; |
1743 | case PHY_INTERFACE_MODE_RGMII_ID: |
1744 | dev_info(dev, "init for RGMII_ID\n" ); |
1745 | bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0); |
1746 | break; |
1747 | case PHY_INTERFACE_MODE_RGMII_RXID: |
1748 | dev_info(dev, "init for RGMII_RXID\n" ); |
1749 | bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0); |
1750 | break; |
1751 | case PHY_INTERFACE_MODE_RGMII_TXID: |
1752 | dev_info(dev, "init for RGMII_TXID\n" ); |
1753 | bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay); |
1754 | break; |
1755 | case PHY_INTERFACE_MODE_RMII: |
1756 | dev_info(dev, "init for RMII\n" ); |
1757 | bsp_priv->ops->set_to_rmii(bsp_priv); |
1758 | break; |
1759 | default: |
1760 | dev_err(dev, "NO interface defined!\n" ); |
1761 | } |
1762 | |
1763 | ret = phy_power_on(bsp_priv, enable: true); |
1764 | if (ret) { |
1765 | gmac_clk_enable(bsp_priv, enable: false); |
1766 | return ret; |
1767 | } |
1768 | |
1769 | pm_runtime_get_sync(dev); |
1770 | |
1771 | if (bsp_priv->integrated_phy) |
1772 | rk_gmac_integrated_phy_powerup(priv: bsp_priv); |
1773 | |
1774 | return 0; |
1775 | } |
1776 | |
1777 | static void rk_gmac_powerdown(struct rk_priv_data *gmac) |
1778 | { |
1779 | if (gmac->integrated_phy) |
1780 | rk_gmac_integrated_phy_powerdown(priv: gmac); |
1781 | |
1782 | pm_runtime_put_sync(dev: &gmac->pdev->dev); |
1783 | |
1784 | phy_power_on(bsp_priv: gmac, enable: false); |
1785 | gmac_clk_enable(bsp_priv: gmac, enable: false); |
1786 | } |
1787 | |
1788 | static void rk_fix_speed(void *priv, unsigned int speed, unsigned int mode) |
1789 | { |
1790 | struct rk_priv_data *bsp_priv = priv; |
1791 | struct device *dev = &bsp_priv->pdev->dev; |
1792 | |
1793 | switch (bsp_priv->phy_iface) { |
1794 | case PHY_INTERFACE_MODE_RGMII: |
1795 | case PHY_INTERFACE_MODE_RGMII_ID: |
1796 | case PHY_INTERFACE_MODE_RGMII_RXID: |
1797 | case PHY_INTERFACE_MODE_RGMII_TXID: |
1798 | if (bsp_priv->ops->set_rgmii_speed) |
1799 | bsp_priv->ops->set_rgmii_speed(bsp_priv, speed); |
1800 | break; |
1801 | case PHY_INTERFACE_MODE_RMII: |
1802 | if (bsp_priv->ops->set_rmii_speed) |
1803 | bsp_priv->ops->set_rmii_speed(bsp_priv, speed); |
1804 | break; |
1805 | default: |
1806 | dev_err(dev, "unsupported interface %d" , bsp_priv->phy_iface); |
1807 | } |
1808 | } |
1809 | |
1810 | static int rk_gmac_probe(struct platform_device *pdev) |
1811 | { |
1812 | struct plat_stmmacenet_data *plat_dat; |
1813 | struct stmmac_resources stmmac_res; |
1814 | const struct rk_gmac_ops *data; |
1815 | int ret; |
1816 | |
1817 | data = of_device_get_match_data(dev: &pdev->dev); |
1818 | if (!data) { |
1819 | dev_err(&pdev->dev, "no of match data provided\n" ); |
1820 | return -EINVAL; |
1821 | } |
1822 | |
1823 | ret = stmmac_get_platform_resources(pdev, stmmac_res: &stmmac_res); |
1824 | if (ret) |
1825 | return ret; |
1826 | |
1827 | plat_dat = devm_stmmac_probe_config_dt(pdev, mac: stmmac_res.mac); |
1828 | if (IS_ERR(ptr: plat_dat)) |
1829 | return PTR_ERR(ptr: plat_dat); |
1830 | |
1831 | /* If the stmmac is not already selected as gmac4, |
1832 | * then make sure we fallback to gmac. |
1833 | */ |
1834 | if (!plat_dat->has_gmac4) |
1835 | plat_dat->has_gmac = true; |
1836 | plat_dat->fix_mac_speed = rk_fix_speed; |
1837 | |
1838 | plat_dat->bsp_priv = rk_gmac_setup(pdev, plat: plat_dat, ops: data); |
1839 | if (IS_ERR(ptr: plat_dat->bsp_priv)) |
1840 | return PTR_ERR(ptr: plat_dat->bsp_priv); |
1841 | |
1842 | ret = rk_gmac_clk_init(plat: plat_dat); |
1843 | if (ret) |
1844 | return ret; |
1845 | |
1846 | ret = rk_gmac_powerup(bsp_priv: plat_dat->bsp_priv); |
1847 | if (ret) |
1848 | return ret; |
1849 | |
1850 | ret = stmmac_dvr_probe(device: &pdev->dev, plat_dat, res: &stmmac_res); |
1851 | if (ret) |
1852 | goto err_gmac_powerdown; |
1853 | |
1854 | return 0; |
1855 | |
1856 | err_gmac_powerdown: |
1857 | rk_gmac_powerdown(gmac: plat_dat->bsp_priv); |
1858 | |
1859 | return ret; |
1860 | } |
1861 | |
1862 | static void rk_gmac_remove(struct platform_device *pdev) |
1863 | { |
1864 | struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev: &pdev->dev); |
1865 | |
1866 | stmmac_dvr_remove(dev: &pdev->dev); |
1867 | |
1868 | rk_gmac_powerdown(gmac: bsp_priv); |
1869 | } |
1870 | |
1871 | #ifdef CONFIG_PM_SLEEP |
1872 | static int rk_gmac_suspend(struct device *dev) |
1873 | { |
1874 | struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); |
1875 | int ret = stmmac_suspend(dev); |
1876 | |
1877 | /* Keep the PHY up if we use Wake-on-Lan. */ |
1878 | if (!device_may_wakeup(dev)) { |
1879 | rk_gmac_powerdown(gmac: bsp_priv); |
1880 | bsp_priv->suspended = true; |
1881 | } |
1882 | |
1883 | return ret; |
1884 | } |
1885 | |
1886 | static int rk_gmac_resume(struct device *dev) |
1887 | { |
1888 | struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev); |
1889 | |
1890 | /* The PHY was up for Wake-on-Lan. */ |
1891 | if (bsp_priv->suspended) { |
1892 | rk_gmac_powerup(bsp_priv); |
1893 | bsp_priv->suspended = false; |
1894 | } |
1895 | |
1896 | return stmmac_resume(dev); |
1897 | } |
1898 | #endif /* CONFIG_PM_SLEEP */ |
1899 | |
1900 | static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume); |
1901 | |
1902 | static const struct of_device_id rk_gmac_dwmac_match[] = { |
1903 | { .compatible = "rockchip,px30-gmac" , .data = &px30_ops }, |
1904 | { .compatible = "rockchip,rk3128-gmac" , .data = &rk3128_ops }, |
1905 | { .compatible = "rockchip,rk3228-gmac" , .data = &rk3228_ops }, |
1906 | { .compatible = "rockchip,rk3288-gmac" , .data = &rk3288_ops }, |
1907 | { .compatible = "rockchip,rk3308-gmac" , .data = &rk3308_ops }, |
1908 | { .compatible = "rockchip,rk3328-gmac" , .data = &rk3328_ops }, |
1909 | { .compatible = "rockchip,rk3366-gmac" , .data = &rk3366_ops }, |
1910 | { .compatible = "rockchip,rk3368-gmac" , .data = &rk3368_ops }, |
1911 | { .compatible = "rockchip,rk3399-gmac" , .data = &rk3399_ops }, |
1912 | { .compatible = "rockchip,rk3568-gmac" , .data = &rk3568_ops }, |
1913 | { .compatible = "rockchip,rk3588-gmac" , .data = &rk3588_ops }, |
1914 | { .compatible = "rockchip,rv1108-gmac" , .data = &rv1108_ops }, |
1915 | { .compatible = "rockchip,rv1126-gmac" , .data = &rv1126_ops }, |
1916 | { } |
1917 | }; |
1918 | MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match); |
1919 | |
1920 | static struct platform_driver rk_gmac_dwmac_driver = { |
1921 | .probe = rk_gmac_probe, |
1922 | .remove_new = rk_gmac_remove, |
1923 | .driver = { |
1924 | .name = "rk_gmac-dwmac" , |
1925 | .pm = &rk_gmac_pm_ops, |
1926 | .of_match_table = rk_gmac_dwmac_match, |
1927 | }, |
1928 | }; |
1929 | module_platform_driver(rk_gmac_dwmac_driver); |
1930 | |
1931 | MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>" ); |
1932 | MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer" ); |
1933 | MODULE_LICENSE("GPL" ); |
1934 | |