1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
4
5
6 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
7*******************************************************************************/
8#ifndef __DWMAC1000_H__
9#define __DWMAC1000_H__
10
11#include <linux/phy.h>
12#include "common.h"
13
14#define GMAC_CONTROL 0x00000000 /* Configuration */
15#define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */
16#define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */
17#define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */
18#define GMAC_MII_ADDR 0x00000010 /* MII Address */
19#define GMAC_MII_DATA 0x00000014 /* MII Data */
20#define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */
21#define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */
22#define GMAC_DEBUG 0x00000024 /* GMAC debug register */
23#define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
24
25#define GMAC_INT_STATUS 0x00000038 /* interrupt status register */
26#define GMAC_INT_STATUS_PMT BIT(3)
27#define GMAC_INT_STATUS_MMCIS BIT(4)
28#define GMAC_INT_STATUS_MMCRIS BIT(5)
29#define GMAC_INT_STATUS_MMCTIS BIT(6)
30#define GMAC_INT_STATUS_MMCCSUM BIT(7)
31#define GMAC_INT_STATUS_TSTAMP BIT(9)
32#define GMAC_INT_STATUS_LPIIS BIT(10)
33
34/* interrupt mask register */
35#define GMAC_INT_MASK 0x0000003c
36#define GMAC_INT_DISABLE_RGMII BIT(0)
37#define GMAC_INT_DISABLE_PCSLINK BIT(1)
38#define GMAC_INT_DISABLE_PCSAN BIT(2)
39#define GMAC_INT_DISABLE_PMT BIT(3)
40#define GMAC_INT_DISABLE_TIMESTAMP BIT(9)
41#define GMAC_INT_DISABLE_PCS (GMAC_INT_DISABLE_RGMII | \
42 GMAC_INT_DISABLE_PCSLINK | \
43 GMAC_INT_DISABLE_PCSAN)
44#define GMAC_INT_DEFAULT_MASK (GMAC_INT_DISABLE_TIMESTAMP | \
45 GMAC_INT_DISABLE_PCS)
46
47/* PMT Control and Status */
48#define GMAC_PMT 0x0000002c
49enum power_event {
50 pointer_reset = 0x80000000,
51 global_unicast = 0x00000200,
52 wake_up_rx_frame = 0x00000040,
53 magic_frame = 0x00000020,
54 wake_up_frame_en = 0x00000004,
55 magic_pkt_en = 0x00000002,
56 power_down = 0x00000001,
57};
58
59/* Energy Efficient Ethernet (EEE)
60 *
61 * LPI status, timer and control register offset
62 */
63#define LPI_CTRL_STATUS 0x0030
64#define LPI_TIMER_CTRL 0x0034
65
66/* LPI control and status defines */
67#define LPI_CTRL_STATUS_LPITXA 0x00080000 /* Enable LPI TX Automate */
68#define LPI_CTRL_STATUS_PLSEN 0x00040000 /* Enable PHY Link Status */
69#define LPI_CTRL_STATUS_PLS 0x00020000 /* PHY Link Status */
70#define LPI_CTRL_STATUS_LPIEN 0x00010000 /* LPI Enable */
71#define LPI_CTRL_STATUS_RLPIST 0x00000200 /* Receive LPI state */
72#define LPI_CTRL_STATUS_TLPIST 0x00000100 /* Transmit LPI state */
73#define LPI_CTRL_STATUS_RLPIEX 0x00000008 /* Receive LPI Exit */
74#define LPI_CTRL_STATUS_RLPIEN 0x00000004 /* Receive LPI Entry */
75#define LPI_CTRL_STATUS_TLPIEX 0x00000002 /* Transmit LPI Exit */
76#define LPI_CTRL_STATUS_TLPIEN 0x00000001 /* Transmit LPI Entry */
77
78/* GMAC HW ADDR regs */
79#define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
80 0x00000040 + (reg * 8))
81#define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
82 0x00000044 + (reg * 8))
83#define GMAC_MAX_PERFECT_ADDRESSES 1
84
85#define GMAC_PCS_BASE 0x000000c0 /* PCS register base */
86#define GMAC_RGSMIIIS 0x000000d8 /* RGMII/SMII status */
87
88/* SGMII/RGMII status register */
89#define GMAC_RGSMIIIS_LNKMODE BIT(0)
90#define GMAC_RGSMIIIS_SPEED GENMASK(2, 1)
91#define GMAC_RGSMIIIS_SPEED_SHIFT 1
92#define GMAC_RGSMIIIS_LNKSTS BIT(3)
93#define GMAC_RGSMIIIS_JABTO BIT(4)
94#define GMAC_RGSMIIIS_FALSECARDET BIT(5)
95#define GMAC_RGSMIIIS_SMIDRXS BIT(16)
96/* LNKMOD */
97#define GMAC_RGSMIIIS_LNKMOD_MASK 0x1
98/* LNKSPEED */
99#define GMAC_RGSMIIIS_SPEED_125 0x2
100#define GMAC_RGSMIIIS_SPEED_25 0x1
101#define GMAC_RGSMIIIS_SPEED_2_5 0x0
102
103/* GMAC Configuration defines */
104#define GMAC_CONTROL_2K 0x08000000 /* IEEE 802.3as 2K packets */
105#define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */
106#define GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */
107#define GMAC_CONTROL_JD 0x00400000 /* Jabber disable */
108#define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */
109#define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */
110enum inter_frame_gap {
111 GMAC_CONTROL_IFG_88 = 0x00040000,
112 GMAC_CONTROL_IFG_80 = 0x00020000,
113 GMAC_CONTROL_IFG_40 = 0x000e0000,
114};
115#define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense */
116#define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */
117#define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */
118#define GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */
119#define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
120#define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */
121#define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */
122#define GMAC_CONTROL_DR 0x00000200 /* Disable Retry */
123#define GMAC_CONTROL_LUD 0x00000100 /* Link up/down */
124#define GMAC_CONTROL_ACS 0x00000080 /* Auto Pad/FCS Stripping */
125#define GMAC_CONTROL_DC 0x00000010 /* Deferral Check */
126#define GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
127#define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */
128
129#define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | \
130 GMAC_CONTROL_BE | GMAC_CONTROL_DCRS)
131
132/* GMAC Frame Filter defines */
133#define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
134#define GMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */
135#define GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */
136#define GMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */
137#define GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */
138#define GMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */
139#define GMAC_FRAME_FILTER_PCF 0x00000080 /* Pass Control frames */
140#define GMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */
141#define GMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */
142#define GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */
143#define GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */
144/* GMII ADDR defines */
145#define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */
146#define GMAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */
147/* GMAC FLOW CTRL defines */
148#define GMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */
149#define GMAC_FLOW_CTRL_PT_SHIFT 16
150#define GMAC_FLOW_CTRL_UP 0x00000008 /* Unicast pause frame enable */
151#define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
152#define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
153#define GMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */
154
155/* DEBUG Register defines */
156/* MTL TxStatus FIFO */
157#define GMAC_DEBUG_TXSTSFSTS BIT(25) /* MTL TxStatus FIFO Full Status */
158#define GMAC_DEBUG_TXFSTS BIT(24) /* MTL Tx FIFO Not Empty Status */
159#define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */
160/* MTL Tx FIFO Read Controller Status */
161#define GMAC_DEBUG_TRCSTS_MASK GENMASK(21, 20)
162#define GMAC_DEBUG_TRCSTS_SHIFT 20
163#define GMAC_DEBUG_TRCSTS_IDLE 0
164#define GMAC_DEBUG_TRCSTS_READ 1
165#define GMAC_DEBUG_TRCSTS_TXW 2
166#define GMAC_DEBUG_TRCSTS_WRITE 3
167#define GMAC_DEBUG_TXPAUSED BIT(19) /* MAC Transmitter in PAUSE */
168/* MAC Transmit Frame Controller Status */
169#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
170#define GMAC_DEBUG_TFCSTS_SHIFT 17
171#define GMAC_DEBUG_TFCSTS_IDLE 0
172#define GMAC_DEBUG_TFCSTS_WAIT 1
173#define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
174#define GMAC_DEBUG_TFCSTS_XFER 3
175/* MAC GMII or MII Transmit Protocol Engine Status */
176#define GMAC_DEBUG_TPESTS BIT(16)
177#define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
178#define GMAC_DEBUG_RXFSTS_SHIFT 8
179#define GMAC_DEBUG_RXFSTS_EMPTY 0
180#define GMAC_DEBUG_RXFSTS_BT 1
181#define GMAC_DEBUG_RXFSTS_AT 2
182#define GMAC_DEBUG_RXFSTS_FULL 3
183#define GMAC_DEBUG_RRCSTS_MASK GENMASK(6, 5) /* MTL Rx FIFO Read Controller */
184#define GMAC_DEBUG_RRCSTS_SHIFT 5
185#define GMAC_DEBUG_RRCSTS_IDLE 0
186#define GMAC_DEBUG_RRCSTS_RDATA 1
187#define GMAC_DEBUG_RRCSTS_RSTAT 2
188#define GMAC_DEBUG_RRCSTS_FLUSH 3
189#define GMAC_DEBUG_RWCSTS BIT(4) /* MTL Rx FIFO Write Controller Active */
190/* MAC Receive Frame Controller FIFO Status */
191#define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
192#define GMAC_DEBUG_RFCFCSTS_SHIFT 1
193/* MAC GMII or MII Receive Protocol Engine Status */
194#define GMAC_DEBUG_RPESTS BIT(0)
195
196/*--- DMA BLOCK defines ---*/
197/* DMA Bus Mode register defines */
198#define DMA_BUS_MODE_DA 0x00000002 /* Arbitration scheme */
199#define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
200#define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */
201/* Programmable burst length (passed thorugh platform)*/
202#define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
203#define DMA_BUS_MODE_PBL_SHIFT 8
204#define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */
205
206enum rx_tx_priority_ratio {
207 double_ratio = 0x00004000, /* 2:1 */
208 triple_ratio = 0x00008000, /* 3:1 */
209 quadruple_ratio = 0x0000c000, /* 4:1 */
210};
211
212#define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */
213#define DMA_BUS_MODE_MB 0x04000000 /* Mixed burst */
214#define DMA_BUS_MODE_RPBL_MASK 0x007e0000 /* Rx-Programmable Burst Len */
215#define DMA_BUS_MODE_RPBL_SHIFT 17
216#define DMA_BUS_MODE_USP 0x00800000
217#define DMA_BUS_MODE_MAXPBL 0x01000000
218#define DMA_BUS_MODE_AAL 0x02000000
219
220/* DMA CRS Control and Status Register Mapping */
221#define DMA_HOST_TX_DESC 0x00001048 /* Current Host Tx descriptor */
222#define DMA_HOST_RX_DESC 0x0000104c /* Current Host Rx descriptor */
223/* DMA Bus Mode register defines */
224#define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */
225#define DMA_BUS_PR_RATIO_SHIFT 14
226#define DMA_BUS_FB 0x00010000 /* Fixed Burst */
227
228/* DMA operation mode defines (start/stop tx/rx are placed in common header)*/
229/* Disable Drop TCP/IP csum error */
230#define DMA_CONTROL_DT 0x04000000
231#define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */
232#define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */
233/* Threshold for Activating the FC */
234enum rfa {
235 act_full_minus_1 = 0x00800000,
236 act_full_minus_2 = 0x00800200,
237 act_full_minus_3 = 0x00800400,
238 act_full_minus_4 = 0x00800600,
239};
240/* Threshold for Deactivating the FC */
241enum rfd {
242 deac_full_minus_1 = 0x00400000,
243 deac_full_minus_2 = 0x00400800,
244 deac_full_minus_3 = 0x00401000,
245 deac_full_minus_4 = 0x00401800,
246};
247#define DMA_CONTROL_TSF 0x00200000 /* Transmit Store and Forward */
248
249enum ttc_control {
250 DMA_CONTROL_TTC_64 = 0x00000000,
251 DMA_CONTROL_TTC_128 = 0x00004000,
252 DMA_CONTROL_TTC_192 = 0x00008000,
253 DMA_CONTROL_TTC_256 = 0x0000c000,
254 DMA_CONTROL_TTC_40 = 0x00010000,
255 DMA_CONTROL_TTC_32 = 0x00014000,
256 DMA_CONTROL_TTC_24 = 0x00018000,
257 DMA_CONTROL_TTC_16 = 0x0001c000,
258};
259#define DMA_CONTROL_TC_TX_MASK 0xfffe3fff
260
261#define DMA_CONTROL_EFC 0x00000100
262#define DMA_CONTROL_FEF 0x00000080
263#define DMA_CONTROL_FUF 0x00000040
264
265/* Receive flow control activation field
266 * RFA field in DMA control register, bits 23,10:9
267 */
268#define DMA_CONTROL_RFA_MASK 0x00800600
269
270/* Receive flow control deactivation field
271 * RFD field in DMA control register, bits 22,12:11
272 */
273#define DMA_CONTROL_RFD_MASK 0x00401800
274
275/* RFD and RFA fields are encoded as follows
276 *
277 * Bit Field
278 * 0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled)
279 * 0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled)
280 * 0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled)
281 * 0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled)
282 * 1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled)
283 * 1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled)
284 * 1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled)
285 * 1,11 - Reserved
286 *
287 * RFD should always be > RFA for a given FIFO size. RFD == RFA may work,
288 * but packet throughput performance may not be as expected.
289 *
290 * Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame
291 * detection (IEEE Specification Requirement, Annex 31B, 31B.1, Pause
292 * Description).
293 *
294 * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6),
295 * is set to 0. This allows pause frames with a quanta of 0 to be sent
296 * as an XOFF message to the link peer.
297 */
298
299#define RFA_FULL_MINUS_1K 0x00000000
300#define RFA_FULL_MINUS_2K 0x00000200
301#define RFA_FULL_MINUS_3K 0x00000400
302#define RFA_FULL_MINUS_4K 0x00000600
303#define RFA_FULL_MINUS_5K 0x00800000
304#define RFA_FULL_MINUS_6K 0x00800200
305#define RFA_FULL_MINUS_7K 0x00800400
306
307#define RFD_FULL_MINUS_1K 0x00000000
308#define RFD_FULL_MINUS_2K 0x00000800
309#define RFD_FULL_MINUS_3K 0x00001000
310#define RFD_FULL_MINUS_4K 0x00001800
311#define RFD_FULL_MINUS_5K 0x00400000
312#define RFD_FULL_MINUS_6K 0x00400800
313#define RFD_FULL_MINUS_7K 0x00401000
314
315enum rtc_control {
316 DMA_CONTROL_RTC_64 = 0x00000000,
317 DMA_CONTROL_RTC_32 = 0x00000008,
318 DMA_CONTROL_RTC_96 = 0x00000010,
319 DMA_CONTROL_RTC_128 = 0x00000018,
320};
321#define DMA_CONTROL_TC_RX_MASK 0xffffffe7
322
323#define DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */
324
325/* MMC registers offset */
326#define GMAC_MMC_CTRL 0x100
327#define GMAC_MMC_RX_INTR 0x104
328#define GMAC_MMC_TX_INTR 0x108
329#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208
330#define GMAC_EXTHASH_BASE 0x500
331
332extern const struct stmmac_dma_ops dwmac1000_dma_ops;
333#endif /* __DWMAC1000_H__ */
334

source code of linux/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h