1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /******************************************************************************* |
3 | DWMAC DMA Header file. |
4 | |
5 | Copyright (C) 2007-2009 STMicroelectronics Ltd |
6 | |
7 | |
8 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
9 | *******************************************************************************/ |
10 | |
11 | #ifndef __DWMAC_DMA_H__ |
12 | #define __DWMAC_DMA_H__ |
13 | |
14 | /* DMA CRS Control and Status Register Mapping */ |
15 | #define DMA_BUS_MODE 0x00001000 /* Bus Mode */ |
16 | #define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */ |
17 | #define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */ |
18 | #define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */ |
19 | #define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */ |
20 | #define DMA_STATUS 0x00001014 /* Status Register */ |
21 | #define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */ |
22 | #define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */ |
23 | #define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */ |
24 | |
25 | /* SW Reset */ |
26 | #define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */ |
27 | |
28 | /* Rx watchdog register */ |
29 | #define DMA_RX_WATCHDOG 0x00001024 |
30 | |
31 | /* AXI Master Bus Mode */ |
32 | #define DMA_AXI_BUS_MODE 0x00001028 |
33 | |
34 | #define DMA_AXI_EN_LPI BIT(31) |
35 | #define DMA_AXI_LPI_XIT_FRM BIT(30) |
36 | #define DMA_AXI_WR_OSR_LMT GENMASK(23, 20) |
37 | #define DMA_AXI_WR_OSR_LMT_SHIFT 20 |
38 | #define DMA_AXI_WR_OSR_LMT_MASK 0xf |
39 | #define DMA_AXI_RD_OSR_LMT GENMASK(19, 16) |
40 | #define DMA_AXI_RD_OSR_LMT_SHIFT 16 |
41 | #define DMA_AXI_RD_OSR_LMT_MASK 0xf |
42 | |
43 | #define DMA_AXI_OSR_MAX 0xf |
44 | #define DMA_AXI_MAX_OSR_LIMIT ((DMA_AXI_OSR_MAX << DMA_AXI_WR_OSR_LMT_SHIFT) | \ |
45 | (DMA_AXI_OSR_MAX << DMA_AXI_RD_OSR_LMT_SHIFT)) |
46 | #define DMA_AXI_1KBBE BIT(13) |
47 | #define DMA_AXI_AAL BIT(12) |
48 | #define DMA_AXI_BLEN256 BIT(7) |
49 | #define DMA_AXI_BLEN128 BIT(6) |
50 | #define DMA_AXI_BLEN64 BIT(5) |
51 | #define DMA_AXI_BLEN32 BIT(4) |
52 | #define DMA_AXI_BLEN16 BIT(3) |
53 | #define DMA_AXI_BLEN8 BIT(2) |
54 | #define DMA_AXI_BLEN4 BIT(1) |
55 | #define DMA_BURST_LEN_DEFAULT (DMA_AXI_BLEN256 | DMA_AXI_BLEN128 | \ |
56 | DMA_AXI_BLEN64 | DMA_AXI_BLEN32 | \ |
57 | DMA_AXI_BLEN16 | DMA_AXI_BLEN8 | \ |
58 | DMA_AXI_BLEN4) |
59 | |
60 | #define DMA_AXI_UNDEF BIT(0) |
61 | |
62 | #define DMA_AXI_BURST_LEN_MASK 0x000000FE |
63 | |
64 | #define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */ |
65 | #define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */ |
66 | #define DMA_HW_FEATURE 0x00001058 /* HW Feature Register */ |
67 | |
68 | /* DMA Control register defines */ |
69 | #define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */ |
70 | #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */ |
71 | |
72 | /* DMA Normal interrupt */ |
73 | #define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */ |
74 | #define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */ |
75 | #define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */ |
76 | #define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */ |
77 | #define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */ |
78 | |
79 | #define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \ |
80 | DMA_INTR_ENA_TIE) |
81 | |
82 | /* DMA Abnormal interrupt */ |
83 | #define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */ |
84 | #define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */ |
85 | #define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */ |
86 | #define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */ |
87 | #define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */ |
88 | #define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */ |
89 | #define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */ |
90 | #define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */ |
91 | #define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */ |
92 | #define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */ |
93 | |
94 | #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \ |
95 | DMA_INTR_ENA_UNE) |
96 | |
97 | /* DMA default interrupt mask */ |
98 | #define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL) |
99 | #define DMA_INTR_DEFAULT_RX (DMA_INTR_ENA_RIE) |
100 | #define DMA_INTR_DEFAULT_TX (DMA_INTR_ENA_TIE) |
101 | |
102 | /* DMA Status register defines */ |
103 | #define DMA_STATUS_GLPII 0x40000000 /* GMAC LPI interrupt */ |
104 | #define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */ |
105 | #define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */ |
106 | #define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */ |
107 | #define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */ |
108 | #define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */ |
109 | #define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */ |
110 | #define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */ |
111 | #define DMA_STATUS_TS_SHIFT 20 |
112 | #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */ |
113 | #define DMA_STATUS_RS_SHIFT 17 |
114 | #define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */ |
115 | #define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */ |
116 | #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */ |
117 | #define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */ |
118 | #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */ |
119 | #define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */ |
120 | #define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */ |
121 | #define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */ |
122 | #define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */ |
123 | #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */ |
124 | #define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */ |
125 | #define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */ |
126 | #define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */ |
127 | #define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */ |
128 | #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */ |
129 | #define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */ |
130 | |
131 | #define DMA_STATUS_MSK_COMMON (DMA_STATUS_NIS | \ |
132 | DMA_STATUS_AIS | \ |
133 | DMA_STATUS_FBI) |
134 | |
135 | #define DMA_STATUS_MSK_RX (DMA_STATUS_ERI | \ |
136 | DMA_STATUS_RWT | \ |
137 | DMA_STATUS_RPS | \ |
138 | DMA_STATUS_RU | \ |
139 | DMA_STATUS_RI | \ |
140 | DMA_STATUS_OVF | \ |
141 | DMA_STATUS_MSK_COMMON) |
142 | |
143 | #define DMA_STATUS_MSK_TX (DMA_STATUS_ETI | \ |
144 | DMA_STATUS_UNF | \ |
145 | DMA_STATUS_TJT | \ |
146 | DMA_STATUS_TU | \ |
147 | DMA_STATUS_TPS | \ |
148 | DMA_STATUS_TI | \ |
149 | DMA_STATUS_MSK_COMMON) |
150 | |
151 | #define NUM_DWMAC100_DMA_REGS 9 |
152 | #define NUM_DWMAC1000_DMA_REGS 23 |
153 | #define NUM_DWMAC4_DMA_REGS 27 |
154 | |
155 | void dwmac_enable_dma_transmission(void __iomem *ioaddr); |
156 | void dwmac_enable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, |
157 | u32 chan, bool rx, bool tx); |
158 | void dwmac_disable_dma_irq(struct stmmac_priv *priv, void __iomem *ioaddr, |
159 | u32 chan, bool rx, bool tx); |
160 | void dwmac_dma_start_tx(struct stmmac_priv *priv, void __iomem *ioaddr, |
161 | u32 chan); |
162 | void dwmac_dma_stop_tx(struct stmmac_priv *priv, void __iomem *ioaddr, |
163 | u32 chan); |
164 | void dwmac_dma_start_rx(struct stmmac_priv *priv, void __iomem *ioaddr, |
165 | u32 chan); |
166 | void dwmac_dma_stop_rx(struct stmmac_priv *priv, void __iomem *ioaddr, |
167 | u32 chan); |
168 | int dwmac_dma_interrupt(struct stmmac_priv *priv, void __iomem *ioaddr, |
169 | struct stmmac_extra_stats *x, u32 chan, u32 dir); |
170 | int dwmac_dma_reset(void __iomem *ioaddr); |
171 | |
172 | #endif /* __DWMAC_DMA_H__ */ |
173 | |