1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /******************************************************************************* |
3 | This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. |
4 | DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for |
5 | developing this code. |
6 | |
7 | This contains the functions to handle the dma. |
8 | |
9 | Copyright (C) 2007-2009 STMicroelectronics Ltd |
10 | |
11 | |
12 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> |
13 | *******************************************************************************/ |
14 | |
15 | #include <asm/io.h> |
16 | #include "dwmac1000.h" |
17 | #include "dwmac_dma.h" |
18 | |
19 | static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) |
20 | { |
21 | u32 value = readl(addr: ioaddr + DMA_AXI_BUS_MODE); |
22 | int i; |
23 | |
24 | pr_info("dwmac1000: Master AXI performs %s burst length\n" , |
25 | !(value & DMA_AXI_UNDEF) ? "fixed" : "any" ); |
26 | |
27 | if (axi->axi_lpi_en) |
28 | value |= DMA_AXI_EN_LPI; |
29 | if (axi->axi_xit_frm) |
30 | value |= DMA_AXI_LPI_XIT_FRM; |
31 | |
32 | value &= ~DMA_AXI_WR_OSR_LMT; |
33 | value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) << |
34 | DMA_AXI_WR_OSR_LMT_SHIFT; |
35 | |
36 | value &= ~DMA_AXI_RD_OSR_LMT; |
37 | value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) << |
38 | DMA_AXI_RD_OSR_LMT_SHIFT; |
39 | |
40 | /* Depending on the UNDEF bit the Master AXI will perform any burst |
41 | * length according to the BLEN programmed (by default all BLEN are |
42 | * set). |
43 | */ |
44 | for (i = 0; i < AXI_BLEN; i++) { |
45 | switch (axi->axi_blen[i]) { |
46 | case 256: |
47 | value |= DMA_AXI_BLEN256; |
48 | break; |
49 | case 128: |
50 | value |= DMA_AXI_BLEN128; |
51 | break; |
52 | case 64: |
53 | value |= DMA_AXI_BLEN64; |
54 | break; |
55 | case 32: |
56 | value |= DMA_AXI_BLEN32; |
57 | break; |
58 | case 16: |
59 | value |= DMA_AXI_BLEN16; |
60 | break; |
61 | case 8: |
62 | value |= DMA_AXI_BLEN8; |
63 | break; |
64 | case 4: |
65 | value |= DMA_AXI_BLEN4; |
66 | break; |
67 | } |
68 | } |
69 | |
70 | writel(val: value, addr: ioaddr + DMA_AXI_BUS_MODE); |
71 | } |
72 | |
73 | static void dwmac1000_dma_init(void __iomem *ioaddr, |
74 | struct stmmac_dma_cfg *dma_cfg, int atds) |
75 | { |
76 | u32 value = readl(addr: ioaddr + DMA_BUS_MODE); |
77 | int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; |
78 | int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; |
79 | |
80 | /* |
81 | * Set the DMA PBL (Programmable Burst Length) mode. |
82 | * |
83 | * Note: before stmmac core 3.50 this mode bit was 4xPBL, and |
84 | * post 3.5 mode bit acts as 8*PBL. |
85 | */ |
86 | if (dma_cfg->pblx8) |
87 | value |= DMA_BUS_MODE_MAXPBL; |
88 | value |= DMA_BUS_MODE_USP; |
89 | value &= ~(DMA_BUS_MODE_PBL_MASK | DMA_BUS_MODE_RPBL_MASK); |
90 | value |= (txpbl << DMA_BUS_MODE_PBL_SHIFT); |
91 | value |= (rxpbl << DMA_BUS_MODE_RPBL_SHIFT); |
92 | |
93 | /* Set the Fixed burst mode */ |
94 | if (dma_cfg->fixed_burst) |
95 | value |= DMA_BUS_MODE_FB; |
96 | |
97 | /* Mixed Burst has no effect when fb is set */ |
98 | if (dma_cfg->mixed_burst) |
99 | value |= DMA_BUS_MODE_MB; |
100 | |
101 | if (atds) |
102 | value |= DMA_BUS_MODE_ATDS; |
103 | |
104 | if (dma_cfg->aal) |
105 | value |= DMA_BUS_MODE_AAL; |
106 | |
107 | writel(val: value, addr: ioaddr + DMA_BUS_MODE); |
108 | |
109 | /* Mask interrupts by writing to CSR7 */ |
110 | writel(DMA_INTR_DEFAULT_MASK, addr: ioaddr + DMA_INTR_ENA); |
111 | } |
112 | |
113 | static void dwmac1000_dma_init_rx(struct stmmac_priv *priv, |
114 | void __iomem *ioaddr, |
115 | struct stmmac_dma_cfg *dma_cfg, |
116 | dma_addr_t dma_rx_phy, u32 chan) |
117 | { |
118 | /* RX descriptor base address list must be written into DMA CSR3 */ |
119 | writel(lower_32_bits(dma_rx_phy), addr: ioaddr + DMA_RCV_BASE_ADDR); |
120 | } |
121 | |
122 | static void dwmac1000_dma_init_tx(struct stmmac_priv *priv, |
123 | void __iomem *ioaddr, |
124 | struct stmmac_dma_cfg *dma_cfg, |
125 | dma_addr_t dma_tx_phy, u32 chan) |
126 | { |
127 | /* TX descriptor base address list must be written into DMA CSR4 */ |
128 | writel(lower_32_bits(dma_tx_phy), addr: ioaddr + DMA_TX_BASE_ADDR); |
129 | } |
130 | |
131 | static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz) |
132 | { |
133 | csr6 &= ~DMA_CONTROL_RFA_MASK; |
134 | csr6 &= ~DMA_CONTROL_RFD_MASK; |
135 | |
136 | /* Leave flow control disabled if receive fifo size is less than |
137 | * 4K or 0. Otherwise, send XOFF when fifo is 1K less than full, |
138 | * and send XON when 2K less than full. |
139 | */ |
140 | if (rxfifosz < 4096) { |
141 | csr6 &= ~DMA_CONTROL_EFC; |
142 | pr_debug("GMAC: disabling flow control, rxfifo too small(%d)\n" , |
143 | rxfifosz); |
144 | } else { |
145 | csr6 |= DMA_CONTROL_EFC; |
146 | csr6 |= RFA_FULL_MINUS_1K; |
147 | csr6 |= RFD_FULL_MINUS_2K; |
148 | } |
149 | return csr6; |
150 | } |
151 | |
152 | static void dwmac1000_dma_operation_mode_rx(struct stmmac_priv *priv, |
153 | void __iomem *ioaddr, int mode, |
154 | u32 channel, int fifosz, u8 qmode) |
155 | { |
156 | u32 csr6 = readl(addr: ioaddr + DMA_CONTROL); |
157 | |
158 | if (mode == SF_DMA_MODE) { |
159 | pr_debug("GMAC: enable RX store and forward mode\n" ); |
160 | csr6 |= DMA_CONTROL_RSF; |
161 | } else { |
162 | pr_debug("GMAC: disable RX SF mode (threshold %d)\n" , mode); |
163 | csr6 &= ~DMA_CONTROL_RSF; |
164 | csr6 &= DMA_CONTROL_TC_RX_MASK; |
165 | if (mode <= 32) |
166 | csr6 |= DMA_CONTROL_RTC_32; |
167 | else if (mode <= 64) |
168 | csr6 |= DMA_CONTROL_RTC_64; |
169 | else if (mode <= 96) |
170 | csr6 |= DMA_CONTROL_RTC_96; |
171 | else |
172 | csr6 |= DMA_CONTROL_RTC_128; |
173 | } |
174 | |
175 | /* Configure flow control based on rx fifo size */ |
176 | csr6 = dwmac1000_configure_fc(csr6, rxfifosz: fifosz); |
177 | |
178 | writel(val: csr6, addr: ioaddr + DMA_CONTROL); |
179 | } |
180 | |
181 | static void dwmac1000_dma_operation_mode_tx(struct stmmac_priv *priv, |
182 | void __iomem *ioaddr, int mode, |
183 | u32 channel, int fifosz, u8 qmode) |
184 | { |
185 | u32 csr6 = readl(addr: ioaddr + DMA_CONTROL); |
186 | |
187 | if (mode == SF_DMA_MODE) { |
188 | pr_debug("GMAC: enable TX store and forward mode\n" ); |
189 | /* Transmit COE type 2 cannot be done in cut-through mode. */ |
190 | csr6 |= DMA_CONTROL_TSF; |
191 | /* Operating on second frame increase the performance |
192 | * especially when transmit store-and-forward is used. |
193 | */ |
194 | csr6 |= DMA_CONTROL_OSF; |
195 | } else { |
196 | pr_debug("GMAC: disabling TX SF (threshold %d)\n" , mode); |
197 | csr6 &= ~DMA_CONTROL_TSF; |
198 | csr6 &= DMA_CONTROL_TC_TX_MASK; |
199 | /* Set the transmit threshold */ |
200 | if (mode <= 32) |
201 | csr6 |= DMA_CONTROL_TTC_32; |
202 | else if (mode <= 64) |
203 | csr6 |= DMA_CONTROL_TTC_64; |
204 | else if (mode <= 128) |
205 | csr6 |= DMA_CONTROL_TTC_128; |
206 | else if (mode <= 192) |
207 | csr6 |= DMA_CONTROL_TTC_192; |
208 | else |
209 | csr6 |= DMA_CONTROL_TTC_256; |
210 | } |
211 | |
212 | writel(val: csr6, addr: ioaddr + DMA_CONTROL); |
213 | } |
214 | |
215 | static void dwmac1000_dump_dma_regs(struct stmmac_priv *priv, |
216 | void __iomem *ioaddr, u32 *reg_space) |
217 | { |
218 | int i; |
219 | |
220 | for (i = 0; i < NUM_DWMAC1000_DMA_REGS; i++) |
221 | if ((i < 12) || (i > 17)) |
222 | reg_space[DMA_BUS_MODE / 4 + i] = |
223 | readl(addr: ioaddr + DMA_BUS_MODE + i * 4); |
224 | } |
225 | |
226 | static int dwmac1000_get_hw_feature(void __iomem *ioaddr, |
227 | struct dma_features *dma_cap) |
228 | { |
229 | u32 hw_cap = readl(addr: ioaddr + DMA_HW_FEATURE); |
230 | |
231 | if (!hw_cap) { |
232 | /* 0x00000000 is the value read on old hardware that does not |
233 | * implement this register |
234 | */ |
235 | return -EOPNOTSUPP; |
236 | } |
237 | |
238 | dma_cap->mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); |
239 | dma_cap->mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; |
240 | dma_cap->half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; |
241 | dma_cap->hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; |
242 | dma_cap->multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5; |
243 | dma_cap->pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; |
244 | dma_cap->sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; |
245 | dma_cap->pmt_remote_wake_up = (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; |
246 | dma_cap->pmt_magic_frame = (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; |
247 | /* MMC */ |
248 | dma_cap->rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; |
249 | /* IEEE 1588-2002 */ |
250 | dma_cap->time_stamp = |
251 | (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; |
252 | /* IEEE 1588-2008 */ |
253 | dma_cap->atime_stamp = (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; |
254 | /* 802.3az - Energy-Efficient Ethernet (EEE) */ |
255 | dma_cap->eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; |
256 | dma_cap->av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; |
257 | /* TX and RX csum */ |
258 | dma_cap->tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; |
259 | dma_cap->rx_coe_type1 = (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; |
260 | dma_cap->rx_coe_type2 = (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; |
261 | dma_cap->rxfifo_over_2048 = (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; |
262 | /* TX and RX number of channels */ |
263 | dma_cap->number_rx_channel = (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; |
264 | dma_cap->number_tx_channel = (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; |
265 | /* Alternate (enhanced) DESC mode */ |
266 | dma_cap->enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; |
267 | |
268 | return 0; |
269 | } |
270 | |
271 | static void dwmac1000_rx_watchdog(struct stmmac_priv *priv, |
272 | void __iomem *ioaddr, u32 riwt, u32 queue) |
273 | { |
274 | writel(val: riwt, addr: ioaddr + DMA_RX_WATCHDOG); |
275 | } |
276 | |
277 | const struct stmmac_dma_ops dwmac1000_dma_ops = { |
278 | .reset = dwmac_dma_reset, |
279 | .init = dwmac1000_dma_init, |
280 | .init_rx_chan = dwmac1000_dma_init_rx, |
281 | .init_tx_chan = dwmac1000_dma_init_tx, |
282 | .axi = dwmac1000_dma_axi, |
283 | .dump_regs = dwmac1000_dump_dma_regs, |
284 | .dma_rx_mode = dwmac1000_dma_operation_mode_rx, |
285 | .dma_tx_mode = dwmac1000_dma_operation_mode_tx, |
286 | .enable_dma_transmission = dwmac_enable_dma_transmission, |
287 | .enable_dma_irq = dwmac_enable_dma_irq, |
288 | .disable_dma_irq = dwmac_disable_dma_irq, |
289 | .start_tx = dwmac_dma_start_tx, |
290 | .stop_tx = dwmac_dma_stop_tx, |
291 | .start_rx = dwmac_dma_start_rx, |
292 | .stop_rx = dwmac_dma_stop_rx, |
293 | .dma_interrupt = dwmac_dma_interrupt, |
294 | .get_hw_feature = dwmac1000_get_hw_feature, |
295 | .rx_watchdog = dwmac1000_rx_watchdog, |
296 | }; |
297 | |