1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* Texas Instruments ICSSG Ethernet Driver |
3 | * |
4 | * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ |
5 | * |
6 | */ |
7 | |
8 | #include <linux/etherdevice.h> |
9 | #include <linux/regmap.h> |
10 | #include <linux/types.h> |
11 | |
12 | #include "icssg_mii_rt.h" |
13 | #include "icssg_prueth.h" |
14 | |
15 | void icssg_mii_update_ipg(struct regmap *mii_rt, int mii, u32 ipg) |
16 | { |
17 | u32 val; |
18 | |
19 | if (mii == ICSS_MII0) { |
20 | regmap_write(map: mii_rt, PRUSS_MII_RT_TX_IPG0, val: ipg); |
21 | } else { |
22 | regmap_read(map: mii_rt, PRUSS_MII_RT_TX_IPG0, val: &val); |
23 | regmap_write(map: mii_rt, PRUSS_MII_RT_TX_IPG1, val: ipg); |
24 | regmap_write(map: mii_rt, PRUSS_MII_RT_TX_IPG0, val); |
25 | } |
26 | } |
27 | |
28 | void icssg_mii_update_mtu(struct regmap *mii_rt, int mii, int mtu) |
29 | { |
30 | mtu += (ETH_HLEN + ETH_FCS_LEN); |
31 | if (mii == ICSS_MII0) { |
32 | regmap_update_bits(map: mii_rt, |
33 | PRUSS_MII_RT_RX_FRMS0, |
34 | PRUSS_MII_RT_RX_FRMS_MAX_FRM_MASK, |
35 | val: (mtu - 1) << PRUSS_MII_RT_RX_FRMS_MAX_FRM_SHIFT); |
36 | } else { |
37 | regmap_update_bits(map: mii_rt, |
38 | PRUSS_MII_RT_RX_FRMS1, |
39 | PRUSS_MII_RT_RX_FRMS_MAX_FRM_MASK, |
40 | val: (mtu - 1) << PRUSS_MII_RT_RX_FRMS_MAX_FRM_SHIFT); |
41 | } |
42 | } |
43 | |
44 | void icssg_update_rgmii_cfg(struct regmap *miig_rt, struct prueth_emac *emac) |
45 | { |
46 | u32 gig_en_mask, gig_val = 0, full_duplex_mask, full_duplex_val = 0; |
47 | int slice = prueth_emac_slice(emac); |
48 | u32 inband_en_mask, inband_val = 0; |
49 | |
50 | gig_en_mask = (slice == ICSS_MII0) ? RGMII_CFG_GIG_EN_MII0 : |
51 | RGMII_CFG_GIG_EN_MII1; |
52 | if (emac->speed == SPEED_1000) |
53 | gig_val = gig_en_mask; |
54 | regmap_update_bits(map: miig_rt, RGMII_CFG_OFFSET, mask: gig_en_mask, val: gig_val); |
55 | |
56 | inband_en_mask = (slice == ICSS_MII0) ? RGMII_CFG_INBAND_EN_MII0 : |
57 | RGMII_CFG_INBAND_EN_MII1; |
58 | if (emac->speed == SPEED_10 && phy_interface_mode_is_rgmii(mode: emac->phy_if)) |
59 | inband_val = inband_en_mask; |
60 | regmap_update_bits(map: miig_rt, RGMII_CFG_OFFSET, mask: inband_en_mask, val: inband_val); |
61 | |
62 | full_duplex_mask = (slice == ICSS_MII0) ? RGMII_CFG_FULL_DUPLEX_MII0 : |
63 | RGMII_CFG_FULL_DUPLEX_MII1; |
64 | if (emac->duplex == DUPLEX_FULL) |
65 | full_duplex_val = full_duplex_mask; |
66 | regmap_update_bits(map: miig_rt, RGMII_CFG_OFFSET, mask: full_duplex_mask, |
67 | val: full_duplex_val); |
68 | } |
69 | |
70 | void icssg_miig_set_interface_mode(struct regmap *miig_rt, int mii, phy_interface_t phy_if) |
71 | { |
72 | u32 val, mask, shift; |
73 | |
74 | mask = mii == ICSS_MII0 ? ICSSG_CFG_MII0_MODE : ICSSG_CFG_MII1_MODE; |
75 | shift = mii == ICSS_MII0 ? ICSSG_CFG_MII0_MODE_SHIFT : ICSSG_CFG_MII1_MODE_SHIFT; |
76 | |
77 | val = MII_MODE_RGMII; |
78 | if (phy_if == PHY_INTERFACE_MODE_MII) |
79 | val = MII_MODE_MII; |
80 | |
81 | val <<= shift; |
82 | regmap_update_bits(map: miig_rt, ICSSG_CFG_OFFSET, mask, val); |
83 | regmap_read(map: miig_rt, ICSSG_CFG_OFFSET, val: &val); |
84 | } |
85 | |
86 | u32 icssg_rgmii_cfg_get_bitfield(struct regmap *miig_rt, u32 mask, u32 shift) |
87 | { |
88 | u32 val; |
89 | |
90 | regmap_read(map: miig_rt, RGMII_CFG_OFFSET, val: &val); |
91 | val &= mask; |
92 | val >>= shift; |
93 | |
94 | return val; |
95 | } |
96 | |
97 | u32 icssg_rgmii_get_speed(struct regmap *miig_rt, int mii) |
98 | { |
99 | u32 shift = RGMII_CFG_SPEED_MII0_SHIFT, mask = RGMII_CFG_SPEED_MII0; |
100 | |
101 | if (mii == ICSS_MII1) { |
102 | shift = RGMII_CFG_SPEED_MII1_SHIFT; |
103 | mask = RGMII_CFG_SPEED_MII1; |
104 | } |
105 | |
106 | return icssg_rgmii_cfg_get_bitfield(miig_rt, mask, shift); |
107 | } |
108 | |
109 | u32 icssg_rgmii_get_fullduplex(struct regmap *miig_rt, int mii) |
110 | { |
111 | u32 shift = RGMII_CFG_FULLDUPLEX_MII0_SHIFT; |
112 | u32 mask = RGMII_CFG_FULLDUPLEX_MII0; |
113 | |
114 | if (mii == ICSS_MII1) { |
115 | shift = RGMII_CFG_FULLDUPLEX_MII1_SHIFT; |
116 | mask = RGMII_CFG_FULLDUPLEX_MII1; |
117 | } |
118 | |
119 | return icssg_rgmii_cfg_get_bitfield(miig_rt, mask, shift); |
120 | } |
121 | |