1	// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2	/*
3	* Copyright (C) 2005-2014, 2018-2023 Intel Corporation
4	* Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5	* Copyright (C) 2016-2017 Intel Deutschland GmbH
6	*/
7	#include <linux/types.h>
8	#include <linux/slab.h>
9	#include <linux/export.h>
10	#include <linux/etherdevice.h>
11	#include <linux/pci.h>
12	#include <linux/firmware.h>
13
14	#include "iwl-drv.h"
15	#include "iwl-modparams.h"
16	#include "iwl-nvm-parse.h"
17	#include "iwl-prph.h"
18	#include "iwl-io.h"
19	#include "iwl-csr.h"
20	#include "fw/acpi.h"
21	#include "fw/api/nvm-reg.h"
22	#include "fw/api/commands.h"
23	#include "fw/api/cmdhdr.h"
24	#include "fw/img.h"
25	#include "mei/iwl-mei.h"
26
27	/* NVM offsets (in words) definitions */
28	enum nvm_offsets {
29	/* NVM HW-Section offset (in words) definitions */
30	SUBSYSTEM_ID = 0x0A,
31	HW_ADDR = 0x15,
32
33	/* NVM SW-Section offset (in words) definitions */
34	NVM_SW_SECTION = 0x1C0,
35	NVM_VERSION = 0,
36	RADIO_CFG = 1,
37	SKU = 2,
38	N_HW_ADDRS = 3,
39	NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
40
41	/* NVM calibration section offset (in words) definitions */
42	NVM_CALIB_SECTION = 0x2B8,
43	XTAL_CALIB = 0x316 - NVM_CALIB_SECTION,
44
45	/* NVM REGULATORY -Section offset (in words) definitions */
46	NVM_CHANNELS_SDP = 0,
47	};
48
49	enum ext_nvm_offsets {
50	/* NVM HW-Section offset (in words) definitions */
51	MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
52
53	/* NVM SW-Section offset (in words) definitions */
54	NVM_VERSION_EXT_NVM = 0,
55	N_HW_ADDRS_FAMILY_8000 = 3,
56
57	/* NVM PHY_SKU-Section offset (in words) definitions */
58	RADIO_CFG_FAMILY_EXT_NVM = 0,
59	SKU_FAMILY_8000 = 2,
60
61	/* NVM REGULATORY -Section offset (in words) definitions */
62	NVM_CHANNELS_EXTENDED = 0,
63	NVM_LAR_OFFSET_OLD = 0x4C7,
64	NVM_LAR_OFFSET = 0x507,
65	NVM_LAR_ENABLED = 0x7,
66	};
67
68	/* SKU Capabilities (actual values from NVM definition) */
69	enum nvm_sku_bits {
70	NVM_SKU_CAP_BAND_24GHZ = BIT(0),
71	NVM_SKU_CAP_BAND_52GHZ = BIT(1),
72	NVM_SKU_CAP_11N_ENABLE = BIT(2),
73	NVM_SKU_CAP_11AC_ENABLE = BIT(3),
74	NVM_SKU_CAP_MIMO_DISABLE = BIT(5),
75	};
76
77	/*
78	* These are the channel numbers in the order that they are stored in the NVM
79	*/
80	static const u16 iwl_nvm_channels[] = {
81	/* 2.4 GHz */
82	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
83	/* 5 GHz */
84	36, 40, 44, 48, 52, 56, 60, 64,
85	100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
86	149, 153, 157, 161, 165
87	};
88
89	static const u16 iwl_ext_nvm_channels[] = {
90	/* 2.4 GHz */
91	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
92	/* 5 GHz */
93	36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
94	96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
95	149, 153, 157, 161, 165, 169, 173, 177, 181
96	};
97
98	static const u16 iwl_uhb_nvm_channels[] = {
99	/* 2.4 GHz */
100	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
101	/* 5 GHz */
102	36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
103	96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
104	149, 153, 157, 161, 165, 169, 173, 177, 181,
105	/* 6-7 GHz */
106	1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69,
107	73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129,
108	133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185,
109	189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233
110	};
111
112	#define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
113	#define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels)
114	#define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels)
115	#define NUM_2GHZ_CHANNELS 14
116	#define NUM_5GHZ_CHANNELS 37
117	#define FIRST_2GHZ_HT_MINUS 5
118	#define LAST_2GHZ_HT_PLUS 9
119	#define N_HW_ADDR_MASK 0xF
120
121	/* rate data (static) */
122	static struct ieee80211_rate iwl_cfg80211_rates[] = {
123	{ .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
124	{ .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
125	.flags = IEEE80211_RATE_SHORT_PREAMBLE, },
126	{ .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
127	.flags = IEEE80211_RATE_SHORT_PREAMBLE, },
128	{ .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
129	.flags = IEEE80211_RATE_SHORT_PREAMBLE, },
130	{ .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
131	{ .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
132	{ .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
133	{ .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
134	{ .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
135	{ .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
136	{ .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
137	{ .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
138	};
139	#define RATES_24_OFFS 0
140	#define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
141	#define RATES_52_OFFS 4
142	#define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
143
144	/**
145	* enum iwl_nvm_channel_flags - channel flags in NVM
146	* @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
147	* @NVM_CHANNEL_IBSS: usable as an IBSS channel
148	* @NVM_CHANNEL_ACTIVE: active scanning allowed
149	* @NVM_CHANNEL_RADAR: radar detection required
150	* @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
151	* @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
152	* on same channel on 2.4 or same UNII band on 5.2
153	* @NVM_CHANNEL_UNIFORM: uniform spreading required
154	* @NVM_CHANNEL_20MHZ: 20 MHz channel okay
155	* @NVM_CHANNEL_40MHZ: 40 MHz channel okay
156	* @NVM_CHANNEL_80MHZ: 80 MHz channel okay
157	* @NVM_CHANNEL_160MHZ: 160 MHz channel okay
158	* @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
159	* @NVM_CHANNEL_VLP: client support connection to UHB VLP AP
160	* @NVM_CHANNEL_AFC: client support connection to UHB AFC AP
161	*/
162	enum iwl_nvm_channel_flags {
163	NVM_CHANNEL_VALID = BIT(0),
164	NVM_CHANNEL_IBSS = BIT(1),
165	NVM_CHANNEL_ACTIVE = BIT(3),
166	NVM_CHANNEL_RADAR = BIT(4),
167	NVM_CHANNEL_INDOOR_ONLY = BIT(5),
168	NVM_CHANNEL_GO_CONCURRENT = BIT(6),
169	NVM_CHANNEL_UNIFORM = BIT(7),
170	NVM_CHANNEL_20MHZ = BIT(8),
171	NVM_CHANNEL_40MHZ = BIT(9),
172	NVM_CHANNEL_80MHZ = BIT(10),
173	NVM_CHANNEL_160MHZ = BIT(11),
174	NVM_CHANNEL_DC_HIGH = BIT(12),
175	NVM_CHANNEL_VLP = BIT(13),
176	NVM_CHANNEL_AFC = BIT(14),
177	};
178
179	/**
180	* enum iwl_reg_capa_flags_v1 - global flags applied for the whole regulatory
181	* domain.
182	* @REG_CAPA_V1_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
183	* 2.4Ghz band is allowed.
184	* @REG_CAPA_V1_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
185	* 5Ghz band is allowed.
186	* @REG_CAPA_V1_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
187	* for this regulatory domain (valid only in 5Ghz).
188	* @REG_CAPA_V1_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
189	* for this regulatory domain (valid only in 5Ghz).
190	* @REG_CAPA_V1_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
191	* @REG_CAPA_V1_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
192	* @REG_CAPA_V1_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden
193	* for this regulatory domain (valid only in 5Ghz).
194	* @REG_CAPA_V1_DC_HIGH_ENABLED: DC HIGH allowed.
195	* @REG_CAPA_V1_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
196	*/
197	enum iwl_reg_capa_flags_v1 {
198	REG_CAPA_V1_BF_CCD_LOW_BAND = BIT(0),
199	REG_CAPA_V1_BF_CCD_HIGH_BAND = BIT(1),
200	REG_CAPA_V1_160MHZ_ALLOWED = BIT(2),
201	REG_CAPA_V1_80MHZ_ALLOWED = BIT(3),
202	REG_CAPA_V1_MCS_8_ALLOWED = BIT(4),
203	REG_CAPA_V1_MCS_9_ALLOWED = BIT(5),
204	REG_CAPA_V1_40MHZ_FORBIDDEN = BIT(7),
205	REG_CAPA_V1_DC_HIGH_ENABLED = BIT(9),
206	REG_CAPA_V1_11AX_DISABLED = BIT(10),
207	}; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_1 */
208
209	/**
210	* enum iwl_reg_capa_flags_v2 - global flags applied for the whole regulatory
211	* domain (version 2).
212	* @REG_CAPA_V2_STRADDLE_DISABLED: Straddle channels (144, 142, 138) are
213	* disabled.
214	* @REG_CAPA_V2_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
215	* 2.4Ghz band is allowed.
216	* @REG_CAPA_V2_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
217	* 5Ghz band is allowed.
218	* @REG_CAPA_V2_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
219	* for this regulatory domain (valid only in 5Ghz).
220	* @REG_CAPA_V2_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
221	* for this regulatory domain (valid only in 5Ghz).
222	* @REG_CAPA_V2_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
223	* @REG_CAPA_V2_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
224	* @REG_CAPA_V2_WEATHER_DISABLED: Weather radar channels (120, 124, 128, 118,
225	* 126, 122) are disabled.
226	* @REG_CAPA_V2_40MHZ_ALLOWED: 11n channel with a width of 40Mhz is allowed
227	* for this regulatory domain (uvalid only in 5Ghz).
228	* @REG_CAPA_V2_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
229	*/
230	enum iwl_reg_capa_flags_v2 {
231	REG_CAPA_V2_STRADDLE_DISABLED = BIT(0),
232	REG_CAPA_V2_BF_CCD_LOW_BAND = BIT(1),
233	REG_CAPA_V2_BF_CCD_HIGH_BAND = BIT(2),
234	REG_CAPA_V2_160MHZ_ALLOWED = BIT(3),
235	REG_CAPA_V2_80MHZ_ALLOWED = BIT(4),
236	REG_CAPA_V2_MCS_8_ALLOWED = BIT(5),
237	REG_CAPA_V2_MCS_9_ALLOWED = BIT(6),
238	REG_CAPA_V2_WEATHER_DISABLED = BIT(7),
239	REG_CAPA_V2_40MHZ_ALLOWED = BIT(8),
240	REG_CAPA_V2_11AX_DISABLED = BIT(10),
241	}; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_2 */
242
243	/**
244	* enum iwl_reg_capa_flags_v4 - global flags applied for the whole regulatory
245	* domain.
246	* @REG_CAPA_V4_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
247	* for this regulatory domain (valid only in 5Ghz).
248	* @REG_CAPA_V4_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
249	* for this regulatory domain (valid only in 5Ghz).
250	* @REG_CAPA_V4_MCS_12_ALLOWED: 11ac with MCS 12 is allowed.
251	* @REG_CAPA_V4_MCS_13_ALLOWED: 11ac with MCS 13 is allowed.
252	* @REG_CAPA_V4_11BE_DISABLED: 11be is forbidden for this regulatory domain.
253	* @REG_CAPA_V4_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
254	* @REG_CAPA_V4_320MHZ_ALLOWED: 11be channel with a width of 320Mhz is allowed
255	* for this regulatory domain (valid only in 5GHz).
256	*/
257	enum iwl_reg_capa_flags_v4 {
258	REG_CAPA_V4_160MHZ_ALLOWED = BIT(3),
259	REG_CAPA_V4_80MHZ_ALLOWED = BIT(4),
260	REG_CAPA_V4_MCS_12_ALLOWED = BIT(5),
261	REG_CAPA_V4_MCS_13_ALLOWED = BIT(6),
262	REG_CAPA_V4_11BE_DISABLED = BIT(8),
263	REG_CAPA_V4_11AX_DISABLED = BIT(13),
264	REG_CAPA_V4_320MHZ_ALLOWED = BIT(16),
265	}; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_4 */
266
267	/*
268	* API v2 for reg_capa_flags is relevant from version 6 and onwards of the
269	* MCC update command response.
270	*/
271	#define REG_CAPA_V2_RESP_VER 6
272
273	/* API v4 for reg_capa_flags is relevant from version 8 and onwards of the
274	* MCC update command response.
275	*/
276	#define REG_CAPA_V4_RESP_VER 8
277
278	/**
279	* struct iwl_reg_capa - struct for global regulatory capabilities, Used for
280	* handling the different APIs of reg_capa_flags.
281	*
282	* @allow_40mhz: 11n channel with a width of 40Mhz is allowed
283	* for this regulatory domain.
284	* @allow_80mhz: 11ac channel with a width of 80Mhz is allowed
285	* for this regulatory domain (valid only in 5 and 6 Ghz).
286	* @allow_160mhz: 11ac channel with a width of 160Mhz is allowed
287	* for this regulatory domain (valid only in 5 and 6 Ghz).
288	* @allow_320mhz: 11be channel with a width of 320Mhz is allowed
289	* for this regulatory domain (valid only in 6 Ghz).
290	* @disable_11ax: 11ax is forbidden for this regulatory domain.
291	* @disable_11be: 11be is forbidden for this regulatory domain.
292	*/
293	struct iwl_reg_capa {
294	bool allow_40mhz;
295	bool allow_80mhz;
296	bool allow_160mhz;
297	bool allow_320mhz;
298	bool disable_11ax;
299	bool disable_11be;
300	};
301
302	static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
303	int chan, u32 flags)
304	{
305	#define CHECK_AND_PRINT_I(x) \
306	((flags & NVM_CHANNEL_##x) ? " " #x : "")
307
308	if (!(flags & NVM_CHANNEL_VALID)) {
309	IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n",
310	chan, flags);
311	return;
312	}
313
314	/* Note: already can print up to 101 characters, 110 is the limit! */
315	IWL_DEBUG_DEV(dev, level,
316	"Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
317	chan, flags,
318	CHECK_AND_PRINT_I(VALID),
319	CHECK_AND_PRINT_I(IBSS),
320	CHECK_AND_PRINT_I(ACTIVE),
321	CHECK_AND_PRINT_I(RADAR),
322	CHECK_AND_PRINT_I(INDOOR_ONLY),
323	CHECK_AND_PRINT_I(GO_CONCURRENT),
324	CHECK_AND_PRINT_I(UNIFORM),
325	CHECK_AND_PRINT_I(20MHZ),
326	CHECK_AND_PRINT_I(40MHZ),
327	CHECK_AND_PRINT_I(80MHZ),
328	CHECK_AND_PRINT_I(160MHZ),
329	CHECK_AND_PRINT_I(DC_HIGH),
330	CHECK_AND_PRINT_I(VLP),
331	CHECK_AND_PRINT_I(AFC));
332	#undef CHECK_AND_PRINT_I
333	}
334
335	static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band,
336	u32 nvm_flags, const struct iwl_cfg *cfg)
337	{
338	u32 flags = IEEE80211_CHAN_NO_HT40;
339
340	if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) {
341	if (ch_num <= LAST_2GHZ_HT_PLUS)
342	flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
343	if (ch_num >= FIRST_2GHZ_HT_MINUS)
344	flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
345	} else if (nvm_flags & NVM_CHANNEL_40MHZ) {
346	if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
347	flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
348	else
349	flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
350	}
351	if (!(nvm_flags & NVM_CHANNEL_80MHZ))
352	flags |= IEEE80211_CHAN_NO_80MHZ;
353	if (!(nvm_flags & NVM_CHANNEL_160MHZ))
354	flags |= IEEE80211_CHAN_NO_160MHZ;
355
356	if (!(nvm_flags & NVM_CHANNEL_IBSS))
357	flags |= IEEE80211_CHAN_NO_IR;
358
359	if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
360	flags |= IEEE80211_CHAN_NO_IR;
361
362	if (nvm_flags & NVM_CHANNEL_RADAR)
363	flags |= IEEE80211_CHAN_RADAR;
364
365	if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
366	flags |= IEEE80211_CHAN_INDOOR_ONLY;
367
368	/* Set the GO concurrent flag only in case that NO_IR is set.
369	* Otherwise it is meaningless
370	*/
371	if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
372	(flags & IEEE80211_CHAN_NO_IR))
373	flags |= IEEE80211_CHAN_IR_CONCURRENT;
374
375	/* Set the AP type for the UHB case. */
376	if (!(nvm_flags & NVM_CHANNEL_VLP))
377	flags |= IEEE80211_CHAN_NO_6GHZ_VLP_CLIENT;
378	if (!(nvm_flags & NVM_CHANNEL_AFC))
379	flags |= IEEE80211_CHAN_NO_6GHZ_AFC_CLIENT;
380
381	return flags;
382	}
383
384	static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx)
385	{
386	if (ch_idx >= NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS) {
387	return NL80211_BAND_6GHZ;
388	}
389
390	if (ch_idx >= NUM_2GHZ_CHANNELS)
391	return NL80211_BAND_5GHZ;
392	return NL80211_BAND_2GHZ;
393	}
394
395	static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
396	struct iwl_nvm_data *data,
397	const void * const nvm_ch_flags,
398	u32 sbands_flags, bool v4)
399	{
400	int ch_idx;
401	int n_channels = 0;
402	struct ieee80211_channel *channel;
403	u32 ch_flags;
404	int num_of_ch;
405	const u16 *nvm_chan;
406
407	if (cfg->uhb_supported) {
408	num_of_ch = IWL_NVM_NUM_CHANNELS_UHB;
409	nvm_chan = iwl_uhb_nvm_channels;
410	} else if (cfg->nvm_type == IWL_NVM_EXT) {
411	num_of_ch = IWL_NVM_NUM_CHANNELS_EXT;
412	nvm_chan = iwl_ext_nvm_channels;
413	} else {
414	num_of_ch = IWL_NVM_NUM_CHANNELS;
415	nvm_chan = iwl_nvm_channels;
416	}
417
418	for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
419	enum nl80211_band band =
420	iwl_nl80211_band_from_channel_idx(ch_idx);
421
422	if (v4)
423	ch_flags =
424	__le32_to_cpup(p: (const __le32 *)nvm_ch_flags + ch_idx);
425	else
426	ch_flags =
427	__le16_to_cpup(p: (const __le16 *)nvm_ch_flags + ch_idx);
428
429	if (band == NL80211_BAND_5GHZ &&
430	!data->sku_cap_band_52ghz_enable)
431	continue;
432
433	/* workaround to disable wide channels in 5GHz */
434	if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) &&
435	band == NL80211_BAND_5GHZ) {
436	ch_flags &= ~(NVM_CHANNEL_40MHZ |
437	NVM_CHANNEL_80MHZ |
438	NVM_CHANNEL_160MHZ);
439	}
440
441	if (ch_flags & NVM_CHANNEL_160MHZ)
442	data->vht160_supported = true;
443
444	if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) &&
445	!(ch_flags & NVM_CHANNEL_VALID)) {
446	/*
447	* Channels might become valid later if lar is
448	* supported, hence we still want to add them to
449	* the list of supported channels to cfg80211.
450	*/
451	iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
452	chan: nvm_chan[ch_idx], flags: ch_flags);
453	continue;
454	}
455
456	channel = &data->channels[n_channels];
457	n_channels++;
458
459	channel->hw_value = nvm_chan[ch_idx];
460	channel->band = band;
461	channel->center_freq =
462	ieee80211_channel_to_frequency(
463	chan: channel->hw_value, band: channel->band);
464
465	/* Initialize regulatory-based run-time data */
466
467	/*
468	* Default value - highest tx power value. max_power
469	* is not used in mvm, and is used for backwards compatibility
470	*/
471	channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
472
473	/* don't put limitations in case we're using LAR */
474	if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR))
475	channel->flags = iwl_get_channel_flags(ch_num: nvm_chan[ch_idx],
476	ch_idx, band,
477	nvm_flags: ch_flags, cfg);
478	else
479	channel->flags = 0;
480
481	/* TODO: Don't put limitations on UHB devices as we still don't
482	* have NVM for them
483	*/
484	if (cfg->uhb_supported)
485	channel->flags = 0;
486	iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
487	chan: channel->hw_value, flags: ch_flags);
488	IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n",
489	channel->hw_value, channel->max_power);
490	}
491
492	return n_channels;
493	}
494
495	static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
496	struct iwl_nvm_data *data,
497	struct ieee80211_sta_vht_cap *vht_cap,
498	u8 tx_chains, u8 rx_chains)
499	{
500	const struct iwl_cfg *cfg = trans->cfg;
501	int num_rx_ants = num_of_ant(mask: rx_chains);
502	int num_tx_ants = num_of_ant(mask: tx_chains);
503
504	vht_cap->vht_supported = true;
505
506	vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
507	IEEE80211_VHT_CAP_RXSTBC_1 |
508	IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
509	3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
510	IEEE80211_VHT_MAX_AMPDU_1024K <<
511	IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
512
513	if (!trans->cfg->ht_params->stbc)
514	vht_cap->cap &= ~IEEE80211_VHT_CAP_RXSTBC_MASK;
515
516	if (data->vht160_supported)
517	vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
518	IEEE80211_VHT_CAP_SHORT_GI_160;
519
520	if (cfg->vht_mu_mimo_supported)
521	vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
522
523	if (cfg->ht_params->ldpc)
524	vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
525
526	if (data->sku_cap_mimo_disabled) {
527	num_rx_ants = 1;
528	num_tx_ants = 1;
529	}
530
531	if (trans->cfg->ht_params->stbc && num_tx_ants > 1)
532	vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
533	else
534	vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
535
536	switch (iwlwifi_mod_params.amsdu_size) {
537	case IWL_AMSDU_DEF:
538	if (trans->trans_cfg->mq_rx_supported)
539	vht_cap->cap |=
540	IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
541	else
542	vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
543	break;
544	case IWL_AMSDU_2K:
545	if (trans->trans_cfg->mq_rx_supported)
546	vht_cap->cap |=
547	IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
548	else
549	WARN(1, "RB size of 2K is not supported by this device\n");
550	break;
551	case IWL_AMSDU_4K:
552	vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
553	break;
554	case IWL_AMSDU_8K:
555	vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
556	break;
557	case IWL_AMSDU_12K:
558	vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
559	break;
560	default:
561	break;
562	}
563
564	vht_cap->vht_mcs.rx_mcs_map =
565	cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
566	IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
567	IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
568	IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
569	IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
570	IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
571	IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
572	IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
573
574	if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
575	vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
576	/* this works because NOT_SUPPORTED == 3 */
577	vht_cap->vht_mcs.rx_mcs_map |=
578	cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
579	}
580
581	vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
582
583	vht_cap->vht_mcs.tx_highest |=
584	cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
585	}
586
587	static const u8 iwl_vendor_caps[] = {
588	0xdd, /* vendor element */
589	0x06, /* length */
590	0x00, 0x17, 0x35, /* Intel OUI */
591	0x08, /* type (Intel Capabilities) */
592	/* followed by 16 bits of capabilities */
593	#define IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE BIT(0)
594	IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE,
595	0x00
596	};
597
598	static const struct ieee80211_sband_iftype_data iwl_he_eht_capa[] = {
599	{
600	.types_mask = BIT(NL80211_IFTYPE_STATION),
601	.he_cap = {
602	.has_he = true,
603	.he_cap_elem = {
604	.mac_cap_info[0] =
605	IEEE80211_HE_MAC_CAP0_HTC_HE,
606	.mac_cap_info[1] =
607	IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
608	IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
609	.mac_cap_info[2] =
610	IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP,
611	.mac_cap_info[3] =
612	IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
613	IEEE80211_HE_MAC_CAP3_RX_CTRL_FRAME_TO_MULTIBSS,
614	.mac_cap_info[4] =
615	IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU |
616	IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39,
617	.mac_cap_info[5] =
618	IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 |
619	IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 |
620	IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU |
621	IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS |
622	IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX,
623	.phy_cap_info[1] =
624	IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK |
625	IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
626	IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
627	.phy_cap_info[2] =
628	IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
629	IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ,
630	.phy_cap_info[3] =
631	IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK |
632	IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
633	IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK |
634	IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
635	.phy_cap_info[4] =
636	IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
637	IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
638	IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
639	.phy_cap_info[6] =
640	IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
641	IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB |
642	IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
643	.phy_cap_info[7] =
644	IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
645	IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI,
646	.phy_cap_info[8] =
647	IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
648	IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
649	IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
650	IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
651	IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242,
652	.phy_cap_info[9] =
653	IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
654	IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
655	(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED <<
656	IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS),
657	.phy_cap_info[10] =
658	IEEE80211_HE_PHY_CAP10_HE_MU_M1RU_MAX_LTF,
659	},
660	/*
661	* Set default Tx/Rx HE MCS NSS Support field.
662	* Indicate support for up to 2 spatial streams and all
663	* MCS, without any special cases
664	*/
665	.he_mcs_nss_supp = {
666	.rx_mcs_80 = cpu_to_le16(0xfffa),
667	.tx_mcs_80 = cpu_to_le16(0xfffa),
668	.rx_mcs_160 = cpu_to_le16(0xfffa),
669	.tx_mcs_160 = cpu_to_le16(0xfffa),
670	.rx_mcs_80p80 = cpu_to_le16(0xffff),
671	.tx_mcs_80p80 = cpu_to_le16(0xffff),
672	},
673	/*
674	* Set default PPE thresholds, with PPET16 set to 0,
675	* PPET8 set to 7
676	*/
677	.ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
678	},
679	.eht_cap = {
680	.has_eht = true,
681	.eht_cap_elem = {
682	.mac_cap_info[0] =
683	IEEE80211_EHT_MAC_CAP0_OM_CONTROL |
684	IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 |
685	IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2 |
686	IEEE80211_EHT_MAC_CAP0_SCS_TRAFFIC_DESC,
687	.phy_cap_info[0] =
688	IEEE80211_EHT_PHY_CAP0_242_TONE_RU_GT20MHZ |
689	IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
690	IEEE80211_EHT_PHY_CAP0_PARTIAL_BW_UL_MU_MIMO |
691	IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE |
692	IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK,
693	.phy_cap_info[1] =
694	IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK |
695	IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK,
696	.phy_cap_info[3] =
697	IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK |
698	IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK |
699	IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
700	IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
701	IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
702	IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK |
703	IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK,
704
705	.phy_cap_info[4] =
706	IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO |
707	IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP |
708	IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI,
709	.phy_cap_info[5] =
710	FIELD_PREP_CONST(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK,
711	IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US) |
712	IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK |
713	IEEE80211_EHT_PHY_CAP5_TX_LESS_242_TONE_RU_SUPP |
714	IEEE80211_EHT_PHY_CAP5_RX_LESS_242_TONE_RU_SUPP,
715	.phy_cap_info[6] =
716	IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK |
717	IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP,
718	.phy_cap_info[8] =
719	IEEE80211_EHT_PHY_CAP8_RX_1024QAM_WIDER_BW_DL_OFDMA |
720	IEEE80211_EHT_PHY_CAP8_RX_4096QAM_WIDER_BW_DL_OFDMA,
721	},
722
723	/* For all MCS and bandwidth, set 2 NSS for both Tx and
724	* Rx - note we don't set the only_20mhz, but due to this
725	* being a union, it gets set correctly anyway.
726	*/
727	.eht_mcs_nss_supp = {
728	.bw._80 = {
729	.rx_tx_mcs9_max_nss = 0x22,
730	.rx_tx_mcs11_max_nss = 0x22,
731	.rx_tx_mcs13_max_nss = 0x22,
732	},
733	.bw._160 = {
734	.rx_tx_mcs9_max_nss = 0x22,
735	.rx_tx_mcs11_max_nss = 0x22,
736	.rx_tx_mcs13_max_nss = 0x22,
737	},
738	.bw._320 = {
739	.rx_tx_mcs9_max_nss = 0x22,
740	.rx_tx_mcs11_max_nss = 0x22,
741	.rx_tx_mcs13_max_nss = 0x22,
742	},
743	},
744
745	/*
746	* PPE thresholds for NSS = 2, and RU index bitmap set
747	* to 0xc.
748	* Note: just for stating what we want, not present in
749	* the transmitted data due to not including
750	* IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT.
751	*/
752	.eht_ppe_thres = {0xc1, 0x0e, 0xe0 }
753	},
754	},
755	{
756	.types_mask = BIT(NL80211_IFTYPE_AP),
757	.he_cap = {
758	.has_he = true,
759	.he_cap_elem = {
760	.mac_cap_info[0] =
761	IEEE80211_HE_MAC_CAP0_HTC_HE,
762	.mac_cap_info[1] =
763	IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
764	.mac_cap_info[3] =
765	IEEE80211_HE_MAC_CAP3_OMI_CONTROL,
766	.phy_cap_info[1] =
767	IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
768	.phy_cap_info[2] =
769	IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ |
770	IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
771	.phy_cap_info[3] =
772	IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK |
773	IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
774	IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK |
775	IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
776	.phy_cap_info[6] =
777	IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
778	.phy_cap_info[7] =
779	IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI,
780	.phy_cap_info[8] =
781	IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
782	IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242,
783	.phy_cap_info[9] =
784	IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED
785	<< IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS,
786	},
787	/*
788	* Set default Tx/Rx HE MCS NSS Support field.
789	* Indicate support for up to 2 spatial streams and all
790	* MCS, without any special cases
791	*/
792	.he_mcs_nss_supp = {
793	.rx_mcs_80 = cpu_to_le16(0xfffa),
794	.tx_mcs_80 = cpu_to_le16(0xfffa),
795	.rx_mcs_160 = cpu_to_le16(0xfffa),
796	.tx_mcs_160 = cpu_to_le16(0xfffa),
797	.rx_mcs_80p80 = cpu_to_le16(0xffff),
798	.tx_mcs_80p80 = cpu_to_le16(0xffff),
799	},
800	/*
801	* Set default PPE thresholds, with PPET16 set to 0,
802	* PPET8 set to 7
803	*/
804	.ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
805	},
806	.eht_cap = {
807	.has_eht = true,
808	.eht_cap_elem = {
809	.mac_cap_info[0] =
810	IEEE80211_EHT_MAC_CAP0_OM_CONTROL |
811	IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 |
812	IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2,
813	.phy_cap_info[0] =
814	IEEE80211_EHT_PHY_CAP0_242_TONE_RU_GT20MHZ |
815	IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI,
816	.phy_cap_info[5] =
817	FIELD_PREP_CONST(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK,
818	IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US),
819	},
820
821	/* For all MCS and bandwidth, set 2 NSS for both Tx and
822	* Rx - note we don't set the only_20mhz, but due to this
823	* being a union, it gets set correctly anyway.
824	*/
825	.eht_mcs_nss_supp = {
826	.bw._80 = {
827	.rx_tx_mcs9_max_nss = 0x22,
828	.rx_tx_mcs11_max_nss = 0x22,
829	.rx_tx_mcs13_max_nss = 0x22,
830	},
831	.bw._160 = {
832	.rx_tx_mcs9_max_nss = 0x22,
833	.rx_tx_mcs11_max_nss = 0x22,
834	.rx_tx_mcs13_max_nss = 0x22,
835	},
836	.bw._320 = {
837	.rx_tx_mcs9_max_nss = 0x22,
838	.rx_tx_mcs11_max_nss = 0x22,
839	.rx_tx_mcs13_max_nss = 0x22,
840	},
841	},
842
843	/*
844	* PPE thresholds for NSS = 2, and RU index bitmap set
845	* to 0xc.
846	* Note: just for stating what we want, not present in
847	* the transmitted data due to not including
848	* IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT.
849	*/
850	.eht_ppe_thres = {0xc1, 0x0e, 0xe0 }
851	},
852	},
853	};
854
855	static void iwl_init_he_6ghz_capa(struct iwl_trans *trans,
856	struct iwl_nvm_data *data,
857	struct ieee80211_supported_band *sband,
858	u8 tx_chains, u8 rx_chains)
859	{
860	struct ieee80211_sta_ht_cap ht_cap;
861	struct ieee80211_sta_vht_cap vht_cap = {};
862	struct ieee80211_sband_iftype_data *iftype_data;
863	u16 he_6ghz_capa = 0;
864	u32 exp;
865	int i;
866
867	if (sband->band != NL80211_BAND_6GHZ)
868	return;
869
870	/* grab HT/VHT capabilities and calculate HE 6 GHz capabilities */
871	iwl_init_ht_hw_capab(trans, data, ht_info: &ht_cap, band: NL80211_BAND_5GHZ,
872	tx_chains, rx_chains);
873	WARN_ON(!ht_cap.ht_supported);
874	iwl_init_vht_hw_capab(trans, data, vht_cap: &vht_cap, tx_chains, rx_chains);
875	WARN_ON(!vht_cap.vht_supported);
876
877	he_6ghz_capa |=
878	u16_encode_bits(v: ht_cap.ampdu_density,
879	IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START);
880	exp = u32_get_bits(v: vht_cap.cap,
881	IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK);
882	he_6ghz_capa |=
883	u16_encode_bits(v: exp, IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP);
884	exp = u32_get_bits(v: vht_cap.cap, IEEE80211_VHT_CAP_MAX_MPDU_MASK);
885	he_6ghz_capa |=
886	u16_encode_bits(v: exp, IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
887	/* we don't support extended_ht_cap_info anywhere, so no RD_RESPONDER */
888	if (vht_cap.cap & IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN)
889	he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS;
890	if (vht_cap.cap & IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN)
891	he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
892
893	IWL_DEBUG_EEPROM(trans->dev, "he_6ghz_capa=0x%x\n", he_6ghz_capa);
894
895	/* we know it's writable - we set it before ourselves */
896	iftype_data = (void *)(uintptr_t)sband->iftype_data;
897	for (i = 0; i < sband->n_iftype_data; i++)
898	iftype_data[i].he_6ghz_capa.capa = cpu_to_le16(he_6ghz_capa);
899	}
900
901	static void
902	iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans,
903	struct iwl_nvm_data *data,
904	struct ieee80211_supported_band *sband,
905	struct ieee80211_sband_iftype_data *iftype_data,
906	u8 tx_chains, u8 rx_chains,
907	const struct iwl_fw *fw)
908	{
909	bool is_ap = iftype_data->types_mask & BIT(NL80211_IFTYPE_AP);
910	bool no_320;
911
912	no_320 = (!trans->trans_cfg->integrated &&
913	trans->pcie_link_speed < PCI_EXP_LNKSTA_CLS_8_0GB) ||
914	trans->reduced_cap_sku;
915
916	if (!data->sku_cap_11be_enable || iwlwifi_mod_params.disable_11be)
917	iftype_data->eht_cap.has_eht = false;
918
919	/* Advertise an A-MPDU exponent extension based on
920	* operating band
921	*/
922	if (sband->band == NL80211_BAND_6GHZ && iftype_data->eht_cap.has_eht)
923	iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
924	IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2;
925	else if (sband->band != NL80211_BAND_2GHZ)
926	iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
927	IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_1;
928	else
929	iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
930	IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
931
932	switch (sband->band) {
933	case NL80211_BAND_2GHZ:
934	iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |=
935	IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
936	iftype_data->eht_cap.eht_cap_elem.mac_cap_info[0] |=
937	u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454,
938	IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
939	break;
940	case NL80211_BAND_6GHZ:
941	if (!no_320) {
942	iftype_data->eht_cap.eht_cap_elem.phy_cap_info[0] |=
943	IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
944	iftype_data->eht_cap.eht_cap_elem.phy_cap_info[1] |=
945	IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK;
946	}
947	fallthrough;
948	case NL80211_BAND_5GHZ:
949	iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |=
950	IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
951	IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
952	break;
953	default:
954	WARN_ON(1);
955	break;
956	}
957
958	if ((tx_chains & rx_chains) == ANT_AB) {
959	iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |=
960	IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ;
961	iftype_data->he_cap.he_cap_elem.phy_cap_info[5] |=
962	IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
963	IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2;
964	if (!is_ap) {
965	iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |=
966	IEEE80211_HE_PHY_CAP7_MAX_NC_2;
967
968	if (iftype_data->eht_cap.has_eht) {
969	/*
970	* Set the number of sounding dimensions for each
971	* bandwidth to 1 to indicate the maximal supported
972	* value of TXVECTOR parameter NUM_STS of 2
973	*/
974	iftype_data->eht_cap.eht_cap_elem.phy_cap_info[2] |= 0x49;
975
976	/*
977	* Set the MAX NC to 1 to indicate sounding feedback of
978	* 2 supported by the beamfomee.
979	*/
980	iftype_data->eht_cap.eht_cap_elem.phy_cap_info[4] |= 0x10;
981	}
982	}
983	} else {
984	struct ieee80211_he_mcs_nss_supp *he_mcs_nss_supp =
985	&iftype_data->he_cap.he_mcs_nss_supp;
986
987	if (iftype_data->eht_cap.has_eht) {
988	struct ieee80211_eht_mcs_nss_supp *mcs_nss =
989	&iftype_data->eht_cap.eht_mcs_nss_supp;
990
991	memset(mcs_nss, 0x11, sizeof(*mcs_nss));
992	}
993
994	if (!is_ap) {
995	/* If not 2x2, we need to indicate 1x1 in the
996	* Midamble RX Max NSTS - but not for AP mode
997	*/
998	iftype_data->he_cap.he_cap_elem.phy_cap_info[1] &=
999	~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS;
1000	iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &=
1001	~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS;
1002	iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |=
1003	IEEE80211_HE_PHY_CAP7_MAX_NC_1;
1004	}
1005
1006	he_mcs_nss_supp->rx_mcs_80 |=
1007	cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1008	he_mcs_nss_supp->tx_mcs_80 |=
1009	cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1010	he_mcs_nss_supp->rx_mcs_160 |=
1011	cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1012	he_mcs_nss_supp->tx_mcs_160 |=
1013	cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1014	he_mcs_nss_supp->rx_mcs_80p80 |=
1015	cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1016	he_mcs_nss_supp->tx_mcs_80p80 |=
1017	cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1018	}
1019
1020	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210 && !is_ap)
1021	iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |=
1022	IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO;
1023
1024	switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
1025	case IWL_CFG_RF_TYPE_GF:
1026	case IWL_CFG_RF_TYPE_MR:
1027	case IWL_CFG_RF_TYPE_MS:
1028	case IWL_CFG_RF_TYPE_FM:
1029	case IWL_CFG_RF_TYPE_WH:
1030	iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |=
1031	IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
1032	if (!is_ap)
1033	iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |=
1034	IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
1035	break;
1036	}
1037
1038	if (CSR_HW_REV_TYPE(trans->hw_rev) == IWL_CFG_MAC_TYPE_GL &&
1039	iftype_data->eht_cap.has_eht) {
1040	iftype_data->eht_cap.eht_cap_elem.mac_cap_info[0] &=
1041	~(IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 |
1042	IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2);
1043	iftype_data->eht_cap.eht_cap_elem.phy_cap_info[3] &=
1044	~(IEEE80211_EHT_PHY_CAP0_PARTIAL_BW_UL_MU_MIMO |
1045	IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK |
1046	IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK |
1047	IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
1048	IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
1049	IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK |
1050	IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK);
1051	iftype_data->eht_cap.eht_cap_elem.phy_cap_info[4] &=
1052	~(IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO |
1053	IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP);
1054	iftype_data->eht_cap.eht_cap_elem.phy_cap_info[5] &=
1055	~IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK;
1056	iftype_data->eht_cap.eht_cap_elem.phy_cap_info[6] &=
1057	~(IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK |
1058	IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP);
1059	iftype_data->eht_cap.eht_cap_elem.phy_cap_info[5] |=
1060	IEEE80211_EHT_PHY_CAP5_SUPP_EXTRA_EHT_LTF;
1061	}
1062
1063	if (fw_has_capa(capabilities: &fw->ucode_capa, capa: IWL_UCODE_TLV_CAPA_BROADCAST_TWT))
1064	iftype_data->he_cap.he_cap_elem.mac_cap_info[2] |=
1065	IEEE80211_HE_MAC_CAP2_BCAST_TWT;
1066
1067	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1068	!is_ap) {
1069	iftype_data->vendor_elems.data = iwl_vendor_caps;
1070	iftype_data->vendor_elems.len = ARRAY_SIZE(iwl_vendor_caps);
1071	}
1072
1073	if (!trans->cfg->ht_params->stbc) {
1074	iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &=
1075	~IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
1076	iftype_data->he_cap.he_cap_elem.phy_cap_info[7] &=
1077	~IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
1078	}
1079
1080	if (trans->step_urm) {
1081	iftype_data->eht_cap.eht_mcs_nss_supp.bw._320.rx_tx_mcs11_max_nss = 0;
1082	iftype_data->eht_cap.eht_mcs_nss_supp.bw._320.rx_tx_mcs13_max_nss = 0;
1083	}
1084
1085	if (trans->no_160)
1086	iftype_data->he_cap.he_cap_elem.phy_cap_info[0] &=
1087	~IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
1088
1089	if (trans->reduced_cap_sku) {
1090	memset(&iftype_data->eht_cap.eht_mcs_nss_supp.bw._320, 0,
1091	sizeof(iftype_data->eht_cap.eht_mcs_nss_supp.bw._320));
1092	iftype_data->eht_cap.eht_mcs_nss_supp.bw._80.rx_tx_mcs13_max_nss = 0;
1093	iftype_data->eht_cap.eht_mcs_nss_supp.bw._160.rx_tx_mcs13_max_nss = 0;
1094	iftype_data->eht_cap.eht_cap_elem.phy_cap_info[8] &=
1095	~IEEE80211_EHT_PHY_CAP8_RX_4096QAM_WIDER_BW_DL_OFDMA;
1096	iftype_data->eht_cap.eht_cap_elem.phy_cap_info[2] &=
1097	~IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK;
1098	}
1099	}
1100
1101	static void iwl_init_he_hw_capab(struct iwl_trans *trans,
1102	struct iwl_nvm_data *data,
1103	struct ieee80211_supported_band *sband,
1104	u8 tx_chains, u8 rx_chains,
1105	const struct iwl_fw *fw)
1106	{
1107	struct ieee80211_sband_iftype_data *iftype_data;
1108	int i;
1109
1110	BUILD_BUG_ON(sizeof(data->iftd.low) != sizeof(iwl_he_eht_capa));
1111	BUILD_BUG_ON(sizeof(data->iftd.high) != sizeof(iwl_he_eht_capa));
1112	BUILD_BUG_ON(sizeof(data->iftd.uhb) != sizeof(iwl_he_eht_capa));
1113
1114	switch (sband->band) {
1115	case NL80211_BAND_2GHZ:
1116	iftype_data = data->iftd.low;
1117	break;
1118	case NL80211_BAND_5GHZ:
1119	iftype_data = data->iftd.high;
1120	break;
1121	case NL80211_BAND_6GHZ:
1122	iftype_data = data->iftd.uhb;
1123	break;
1124	default:
1125	WARN_ON(1);
1126	return;
1127	}
1128
1129	memcpy(iftype_data, iwl_he_eht_capa, sizeof(iwl_he_eht_capa));
1130
1131	_ieee80211_set_sband_iftype_data(sband, iftd: iftype_data,
1132	ARRAY_SIZE(iwl_he_eht_capa));
1133
1134	for (i = 0; i < sband->n_iftype_data; i++)
1135	iwl_nvm_fixup_sband_iftd(trans, data, sband, iftype_data: &iftype_data[i],
1136	tx_chains, rx_chains, fw);
1137
1138	iwl_init_he_6ghz_capa(trans, data, sband, tx_chains, rx_chains);
1139	}
1140
1141	void iwl_reinit_cab(struct iwl_trans *trans, struct iwl_nvm_data *data,
1142	u8 tx_chains, u8 rx_chains, const struct iwl_fw *fw)
1143	{
1144	struct ieee80211_supported_band *sband;
1145
1146	sband = &data->bands[NL80211_BAND_2GHZ];
1147	iwl_init_ht_hw_capab(trans, data, ht_info: &sband->ht_cap, band: NL80211_BAND_2GHZ,
1148	tx_chains, rx_chains);
1149
1150	if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1151	iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1152	fw);
1153
1154	sband = &data->bands[NL80211_BAND_5GHZ];
1155	iwl_init_ht_hw_capab(trans, data, ht_info: &sband->ht_cap, band: NL80211_BAND_5GHZ,
1156	tx_chains, rx_chains);
1157	if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
1158	iwl_init_vht_hw_capab(trans, data, vht_cap: &sband->vht_cap,
1159	tx_chains, rx_chains);
1160
1161	if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1162	iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1163	fw);
1164
1165	sband = &data->bands[NL80211_BAND_6GHZ];
1166	if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1167	iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1168	fw);
1169	}
1170	IWL_EXPORT_SYMBOL(iwl_reinit_cab);
1171
1172	static void iwl_init_sbands(struct iwl_trans *trans,
1173	struct iwl_nvm_data *data,
1174	const void *nvm_ch_flags, u8 tx_chains,
1175	u8 rx_chains, u32 sbands_flags, bool v4,
1176	const struct iwl_fw *fw)
1177	{
1178	struct device *dev = trans->dev;
1179	const struct iwl_cfg *cfg = trans->cfg;
1180	int n_channels;
1181	int n_used = 0;
1182	struct ieee80211_supported_band *sband;
1183
1184	n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags,
1185	sbands_flags, v4);
1186	sband = &data->bands[NL80211_BAND_2GHZ];
1187	sband->band = NL80211_BAND_2GHZ;
1188	sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
1189	sband->n_bitrates = N_RATES_24;
1190	n_used += iwl_init_sband_channels(data, sband, n_channels,
1191	band: NL80211_BAND_2GHZ);
1192	iwl_init_ht_hw_capab(trans, data, ht_info: &sband->ht_cap, band: NL80211_BAND_2GHZ,
1193	tx_chains, rx_chains);
1194
1195	if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1196	iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1197	fw);
1198
1199	sband = &data->bands[NL80211_BAND_5GHZ];
1200	sband->band = NL80211_BAND_5GHZ;
1201	sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
1202	sband->n_bitrates = N_RATES_52;
1203	n_used += iwl_init_sband_channels(data, sband, n_channels,
1204	band: NL80211_BAND_5GHZ);
1205	iwl_init_ht_hw_capab(trans, data, ht_info: &sband->ht_cap, band: NL80211_BAND_5GHZ,
1206	tx_chains, rx_chains);
1207	if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
1208	iwl_init_vht_hw_capab(trans, data, vht_cap: &sband->vht_cap,
1209	tx_chains, rx_chains);
1210
1211	if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1212	iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1213	fw);
1214
1215	/* 6GHz band. */
1216	sband = &data->bands[NL80211_BAND_6GHZ];
1217	sband->band = NL80211_BAND_6GHZ;
1218	/* use the same rates as 5GHz band */
1219	sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
1220	sband->n_bitrates = N_RATES_52;
1221	n_used += iwl_init_sband_channels(data, sband, n_channels,
1222	band: NL80211_BAND_6GHZ);
1223
1224	if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1225	iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1226	fw);
1227	else
1228	sband->n_channels = 0;
1229	if (n_channels != n_used)
1230	IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
1231	n_used, n_channels);
1232	}
1233
1234	static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
1235	const __le16 *phy_sku)
1236	{
1237	if (cfg->nvm_type != IWL_NVM_EXT)
1238	return le16_to_cpup(p: nvm_sw + SKU);
1239
1240	return le32_to_cpup(p: (const __le32 *)(phy_sku + SKU_FAMILY_8000));
1241	}
1242
1243	static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
1244	{
1245	if (cfg->nvm_type != IWL_NVM_EXT)
1246	return le16_to_cpup(p: nvm_sw + NVM_VERSION);
1247	else
1248	return le32_to_cpup(p: (const __le32 *)(nvm_sw +
1249	NVM_VERSION_EXT_NVM));
1250	}
1251
1252	static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
1253	const __le16 *phy_sku)
1254	{
1255	if (cfg->nvm_type != IWL_NVM_EXT)
1256	return le16_to_cpup(p: nvm_sw + RADIO_CFG);
1257
1258	return le32_to_cpup(p: (const __le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
1259
1260	}
1261
1262	static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
1263	{
1264	int n_hw_addr;
1265
1266	if (cfg->nvm_type != IWL_NVM_EXT)
1267	return le16_to_cpup(p: nvm_sw + N_HW_ADDRS);
1268
1269	n_hw_addr = le32_to_cpup(p: (const __le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
1270
1271	return n_hw_addr & N_HW_ADDR_MASK;
1272	}
1273
1274	static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
1275	struct iwl_nvm_data *data,
1276	u32 radio_cfg)
1277	{
1278	if (cfg->nvm_type != IWL_NVM_EXT) {
1279	data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
1280	data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
1281	data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
1282	data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
1283	return;
1284	}
1285
1286	/* set the radio configuration for family 8000 */
1287	data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
1288	data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
1289	data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
1290	data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
1291	data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
1292	data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
1293	}
1294
1295	static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
1296	{
1297	const u8 *hw_addr;
1298
1299	hw_addr = (const u8 *)&mac_addr0;
1300	dest[0] = hw_addr[3];
1301	dest[1] = hw_addr[2];
1302	dest[2] = hw_addr[1];
1303	dest[3] = hw_addr[0];
1304
1305	hw_addr = (const u8 *)&mac_addr1;
1306	dest[4] = hw_addr[1];
1307	dest[5] = hw_addr[0];
1308	}
1309
1310	static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
1311	struct iwl_nvm_data *data)
1312	{
1313	__le32 mac_addr0 = cpu_to_le32(iwl_read32(trans,
1314	CSR_MAC_ADDR0_STRAP(trans)));
1315	__le32 mac_addr1 = cpu_to_le32(iwl_read32(trans,
1316	CSR_MAC_ADDR1_STRAP(trans)));
1317
1318	iwl_flip_hw_address(mac_addr0, mac_addr1, dest: data->hw_addr);
1319	/*
1320	* If the OEM fused a valid address, use it instead of the one in the
1321	* OTP
1322	*/
1323	if (is_valid_ether_addr(addr: data->hw_addr))
1324	return;
1325
1326	mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans)));
1327	mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans)));
1328
1329	iwl_flip_hw_address(mac_addr0, mac_addr1, dest: data->hw_addr);
1330	}
1331
1332	static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
1333	const struct iwl_cfg *cfg,
1334	struct iwl_nvm_data *data,
1335	const __le16 *mac_override,
1336	const __be16 *nvm_hw)
1337	{
1338	const u8 *hw_addr;
1339
1340	if (mac_override) {
1341	static const u8 reserved_mac[] = {
1342	0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
1343	};
1344
1345	hw_addr = (const u8 *)(mac_override +
1346	MAC_ADDRESS_OVERRIDE_EXT_NVM);
1347
1348	/*
1349	* Store the MAC address from MAO section.
1350	* No byte swapping is required in MAO section
1351	*/
1352	memcpy(data->hw_addr, hw_addr, ETH_ALEN);
1353
1354	/*
1355	* Force the use of the OTP MAC address in case of reserved MAC
1356	* address in the NVM, or if address is given but invalid.
1357	*/
1358	if (is_valid_ether_addr(addr: data->hw_addr) &&
1359	memcmp(p: reserved_mac, q: hw_addr, ETH_ALEN) != 0)
1360	return;
1361
1362	IWL_ERR(trans,
1363	"mac address from nvm override section is not valid\n");
1364	}
1365
1366	if (nvm_hw) {
1367	/* read the mac address from WFMP registers */
1368	__le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
1369	WFMP_MAC_ADDR_0));
1370	__le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
1371	WFMP_MAC_ADDR_1));
1372
1373	iwl_flip_hw_address(mac_addr0, mac_addr1, dest: data->hw_addr);
1374
1375	return;
1376	}
1377
1378	IWL_ERR(trans, "mac address is not found\n");
1379	}
1380
1381	static int iwl_set_hw_address(struct iwl_trans *trans,
1382	const struct iwl_cfg *cfg,
1383	struct iwl_nvm_data *data, const __be16 *nvm_hw,
1384	const __le16 *mac_override)
1385	{
1386	if (cfg->mac_addr_from_csr) {
1387	iwl_set_hw_address_from_csr(trans, data);
1388	} else if (cfg->nvm_type != IWL_NVM_EXT) {
1389	const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
1390
1391	/* The byte order is little endian 16 bit, meaning 214365 */
1392	data->hw_addr[0] = hw_addr[1];
1393	data->hw_addr[1] = hw_addr[0];
1394	data->hw_addr[2] = hw_addr[3];
1395	data->hw_addr[3] = hw_addr[2];
1396	data->hw_addr[4] = hw_addr[5];
1397	data->hw_addr[5] = hw_addr[4];
1398	} else {
1399	iwl_set_hw_address_family_8000(trans, cfg, data,
1400	mac_override, nvm_hw);
1401	}
1402
1403	if (!is_valid_ether_addr(addr: data->hw_addr)) {
1404	IWL_ERR(trans, "no valid mac address was found\n");
1405	return -EINVAL;
1406	}
1407
1408	if (!trans->csme_own)
1409	IWL_INFO(trans, "base HW address: %pM, OTP minor version: 0x%x\n",
1410	data->hw_addr, iwl_read_prph(trans, REG_OTP_MINOR));
1411
1412	return 0;
1413	}
1414
1415	static bool
1416	iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1417	const __be16 *nvm_hw)
1418	{
1419	/*
1420	* Workaround a bug in Indonesia SKUs where the regulatory in
1421	* some 7000-family OTPs erroneously allow wide channels in
1422	* 5GHz. To check for Indonesia, we take the SKU value from
1423	* bits 1-4 in the subsystem ID and check if it is either 5 or
1424	* 9. In those cases, we need to force-disable wide channels
1425	* in 5GHz otherwise the FW will throw a sysassert when we try
1426	* to use them.
1427	*/
1428	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1429	/*
1430	* Unlike the other sections in the NVM, the hw
1431	* section uses big-endian.
1432	*/
1433	u16 subsystem_id = be16_to_cpup(p: nvm_hw + SUBSYSTEM_ID);
1434	u8 sku = (subsystem_id & 0x1e) >> 1;
1435
1436	if (sku == 5 || sku == 9) {
1437	IWL_DEBUG_EEPROM(trans->dev,
1438	"disabling wide channels in 5GHz (0x%0x %d)\n",
1439	subsystem_id, sku);
1440	return true;
1441	}
1442	}
1443
1444	return false;
1445	}
1446
1447	struct iwl_nvm_data *
1448	iwl_parse_mei_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1449	const struct iwl_mei_nvm *mei_nvm,
1450	const struct iwl_fw *fw, u8 tx_ant, u8 rx_ant)
1451	{
1452	struct iwl_nvm_data *data;
1453	u32 sbands_flags = 0;
1454	u8 rx_chains = fw->valid_rx_ant;
1455	u8 tx_chains = fw->valid_rx_ant;
1456
1457	if (cfg->uhb_supported)
1458	data = kzalloc(struct_size(data, channels,
1459	IWL_NVM_NUM_CHANNELS_UHB),
1460	GFP_KERNEL);
1461	else
1462	data = kzalloc(struct_size(data, channels,
1463	IWL_NVM_NUM_CHANNELS_EXT),
1464	GFP_KERNEL);
1465	if (!data)
1466	return NULL;
1467
1468	BUILD_BUG_ON(ARRAY_SIZE(mei_nvm->channels) !=
1469	IWL_NVM_NUM_CHANNELS_UHB);
1470	data->nvm_version = mei_nvm->nvm_version;
1471
1472	iwl_set_radio_cfg(cfg, data, radio_cfg: mei_nvm->radio_cfg);
1473	if (data->valid_tx_ant)
1474	tx_chains &= data->valid_tx_ant;
1475	if (data->valid_rx_ant)
1476	rx_chains &= data->valid_rx_ant;
1477	if (tx_ant)
1478	tx_chains &= tx_ant;
1479	if (rx_ant)
1480	rx_chains &= rx_ant;
1481
1482	data->sku_cap_mimo_disabled = false;
1483	data->sku_cap_band_24ghz_enable = true;
1484	data->sku_cap_band_52ghz_enable = true;
1485	data->sku_cap_11n_enable =
1486	!(iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL);
1487	data->sku_cap_11ac_enable = true;
1488	data->sku_cap_11ax_enable =
1489	mei_nvm->caps & MEI_NVM_CAPS_11AX_SUPPORT;
1490
1491	data->lar_enabled = mei_nvm->caps & MEI_NVM_CAPS_LARI_SUPPORT;
1492
1493	data->n_hw_addrs = mei_nvm->n_hw_addrs;
1494	/* If no valid mac address was found - bail out */
1495	if (iwl_set_hw_address(trans, cfg, data, NULL, NULL)) {
1496	kfree(objp: data);
1497	return NULL;
1498	}
1499
1500	if (data->lar_enabled &&
1501	fw_has_capa(capabilities: &fw->ucode_capa, capa: IWL_UCODE_TLV_CAPA_LAR_SUPPORT))
1502	sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1503
1504	iwl_init_sbands(trans, data, nvm_ch_flags: mei_nvm->channels, tx_chains, rx_chains,
1505	sbands_flags, v4: true, fw);
1506
1507	return data;
1508	}
1509	IWL_EXPORT_SYMBOL(iwl_parse_mei_nvm_data);
1510
1511	struct iwl_nvm_data *
1512	iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1513	const struct iwl_fw *fw,
1514	const __be16 *nvm_hw, const __le16 *nvm_sw,
1515	const __le16 *nvm_calib, const __le16 *regulatory,
1516	const __le16 *mac_override, const __le16 *phy_sku,
1517	u8 tx_chains, u8 rx_chains)
1518	{
1519	struct iwl_nvm_data *data;
1520	bool lar_enabled;
1521	u32 sku, radio_cfg;
1522	u32 sbands_flags = 0;
1523	u16 lar_config;
1524	const __le16 *ch_section;
1525
1526	if (cfg->uhb_supported)
1527	data = kzalloc(struct_size(data, channels,
1528	IWL_NVM_NUM_CHANNELS_UHB),
1529	GFP_KERNEL);
1530	else if (cfg->nvm_type != IWL_NVM_EXT)
1531	data = kzalloc(struct_size(data, channels,
1532	IWL_NVM_NUM_CHANNELS),
1533	GFP_KERNEL);
1534	else
1535	data = kzalloc(struct_size(data, channels,
1536	IWL_NVM_NUM_CHANNELS_EXT),
1537	GFP_KERNEL);
1538	if (!data)
1539	return NULL;
1540
1541	data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
1542
1543	radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
1544	iwl_set_radio_cfg(cfg, data, radio_cfg);
1545	if (data->valid_tx_ant)
1546	tx_chains &= data->valid_tx_ant;
1547	if (data->valid_rx_ant)
1548	rx_chains &= data->valid_rx_ant;
1549
1550	sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
1551	data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
1552	data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
1553	data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
1554	if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
1555	data->sku_cap_11n_enable = false;
1556	data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
1557	(sku & NVM_SKU_CAP_11AC_ENABLE);
1558	data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
1559
1560	data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
1561
1562	if (cfg->nvm_type != IWL_NVM_EXT) {
1563	/* Checking for required sections */
1564	if (!nvm_calib) {
1565	IWL_ERR(trans,
1566	"Can't parse empty Calib NVM sections\n");
1567	kfree(objp: data);
1568	return NULL;
1569	}
1570
1571	ch_section = cfg->nvm_type == IWL_NVM_SDP ?
1572	&regulatory[NVM_CHANNELS_SDP] :
1573	&nvm_sw[NVM_CHANNELS];
1574
1575	/* in family 8000 Xtal calibration values moved to OTP */
1576	data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
1577	data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
1578	lar_enabled = true;
1579	} else {
1580	u16 lar_offset = data->nvm_version < 0xE39 ?
1581	NVM_LAR_OFFSET_OLD :
1582	NVM_LAR_OFFSET;
1583
1584	lar_config = le16_to_cpup(p: regulatory + lar_offset);
1585	data->lar_enabled = !!(lar_config &
1586	NVM_LAR_ENABLED);
1587	lar_enabled = data->lar_enabled;
1588	ch_section = &regulatory[NVM_CHANNELS_EXTENDED];
1589	}
1590
1591	/* If no valid mac address was found - bail out */
1592	if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
1593	kfree(objp: data);
1594	return NULL;
1595	}
1596
1597	if (lar_enabled &&
1598	fw_has_capa(capabilities: &fw->ucode_capa, capa: IWL_UCODE_TLV_CAPA_LAR_SUPPORT))
1599	sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1600
1601	if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw))
1602	sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ;
1603
1604	iwl_init_sbands(trans, data, nvm_ch_flags: ch_section, tx_chains, rx_chains,
1605	sbands_flags, v4: false, fw);
1606	data->calib_version = 255;
1607
1608	return data;
1609	}
1610	IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
1611
1612	static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan,
1613	int ch_idx, u16 nvm_flags,
1614	struct iwl_reg_capa reg_capa,
1615	const struct iwl_cfg *cfg,
1616	bool uats_enabled)
1617	{
1618	u32 flags = NL80211_RRF_NO_HT40;
1619
1620	if (ch_idx < NUM_2GHZ_CHANNELS &&
1621	(nvm_flags & NVM_CHANNEL_40MHZ)) {
1622	if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
1623	flags &= ~NL80211_RRF_NO_HT40PLUS;
1624	if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
1625	flags &= ~NL80211_RRF_NO_HT40MINUS;
1626	} else if (nvm_flags & NVM_CHANNEL_40MHZ) {
1627	if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
1628	flags &= ~NL80211_RRF_NO_HT40PLUS;
1629	else
1630	flags &= ~NL80211_RRF_NO_HT40MINUS;
1631	}
1632
1633	if (!(nvm_flags & NVM_CHANNEL_80MHZ))
1634	flags |= NL80211_RRF_NO_80MHZ;
1635	if (!(nvm_flags & NVM_CHANNEL_160MHZ))
1636	flags |= NL80211_RRF_NO_160MHZ;
1637
1638	if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
1639	flags |= NL80211_RRF_NO_IR;
1640
1641	if (nvm_flags & NVM_CHANNEL_RADAR)
1642	flags |= NL80211_RRF_DFS;
1643
1644	if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
1645	flags |= NL80211_RRF_NO_OUTDOOR;
1646
1647	/* Set the GO concurrent flag only in case that NO_IR is set.
1648	* Otherwise it is meaningless
1649	*/
1650	if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT)) {
1651	if (flags & NL80211_RRF_NO_IR)
1652	flags |= NL80211_RRF_GO_CONCURRENT;
1653	if (flags & NL80211_RRF_DFS) {
1654	flags |= NL80211_RRF_DFS_CONCURRENT;
1655	/* Our device doesn't set active bit for DFS channels
1656	* however, once marked as DFS no-ir is not needed.
1657	*/
1658	flags &= ~NL80211_RRF_NO_IR;
1659	}
1660	}
1661
1662	/* Set the AP type for the UHB case. */
1663	if (uats_enabled) {
1664	if (!(nvm_flags & NVM_CHANNEL_VLP))
1665	flags |= NL80211_RRF_NO_6GHZ_VLP_CLIENT;
1666
1667	if (!(nvm_flags & NVM_CHANNEL_AFC))
1668	flags |= NL80211_RRF_NO_6GHZ_AFC_CLIENT;
1669	}
1670
1671	/*
1672	* reg_capa is per regulatory domain so apply it for every channel
1673	*/
1674	if (ch_idx >= NUM_2GHZ_CHANNELS) {
1675	if (!reg_capa.allow_40mhz)
1676	flags |= NL80211_RRF_NO_HT40;
1677
1678	if (!reg_capa.allow_80mhz)
1679	flags |= NL80211_RRF_NO_80MHZ;
1680
1681	if (!reg_capa.allow_160mhz)
1682	flags |= NL80211_RRF_NO_160MHZ;
1683
1684	if (!reg_capa.allow_320mhz)
1685	flags |= NL80211_RRF_NO_320MHZ;
1686	}
1687
1688	if (reg_capa.disable_11ax)
1689	flags |= NL80211_RRF_NO_HE;
1690
1691	if (reg_capa.disable_11be)
1692	flags |= NL80211_RRF_NO_EHT;
1693
1694	return flags;
1695	}
1696
1697	static struct iwl_reg_capa iwl_get_reg_capa(u32 flags, u8 resp_ver)
1698	{
1699	struct iwl_reg_capa reg_capa = {};
1700
1701	if (resp_ver >= REG_CAPA_V4_RESP_VER) {
1702	reg_capa.allow_40mhz = true;
1703	reg_capa.allow_80mhz = flags & REG_CAPA_V4_80MHZ_ALLOWED;
1704	reg_capa.allow_160mhz = flags & REG_CAPA_V4_160MHZ_ALLOWED;
1705	reg_capa.allow_320mhz = flags & REG_CAPA_V4_320MHZ_ALLOWED;
1706	reg_capa.disable_11ax = flags & REG_CAPA_V4_11AX_DISABLED;
1707	reg_capa.disable_11be = flags & REG_CAPA_V4_11BE_DISABLED;
1708	} else if (resp_ver >= REG_CAPA_V2_RESP_VER) {
1709	reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED;
1710	reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED;
1711	reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED;
1712	reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED;
1713	} else {
1714	reg_capa.allow_40mhz = !(flags & REG_CAPA_V1_40MHZ_FORBIDDEN);
1715	reg_capa.allow_80mhz = flags & REG_CAPA_V1_80MHZ_ALLOWED;
1716	reg_capa.allow_160mhz = flags & REG_CAPA_V1_160MHZ_ALLOWED;
1717	reg_capa.disable_11ax = flags & REG_CAPA_V1_11AX_DISABLED;
1718	}
1719	return reg_capa;
1720	}
1721
1722	struct ieee80211_regdomain *
1723	iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
1724	int num_of_ch, __le32 *channels, u16 fw_mcc,
1725	u16 geo_info, u32 cap, u8 resp_ver, bool uats_enabled)
1726	{
1727	int ch_idx;
1728	u16 ch_flags;
1729	u32 reg_rule_flags, prev_reg_rule_flags = 0;
1730	const u16 *nvm_chan;
1731	struct ieee80211_regdomain *regd, *copy_rd;
1732	struct ieee80211_reg_rule *rule;
1733	enum nl80211_band band;
1734	int center_freq, prev_center_freq = 0;
1735	int valid_rules = 0;
1736	bool new_rule;
1737	int max_num_ch;
1738	struct iwl_reg_capa reg_capa;
1739
1740	if (cfg->uhb_supported) {
1741	max_num_ch = IWL_NVM_NUM_CHANNELS_UHB;
1742	nvm_chan = iwl_uhb_nvm_channels;
1743	} else if (cfg->nvm_type == IWL_NVM_EXT) {
1744	max_num_ch = IWL_NVM_NUM_CHANNELS_EXT;
1745	nvm_chan = iwl_ext_nvm_channels;
1746	} else {
1747	max_num_ch = IWL_NVM_NUM_CHANNELS;
1748	nvm_chan = iwl_nvm_channels;
1749	}
1750
1751	if (num_of_ch > max_num_ch) {
1752	IWL_DEBUG_DEV(dev, IWL_DL_LAR,
1753	"Num of channels (%d) is greater than expected. Truncating to %d\n",
1754	num_of_ch, max_num_ch);
1755	num_of_ch = max_num_ch;
1756	}
1757
1758	if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
1759	return ERR_PTR(error: -EINVAL);
1760
1761	IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
1762	num_of_ch);
1763
1764	/* build a regdomain rule for every valid channel */
1765	regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL);
1766	if (!regd)
1767	return ERR_PTR(error: -ENOMEM);
1768
1769	/* set alpha2 from FW. */
1770	regd->alpha2[0] = fw_mcc >> 8;
1771	regd->alpha2[1] = fw_mcc & 0xff;
1772
1773	/* parse regulatory capability flags */
1774	reg_capa = iwl_get_reg_capa(flags: cap, resp_ver);
1775
1776	for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
1777	ch_flags = (u16)__le32_to_cpup(p: channels + ch_idx);
1778	band = iwl_nl80211_band_from_channel_idx(ch_idx);
1779	center_freq = ieee80211_channel_to_frequency(chan: nvm_chan[ch_idx],
1780	band);
1781	new_rule = false;
1782
1783	if (!(ch_flags & NVM_CHANNEL_VALID)) {
1784	iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1785	chan: nvm_chan[ch_idx], flags: ch_flags);
1786	continue;
1787	}
1788
1789	reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
1790	nvm_flags: ch_flags, reg_capa,
1791	cfg, uats_enabled);
1792
1793	/* we can't continue the same rule */
1794	if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
1795	center_freq - prev_center_freq > 20) {
1796	valid_rules++;
1797	new_rule = true;
1798	}
1799
1800	rule = &regd->reg_rules[valid_rules - 1];
1801
1802	if (new_rule)
1803	rule->freq_range.start_freq_khz =
1804	MHZ_TO_KHZ(center_freq - 10);
1805
1806	rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
1807
1808	/* this doesn't matter - not used by FW */
1809	rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1810	rule->power_rule.max_eirp =
1811	DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1812
1813	rule->flags = reg_rule_flags;
1814
1815	/* rely on auto-calculation to merge BW of contiguous chans */
1816	rule->flags |= NL80211_RRF_AUTO_BW;
1817	rule->freq_range.max_bandwidth_khz = 0;
1818
1819	prev_center_freq = center_freq;
1820	prev_reg_rule_flags = reg_rule_flags;
1821
1822	iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1823	chan: nvm_chan[ch_idx], flags: ch_flags);
1824
1825	if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) ||
1826	band == NL80211_BAND_2GHZ)
1827	continue;
1828
1829	reg_query_regdb_wmm(alpha2: regd->alpha2, freq: center_freq, rule);
1830	}
1831
1832	/*
1833	* Certain firmware versions might report no valid channels
1834	* if booted in RF-kill, i.e. not all calibrations etc. are
1835	* running. We'll get out of this situation later when the
1836	* rfkill is removed and we update the regdomain again, but
1837	* since cfg80211 doesn't accept an empty regdomain, add a
1838	* dummy (unusable) rule here in this case so we can init.
1839	*/
1840	if (!valid_rules) {
1841	valid_rules = 1;
1842	rule = &regd->reg_rules[valid_rules - 1];
1843	rule->freq_range.start_freq_khz = MHZ_TO_KHZ(2412);
1844	rule->freq_range.end_freq_khz = MHZ_TO_KHZ(2413);
1845	rule->freq_range.max_bandwidth_khz = MHZ_TO_KHZ(1);
1846	rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1847	rule->power_rule.max_eirp =
1848	DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1849	}
1850
1851	regd->n_reg_rules = valid_rules;
1852
1853	/*
1854	* Narrow down regdom for unused regulatory rules to prevent hole
1855	* between reg rules to wmm rules.
1856	*/
1857	copy_rd = kmemdup(p: regd, struct_size(regd, reg_rules, valid_rules),
1858	GFP_KERNEL);
1859	if (!copy_rd)
1860	copy_rd = ERR_PTR(error: -ENOMEM);
1861
1862	kfree(objp: regd);
1863	return copy_rd;
1864	}
1865	IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
1866
1867	#define IWL_MAX_NVM_SECTION_SIZE 0x1b58
1868	#define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc
1869	#define MAX_NVM_FILE_LEN 16384
1870
1871	void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
1872	unsigned int len)
1873	{
1874	#define IWL_4165_DEVICE_ID 0x5501
1875	#define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
1876
1877	if (section == NVM_SECTION_TYPE_PHY_SKU &&
1878	hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
1879	(data[4] & NVM_SKU_CAP_MIMO_DISABLE))
1880	/* OTP 0x52 bug work around: it's a 1x1 device */
1881	data[3] = ANT_B | (ANT_B << 4);
1882	}
1883	IWL_EXPORT_SYMBOL(iwl_nvm_fixups);
1884
1885	/*
1886	* Reads external NVM from a file into mvm->nvm_sections
1887	*
1888	* HOW TO CREATE THE NVM FILE FORMAT:
1889	* ------------------------------
1890	* 1. create hex file, format:
1891	* 3800 -> header
1892	* 0000 -> header
1893	* 5a40 -> data
1894	*
1895	* rev - 6 bit (word1)
1896	* len - 10 bit (word1)
1897	* id - 4 bit (word2)
1898	* rsv - 12 bit (word2)
1899	*
1900	* 2. flip 8bits with 8 bits per line to get the right NVM file format
1901	*
1902	* 3. create binary file from the hex file
1903	*
1904	* 4. save as "iNVM_xxx.bin" under /lib/firmware
1905	*/
1906	int iwl_read_external_nvm(struct iwl_trans *trans,
1907	const char *nvm_file_name,
1908	struct iwl_nvm_section *nvm_sections)
1909	{
1910	int ret, section_size;
1911	u16 section_id;
1912	const struct firmware *fw_entry;
1913	const struct {
1914	__le16 word1;
1915	__le16 word2;
1916	u8 data[];
1917	} *file_sec;
1918	const u8 *eof;
1919	u8 *temp;
1920	int max_section_size;
1921	const __le32 *dword_buff;
1922
1923	#define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
1924	#define NVM_WORD2_ID(x) (x >> 12)
1925	#define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
1926	#define EXT_NVM_WORD1_ID(x) ((x) >> 4)
1927	#define NVM_HEADER_0 (0x2A504C54)
1928	#define NVM_HEADER_1 (0x4E564D2A)
1929	#define NVM_HEADER_SIZE (4 * sizeof(u32))
1930
1931	IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n");
1932
1933	/* Maximal size depends on NVM version */
1934	if (trans->cfg->nvm_type != IWL_NVM_EXT)
1935	max_section_size = IWL_MAX_NVM_SECTION_SIZE;
1936	else
1937	max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
1938
1939	/*
1940	* Obtain NVM image via request_firmware. Since we already used
1941	* request_firmware_nowait() for the firmware binary load and only
1942	* get here after that we assume the NVM request can be satisfied
1943	* synchronously.
1944	*/
1945	ret = request_firmware(fw: &fw_entry, name: nvm_file_name, device: trans->dev);
1946	if (ret) {
1947	IWL_ERR(trans, "ERROR: %s isn't available %d\n",
1948	nvm_file_name, ret);
1949	return ret;
1950	}
1951
1952	IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n",
1953	nvm_file_name, fw_entry->size);
1954
1955	if (fw_entry->size > MAX_NVM_FILE_LEN) {
1956	IWL_ERR(trans, "NVM file too large\n");
1957	ret = -EINVAL;
1958	goto out;
1959	}
1960
1961	eof = fw_entry->data + fw_entry->size;
1962	dword_buff = (const __le32 *)fw_entry->data;
1963
1964	/* some NVM file will contain a header.
1965	* The header is identified by 2 dwords header as follow:
1966	* dword[0] = 0x2A504C54
1967	* dword[1] = 0x4E564D2A
1968	*
1969	* This header must be skipped when providing the NVM data to the FW.
1970	*/
1971	if (fw_entry->size > NVM_HEADER_SIZE &&
1972	dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
1973	dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
1974	file_sec = (const void *)(fw_entry->data + NVM_HEADER_SIZE);
1975	IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
1976	IWL_INFO(trans, "NVM Manufacturing date %08X\n",
1977	le32_to_cpu(dword_buff[3]));
1978
1979	/* nvm file validation, dword_buff[2] holds the file version */
1980	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
1981	trans->hw_rev_step == SILICON_C_STEP &&
1982	le32_to_cpu(dword_buff[2]) < 0xE4A) {
1983	ret = -EFAULT;
1984	goto out;
1985	}
1986	} else {
1987	file_sec = (const void *)fw_entry->data;
1988	}
1989
1990	while (true) {
1991	if (file_sec->data > eof) {
1992	IWL_ERR(trans,
1993	"ERROR - NVM file too short for section header\n");
1994	ret = -EINVAL;
1995	break;
1996	}
1997
1998	/* check for EOF marker */
1999	if (!file_sec->word1 && !file_sec->word2) {
2000	ret = 0;
2001	break;
2002	}
2003
2004	if (trans->cfg->nvm_type != IWL_NVM_EXT) {
2005	section_size =
2006	2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
2007	section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
2008	} else {
2009	section_size = 2 * EXT_NVM_WORD2_LEN(
2010	le16_to_cpu(file_sec->word2));
2011	section_id = EXT_NVM_WORD1_ID(
2012	le16_to_cpu(file_sec->word1));
2013	}
2014
2015	if (section_size > max_section_size) {
2016	IWL_ERR(trans, "ERROR - section too large (%d)\n",
2017	section_size);
2018	ret = -EINVAL;
2019	break;
2020	}
2021
2022	if (!section_size) {
2023	IWL_ERR(trans, "ERROR - section empty\n");
2024	ret = -EINVAL;
2025	break;
2026	}
2027
2028	if (file_sec->data + section_size > eof) {
2029	IWL_ERR(trans,
2030	"ERROR - NVM file too short for section (%d bytes)\n",
2031	section_size);
2032	ret = -EINVAL;
2033	break;
2034	}
2035
2036	if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
2037	"Invalid NVM section ID %d\n", section_id)) {
2038	ret = -EINVAL;
2039	break;
2040	}
2041
2042	temp = kmemdup(p: file_sec->data, size: section_size, GFP_KERNEL);
2043	if (!temp) {
2044	ret = -ENOMEM;
2045	break;
2046	}
2047
2048	iwl_nvm_fixups(hw_id: trans->hw_id, section: section_id, data: temp, len: section_size);
2049
2050	kfree(objp: nvm_sections[section_id].data);
2051	nvm_sections[section_id].data = temp;
2052	nvm_sections[section_id].length = section_size;
2053
2054	/* advance to the next section */
2055	file_sec = (const void *)(file_sec->data + section_size);
2056	}
2057	out:
2058	release_firmware(fw: fw_entry);
2059	return ret;
2060	}
2061	IWL_EXPORT_SYMBOL(iwl_read_external_nvm);
2062
2063	struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
2064	const struct iwl_fw *fw,
2065	u8 set_tx_ant, u8 set_rx_ant)
2066	{
2067	struct iwl_nvm_get_info cmd = {};
2068	struct iwl_nvm_data *nvm;
2069	struct iwl_host_cmd hcmd = {
2070	.flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
2071	.data = { &cmd, },
2072	.len = { sizeof(cmd) },
2073	.id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
2074	};
2075	int ret;
2076	bool empty_otp;
2077	u32 mac_flags;
2078	u32 sbands_flags = 0;
2079	u8 tx_ant;
2080	u8 rx_ant;
2081
2082	/*
2083	* All the values in iwl_nvm_get_info_rsp v4 are the same as
2084	* in v3, except for the channel profile part of the
2085	* regulatory. So we can just access the new struct, with the
2086	* exception of the latter.
2087	*/
2088	struct iwl_nvm_get_info_rsp *rsp;
2089	struct iwl_nvm_get_info_rsp_v3 *rsp_v3;
2090	bool v4 = fw_has_api(capabilities: &fw->ucode_capa,
2091	api: IWL_UCODE_TLV_API_REGULATORY_NVM_INFO);
2092	size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3);
2093	void *channel_profile;
2094
2095	ret = iwl_trans_send_cmd(trans, cmd: &hcmd);
2096	if (ret)
2097	return ERR_PTR(error: ret);
2098
2099	if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size,
2100	"Invalid payload len in NVM response from FW %d",
2101	iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
2102	ret = -EINVAL;
2103	goto out;
2104	}
2105
2106	rsp = (void *)hcmd.resp_pkt->data;
2107	empty_otp = !!(le32_to_cpu(rsp->general.flags) &
2108	NVM_GENERAL_FLAGS_EMPTY_OTP);
2109	if (empty_otp)
2110	IWL_INFO(trans, "OTP is empty\n");
2111
2112	nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL);
2113	if (!nvm) {
2114	ret = -ENOMEM;
2115	goto out;
2116	}
2117
2118	iwl_set_hw_address_from_csr(trans, data: nvm);
2119	/* TODO: if platform NVM has MAC address - override it here */
2120
2121	if (!is_valid_ether_addr(addr: nvm->hw_addr)) {
2122	IWL_ERR(trans, "no valid mac address was found\n");
2123	ret = -EINVAL;
2124	goto err_free;
2125	}
2126
2127	IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
2128
2129	/* Initialize general data */
2130	nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
2131	nvm->n_hw_addrs = rsp->general.n_hw_addrs;
2132	if (nvm->n_hw_addrs == 0)
2133	IWL_WARN(trans,
2134	"Firmware declares no reserved mac addresses. OTP is empty: %d\n",
2135	empty_otp);
2136
2137	/* Initialize MAC sku data */
2138	mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags);
2139	nvm->sku_cap_11ac_enable =
2140	!!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED);
2141	nvm->sku_cap_11n_enable =
2142	!!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED);
2143	nvm->sku_cap_11ax_enable =
2144	!!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED);
2145	nvm->sku_cap_band_24ghz_enable =
2146	!!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED);
2147	nvm->sku_cap_band_52ghz_enable =
2148	!!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED);
2149	nvm->sku_cap_mimo_disabled =
2150	!!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED);
2151	if (CSR_HW_RFID_TYPE(trans->hw_rf_id) >= IWL_CFG_RF_TYPE_FM)
2152	nvm->sku_cap_11be_enable = true;
2153
2154	/* Initialize PHY sku data */
2155	nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
2156	nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
2157
2158	if (le32_to_cpu(rsp->regulatory.lar_enabled) &&
2159	fw_has_capa(capabilities: &fw->ucode_capa,
2160	capa: IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) {
2161	nvm->lar_enabled = true;
2162	sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
2163	}
2164
2165	rsp_v3 = (void *)rsp;
2166	channel_profile = v4 ? (void *)rsp->regulatory.channel_profile :
2167	(void *)rsp_v3->regulatory.channel_profile;
2168
2169	tx_ant = nvm->valid_tx_ant & fw->valid_tx_ant;
2170	rx_ant = nvm->valid_rx_ant & fw->valid_rx_ant;
2171
2172	if (set_tx_ant)
2173	tx_ant &= set_tx_ant;
2174	if (set_rx_ant)
2175	rx_ant &= set_rx_ant;
2176
2177	iwl_init_sbands(trans, data: nvm, nvm_ch_flags: channel_profile, tx_chains: tx_ant, rx_chains: rx_ant,
2178	sbands_flags, v4, fw);
2179
2180	iwl_free_resp(cmd: &hcmd);
2181	return nvm;
2182
2183	err_free:
2184	kfree(objp: nvm);
2185	out:
2186	iwl_free_resp(cmd: &hcmd);
2187	return ERR_PTR(error: ret);
2188	}
2189	IWL_EXPORT_SYMBOL(iwl_get_nvm);
2190