1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * eisa.c - provide support for EISA adapters in PA-RISC machines |
4 | * |
5 | * Copyright (c) 2001 Matthew Wilcox for Hewlett Packard |
6 | * Copyright (c) 2001 Daniel Engstrom <5116@telia.com> |
7 | * |
8 | * There are two distinct EISA adapters. Mongoose is found in machines |
9 | * before the 712; then the Wax ASIC is used. To complicate matters, the |
10 | * Wax ASIC also includes a PS/2 and RS-232 controller, but those are |
11 | * dealt with elsewhere; this file is concerned only with the EISA portions |
12 | * of Wax. |
13 | * |
14 | * HINT: |
15 | * ----- |
16 | * To allow an ISA card to work properly in the EISA slot you need to |
17 | * set an edge trigger level. This may be done on the palo command line |
18 | * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with |
19 | * n and n2 as the irq levels you want to use. |
20 | * |
21 | * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at |
22 | * irq levels 10 and 11. |
23 | */ |
24 | |
25 | #include <linux/init.h> |
26 | #include <linux/ioport.h> |
27 | #include <linux/interrupt.h> |
28 | #include <linux/kernel.h> |
29 | #include <linux/module.h> |
30 | #include <linux/pci.h> |
31 | #include <linux/spinlock.h> |
32 | #include <linux/eisa.h> |
33 | |
34 | #include <asm/byteorder.h> |
35 | #include <asm/io.h> |
36 | #include <asm/hardware.h> |
37 | #include <asm/processor.h> |
38 | #include <asm/parisc-device.h> |
39 | #include <asm/delay.h> |
40 | #include <asm/eisa_bus.h> |
41 | #include <asm/eisa_eeprom.h> |
42 | |
43 | #include "iommu.h" |
44 | |
45 | #if 0 |
46 | #define EISA_DBG(msg, arg...) printk(KERN_DEBUG "eisa: " msg, ## arg) |
47 | #else |
48 | #define EISA_DBG(msg, arg...) |
49 | #endif |
50 | |
51 | #define SNAKES_EEPROM_BASE_ADDR 0xF0810400 |
52 | #define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400 |
53 | |
54 | static DEFINE_SPINLOCK(eisa_irq_lock); |
55 | |
56 | void __iomem *eisa_eeprom_addr __read_mostly; |
57 | |
58 | /* We can only have one EISA adapter in the system because neither |
59 | * implementation can be flexed. |
60 | */ |
61 | static struct eisa_ba { |
62 | struct pci_hba_data hba; |
63 | unsigned long eeprom_addr; |
64 | struct eisa_root_device root; |
65 | } eisa_dev; |
66 | |
67 | /* Port ops */ |
68 | |
69 | static inline unsigned long eisa_permute(unsigned short port) |
70 | { |
71 | if (port & 0x300) { |
72 | return 0xfc000000 | ((port & 0xfc00) >> 6) |
73 | | ((port & 0x3f8) << 9) | (port & 7); |
74 | } else { |
75 | return 0xfc000000 | port; |
76 | } |
77 | } |
78 | |
79 | unsigned char eisa_in8(unsigned short port) |
80 | { |
81 | if (EISA_bus) |
82 | return gsc_readb(eisa_permute(port)); |
83 | return 0xff; |
84 | } |
85 | |
86 | unsigned short eisa_in16(unsigned short port) |
87 | { |
88 | if (EISA_bus) |
89 | return le16_to_cpu(gsc_readw(eisa_permute(port))); |
90 | return 0xffff; |
91 | } |
92 | |
93 | unsigned int eisa_in32(unsigned short port) |
94 | { |
95 | if (EISA_bus) |
96 | return le32_to_cpu(gsc_readl(eisa_permute(port))); |
97 | return 0xffffffff; |
98 | } |
99 | |
100 | void eisa_out8(unsigned char data, unsigned short port) |
101 | { |
102 | if (EISA_bus) |
103 | gsc_writeb(data, eisa_permute(port)); |
104 | } |
105 | |
106 | void eisa_out16(unsigned short data, unsigned short port) |
107 | { |
108 | if (EISA_bus) |
109 | gsc_writew(cpu_to_le16(data), eisa_permute(port)); |
110 | } |
111 | |
112 | void eisa_out32(unsigned int data, unsigned short port) |
113 | { |
114 | if (EISA_bus) |
115 | gsc_writel(cpu_to_le32(data), eisa_permute(port)); |
116 | } |
117 | |
118 | #ifndef CONFIG_PCI |
119 | /* We call these directly without PCI. See asm/io.h. */ |
120 | EXPORT_SYMBOL(eisa_in8); |
121 | EXPORT_SYMBOL(eisa_in16); |
122 | EXPORT_SYMBOL(eisa_in32); |
123 | EXPORT_SYMBOL(eisa_out8); |
124 | EXPORT_SYMBOL(eisa_out16); |
125 | EXPORT_SYMBOL(eisa_out32); |
126 | #endif |
127 | |
128 | /* Interrupt handling */ |
129 | |
130 | /* cached interrupt mask registers */ |
131 | static int master_mask; |
132 | static int slave_mask; |
133 | |
134 | /* the trig level can be set with the |
135 | * eisa_irq_edge=n,n,n commandline parameter |
136 | * We should really read this from the EEPROM |
137 | * in the furure. |
138 | */ |
139 | /* irq 13,8,2,1,0 must be edge */ |
140 | static unsigned int eisa_irq_level __read_mostly; /* default to edge triggered */ |
141 | |
142 | |
143 | /* called by free irq */ |
144 | static void eisa_mask_irq(struct irq_data *d) |
145 | { |
146 | unsigned int irq = d->irq; |
147 | unsigned long flags; |
148 | |
149 | EISA_DBG("disable irq %d\n" , irq); |
150 | /* just mask for now */ |
151 | spin_lock_irqsave(&eisa_irq_lock, flags); |
152 | if (irq & 8) { |
153 | slave_mask |= (1 << (irq&7)); |
154 | eisa_out8(data: slave_mask, port: 0xa1); |
155 | } else { |
156 | master_mask |= (1 << (irq&7)); |
157 | eisa_out8(data: master_mask, port: 0x21); |
158 | } |
159 | spin_unlock_irqrestore(lock: &eisa_irq_lock, flags); |
160 | EISA_DBG("pic0 mask %02x\n" , eisa_in8(0x21)); |
161 | EISA_DBG("pic1 mask %02x\n" , eisa_in8(0xa1)); |
162 | } |
163 | |
164 | /* called by request irq */ |
165 | static void eisa_unmask_irq(struct irq_data *d) |
166 | { |
167 | unsigned int irq = d->irq; |
168 | unsigned long flags; |
169 | EISA_DBG("enable irq %d\n" , irq); |
170 | |
171 | spin_lock_irqsave(&eisa_irq_lock, flags); |
172 | if (irq & 8) { |
173 | slave_mask &= ~(1 << (irq&7)); |
174 | eisa_out8(data: slave_mask, port: 0xa1); |
175 | } else { |
176 | master_mask &= ~(1 << (irq&7)); |
177 | eisa_out8(data: master_mask, port: 0x21); |
178 | } |
179 | spin_unlock_irqrestore(lock: &eisa_irq_lock, flags); |
180 | EISA_DBG("pic0 mask %02x\n" , eisa_in8(0x21)); |
181 | EISA_DBG("pic1 mask %02x\n" , eisa_in8(0xa1)); |
182 | } |
183 | |
184 | static struct irq_chip eisa_interrupt_type = { |
185 | .name = "EISA" , |
186 | .irq_unmask = eisa_unmask_irq, |
187 | .irq_mask = eisa_mask_irq, |
188 | }; |
189 | |
190 | static irqreturn_t eisa_irq(int wax_irq, void *intr_dev) |
191 | { |
192 | int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */ |
193 | unsigned long flags; |
194 | |
195 | spin_lock_irqsave(&eisa_irq_lock, flags); |
196 | /* read IRR command */ |
197 | eisa_out8(data: 0x0a, port: 0x20); |
198 | eisa_out8(data: 0x0a, port: 0xa0); |
199 | |
200 | EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n" , |
201 | irq, eisa_in8(0x20), eisa_in8(0xa0)); |
202 | |
203 | /* read ISR command */ |
204 | eisa_out8(data: 0x0a, port: 0x20); |
205 | eisa_out8(data: 0x0a, port: 0xa0); |
206 | EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n" , |
207 | eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1)); |
208 | |
209 | irq &= 0xf; |
210 | |
211 | /* mask irq and write eoi */ |
212 | if (irq & 8) { |
213 | slave_mask |= (1 << (irq&7)); |
214 | eisa_out8(data: slave_mask, port: 0xa1); |
215 | eisa_out8(data: 0x60 | (irq&7),port: 0xa0);/* 'Specific EOI' to slave */ |
216 | eisa_out8(data: 0x62, port: 0x20); /* 'Specific EOI' to master-IRQ2 */ |
217 | |
218 | } else { |
219 | master_mask |= (1 << (irq&7)); |
220 | eisa_out8(data: master_mask, port: 0x21); |
221 | eisa_out8(data: 0x60|irq, port: 0x20); /* 'Specific EOI' to master */ |
222 | } |
223 | spin_unlock_irqrestore(lock: &eisa_irq_lock, flags); |
224 | |
225 | generic_handle_irq(irq); |
226 | |
227 | spin_lock_irqsave(&eisa_irq_lock, flags); |
228 | /* unmask */ |
229 | if (irq & 8) { |
230 | slave_mask &= ~(1 << (irq&7)); |
231 | eisa_out8(data: slave_mask, port: 0xa1); |
232 | } else { |
233 | master_mask &= ~(1 << (irq&7)); |
234 | eisa_out8(data: master_mask, port: 0x21); |
235 | } |
236 | spin_unlock_irqrestore(lock: &eisa_irq_lock, flags); |
237 | return IRQ_HANDLED; |
238 | } |
239 | |
240 | static irqreturn_t dummy_irq2_handler(int _, void *dev) |
241 | { |
242 | printk(KERN_ALERT "eisa: uhh, irq2?\n" ); |
243 | return IRQ_HANDLED; |
244 | } |
245 | |
246 | static void init_eisa_pic(void) |
247 | { |
248 | unsigned long flags; |
249 | |
250 | spin_lock_irqsave(&eisa_irq_lock, flags); |
251 | |
252 | eisa_out8(data: 0xff, port: 0x21); /* mask during init */ |
253 | eisa_out8(data: 0xff, port: 0xa1); /* mask during init */ |
254 | |
255 | /* master pic */ |
256 | eisa_out8(data: 0x11, port: 0x20); /* ICW1 */ |
257 | eisa_out8(data: 0x00, port: 0x21); /* ICW2 */ |
258 | eisa_out8(data: 0x04, port: 0x21); /* ICW3 */ |
259 | eisa_out8(data: 0x01, port: 0x21); /* ICW4 */ |
260 | eisa_out8(data: 0x40, port: 0x20); /* OCW2 */ |
261 | |
262 | /* slave pic */ |
263 | eisa_out8(data: 0x11, port: 0xa0); /* ICW1 */ |
264 | eisa_out8(data: 0x08, port: 0xa1); /* ICW2 */ |
265 | eisa_out8(data: 0x02, port: 0xa1); /* ICW3 */ |
266 | eisa_out8(data: 0x01, port: 0xa1); /* ICW4 */ |
267 | eisa_out8(data: 0x40, port: 0xa0); /* OCW2 */ |
268 | |
269 | udelay(100); |
270 | |
271 | slave_mask = 0xff; |
272 | master_mask = 0xfb; |
273 | eisa_out8(data: slave_mask, port: 0xa1); /* OCW1 */ |
274 | eisa_out8(data: master_mask, port: 0x21); /* OCW1 */ |
275 | |
276 | /* setup trig level */ |
277 | EISA_DBG("EISA edge/level %04x\n" , eisa_irq_level); |
278 | |
279 | eisa_out8(data: eisa_irq_level&0xff, port: 0x4d0); /* Set all irq's to edge */ |
280 | eisa_out8(data: (eisa_irq_level >> 8) & 0xff, port: 0x4d1); |
281 | |
282 | EISA_DBG("pic0 mask %02x\n" , eisa_in8(0x21)); |
283 | EISA_DBG("pic1 mask %02x\n" , eisa_in8(0xa1)); |
284 | EISA_DBG("pic0 edge/level %02x\n" , eisa_in8(0x4d0)); |
285 | EISA_DBG("pic1 edge/level %02x\n" , eisa_in8(0x4d1)); |
286 | |
287 | spin_unlock_irqrestore(lock: &eisa_irq_lock, flags); |
288 | } |
289 | |
290 | /* Device initialisation */ |
291 | |
292 | #define is_mongoose(dev) (dev->id.sversion == 0x00076) |
293 | |
294 | static int __init eisa_probe(struct parisc_device *dev) |
295 | { |
296 | int i, result; |
297 | |
298 | char *name = is_mongoose(dev) ? "Mongoose" : "Wax" ; |
299 | |
300 | printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n" , |
301 | name, (unsigned long)dev->hpa.start); |
302 | |
303 | eisa_dev.hba.dev = dev; |
304 | eisa_dev.hba.iommu = ccio_get_iommu(dev); |
305 | |
306 | eisa_dev.hba.lmmio_space.name = "EISA" ; |
307 | eisa_dev.hba.lmmio_space.start = F_EXTEND(0xfc000000); |
308 | eisa_dev.hba.lmmio_space.end = F_EXTEND(0xffbfffff); |
309 | eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM; |
310 | result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space); |
311 | if (result < 0) { |
312 | printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n" ); |
313 | return result; |
314 | } |
315 | eisa_dev.hba.io_space.name = "EISA" ; |
316 | eisa_dev.hba.io_space.start = 0; |
317 | eisa_dev.hba.io_space.end = 0xffff; |
318 | eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO; |
319 | result = request_resource(root: &ioport_resource, new: &eisa_dev.hba.io_space); |
320 | if (result < 0) { |
321 | printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n" ); |
322 | return result; |
323 | } |
324 | pcibios_register_hba(&eisa_dev.hba); |
325 | |
326 | result = request_irq(irq: dev->irq, handler: eisa_irq, IRQF_SHARED, name: "EISA" , dev: &eisa_dev); |
327 | if (result) { |
328 | printk(KERN_ERR "EISA: request_irq failed!\n" ); |
329 | goto error_release; |
330 | } |
331 | |
332 | /* Reserve IRQ2 */ |
333 | if (request_irq(irq: 2, handler: dummy_irq2_handler, flags: 0, name: "cascade" , NULL)) |
334 | pr_err("Failed to request irq 2 (cascade)\n" ); |
335 | for (i = 0; i < 16; i++) { |
336 | irq_set_chip_and_handler(i, &eisa_interrupt_type, |
337 | handle_simple_irq); |
338 | } |
339 | |
340 | EISA_bus = 1; |
341 | |
342 | if (dev->num_addrs) { |
343 | /* newer firmware hand out the eeprom address */ |
344 | eisa_dev.eeprom_addr = dev->addr[0]; |
345 | } else { |
346 | /* old firmware, need to figure out the box */ |
347 | if (is_mongoose(dev)) { |
348 | eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR; |
349 | } else { |
350 | eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR; |
351 | } |
352 | } |
353 | eisa_eeprom_addr = ioremap(offset: eisa_dev.eeprom_addr, size: HPEE_MAX_LENGTH); |
354 | if (!eisa_eeprom_addr) { |
355 | result = -ENOMEM; |
356 | printk(KERN_ERR "EISA: ioremap failed!\n" ); |
357 | goto error_free_irq; |
358 | } |
359 | result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space, |
360 | &eisa_dev.hba.lmmio_space); |
361 | init_eisa_pic(); |
362 | |
363 | if (result >= 0) { |
364 | /* FIXME : Don't enumerate the bus twice. */ |
365 | eisa_dev.root.dev = &dev->dev; |
366 | dev_set_drvdata(dev: &dev->dev, data: &eisa_dev.root); |
367 | eisa_dev.root.bus_base_addr = 0; |
368 | eisa_dev.root.res = &eisa_dev.hba.io_space; |
369 | eisa_dev.root.slots = result; |
370 | eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */ |
371 | if (eisa_root_register (root: &eisa_dev.root)) { |
372 | printk(KERN_ERR "EISA: Failed to register EISA root\n" ); |
373 | result = -ENOMEM; |
374 | goto error_iounmap; |
375 | } |
376 | } |
377 | |
378 | return 0; |
379 | |
380 | error_iounmap: |
381 | iounmap(addr: eisa_eeprom_addr); |
382 | error_free_irq: |
383 | free_irq(dev->irq, &eisa_dev); |
384 | error_release: |
385 | release_resource(new: &eisa_dev.hba.io_space); |
386 | return result; |
387 | } |
388 | |
389 | static const struct parisc_device_id eisa_tbl[] __initconst = { |
390 | { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */ |
391 | { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */ |
392 | { 0, } |
393 | }; |
394 | |
395 | MODULE_DEVICE_TABLE(parisc, eisa_tbl); |
396 | |
397 | static struct parisc_driver eisa_driver __refdata = { |
398 | .name = "eisa_ba" , |
399 | .id_table = eisa_tbl, |
400 | .probe = eisa_probe, |
401 | }; |
402 | |
403 | static int __init parisc_eisa_init(void) |
404 | { |
405 | return register_parisc_driver(&eisa_driver); |
406 | } |
407 | arch_initcall(parisc_eisa_init); |
408 | |
409 | |
410 | static unsigned int eisa_irq_configured; |
411 | void eisa_make_irq_level(int num) |
412 | { |
413 | if (eisa_irq_configured& (1<<num)) { |
414 | printk(KERN_WARNING |
415 | "IRQ %d polarity configured twice (last to level)\n" , |
416 | num); |
417 | } |
418 | eisa_irq_level |= (1<<num); /* set the corresponding bit */ |
419 | eisa_irq_configured |= (1<<num); /* set the corresponding bit */ |
420 | } |
421 | |
422 | void eisa_make_irq_edge(int num) |
423 | { |
424 | if (eisa_irq_configured& (1<<num)) { |
425 | printk(KERN_WARNING |
426 | "IRQ %d polarity configured twice (last to edge)\n" , |
427 | num); |
428 | } |
429 | eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */ |
430 | eisa_irq_configured |= (1<<num); /* set the corresponding bit */ |
431 | } |
432 | |
433 | static int __init eisa_irq_setup(char *str) |
434 | { |
435 | char *cur = str; |
436 | int val; |
437 | |
438 | EISA_DBG("IRQ setup\n" ); |
439 | while (cur != NULL) { |
440 | char *pe; |
441 | |
442 | val = (int) simple_strtoul(cur, &pe, 0); |
443 | if (val > 15 || val < 0) { |
444 | printk(KERN_ERR "eisa: EISA irq value are 0-15\n" ); |
445 | continue; |
446 | } |
447 | if (val == 2) { |
448 | val = 9; |
449 | } |
450 | eisa_make_irq_edge(num: val); /* clear the corresponding bit */ |
451 | EISA_DBG("setting IRQ %d to edge-triggered mode\n" , val); |
452 | |
453 | if ((cur = strchr(cur, ','))) { |
454 | cur++; |
455 | } else { |
456 | break; |
457 | } |
458 | } |
459 | return 1; |
460 | } |
461 | |
462 | __setup("eisa_irq_edge=" , eisa_irq_setup); |
463 | |
464 | |