1// SPDX-License-Identifier: GPL-2.0+
2//
3// Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver
4// with eint support.
5//
6// Copyright (c) 2012 Samsung Electronics Co., Ltd.
7// http://www.samsung.com
8// Copyright (c) 2012 Linaro Ltd
9// http://www.linaro.org
10// Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
11//
12// This file contains the Samsung Exynos specific information required by the
13// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
14// external gpio and wakeup interrupt support.
15
16#include <linux/slab.h>
17#include <linux/soc/samsung/exynos-regs-pmu.h>
18
19#include "pinctrl-samsung.h"
20#include "pinctrl-exynos.h"
21
22static const struct samsung_pin_bank_type bank_type_off = {
23 .fld_width = { 4, 1, 2, 2, 2, 2, },
24 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
25};
26
27static const struct samsung_pin_bank_type bank_type_alive = {
28 .fld_width = { 4, 1, 2, 2, },
29 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
30};
31
32/* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */
33static const struct samsung_pin_bank_type exynos5433_bank_type_off = {
34 .fld_width = { 4, 1, 2, 4, 2, 2, },
35 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
36};
37
38static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
39 .fld_width = { 4, 1, 2, 4, },
40 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
41};
42
43/*
44 * Bank type for non-alive type. Bit fields:
45 * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4
46 */
47static const struct samsung_pin_bank_type exynos850_bank_type_off = {
48 .fld_width = { 4, 1, 4, 4, 2, 4, },
49 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
50};
51
52/*
53 * Bank type for alive type. Bit fields:
54 * CON: 4, DAT: 1, PUD: 4, DRV: 4
55 */
56static const struct samsung_pin_bank_type exynos850_bank_type_alive = {
57 .fld_width = { 4, 1, 4, 4, },
58 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
59};
60
61/* Pad retention control code for accessing PMU regmap */
62static atomic_t exynos_shared_retention_refcnt;
63
64/* pin banks of exynos5433 pin-controller - ALIVE */
65static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = {
66 /* Must start with EINTG banks, ordered by EINT group number. */
67 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
68 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
69 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
70 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
71 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
72 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
73 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),
74 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),
75 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),
76};
77
78/* pin banks of exynos5433 pin-controller - AUD */
79static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = {
80 /* Must start with EINTG banks, ordered by EINT group number. */
81 EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
82 EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
83};
84
85/* pin banks of exynos5433 pin-controller - CPIF */
86static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = {
87 /* Must start with EINTG banks, ordered by EINT group number. */
88 EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
89};
90
91/* pin banks of exynos5433 pin-controller - eSE */
92static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = {
93 /* Must start with EINTG banks, ordered by EINT group number. */
94 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
95};
96
97/* pin banks of exynos5433 pin-controller - FINGER */
98static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = {
99 /* Must start with EINTG banks, ordered by EINT group number. */
100 EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
101};
102
103/* pin banks of exynos5433 pin-controller - FSYS */
104static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = {
105 /* Must start with EINTG banks, ordered by EINT group number. */
106 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
107 EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
108 EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
109 EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
110 EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
111 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
112};
113
114/* pin banks of exynos5433 pin-controller - IMEM */
115static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = {
116 /* Must start with EINTG banks, ordered by EINT group number. */
117 EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
118};
119
120/* pin banks of exynos5433 pin-controller - NFC */
121static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = {
122 /* Must start with EINTG banks, ordered by EINT group number. */
123 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
124};
125
126/* pin banks of exynos5433 pin-controller - PERIC */
127static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = {
128 /* Must start with EINTG banks, ordered by EINT group number. */
129 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
130 EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
131 EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
132 EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
133 EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
134 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
135 EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
136 EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
137 EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
138 EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
139 EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
140 EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
141 EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
142 EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
143 EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
144 EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
145 EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
146};
147
148/* pin banks of exynos5433 pin-controller - TOUCH */
149static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = {
150 /* Must start with EINTG banks, ordered by EINT group number. */
151 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
152};
153
154/* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */
155static const u32 exynos5433_retention_regs[] = {
156 EXYNOS5433_PAD_RETENTION_TOP_OPTION,
157 EXYNOS5433_PAD_RETENTION_UART_OPTION,
158 EXYNOS5433_PAD_RETENTION_EBIA_OPTION,
159 EXYNOS5433_PAD_RETENTION_EBIB_OPTION,
160 EXYNOS5433_PAD_RETENTION_SPI_OPTION,
161 EXYNOS5433_PAD_RETENTION_MIF_OPTION,
162 EXYNOS5433_PAD_RETENTION_USBXTI_OPTION,
163 EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION,
164 EXYNOS5433_PAD_RETENTION_UFS_OPTION,
165 EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION,
166};
167
168static const struct samsung_retention_data exynos5433_retention_data __initconst = {
169 .regs = exynos5433_retention_regs,
170 .nr_regs = ARRAY_SIZE(exynos5433_retention_regs),
171 .value = EXYNOS_WAKEUP_FROM_LOWPWR,
172 .refcnt = &exynos_shared_retention_refcnt,
173 .init = exynos_retention_init,
174};
175
176/* PMU retention control for audio pins can be tied to audio pin bank */
177static const u32 exynos5433_audio_retention_regs[] = {
178 EXYNOS5433_PAD_RETENTION_AUD_OPTION,
179};
180
181static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = {
182 .regs = exynos5433_audio_retention_regs,
183 .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs),
184 .value = EXYNOS_WAKEUP_FROM_LOWPWR,
185 .init = exynos_retention_init,
186};
187
188/* PMU retention control for mmc pins can be tied to fsys pin bank */
189static const u32 exynos5433_fsys_retention_regs[] = {
190 EXYNOS5433_PAD_RETENTION_MMC0_OPTION,
191 EXYNOS5433_PAD_RETENTION_MMC1_OPTION,
192 EXYNOS5433_PAD_RETENTION_MMC2_OPTION,
193};
194
195static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = {
196 .regs = exynos5433_fsys_retention_regs,
197 .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs),
198 .value = EXYNOS_WAKEUP_FROM_LOWPWR,
199 .init = exynos_retention_init,
200};
201
202/*
203 * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
204 * ten gpio/pin-mux/pinconfig controllers.
205 */
206static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
207 {
208 /* pin-controller instance 0 data */
209 .pin_banks = exynos5433_pin_banks0,
210 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0),
211 .eint_wkup_init = exynos_eint_wkup_init,
212 .suspend = exynos_pinctrl_suspend,
213 .resume = exynos_pinctrl_resume,
214 .nr_ext_resources = 1,
215 .retention_data = &exynos5433_retention_data,
216 }, {
217 /* pin-controller instance 1 data */
218 .pin_banks = exynos5433_pin_banks1,
219 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1),
220 .eint_gpio_init = exynos_eint_gpio_init,
221 .suspend = exynos_pinctrl_suspend,
222 .resume = exynos_pinctrl_resume,
223 .retention_data = &exynos5433_audio_retention_data,
224 }, {
225 /* pin-controller instance 2 data */
226 .pin_banks = exynos5433_pin_banks2,
227 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2),
228 .eint_gpio_init = exynos_eint_gpio_init,
229 .suspend = exynos_pinctrl_suspend,
230 .resume = exynos_pinctrl_resume,
231 .retention_data = &exynos5433_retention_data,
232 }, {
233 /* pin-controller instance 3 data */
234 .pin_banks = exynos5433_pin_banks3,
235 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3),
236 .eint_gpio_init = exynos_eint_gpio_init,
237 .suspend = exynos_pinctrl_suspend,
238 .resume = exynos_pinctrl_resume,
239 .retention_data = &exynos5433_retention_data,
240 }, {
241 /* pin-controller instance 4 data */
242 .pin_banks = exynos5433_pin_banks4,
243 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4),
244 .eint_gpio_init = exynos_eint_gpio_init,
245 .suspend = exynos_pinctrl_suspend,
246 .resume = exynos_pinctrl_resume,
247 .retention_data = &exynos5433_retention_data,
248 }, {
249 /* pin-controller instance 5 data */
250 .pin_banks = exynos5433_pin_banks5,
251 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5),
252 .eint_gpio_init = exynos_eint_gpio_init,
253 .suspend = exynos_pinctrl_suspend,
254 .resume = exynos_pinctrl_resume,
255 .retention_data = &exynos5433_fsys_retention_data,
256 }, {
257 /* pin-controller instance 6 data */
258 .pin_banks = exynos5433_pin_banks6,
259 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6),
260 .eint_gpio_init = exynos_eint_gpio_init,
261 .suspend = exynos_pinctrl_suspend,
262 .resume = exynos_pinctrl_resume,
263 .retention_data = &exynos5433_retention_data,
264 }, {
265 /* pin-controller instance 7 data */
266 .pin_banks = exynos5433_pin_banks7,
267 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7),
268 .eint_gpio_init = exynos_eint_gpio_init,
269 .suspend = exynos_pinctrl_suspend,
270 .resume = exynos_pinctrl_resume,
271 .retention_data = &exynos5433_retention_data,
272 }, {
273 /* pin-controller instance 8 data */
274 .pin_banks = exynos5433_pin_banks8,
275 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8),
276 .eint_gpio_init = exynos_eint_gpio_init,
277 .suspend = exynos_pinctrl_suspend,
278 .resume = exynos_pinctrl_resume,
279 .retention_data = &exynos5433_retention_data,
280 }, {
281 /* pin-controller instance 9 data */
282 .pin_banks = exynos5433_pin_banks9,
283 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9),
284 .eint_gpio_init = exynos_eint_gpio_init,
285 .suspend = exynos_pinctrl_suspend,
286 .resume = exynos_pinctrl_resume,
287 .retention_data = &exynos5433_retention_data,
288 },
289};
290
291const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = {
292 .ctrl = exynos5433_pin_ctrl,
293 .num_ctrl = ARRAY_SIZE(exynos5433_pin_ctrl),
294};
295
296/* pin banks of exynos7 pin-controller - ALIVE */
297static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
298 /* Must start with EINTG banks, ordered by EINT group number. */
299 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
300 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
301 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
302 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
303};
304
305/* pin banks of exynos7 pin-controller - BUS0 */
306static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
307 /* Must start with EINTG banks, ordered by EINT group number. */
308 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
309 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
310 EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
311 EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
312 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
313 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
314 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
315 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
316 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
317 EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
318 EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
319 EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
320 EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
321 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
322 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
323};
324
325/* pin banks of exynos7 pin-controller - NFC */
326static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {
327 /* Must start with EINTG banks, ordered by EINT group number. */
328 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
329};
330
331/* pin banks of exynos7 pin-controller - TOUCH */
332static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {
333 /* Must start with EINTG banks, ordered by EINT group number. */
334 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
335};
336
337/* pin banks of exynos7 pin-controller - FF */
338static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {
339 /* Must start with EINTG banks, ordered by EINT group number. */
340 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
341};
342
343/* pin banks of exynos7 pin-controller - ESE */
344static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {
345 /* Must start with EINTG banks, ordered by EINT group number. */
346 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
347};
348
349/* pin banks of exynos7 pin-controller - FSYS0 */
350static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {
351 /* Must start with EINTG banks, ordered by EINT group number. */
352 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
353};
354
355/* pin banks of exynos7 pin-controller - FSYS1 */
356static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
357 /* Must start with EINTG banks, ordered by EINT group number. */
358 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
359 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
360 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
361 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
362};
363
364/* pin banks of exynos7 pin-controller - BUS1 */
365static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
366 /* Must start with EINTG banks, ordered by EINT group number. */
367 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
368 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
369 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
370 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
371 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
372 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
373 EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
374 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
375 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
376 EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
377};
378
379static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = {
380 /* Must start with EINTG banks, ordered by EINT group number. */
381 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
382 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
383};
384
385static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
386 {
387 /* pin-controller instance 0 Alive data */
388 .pin_banks = exynos7_pin_banks0,
389 .nr_banks = ARRAY_SIZE(exynos7_pin_banks0),
390 .eint_wkup_init = exynos_eint_wkup_init,
391 }, {
392 /* pin-controller instance 1 BUS0 data */
393 .pin_banks = exynos7_pin_banks1,
394 .nr_banks = ARRAY_SIZE(exynos7_pin_banks1),
395 .eint_gpio_init = exynos_eint_gpio_init,
396 }, {
397 /* pin-controller instance 2 NFC data */
398 .pin_banks = exynos7_pin_banks2,
399 .nr_banks = ARRAY_SIZE(exynos7_pin_banks2),
400 .eint_gpio_init = exynos_eint_gpio_init,
401 }, {
402 /* pin-controller instance 3 TOUCH data */
403 .pin_banks = exynos7_pin_banks3,
404 .nr_banks = ARRAY_SIZE(exynos7_pin_banks3),
405 .eint_gpio_init = exynos_eint_gpio_init,
406 }, {
407 /* pin-controller instance 4 FF data */
408 .pin_banks = exynos7_pin_banks4,
409 .nr_banks = ARRAY_SIZE(exynos7_pin_banks4),
410 .eint_gpio_init = exynos_eint_gpio_init,
411 }, {
412 /* pin-controller instance 5 ESE data */
413 .pin_banks = exynos7_pin_banks5,
414 .nr_banks = ARRAY_SIZE(exynos7_pin_banks5),
415 .eint_gpio_init = exynos_eint_gpio_init,
416 }, {
417 /* pin-controller instance 6 FSYS0 data */
418 .pin_banks = exynos7_pin_banks6,
419 .nr_banks = ARRAY_SIZE(exynos7_pin_banks6),
420 .eint_gpio_init = exynos_eint_gpio_init,
421 }, {
422 /* pin-controller instance 7 FSYS1 data */
423 .pin_banks = exynos7_pin_banks7,
424 .nr_banks = ARRAY_SIZE(exynos7_pin_banks7),
425 .eint_gpio_init = exynos_eint_gpio_init,
426 }, {
427 /* pin-controller instance 8 BUS1 data */
428 .pin_banks = exynos7_pin_banks8,
429 .nr_banks = ARRAY_SIZE(exynos7_pin_banks8),
430 .eint_gpio_init = exynos_eint_gpio_init,
431 }, {
432 /* pin-controller instance 9 AUD data */
433 .pin_banks = exynos7_pin_banks9,
434 .nr_banks = ARRAY_SIZE(exynos7_pin_banks9),
435 .eint_gpio_init = exynos_eint_gpio_init,
436 },
437};
438
439const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = {
440 .ctrl = exynos7_pin_ctrl,
441 .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl),
442};
443
444/* pin banks of exynos7885 pin-controller 0 (ALIVE) */
445static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = {
446 EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"),
447 EXYNOS_PIN_BANK_EINTN(3, 0x020, "etc1"),
448 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00),
449 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04),
450 EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08),
451 EXYNOS850_PIN_BANK_EINTW(5, 0x0a0, "gpq0", 0x0c),
452};
453
454/* pin banks of exynos7885 pin-controller 1 (DISPAUD) */
455static const struct samsung_pin_bank_data exynos7885_pin_banks1[] __initconst = {
456 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
457 EXYNOS850_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04),
458 EXYNOS850_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08),
459};
460
461/* pin banks of exynos7885 pin-controller 2 (FSYS) */
462static const struct samsung_pin_bank_data exynos7885_pin_banks2[] __initconst = {
463 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00),
464 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf2", 0x04),
465 EXYNOS850_PIN_BANK_EINTG(6, 0x040, "gpf3", 0x08),
466 EXYNOS850_PIN_BANK_EINTG(6, 0x060, "gpf4", 0x0c),
467};
468
469/* pin banks of exynos7885 pin-controller 3 (TOP) */
470static const struct samsung_pin_bank_data exynos7885_pin_banks3[] __initconst = {
471 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpp0", 0x00),
472 EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gpg0", 0x04),
473 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08),
474 EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c),
475 EXYNOS850_PIN_BANK_EINTG(3, 0x080, "gpp3", 0x10),
476 EXYNOS850_PIN_BANK_EINTG(6, 0x0a0, "gpp4", 0x14),
477 EXYNOS850_PIN_BANK_EINTG(4, 0x0c0, "gpp5", 0x18),
478 EXYNOS850_PIN_BANK_EINTG(5, 0x0e0, "gpp6", 0x1c),
479 EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpp7", 0x20),
480 EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp8", 0x24),
481 EXYNOS850_PIN_BANK_EINTG(8, 0x140, "gpg1", 0x28),
482 EXYNOS850_PIN_BANK_EINTG(8, 0x160, "gpg2", 0x2c),
483 EXYNOS850_PIN_BANK_EINTG(8, 0x180, "gpg3", 0x30),
484 EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpg4", 0x34),
485 EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpc0", 0x38),
486 EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpc1", 0x3c),
487 EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpc2", 0x40),
488};
489
490static const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = {
491 {
492 /* pin-controller instance 0 Alive data */
493 .pin_banks = exynos7885_pin_banks0,
494 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks0),
495 .eint_gpio_init = exynos_eint_gpio_init,
496 .eint_wkup_init = exynos_eint_wkup_init,
497 .suspend = exynos_pinctrl_suspend,
498 .resume = exynos_pinctrl_resume,
499 }, {
500 /* pin-controller instance 1 DISPAUD data */
501 .pin_banks = exynos7885_pin_banks1,
502 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks1),
503 }, {
504 /* pin-controller instance 2 FSYS data */
505 .pin_banks = exynos7885_pin_banks2,
506 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks2),
507 .eint_gpio_init = exynos_eint_gpio_init,
508 .suspend = exynos_pinctrl_suspend,
509 .resume = exynos_pinctrl_resume,
510 }, {
511 /* pin-controller instance 3 TOP data */
512 .pin_banks = exynos7885_pin_banks3,
513 .nr_banks = ARRAY_SIZE(exynos7885_pin_banks3),
514 .eint_gpio_init = exynos_eint_gpio_init,
515 .suspend = exynos_pinctrl_suspend,
516 .resume = exynos_pinctrl_resume,
517 },
518};
519
520const struct samsung_pinctrl_of_match_data exynos7885_of_data __initconst = {
521 .ctrl = exynos7885_pin_ctrl,
522 .num_ctrl = ARRAY_SIZE(exynos7885_pin_ctrl),
523};
524
525/* pin banks of exynos850 pin-controller 0 (ALIVE) */
526static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = {
527 /* Must start with EINTG banks, ordered by EINT group number. */
528 EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
529 EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
530 EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
531 EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
532 EXYNOS850_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10),
533 EXYNOS850_PIN_BANK_EINTN(3, 0x0a0, "gpq0"),
534};
535
536/* pin banks of exynos850 pin-controller 1 (CMGP) */
537static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = {
538 /* Must start with EINTG banks, ordered by EINT group number. */
539 EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00),
540 EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04),
541 EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08),
542 EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0c),
543 EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10),
544 EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpm5", 0x14),
545 EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpm6", 0x18),
546 EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpm7", 0x1c),
547};
548
549/* pin banks of exynos850 pin-controller 2 (AUD) */
550static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = {
551 /* Must start with EINTG banks, ordered by EINT group number. */
552 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
553 EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04),
554};
555
556/* pin banks of exynos850 pin-controller 3 (HSI) */
557static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = {
558 /* Must start with EINTG banks, ordered by EINT group number. */
559 EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00),
560};
561
562/* pin banks of exynos850 pin-controller 4 (CORE) */
563static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = {
564 /* Must start with EINTG banks, ordered by EINT group number. */
565 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00),
566 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04),
567};
568
569/* pin banks of exynos850 pin-controller 5 (PERI) */
570static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = {
571 /* Must start with EINTG banks, ordered by EINT group number. */
572 EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00),
573 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04),
574 EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08),
575 EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c),
576 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10),
577 EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpg2", 0x14),
578 EXYNOS850_PIN_BANK_EINTG(1, 0x0c0, "gpg3", 0x18),
579 EXYNOS850_PIN_BANK_EINTG(3, 0x0e0, "gpc0", 0x1c),
580 EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20),
581};
582
583static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = {
584 {
585 /* pin-controller instance 0 ALIVE data */
586 .pin_banks = exynos850_pin_banks0,
587 .nr_banks = ARRAY_SIZE(exynos850_pin_banks0),
588 .eint_wkup_init = exynos_eint_wkup_init,
589 }, {
590 /* pin-controller instance 1 CMGP data */
591 .pin_banks = exynos850_pin_banks1,
592 .nr_banks = ARRAY_SIZE(exynos850_pin_banks1),
593 .eint_wkup_init = exynos_eint_wkup_init,
594 }, {
595 /* pin-controller instance 2 AUD data */
596 .pin_banks = exynos850_pin_banks2,
597 .nr_banks = ARRAY_SIZE(exynos850_pin_banks2),
598 }, {
599 /* pin-controller instance 3 HSI data */
600 .pin_banks = exynos850_pin_banks3,
601 .nr_banks = ARRAY_SIZE(exynos850_pin_banks3),
602 .eint_gpio_init = exynos_eint_gpio_init,
603 }, {
604 /* pin-controller instance 4 CORE data */
605 .pin_banks = exynos850_pin_banks4,
606 .nr_banks = ARRAY_SIZE(exynos850_pin_banks4),
607 .eint_gpio_init = exynos_eint_gpio_init,
608 }, {
609 /* pin-controller instance 5 PERI data */
610 .pin_banks = exynos850_pin_banks5,
611 .nr_banks = ARRAY_SIZE(exynos850_pin_banks5),
612 .eint_gpio_init = exynos_eint_gpio_init,
613 },
614};
615
616const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = {
617 .ctrl = exynos850_pin_ctrl,
618 .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl),
619};
620
621/* pin banks of exynosautov9 pin-controller 0 (ALIVE) */
622static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = {
623 EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
624 EXYNOS850_PIN_BANK_EINTW(2, 0x020, "gpa1", 0x04),
625 EXYNOS850_PIN_BANK_EINTN(2, 0x040, "gpq0"),
626};
627
628/* pin banks of exynosautov9 pin-controller 1 (AUD) */
629static const struct samsung_pin_bank_data exynosautov9_pin_banks1[] __initconst = {
630 EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
631 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04),
632 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpb2", 0x08),
633 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpb3", 0x0C),
634};
635
636/* pin banks of exynosautov9 pin-controller 2 (FSYS0) */
637static const struct samsung_pin_bank_data exynosautov9_pin_banks2[] __initconst = {
638 EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf0", 0x00),
639 EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04),
640};
641
642/* pin banks of exynosautov9 pin-controller 3 (FSYS1) */
643static const struct samsung_pin_bank_data exynosautov9_pin_banks3[] __initconst = {
644 EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf8", 0x00),
645};
646
647/* pin banks of exynosautov9 pin-controller 4 (FSYS2) */
648static const struct samsung_pin_bank_data exynosautov9_pin_banks4[] __initconst = {
649 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf2", 0x00),
650 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf3", 0x04),
651 EXYNOS850_PIN_BANK_EINTG(7, 0x040, "gpf4", 0x08),
652 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpf5", 0x0C),
653 EXYNOS850_PIN_BANK_EINTG(7, 0x080, "gpf6", 0x10),
654};
655
656/* pin banks of exynosautov9 pin-controller 5 (PERIC0) */
657static const struct samsung_pin_bank_data exynosautov9_pin_banks5[] __initconst = {
658 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00),
659 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04),
660 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08),
661 EXYNOS850_PIN_BANK_EINTG(5, 0x060, "gpg0", 0x0C),
662};
663
664/* pin banks of exynosautov9 pin-controller 6 (PERIC1) */
665static const struct samsung_pin_bank_data exynosautov9_pin_banks6[] __initconst = {
666 EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp3", 0x00),
667 EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp4", 0x04),
668 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp5", 0x08),
669 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpg1", 0x0C),
670 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg2", 0x10),
671 EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpg3", 0x14),
672};
673
674static const struct samsung_pin_ctrl exynosautov9_pin_ctrl[] __initconst = {
675 {
676 /* pin-controller instance 0 ALIVE data */
677 .pin_banks = exynosautov9_pin_banks0,
678 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks0),
679 .eint_wkup_init = exynos_eint_wkup_init,
680 .suspend = exynos_pinctrl_suspend,
681 .resume = exynos_pinctrl_resume,
682 }, {
683 /* pin-controller instance 1 AUD data */
684 .pin_banks = exynosautov9_pin_banks1,
685 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks1),
686 }, {
687 /* pin-controller instance 2 FSYS0 data */
688 .pin_banks = exynosautov9_pin_banks2,
689 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks2),
690 .eint_gpio_init = exynos_eint_gpio_init,
691 .suspend = exynos_pinctrl_suspend,
692 .resume = exynos_pinctrl_resume,
693 }, {
694 /* pin-controller instance 3 FSYS1 data */
695 .pin_banks = exynosautov9_pin_banks3,
696 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks3),
697 .eint_gpio_init = exynos_eint_gpio_init,
698 .suspend = exynos_pinctrl_suspend,
699 .resume = exynos_pinctrl_resume,
700 }, {
701 /* pin-controller instance 4 FSYS2 data */
702 .pin_banks = exynosautov9_pin_banks4,
703 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks4),
704 .eint_gpio_init = exynos_eint_gpio_init,
705 .suspend = exynos_pinctrl_suspend,
706 .resume = exynos_pinctrl_resume,
707 }, {
708 /* pin-controller instance 5 PERIC0 data */
709 .pin_banks = exynosautov9_pin_banks5,
710 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks5),
711 .eint_gpio_init = exynos_eint_gpio_init,
712 .suspend = exynos_pinctrl_suspend,
713 .resume = exynos_pinctrl_resume,
714 }, {
715 /* pin-controller instance 6 PERIC1 data */
716 .pin_banks = exynosautov9_pin_banks6,
717 .nr_banks = ARRAY_SIZE(exynosautov9_pin_banks6),
718 .eint_gpio_init = exynos_eint_gpio_init,
719 .suspend = exynos_pinctrl_suspend,
720 .resume = exynos_pinctrl_resume,
721 },
722};
723
724const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = {
725 .ctrl = exynosautov9_pin_ctrl,
726 .num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl),
727};
728
729/* pin banks of exynosautov920 pin-controller 0 (ALIVE) */
730static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = {
731 EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28),
732 EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24),
733 EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"),
734};
735
736/* pin banks of exynosautov920 pin-controller 1 (AUD) */
737static const struct samsung_pin_bank_data exynosautov920_pin_banks1[] = {
738 EXYNOSV920_PIN_BANK_EINTG(7, 0x0000, "gpb0", 0x18, 0x24, 0x28),
739 EXYNOSV920_PIN_BANK_EINTG(6, 0x1000, "gpb1", 0x18, 0x24, 0x28),
740 EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpb2", 0x18, 0x24, 0x28),
741 EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpb3", 0x18, 0x24, 0x28),
742 EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpb4", 0x18, 0x24, 0x28),
743 EXYNOSV920_PIN_BANK_EINTG(5, 0x5000, "gpb5", 0x18, 0x24, 0x28),
744 EXYNOSV920_PIN_BANK_EINTG(5, 0x6000, "gpb6", 0x18, 0x24, 0x28),
745};
746
747/* pin banks of exynosautov920 pin-controller 2 (HSI0) */
748static const struct samsung_pin_bank_data exynosautov920_pin_banks2[] = {
749 EXYNOSV920_PIN_BANK_EINTG(6, 0x0000, "gph0", 0x18, 0x24, 0x28),
750 EXYNOSV920_PIN_BANK_EINTG(2, 0x1000, "gph1", 0x18, 0x20, 0x24),
751};
752
753/* pin banks of exynosautov920 pin-controller 3 (HSI1) */
754static const struct samsung_pin_bank_data exynosautov920_pin_banks3[] = {
755 EXYNOSV920_PIN_BANK_EINTG(7, 0x000, "gph8", 0x18, 0x24, 0x28),
756};
757
758/* pin banks of exynosautov920 pin-controller 4 (HSI2) */
759static const struct samsung_pin_bank_data exynosautov920_pin_banks4[] = {
760 EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gph3", 0x18, 0x24, 0x28),
761 EXYNOSV920_PIN_BANK_EINTG(7, 0x1000, "gph4", 0x18, 0x24, 0x28),
762 EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gph5", 0x18, 0x24, 0x28),
763 EXYNOSV920_PIN_BANK_EINTG(7, 0x3000, "gph6", 0x18, 0x24, 0x28),
764};
765
766/* pin banks of exynosautov920 pin-controller 5 (HSI2UFS) */
767static const struct samsung_pin_bank_data exynosautov920_pin_banks5[] = {
768 EXYNOSV920_PIN_BANK_EINTG(4, 0x000, "gph2", 0x18, 0x20, 0x24),
769};
770
771/* pin banks of exynosautov920 pin-controller 6 (PERIC0) */
772static const struct samsung_pin_bank_data exynosautov920_pin_banks6[] = {
773 EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp0", 0x18, 0x24, 0x28),
774 EXYNOSV920_PIN_BANK_EINTG(8, 0x1000, "gpp1", 0x18, 0x24, 0x28),
775 EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpp2", 0x18, 0x24, 0x28),
776 EXYNOSV920_PIN_BANK_EINTG(5, 0x3000, "gpg0", 0x18, 0x24, 0x28),
777 EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpp3", 0x18, 0x24, 0x28),
778 EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp4", 0x18, 0x20, 0x24),
779 EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpg2", 0x18, 0x20, 0x24),
780 EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpg5", 0x18, 0x20, 0x24),
781 EXYNOSV920_PIN_BANK_EINTG(3, 0x8000, "gpg3", 0x18, 0x20, 0x24),
782 EXYNOSV920_PIN_BANK_EINTG(5, 0x9000, "gpg4", 0x18, 0x24, 0x28),
783};
784
785/* pin banks of exynosautov920 pin-controller 7 (PERIC1) */
786static const struct samsung_pin_bank_data exynosautov920_pin_banks7[] = {
787 EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp5", 0x18, 0x24, 0x28),
788 EXYNOSV920_PIN_BANK_EINTG(5, 0x1000, "gpp6", 0x18, 0x24, 0x28),
789 EXYNOSV920_PIN_BANK_EINTG(4, 0x2000, "gpp10", 0x18, 0x20, 0x24),
790 EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpp7", 0x18, 0x24, 0x28),
791 EXYNOSV920_PIN_BANK_EINTG(4, 0x4000, "gpp8", 0x18, 0x20, 0x24),
792 EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp11", 0x18, 0x20, 0x24),
793 EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpp9", 0x18, 0x20, 0x24),
794 EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpp12", 0x18, 0x20, 0x24),
795 EXYNOSV920_PIN_BANK_EINTG(8, 0x8000, "gpg1", 0x18, 0x24, 0x28),
796};
797
798static const struct samsung_retention_data exynosautov920_retention_data __initconst = {
799 .regs = NULL,
800 .nr_regs = 0,
801 .value = 0,
802 .refcnt = &exynos_shared_retention_refcnt,
803 .init = exynos_retention_init,
804};
805
806static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = {
807 {
808 /* pin-controller instance 0 ALIVE data */
809 .pin_banks = exynosautov920_pin_banks0,
810 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0),
811 .eint_wkup_init = exynos_eint_wkup_init,
812 .suspend = exynos_pinctrl_suspend,
813 .resume = exynos_pinctrl_resume,
814 .retention_data = &exynosautov920_retention_data,
815 }, {
816 /* pin-controller instance 1 AUD data */
817 .pin_banks = exynosautov920_pin_banks1,
818 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks1),
819 }, {
820 /* pin-controller instance 2 HSI0 data */
821 .pin_banks = exynosautov920_pin_banks2,
822 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2),
823 .eint_gpio_init = exynos_eint_gpio_init,
824 .suspend = exynos_pinctrl_suspend,
825 .resume = exynos_pinctrl_resume,
826 }, {
827 /* pin-controller instance 3 HSI1 data */
828 .pin_banks = exynosautov920_pin_banks3,
829 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3),
830 .eint_gpio_init = exynos_eint_gpio_init,
831 .suspend = exynos_pinctrl_suspend,
832 .resume = exynos_pinctrl_resume,
833 }, {
834 /* pin-controller instance 4 HSI2 data */
835 .pin_banks = exynosautov920_pin_banks4,
836 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4),
837 .eint_gpio_init = exynos_eint_gpio_init,
838 .suspend = exynos_pinctrl_suspend,
839 .resume = exynos_pinctrl_resume,
840 }, {
841 /* pin-controller instance 5 HSI2UFS data */
842 .pin_banks = exynosautov920_pin_banks5,
843 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5),
844 .eint_gpio_init = exynos_eint_gpio_init,
845 .suspend = exynos_pinctrl_suspend,
846 .resume = exynos_pinctrl_resume,
847 }, {
848 /* pin-controller instance 6 PERIC0 data */
849 .pin_banks = exynosautov920_pin_banks6,
850 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6),
851 .eint_gpio_init = exynos_eint_gpio_init,
852 .suspend = exynos_pinctrl_suspend,
853 .resume = exynos_pinctrl_resume,
854 }, {
855 /* pin-controller instance 7 PERIC1 data */
856 .pin_banks = exynosautov920_pin_banks7,
857 .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7),
858 .eint_gpio_init = exynos_eint_gpio_init,
859 .suspend = exynos_pinctrl_suspend,
860 .resume = exynos_pinctrl_resume,
861 },
862};
863
864const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = {
865 .ctrl = exynosautov920_pin_ctrl,
866 .num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl),
867};
868
869/*
870 * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three
871 * gpio/pin-mux/pinconfig controllers.
872 */
873
874/* pin banks of FSD pin-controller 0 (FSYS) */
875static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = {
876 EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00),
877 EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04),
878 EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08),
879 EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c),
880 EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10),
881};
882
883/* pin banks of FSD pin-controller 1 (PERIC) */
884static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = {
885 EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00),
886 EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04),
887 EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08),
888 EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c),
889 EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10),
890 EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14),
891 EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18),
892 EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c),
893 EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20),
894 EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24),
895 EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28),
896 EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
897 EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30),
898 EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34),
899 EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38),
900 EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c),
901 EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
902 EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44),
903 EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48),
904 EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c),
905 EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50),
906};
907
908/* pin banks of FSD pin-controller 2 (PMU) */
909static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = {
910 EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"),
911};
912
913static const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = {
914 {
915 /* pin-controller instance 0 FSYS0 data */
916 .pin_banks = fsd_pin_banks0,
917 .nr_banks = ARRAY_SIZE(fsd_pin_banks0),
918 .eint_gpio_init = exynos_eint_gpio_init,
919 .suspend = exynos_pinctrl_suspend,
920 .resume = exynos_pinctrl_resume,
921 }, {
922 /* pin-controller instance 1 PERIC data */
923 .pin_banks = fsd_pin_banks1,
924 .nr_banks = ARRAY_SIZE(fsd_pin_banks1),
925 .eint_gpio_init = exynos_eint_gpio_init,
926 .suspend = exynos_pinctrl_suspend,
927 .resume = exynos_pinctrl_resume,
928 }, {
929 /* pin-controller instance 2 PMU data */
930 .pin_banks = fsd_pin_banks2,
931 .nr_banks = ARRAY_SIZE(fsd_pin_banks2),
932 },
933};
934
935const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
936 .ctrl = fsd_pin_ctrl,
937 .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl),
938};
939
940/* pin banks of gs101 pin-controller (ALIVE) */
941static const struct samsung_pin_bank_data gs101_pin_alive[] = {
942 EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00),
943 EXYNOS850_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04),
944 EXYNOS850_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08),
945 EXYNOS850_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c),
946 EXYNOS850_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10),
947 EXYNOS850_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14),
948 EXYNOS850_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18),
949 EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c),
950};
951
952/* pin banks of gs101 pin-controller (FAR_ALIVE) */
953static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
954 EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00),
955 EXYNOS850_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04),
956 EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08),
957 EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c),
958};
959
960/* pin banks of gs101 pin-controller (GSACORE) */
961static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
962 EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00),
963 EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04),
964 EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08),
965};
966
967/* pin banks of gs101 pin-controller (GSACTRL) */
968static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
969 EXYNOS850_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00),
970};
971
972/* pin banks of gs101 pin-controller (PERIC0) */
973static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
974 EXYNOS850_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00),
975 EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04),
976 EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08),
977 EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c),
978 EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10),
979 EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14),
980 EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18),
981 EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c),
982 EXYNOS850_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20),
983 EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24),
984 EXYNOS850_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28),
985 EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c),
986 EXYNOS850_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30),
987 EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34),
988 EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38),
989 EXYNOS850_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c),
990 EXYNOS850_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40),
991 EXYNOS850_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44),
992 EXYNOS850_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48),
993 EXYNOS850_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c),
994};
995
996/* pin banks of gs101 pin-controller (PERIC1) */
997static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
998 EXYNOS850_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00),
999 EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04),
1000 EXYNOS850_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08),
1001 EXYNOS850_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c),
1002 EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10),
1003 EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14),
1004 EXYNOS850_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18),
1005 EXYNOS850_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c),
1006};
1007
1008/* pin banks of gs101 pin-controller (HSI1) */
1009static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
1010 EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00),
1011 EXYNOS850_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04),
1012};
1013
1014/* pin banks of gs101 pin-controller (HSI2) */
1015static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
1016 EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00),
1017 EXYNOS850_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04),
1018 EXYNOS850_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08),
1019};
1020
1021static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
1022 {
1023 /* pin banks of gs101 pin-controller (ALIVE) */
1024 .pin_banks = gs101_pin_alive,
1025 .nr_banks = ARRAY_SIZE(gs101_pin_alive),
1026 .eint_wkup_init = exynos_eint_wkup_init,
1027 .suspend = exynos_pinctrl_suspend,
1028 .resume = exynos_pinctrl_resume,
1029 }, {
1030 /* pin banks of gs101 pin-controller (FAR_ALIVE) */
1031 .pin_banks = gs101_pin_far_alive,
1032 .nr_banks = ARRAY_SIZE(gs101_pin_far_alive),
1033 .eint_wkup_init = exynos_eint_wkup_init,
1034 .suspend = exynos_pinctrl_suspend,
1035 .resume = exynos_pinctrl_resume,
1036 }, {
1037 /* pin banks of gs101 pin-controller (GSACORE) */
1038 .pin_banks = gs101_pin_gsacore,
1039 .nr_banks = ARRAY_SIZE(gs101_pin_gsacore),
1040 }, {
1041 /* pin banks of gs101 pin-controller (GSACTRL) */
1042 .pin_banks = gs101_pin_gsactrl,
1043 .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl),
1044 }, {
1045 /* pin banks of gs101 pin-controller (PERIC0) */
1046 .pin_banks = gs101_pin_peric0,
1047 .nr_banks = ARRAY_SIZE(gs101_pin_peric0),
1048 .eint_gpio_init = exynos_eint_gpio_init,
1049 .suspend = exynos_pinctrl_suspend,
1050 .resume = exynos_pinctrl_resume,
1051 }, {
1052 /* pin banks of gs101 pin-controller (PERIC1) */
1053 .pin_banks = gs101_pin_peric1,
1054 .nr_banks = ARRAY_SIZE(gs101_pin_peric1),
1055 .eint_gpio_init = exynos_eint_gpio_init,
1056 .suspend = exynos_pinctrl_suspend,
1057 .resume = exynos_pinctrl_resume,
1058 }, {
1059 /* pin banks of gs101 pin-controller (HSI1) */
1060 .pin_banks = gs101_pin_hsi1,
1061 .nr_banks = ARRAY_SIZE(gs101_pin_hsi1),
1062 .eint_gpio_init = exynos_eint_gpio_init,
1063 .suspend = exynos_pinctrl_suspend,
1064 .resume = exynos_pinctrl_resume,
1065 }, {
1066 /* pin banks of gs101 pin-controller (HSI2) */
1067 .pin_banks = gs101_pin_hsi2,
1068 .nr_banks = ARRAY_SIZE(gs101_pin_hsi2),
1069 .eint_gpio_init = exynos_eint_gpio_init,
1070 .suspend = exynos_pinctrl_suspend,
1071 .resume = exynos_pinctrl_resume,
1072 },
1073};
1074
1075const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
1076 .ctrl = gs101_pin_ctrl,
1077 .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl),
1078};
1079

source code of linux/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c