1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Primary to Sideband (P2SB) bridge access support |
4 | * |
5 | * Copyright (c) 2017, 2021-2022 Intel Corporation. |
6 | * |
7 | * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
8 | * Jonathan Yong <jonathan.yong@intel.com> |
9 | */ |
10 | |
11 | #include <linux/bits.h> |
12 | #include <linux/export.h> |
13 | #include <linux/pci.h> |
14 | #include <linux/platform_data/x86/p2sb.h> |
15 | |
16 | #include <asm/cpu_device_id.h> |
17 | #include <asm/intel-family.h> |
18 | |
19 | #define P2SBC 0xe0 |
20 | #define P2SBC_HIDE BIT(8) |
21 | |
22 | #define P2SB_DEVFN_DEFAULT PCI_DEVFN(31, 1) |
23 | #define P2SB_DEVFN_GOLDMONT PCI_DEVFN(13, 0) |
24 | #define SPI_DEVFN_GOLDMONT PCI_DEVFN(13, 2) |
25 | |
26 | static const struct x86_cpu_id p2sb_cpu_ids[] = { |
27 | X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, P2SB_DEVFN_GOLDMONT), |
28 | {} |
29 | }; |
30 | |
31 | /* |
32 | * Cache BAR0 of P2SB device functions 0 to 7. |
33 | * TODO: The constant 8 is the number of functions that PCI specification |
34 | * defines. Same definitions exist tree-wide. Unify this definition and |
35 | * the other definitions then move to include/uapi/linux/pci.h. |
36 | */ |
37 | #define NR_P2SB_RES_CACHE 8 |
38 | |
39 | struct p2sb_res_cache { |
40 | u32 bus_dev_id; |
41 | struct resource res; |
42 | }; |
43 | |
44 | static struct p2sb_res_cache p2sb_resources[NR_P2SB_RES_CACHE]; |
45 | |
46 | static int p2sb_get_devfn(unsigned int *devfn) |
47 | { |
48 | unsigned int fn = P2SB_DEVFN_DEFAULT; |
49 | const struct x86_cpu_id *id; |
50 | |
51 | id = x86_match_cpu(match: p2sb_cpu_ids); |
52 | if (id) |
53 | fn = (unsigned int)id->driver_data; |
54 | |
55 | *devfn = fn; |
56 | return 0; |
57 | } |
58 | |
59 | static bool p2sb_valid_resource(struct resource *res) |
60 | { |
61 | if (res->flags) |
62 | return true; |
63 | |
64 | return false; |
65 | } |
66 | |
67 | /* Copy resource from the first BAR of the device in question */ |
68 | static void p2sb_read_bar0(struct pci_dev *pdev, struct resource *mem) |
69 | { |
70 | struct resource *bar0 = pci_resource_n(pdev, 0); |
71 | |
72 | /* Make sure we have no dangling pointers in the output */ |
73 | memset(mem, 0, sizeof(*mem)); |
74 | |
75 | /* |
76 | * We copy only selected fields from the original resource. |
77 | * Because a PCI device will be removed soon, we may not use |
78 | * any allocated data, hence we may not copy any pointers. |
79 | */ |
80 | mem->start = bar0->start; |
81 | mem->end = bar0->end; |
82 | mem->flags = bar0->flags; |
83 | mem->desc = bar0->desc; |
84 | } |
85 | |
86 | static void p2sb_scan_and_cache_devfn(struct pci_bus *bus, unsigned int devfn) |
87 | { |
88 | struct p2sb_res_cache *cache = &p2sb_resources[PCI_FUNC(devfn)]; |
89 | struct pci_dev *pdev; |
90 | |
91 | pdev = pci_scan_single_device(bus, devfn); |
92 | if (!pdev) |
93 | return; |
94 | |
95 | p2sb_read_bar0(pdev, mem: &cache->res); |
96 | cache->bus_dev_id = bus->dev.id; |
97 | |
98 | pci_stop_and_remove_bus_device(dev: pdev); |
99 | } |
100 | |
101 | static int p2sb_scan_and_cache(struct pci_bus *bus, unsigned int devfn) |
102 | { |
103 | /* Scan the P2SB device and cache its BAR0 */ |
104 | p2sb_scan_and_cache_devfn(bus, devfn); |
105 | |
106 | /* On Goldmont p2sb_bar() also gets called for the SPI controller */ |
107 | if (devfn == P2SB_DEVFN_GOLDMONT) |
108 | p2sb_scan_and_cache_devfn(bus, SPI_DEVFN_GOLDMONT); |
109 | |
110 | if (!p2sb_valid_resource(res: &p2sb_resources[PCI_FUNC(devfn)].res)) |
111 | return -ENOENT; |
112 | |
113 | return 0; |
114 | } |
115 | |
116 | static struct pci_bus *p2sb_get_bus(struct pci_bus *bus) |
117 | { |
118 | static struct pci_bus *p2sb_bus; |
119 | |
120 | bus = bus ?: p2sb_bus; |
121 | if (bus) |
122 | return bus; |
123 | |
124 | /* Assume P2SB is on the bus 0 in domain 0 */ |
125 | p2sb_bus = pci_find_bus(domain: 0, busnr: 0); |
126 | return p2sb_bus; |
127 | } |
128 | |
129 | static int p2sb_cache_resources(void) |
130 | { |
131 | unsigned int devfn_p2sb; |
132 | u32 value = P2SBC_HIDE; |
133 | struct pci_bus *bus; |
134 | u16 class; |
135 | int ret; |
136 | |
137 | /* Get devfn for P2SB device itself */ |
138 | ret = p2sb_get_devfn(devfn: &devfn_p2sb); |
139 | if (ret) |
140 | return ret; |
141 | |
142 | bus = p2sb_get_bus(NULL); |
143 | if (!bus) |
144 | return -ENODEV; |
145 | |
146 | /* |
147 | * When a device with same devfn exists and its device class is not |
148 | * PCI_CLASS_MEMORY_OTHER for P2SB, do not touch it. |
149 | */ |
150 | pci_bus_read_config_word(bus, devfn: devfn_p2sb, PCI_CLASS_DEVICE, val: &class); |
151 | if (!PCI_POSSIBLE_ERROR(class) && class != PCI_CLASS_MEMORY_OTHER) |
152 | return -ENODEV; |
153 | |
154 | /* |
155 | * Prevent concurrent PCI bus scan from seeing the P2SB device and |
156 | * removing via sysfs while it is temporarily exposed. |
157 | */ |
158 | pci_lock_rescan_remove(); |
159 | |
160 | /* |
161 | * The BIOS prevents the P2SB device from being enumerated by the PCI |
162 | * subsystem, so we need to unhide and hide it back to lookup the BAR. |
163 | * Unhide the P2SB device here, if needed. |
164 | */ |
165 | pci_bus_read_config_dword(bus, devfn: devfn_p2sb, P2SBC, val: &value); |
166 | if (value & P2SBC_HIDE) |
167 | pci_bus_write_config_dword(bus, devfn: devfn_p2sb, P2SBC, val: 0); |
168 | |
169 | ret = p2sb_scan_and_cache(bus, devfn: devfn_p2sb); |
170 | |
171 | /* Hide the P2SB device, if it was hidden */ |
172 | if (value & P2SBC_HIDE) |
173 | pci_bus_write_config_dword(bus, devfn: devfn_p2sb, P2SBC, P2SBC_HIDE); |
174 | |
175 | pci_unlock_rescan_remove(); |
176 | |
177 | return ret; |
178 | } |
179 | |
180 | /** |
181 | * p2sb_bar - Get Primary to Sideband (P2SB) bridge device BAR |
182 | * @bus: PCI bus to communicate with |
183 | * @devfn: PCI slot and function to communicate with |
184 | * @mem: memory resource to be filled in |
185 | * |
186 | * If @bus is NULL, the bus 0 in domain 0 will be used. |
187 | * If @devfn is 0, it will be replaced by devfn of the P2SB device. |
188 | * |
189 | * Caller must provide a valid pointer to @mem. |
190 | * |
191 | * Return: |
192 | * 0 on success or appropriate errno value on error. |
193 | */ |
194 | int p2sb_bar(struct pci_bus *bus, unsigned int devfn, struct resource *mem) |
195 | { |
196 | struct p2sb_res_cache *cache; |
197 | int ret; |
198 | |
199 | bus = p2sb_get_bus(bus); |
200 | if (!bus) |
201 | return -ENODEV; |
202 | |
203 | if (!devfn) { |
204 | ret = p2sb_get_devfn(devfn: &devfn); |
205 | if (ret) |
206 | return ret; |
207 | } |
208 | |
209 | cache = &p2sb_resources[PCI_FUNC(devfn)]; |
210 | if (cache->bus_dev_id != bus->dev.id) |
211 | return -ENODEV; |
212 | |
213 | if (!p2sb_valid_resource(res: &cache->res)) |
214 | return -ENOENT; |
215 | |
216 | memcpy(mem, &cache->res, sizeof(*mem)); |
217 | return 0; |
218 | } |
219 | EXPORT_SYMBOL_GPL(p2sb_bar); |
220 | |
221 | static int __init p2sb_fs_init(void) |
222 | { |
223 | p2sb_cache_resources(); |
224 | return 0; |
225 | } |
226 | |
227 | /* |
228 | * pci_rescan_remove_lock to avoid access to unhidden P2SB devices can |
229 | * not be locked in sysfs pci bus rescan path because of deadlock. To |
230 | * avoid the deadlock, access to P2SB devices with the lock at an early |
231 | * step in kernel initialization and cache required resources. This |
232 | * should happen after subsys_initcall which initializes PCI subsystem |
233 | * and before device_initcall which requires P2SB resources. |
234 | */ |
235 | fs_initcall(p2sb_fs_init); |
236 | |