1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Tsi721 PCIExpress-to-SRIO bridge definitions
4 *
5 * Copyright 2011, Integrated Device Technology, Inc.
6 */
7
8#ifndef __TSI721_H
9#define __TSI721_H
10
11/* Debug output filtering masks */
12enum {
13 DBG_NONE = 0,
14 DBG_INIT = BIT(0), /* driver init */
15 DBG_EXIT = BIT(1), /* driver exit */
16 DBG_MPORT = BIT(2), /* mport add/remove */
17 DBG_MAINT = BIT(3), /* maintenance ops messages */
18 DBG_DMA = BIT(4), /* DMA transfer messages */
19 DBG_DMAV = BIT(5), /* verbose DMA transfer messages */
20 DBG_IBW = BIT(6), /* inbound window */
21 DBG_EVENT = BIT(7), /* event handling messages */
22 DBG_OBW = BIT(8), /* outbound window messages */
23 DBG_DBELL = BIT(9), /* doorbell messages */
24 DBG_OMSG = BIT(10), /* doorbell messages */
25 DBG_IMSG = BIT(11), /* doorbell messages */
26 DBG_ALL = ~0,
27};
28
29#ifdef DEBUG
30extern u32 tsi_dbg_level;
31
32#define tsi_debug(level, dev, fmt, arg...) \
33 do { \
34 if (DBG_##level & tsi_dbg_level) \
35 dev_dbg(dev, "%s: " fmt "\n", __func__, ##arg); \
36 } while (0)
37#else
38#define tsi_debug(level, dev, fmt, arg...) \
39 no_printk(KERN_DEBUG "%s: " fmt "\n", __func__, ##arg)
40#endif
41
42#define tsi_info(dev, fmt, arg...) \
43 dev_info(dev, "%s: " fmt "\n", __func__, ##arg)
44
45#define tsi_warn(dev, fmt, arg...) \
46 dev_warn(dev, "%s: WARNING " fmt "\n", __func__, ##arg)
47
48#define tsi_err(dev, fmt, arg...) \
49 dev_err(dev, "%s: ERROR " fmt "\n", __func__, ##arg)
50
51#define DRV_NAME "tsi721"
52
53#define DEFAULT_HOPCOUNT 0xff
54#define DEFAULT_DESTID 0xff
55
56/* PCI device ID */
57#define PCI_DEVICE_ID_TSI721 0x80ab
58
59#define BAR_0 0
60#define BAR_1 1
61#define BAR_2 2
62#define BAR_4 4
63
64#define TSI721_PC2SR_BARS 2
65#define TSI721_PC2SR_WINS 8
66#define TSI721_PC2SR_ZONES 8
67#define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
68#define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
69#define IDB_QSIZE 512 /* Inbound Doorbell Queue size */
70
71/* Memory space sizes */
72#define TSI721_REG_SPACE_SIZE (512 * 1024) /* 512K */
73#define TSI721_DB_WIN_SIZE (16 * 1024 * 1024) /* 16MB */
74
75#define RIO_TT_CODE_8 0x00000000
76#define RIO_TT_CODE_16 0x00000001
77
78#define TSI721_DMA_MAXCH 8
79#define TSI721_DMA_MINSTSSZ 32
80#define TSI721_DMA_STSBLKSZ 8
81
82#define TSI721_SRIO_MAXCH 8
83
84#define DBELL_SID(buf) (((u8)buf[2] << 8) | (u8)buf[3])
85#define DBELL_TID(buf) (((u8)buf[4] << 8) | (u8)buf[5])
86#define DBELL_INF(buf) (((u8)buf[0] << 8) | (u8)buf[1])
87
88#define TSI721_RIO_PW_MSG_SIZE 16 /* Tsi721 saves only 16 bytes of PW msg */
89
90/* Register definitions */
91
92/*
93 * Registers in PCIe configuration space
94 */
95
96#define TSI721_PCIECFG_MSIXTBL 0x0a4
97#define TSI721_MSIXTBL_OFFSET 0x2c000
98#define TSI721_PCIECFG_MSIXPBA 0x0a8
99#define TSI721_MSIXPBA_OFFSET 0x2a000
100#define TSI721_PCIECFG_EPCTL 0x400
101
102/*
103 * Event Management Registers
104 */
105
106#define TSI721_RIO_EM_INT_STAT 0x10910
107#define TSI721_RIO_EM_INT_STAT_PW_RX 0x00010000
108
109#define TSI721_RIO_EM_INT_ENABLE 0x10914
110#define TSI721_RIO_EM_INT_ENABLE_PW_RX 0x00010000
111
112#define TSI721_RIO_EM_DEV_INT_EN 0x10930
113#define TSI721_RIO_EM_DEV_INT_EN_INT 0x00000001
114
115/*
116 * Port-Write Block Registers
117 */
118
119#define TSI721_RIO_PW_CTL 0x10a04
120#define TSI721_RIO_PW_CTL_PW_TIMER 0xf0000000
121#define TSI721_RIO_PW_CTL_PWT_DIS (0 << 28)
122#define TSI721_RIO_PW_CTL_PWT_103 (1 << 28)
123#define TSI721_RIO_PW_CTL_PWT_205 (1 << 29)
124#define TSI721_RIO_PW_CTL_PWT_410 (1 << 30)
125#define TSI721_RIO_PW_CTL_PWT_820 (1 << 31)
126#define TSI721_RIO_PW_CTL_PWC_MODE 0x01000000
127#define TSI721_RIO_PW_CTL_PWC_CONT 0x00000000
128#define TSI721_RIO_PW_CTL_PWC_REL 0x01000000
129
130#define TSI721_RIO_PW_RX_STAT 0x10a10
131#define TSI721_RIO_PW_RX_STAT_WR_SIZE 0x0000f000
132#define TSI_RIO_PW_RX_STAT_WDPTR 0x00000100
133#define TSI721_RIO_PW_RX_STAT_PW_SHORT 0x00000008
134#define TSI721_RIO_PW_RX_STAT_PW_TRUNC 0x00000004
135#define TSI721_RIO_PW_RX_STAT_PW_DISC 0x00000002
136#define TSI721_RIO_PW_RX_STAT_PW_VAL 0x00000001
137
138#define TSI721_RIO_PW_RX_CAPT(x) (0x10a20 + (x)*4)
139
140/*
141 * Inbound Doorbells
142 */
143
144#define TSI721_IDB_ENTRY_SIZE 64
145
146#define TSI721_IDQ_CTL(x) (0x20000 + (x) * 0x1000)
147#define TSI721_IDQ_SUSPEND 0x00000002
148#define TSI721_IDQ_INIT 0x00000001
149
150#define TSI721_IDQ_STS(x) (0x20004 + (x) * 0x1000)
151#define TSI721_IDQ_RUN 0x00200000
152
153#define TSI721_IDQ_MASK(x) (0x20008 + (x) * 0x1000)
154#define TSI721_IDQ_MASK_MASK 0xffff0000
155#define TSI721_IDQ_MASK_PATT 0x0000ffff
156
157#define TSI721_IDQ_RP(x) (0x2000c + (x) * 0x1000)
158#define TSI721_IDQ_RP_PTR 0x0007ffff
159
160#define TSI721_IDQ_WP(x) (0x20010 + (x) * 0x1000)
161#define TSI721_IDQ_WP_PTR 0x0007ffff
162
163#define TSI721_IDQ_BASEL(x) (0x20014 + (x) * 0x1000)
164#define TSI721_IDQ_BASEL_ADDR 0xffffffc0
165#define TSI721_IDQ_BASEU(x) (0x20018 + (x) * 0x1000)
166#define TSI721_IDQ_SIZE(x) (0x2001c + (x) * 0x1000)
167#define TSI721_IDQ_SIZE_VAL(size) (__fls(size) - 4)
168#define TSI721_IDQ_SIZE_MIN 512
169#define TSI721_IDQ_SIZE_MAX (512 * 1024)
170
171#define TSI721_SR_CHINT(x) (0x20040 + (x) * 0x1000)
172#define TSI721_SR_CHINTE(x) (0x20044 + (x) * 0x1000)
173#define TSI721_SR_CHINTSET(x) (0x20048 + (x) * 0x1000)
174#define TSI721_SR_CHINT_ODBOK 0x00000020
175#define TSI721_SR_CHINT_IDBQRCV 0x00000010
176#define TSI721_SR_CHINT_SUSP 0x00000008
177#define TSI721_SR_CHINT_ODBTO 0x00000004
178#define TSI721_SR_CHINT_ODBRTRY 0x00000002
179#define TSI721_SR_CHINT_ODBERR 0x00000001
180#define TSI721_SR_CHINT_ALL 0x0000003f
181
182#define TSI721_IBWIN_NUM 8
183
184#define TSI721_IBWIN_LB(x) (0x29000 + (x) * 0x20)
185#define TSI721_IBWIN_LB_BA 0xfffff000
186#define TSI721_IBWIN_LB_WEN 0x00000001
187
188#define TSI721_IBWIN_UB(x) (0x29004 + (x) * 0x20)
189#define TSI721_IBWIN_SZ(x) (0x29008 + (x) * 0x20)
190#define TSI721_IBWIN_SZ_SIZE 0x00001f00
191#define TSI721_IBWIN_SIZE(size) (__fls(size) - 12)
192
193#define TSI721_IBWIN_TLA(x) (0x2900c + (x) * 0x20)
194#define TSI721_IBWIN_TLA_ADD 0xfffff000
195#define TSI721_IBWIN_TUA(x) (0x29010 + (x) * 0x20)
196
197#define TSI721_SR2PC_GEN_INTE 0x29800
198#define TSI721_SR2PC_PWE 0x29804
199#define TSI721_SR2PC_GEN_INT 0x29808
200
201#define TSI721_DEV_INTE 0x29840
202#define TSI721_DEV_INT 0x29844
203#define TSI721_DEV_INTSET 0x29848
204#define TSI721_DEV_INT_BDMA_CH 0x00002000
205#define TSI721_DEV_INT_BDMA_NCH 0x00001000
206#define TSI721_DEV_INT_SMSG_CH 0x00000800
207#define TSI721_DEV_INT_SMSG_NCH 0x00000400
208#define TSI721_DEV_INT_SR2PC_CH 0x00000200
209#define TSI721_DEV_INT_SRIO 0x00000020
210
211#define TSI721_DEV_CHAN_INTE 0x2984c
212#define TSI721_DEV_CHAN_INT 0x29850
213
214#define TSI721_INT_SR2PC_CHAN_M 0xff000000
215#define TSI721_INT_SR2PC_CHAN(x) (1 << (24 + (x)))
216#define TSI721_INT_IMSG_CHAN_M 0x00ff0000
217#define TSI721_INT_IMSG_CHAN(x) (1 << (16 + (x)))
218#define TSI721_INT_OMSG_CHAN_M 0x0000ff00
219#define TSI721_INT_OMSG_CHAN(x) (1 << (8 + (x)))
220#define TSI721_INT_BDMA_CHAN_M 0x000000ff
221#define TSI721_INT_BDMA_CHAN(x) (1 << (x))
222
223/*
224 * PC2SR block registers
225 */
226#define TSI721_OBWIN_NUM TSI721_PC2SR_WINS
227
228#define TSI721_OBWINLB(x) (0x40000 + (x) * 0x20)
229#define TSI721_OBWINLB_BA 0xffff8000
230#define TSI721_OBWINLB_WEN 0x00000001
231
232#define TSI721_OBWINUB(x) (0x40004 + (x) * 0x20)
233
234#define TSI721_OBWINSZ(x) (0x40008 + (x) * 0x20)
235#define TSI721_OBWINSZ_SIZE 0x00001f00
236#define TSI721_OBWIN_SIZE(size) (__fls(size) - 15)
237
238#define TSI721_ZONE_SEL 0x41300
239#define TSI721_ZONE_SEL_RD_WRB 0x00020000
240#define TSI721_ZONE_SEL_GO 0x00010000
241#define TSI721_ZONE_SEL_WIN 0x00000038
242#define TSI721_ZONE_SEL_ZONE 0x00000007
243
244#define TSI721_LUT_DATA0 0x41304
245#define TSI721_LUT_DATA0_ADD 0xfffff000
246#define TSI721_LUT_DATA0_RDTYPE 0x00000f00
247#define TSI721_LUT_DATA0_NREAD 0x00000100
248#define TSI721_LUT_DATA0_MNTRD 0x00000200
249#define TSI721_LUT_DATA0_RDCRF 0x00000020
250#define TSI721_LUT_DATA0_WRCRF 0x00000010
251#define TSI721_LUT_DATA0_WRTYPE 0x0000000f
252#define TSI721_LUT_DATA0_NWR 0x00000001
253#define TSI721_LUT_DATA0_MNTWR 0x00000002
254#define TSI721_LUT_DATA0_NWR_R 0x00000004
255
256#define TSI721_LUT_DATA1 0x41308
257
258#define TSI721_LUT_DATA2 0x4130c
259#define TSI721_LUT_DATA2_HC 0xff000000
260#define TSI721_LUT_DATA2_ADD65 0x000c0000
261#define TSI721_LUT_DATA2_TT 0x00030000
262#define TSI721_LUT_DATA2_DSTID 0x0000ffff
263
264#define TSI721_PC2SR_INTE 0x41310
265
266#define TSI721_DEVCTL 0x48004
267#define TSI721_DEVCTL_SRBOOT_CMPL 0x00000004
268
269#define TSI721_I2C_INT_ENABLE 0x49120
270
271/*
272 * Block DMA Engine Registers
273 * x = 0..7
274 */
275
276#define TSI721_DMAC_BASE(x) (0x51000 + (x) * 0x1000)
277
278#define TSI721_DMAC_DWRCNT 0x000
279#define TSI721_DMAC_DRDCNT 0x004
280
281#define TSI721_DMAC_CTL 0x008
282#define TSI721_DMAC_CTL_SUSP 0x00000002
283#define TSI721_DMAC_CTL_INIT 0x00000001
284
285#define TSI721_DMAC_INT 0x00c
286#define TSI721_DMAC_INT_STFULL 0x00000010
287#define TSI721_DMAC_INT_DONE 0x00000008
288#define TSI721_DMAC_INT_SUSP 0x00000004
289#define TSI721_DMAC_INT_ERR 0x00000002
290#define TSI721_DMAC_INT_IOFDONE 0x00000001
291#define TSI721_DMAC_INT_ALL 0x0000001f
292
293#define TSI721_DMAC_INTSET 0x010
294
295#define TSI721_DMAC_STS 0x014
296#define TSI721_DMAC_STS_ABORT 0x00400000
297#define TSI721_DMAC_STS_RUN 0x00200000
298#define TSI721_DMAC_STS_CS 0x001f0000
299
300#define TSI721_DMAC_INTE 0x018
301
302#define TSI721_DMAC_DPTRL 0x024
303#define TSI721_DMAC_DPTRL_MASK 0xffffffe0
304
305#define TSI721_DMAC_DPTRH 0x028
306
307#define TSI721_DMAC_DSBL 0x02c
308#define TSI721_DMAC_DSBL_MASK 0xffffffc0
309
310#define TSI721_DMAC_DSBH 0x030
311
312#define TSI721_DMAC_DSSZ 0x034
313#define TSI721_DMAC_DSSZ_SIZE_M 0x0000000f
314#define TSI721_DMAC_DSSZ_SIZE(size) (__fls(size) - 4)
315
316#define TSI721_DMAC_DSRP 0x038
317#define TSI721_DMAC_DSRP_MASK 0x0007ffff
318
319#define TSI721_DMAC_DSWP 0x03c
320#define TSI721_DMAC_DSWP_MASK 0x0007ffff
321
322#define TSI721_BDMA_INTE 0x5f000
323
324/*
325 * Messaging definitions
326 */
327#define TSI721_MSG_BUFFER_SIZE RIO_MAX_MSG_SIZE
328#define TSI721_MSG_MAX_SIZE RIO_MAX_MSG_SIZE
329#define TSI721_IMSG_MAXCH 8
330#define TSI721_IMSG_CHNUM TSI721_IMSG_MAXCH
331#define TSI721_IMSGD_MIN_RING_SIZE 32
332#define TSI721_IMSGD_RING_SIZE 512
333
334#define TSI721_OMSG_CHNUM 4 /* One channel per MBOX */
335#define TSI721_OMSGD_MIN_RING_SIZE 32
336#define TSI721_OMSGD_RING_SIZE 512
337
338/*
339 * Outbound Messaging Engine Registers
340 * x = 0..7
341 */
342
343#define TSI721_OBDMAC_DWRCNT(x) (0x61000 + (x) * 0x1000)
344
345#define TSI721_OBDMAC_DRDCNT(x) (0x61004 + (x) * 0x1000)
346
347#define TSI721_OBDMAC_CTL(x) (0x61008 + (x) * 0x1000)
348#define TSI721_OBDMAC_CTL_MASK 0x00000007
349#define TSI721_OBDMAC_CTL_RETRY_THR 0x00000004
350#define TSI721_OBDMAC_CTL_SUSPEND 0x00000002
351#define TSI721_OBDMAC_CTL_INIT 0x00000001
352
353#define TSI721_OBDMAC_INT(x) (0x6100c + (x) * 0x1000)
354#define TSI721_OBDMAC_INTSET(x) (0x61010 + (x) * 0x1000)
355#define TSI721_OBDMAC_INTE(x) (0x61018 + (x) * 0x1000)
356#define TSI721_OBDMAC_INT_MASK 0x0000001F
357#define TSI721_OBDMAC_INT_ST_FULL 0x00000010
358#define TSI721_OBDMAC_INT_DONE 0x00000008
359#define TSI721_OBDMAC_INT_SUSPENDED 0x00000004
360#define TSI721_OBDMAC_INT_ERROR 0x00000002
361#define TSI721_OBDMAC_INT_IOF_DONE 0x00000001
362#define TSI721_OBDMAC_INT_ALL TSI721_OBDMAC_INT_MASK
363
364#define TSI721_OBDMAC_STS(x) (0x61014 + (x) * 0x1000)
365#define TSI721_OBDMAC_STS_MASK 0x007f0000
366#define TSI721_OBDMAC_STS_ABORT 0x00400000
367#define TSI721_OBDMAC_STS_RUN 0x00200000
368#define TSI721_OBDMAC_STS_CS 0x001f0000
369
370#define TSI721_OBDMAC_PWE(x) (0x6101c + (x) * 0x1000)
371#define TSI721_OBDMAC_PWE_MASK 0x00000002
372#define TSI721_OBDMAC_PWE_ERROR_EN 0x00000002
373
374#define TSI721_OBDMAC_DPTRL(x) (0x61020 + (x) * 0x1000)
375#define TSI721_OBDMAC_DPTRL_MASK 0xfffffff0
376
377#define TSI721_OBDMAC_DPTRH(x) (0x61024 + (x) * 0x1000)
378#define TSI721_OBDMAC_DPTRH_MASK 0xffffffff
379
380#define TSI721_OBDMAC_DSBL(x) (0x61040 + (x) * 0x1000)
381#define TSI721_OBDMAC_DSBL_MASK 0xffffffc0
382
383#define TSI721_OBDMAC_DSBH(x) (0x61044 + (x) * 0x1000)
384#define TSI721_OBDMAC_DSBH_MASK 0xffffffff
385
386#define TSI721_OBDMAC_DSSZ(x) (0x61048 + (x) * 0x1000)
387#define TSI721_OBDMAC_DSSZ_MASK 0x0000000f
388
389#define TSI721_OBDMAC_DSRP(x) (0x6104c + (x) * 0x1000)
390#define TSI721_OBDMAC_DSRP_MASK 0x0007ffff
391
392#define TSI721_OBDMAC_DSWP(x) (0x61050 + (x) * 0x1000)
393#define TSI721_OBDMAC_DSWP_MASK 0x0007ffff
394
395#define TSI721_RQRPTO 0x60010
396#define TSI721_RQRPTO_MASK 0x00ffffff
397#define TSI721_RQRPTO_VAL 400 /* Response TO value */
398
399/*
400 * Inbound Messaging Engine Registers
401 * x = 0..7
402 */
403
404#define TSI721_IB_DEVID_GLOBAL 0xffff
405#define TSI721_IBDMAC_FQBL(x) (0x61200 + (x) * 0x1000)
406#define TSI721_IBDMAC_FQBL_MASK 0xffffffc0
407
408#define TSI721_IBDMAC_FQBH(x) (0x61204 + (x) * 0x1000)
409#define TSI721_IBDMAC_FQBH_MASK 0xffffffff
410
411#define TSI721_IBDMAC_FQSZ_ENTRY_INX TSI721_IMSGD_RING_SIZE
412#define TSI721_IBDMAC_FQSZ(x) (0x61208 + (x) * 0x1000)
413#define TSI721_IBDMAC_FQSZ_MASK 0x0000000f
414
415#define TSI721_IBDMAC_FQRP(x) (0x6120c + (x) * 0x1000)
416#define TSI721_IBDMAC_FQRP_MASK 0x0007ffff
417
418#define TSI721_IBDMAC_FQWP(x) (0x61210 + (x) * 0x1000)
419#define TSI721_IBDMAC_FQWP_MASK 0x0007ffff
420
421#define TSI721_IBDMAC_FQTH(x) (0x61214 + (x) * 0x1000)
422#define TSI721_IBDMAC_FQTH_MASK 0x0007ffff
423
424#define TSI721_IB_DEVID 0x60020
425#define TSI721_IB_DEVID_MASK 0x0000ffff
426
427#define TSI721_IBDMAC_CTL(x) (0x61240 + (x) * 0x1000)
428#define TSI721_IBDMAC_CTL_MASK 0x00000003
429#define TSI721_IBDMAC_CTL_SUSPEND 0x00000002
430#define TSI721_IBDMAC_CTL_INIT 0x00000001
431
432#define TSI721_IBDMAC_STS(x) (0x61244 + (x) * 0x1000)
433#define TSI721_IBDMAC_STS_MASK 0x007f0000
434#define TSI721_IBSMAC_STS_ABORT 0x00400000
435#define TSI721_IBSMAC_STS_RUN 0x00200000
436#define TSI721_IBSMAC_STS_CS 0x001f0000
437
438#define TSI721_IBDMAC_INT(x) (0x61248 + (x) * 0x1000)
439#define TSI721_IBDMAC_INTSET(x) (0x6124c + (x) * 0x1000)
440#define TSI721_IBDMAC_INTE(x) (0x61250 + (x) * 0x1000)
441#define TSI721_IBDMAC_INT_MASK 0x0000100f
442#define TSI721_IBDMAC_INT_SRTO 0x00001000
443#define TSI721_IBDMAC_INT_SUSPENDED 0x00000008
444#define TSI721_IBDMAC_INT_PC_ERROR 0x00000004
445#define TSI721_IBDMAC_INT_FQ_LOW 0x00000002
446#define TSI721_IBDMAC_INT_DQ_RCV 0x00000001
447#define TSI721_IBDMAC_INT_ALL TSI721_IBDMAC_INT_MASK
448
449#define TSI721_IBDMAC_PWE(x) (0x61254 + (x) * 0x1000)
450#define TSI721_IBDMAC_PWE_MASK 0x00001700
451#define TSI721_IBDMAC_PWE_SRTO 0x00001000
452#define TSI721_IBDMAC_PWE_ILL_FMT 0x00000400
453#define TSI721_IBDMAC_PWE_ILL_DEC 0x00000200
454#define TSI721_IBDMAC_PWE_IMP_SP 0x00000100
455
456#define TSI721_IBDMAC_DQBL(x) (0x61300 + (x) * 0x1000)
457#define TSI721_IBDMAC_DQBL_MASK 0xffffffc0
458#define TSI721_IBDMAC_DQBL_ADDR 0xffffffc0
459
460#define TSI721_IBDMAC_DQBH(x) (0x61304 + (x) * 0x1000)
461#define TSI721_IBDMAC_DQBH_MASK 0xffffffff
462
463#define TSI721_IBDMAC_DQRP(x) (0x61308 + (x) * 0x1000)
464#define TSI721_IBDMAC_DQRP_MASK 0x0007ffff
465
466#define TSI721_IBDMAC_DQWR(x) (0x6130c + (x) * 0x1000)
467#define TSI721_IBDMAC_DQWR_MASK 0x0007ffff
468
469#define TSI721_IBDMAC_DQSZ(x) (0x61314 + (x) * 0x1000)
470#define TSI721_IBDMAC_DQSZ_MASK 0x0000000f
471
472/*
473 * Messaging Engine Interrupts
474 */
475
476#define TSI721_SMSG_PWE 0x6a004
477
478#define TSI721_SMSG_INTE 0x6a000
479#define TSI721_SMSG_INT 0x6a008
480#define TSI721_SMSG_INTSET 0x6a010
481#define TSI721_SMSG_INT_MASK 0x0086ffff
482#define TSI721_SMSG_INT_UNS_RSP 0x00800000
483#define TSI721_SMSG_INT_ECC_NCOR 0x00040000
484#define TSI721_SMSG_INT_ECC_COR 0x00020000
485#define TSI721_SMSG_INT_ECC_NCOR_CH 0x0000ff00
486#define TSI721_SMSG_INT_ECC_COR_CH 0x000000ff
487
488#define TSI721_SMSG_ECC_LOG 0x6a014
489#define TSI721_SMSG_ECC_LOG_MASK 0x00070007
490#define TSI721_SMSG_ECC_LOG_ECC_NCOR_M 0x00070000
491#define TSI721_SMSG_ECC_LOG_ECC_COR_M 0x00000007
492
493#define TSI721_RETRY_GEN_CNT 0x6a100
494#define TSI721_RETRY_GEN_CNT_MASK 0xffffffff
495
496#define TSI721_RETRY_RX_CNT 0x6a104
497#define TSI721_RETRY_RX_CNT_MASK 0xffffffff
498
499#define TSI721_SMSG_ECC_COR_LOG(x) (0x6a300 + (x) * 4)
500#define TSI721_SMSG_ECC_COR_LOG_MASK 0x000000ff
501
502#define TSI721_SMSG_ECC_NCOR(x) (0x6a340 + (x) * 4)
503#define TSI721_SMSG_ECC_NCOR_MASK 0x000000ff
504
505/*
506 * Block DMA Descriptors
507 */
508
509struct tsi721_dma_desc {
510 __le32 type_id;
511
512#define TSI721_DMAD_DEVID 0x0000ffff
513#define TSI721_DMAD_CRF 0x00010000
514#define TSI721_DMAD_PRIO 0x00060000
515#define TSI721_DMAD_RTYPE 0x00780000
516#define TSI721_DMAD_IOF 0x08000000
517#define TSI721_DMAD_DTYPE 0xe0000000
518
519 __le32 bcount;
520
521#define TSI721_DMAD_BCOUNT1 0x03ffffff /* if DTYPE == 1 */
522#define TSI721_DMAD_BCOUNT2 0x0000000f /* if DTYPE == 2 */
523#define TSI721_DMAD_TT 0x0c000000
524#define TSI721_DMAD_RADDR0 0xc0000000
525
526 union {
527 __le32 raddr_lo; /* if DTYPE == (1 || 2) */
528 __le32 next_lo; /* if DTYPE == 3 */
529 };
530
531#define TSI721_DMAD_CFGOFF 0x00ffffff
532#define TSI721_DMAD_HOPCNT 0xff000000
533
534 union {
535 __le32 raddr_hi; /* if DTYPE == (1 || 2) */
536 __le32 next_hi; /* if DTYPE == 3 */
537 };
538
539 union {
540 struct { /* if DTYPE == 1 */
541 __le32 bufptr_lo;
542 __le32 bufptr_hi;
543 __le32 s_dist;
544 __le32 s_size;
545 } t1;
546 __le32 data[4]; /* if DTYPE == 2 */
547 u32 reserved[4]; /* if DTYPE == 3 */
548 };
549} __aligned(32);
550
551/*
552 * Inbound Messaging Descriptor
553 */
554struct tsi721_imsg_desc {
555 __le32 type_id;
556
557#define TSI721_IMD_DEVID 0x0000ffff
558#define TSI721_IMD_CRF 0x00010000
559#define TSI721_IMD_PRIO 0x00060000
560#define TSI721_IMD_TT 0x00180000
561#define TSI721_IMD_DTYPE 0xe0000000
562
563 __le32 msg_info;
564
565#define TSI721_IMD_BCOUNT 0x00000ff8
566#define TSI721_IMD_SSIZE 0x0000f000
567#define TSI721_IMD_LETER 0x00030000
568#define TSI721_IMD_XMBOX 0x003c0000
569#define TSI721_IMD_MBOX 0x00c00000
570#define TSI721_IMD_CS 0x78000000
571#define TSI721_IMD_HO 0x80000000
572
573 __le32 bufptr_lo;
574 __le32 bufptr_hi;
575 u32 reserved[12];
576
577} __aligned(64);
578
579/*
580 * Outbound Messaging Descriptor
581 */
582struct tsi721_omsg_desc {
583 __le32 type_id;
584
585#define TSI721_OMD_DEVID 0x0000ffff
586#define TSI721_OMD_CRF 0x00010000
587#define TSI721_OMD_PRIO 0x00060000
588#define TSI721_OMD_IOF 0x08000000
589#define TSI721_OMD_DTYPE 0xe0000000
590#define TSI721_OMD_RSRVD 0x17f80000
591
592 __le32 msg_info;
593
594#define TSI721_OMD_BCOUNT 0x00000ff8
595#define TSI721_OMD_SSIZE 0x0000f000
596#define TSI721_OMD_LETER 0x00030000
597#define TSI721_OMD_XMBOX 0x003c0000
598#define TSI721_OMD_MBOX 0x00c00000
599#define TSI721_OMD_TT 0x0c000000
600
601 union {
602 __le32 bufptr_lo; /* if DTYPE == 4 */
603 __le32 next_lo; /* if DTYPE == 5 */
604 };
605
606 union {
607 __le32 bufptr_hi; /* if DTYPE == 4 */
608 __le32 next_hi; /* if DTYPE == 5 */
609 };
610
611} __aligned(16);
612
613struct tsi721_dma_sts {
614 __le64 desc_sts[8];
615} __aligned(64);
616
617struct tsi721_desc_sts_fifo {
618 union {
619 __le64 da64;
620 struct {
621 __le32 lo;
622 __le32 hi;
623 } da32;
624 } stat[8];
625} __aligned(64);
626
627/* Descriptor types for BDMA and Messaging blocks */
628enum dma_dtype {
629 DTYPE1 = 1, /* Data Transfer DMA Descriptor */
630 DTYPE2 = 2, /* Immediate Data Transfer DMA Descriptor */
631 DTYPE3 = 3, /* Block Pointer DMA Descriptor */
632 DTYPE4 = 4, /* Outbound Msg DMA Descriptor */
633 DTYPE5 = 5, /* OB Messaging Block Pointer Descriptor */
634 DTYPE6 = 6 /* Inbound Messaging Descriptor */
635};
636
637enum dma_rtype {
638 NREAD = 0,
639 LAST_NWRITE_R = 1,
640 ALL_NWRITE = 2,
641 ALL_NWRITE_R = 3,
642 MAINT_RD = 4,
643 MAINT_WR = 5
644};
645
646/*
647 * mport Driver Definitions
648 */
649#define TSI721_DMA_CHNUM TSI721_DMA_MAXCH
650
651#define TSI721_DMACH_MAINT 7 /* DMA channel for maint requests */
652#define TSI721_DMACH_MAINT_NBD 32 /* Number of BDs for maint requests */
653
654#define TSI721_DMACH_DMA 1 /* DMA channel for data transfers */
655
656#define MSG_DMA_ENTRY_INX_TO_SIZE(x) ((0x10 << (x)) & 0xFFFF0)
657
658enum tsi721_smsg_int_flag {
659 SMSG_INT_NONE = 0x00000000,
660 SMSG_INT_ECC_COR_CH = 0x000000ff,
661 SMSG_INT_ECC_NCOR_CH = 0x0000ff00,
662 SMSG_INT_ECC_COR = 0x00020000,
663 SMSG_INT_ECC_NCOR = 0x00040000,
664 SMSG_INT_UNS_RSP = 0x00800000,
665 SMSG_INT_ALL = 0x0006ffff
666};
667
668/* Structures */
669
670#ifdef CONFIG_RAPIDIO_DMA_ENGINE
671
672#define TSI721_BDMA_MAX_BCOUNT (TSI721_DMAD_BCOUNT1 + 1)
673
674struct tsi721_tx_desc {
675 struct dma_async_tx_descriptor txd;
676 u16 destid;
677 /* low 64-bits of 66-bit RIO address */
678 u64 rio_addr;
679 /* upper 2-bits of 66-bit RIO address */
680 u8 rio_addr_u;
681 enum dma_rtype rtype;
682 struct list_head desc_node;
683 struct scatterlist *sg;
684 unsigned int sg_len;
685 enum dma_status status;
686};
687
688struct tsi721_bdma_chan {
689 int id;
690 void __iomem *regs;
691 int bd_num; /* number of HW buffer descriptors */
692 void *bd_base; /* start of DMA descriptors */
693 dma_addr_t bd_phys;
694 void *sts_base; /* start of DMA BD status FIFO */
695 dma_addr_t sts_phys;
696 int sts_size;
697 u32 sts_rdptr;
698 u32 wr_count;
699 u32 wr_count_next;
700
701 struct dma_chan dchan;
702 struct tsi721_tx_desc *tx_desc;
703 spinlock_t lock;
704 struct tsi721_tx_desc *active_tx;
705 struct list_head queue;
706 struct list_head free_list;
707 struct tasklet_struct tasklet;
708 bool active;
709};
710
711#endif /* CONFIG_RAPIDIO_DMA_ENGINE */
712
713struct tsi721_bdma_maint {
714 int ch_id; /* BDMA channel number */
715 int bd_num; /* number of buffer descriptors */
716 void *bd_base; /* start of DMA descriptors */
717 dma_addr_t bd_phys;
718 void *sts_base; /* start of DMA BD status FIFO */
719 dma_addr_t sts_phys;
720 int sts_size;
721};
722
723struct tsi721_imsg_ring {
724 u32 size;
725 /* VA/PA of data buffers for incoming messages */
726 void *buf_base;
727 dma_addr_t buf_phys;
728 /* VA/PA of circular free buffer list */
729 void *imfq_base;
730 dma_addr_t imfq_phys;
731 /* VA/PA of Inbound message descriptors */
732 void *imd_base;
733 dma_addr_t imd_phys;
734 /* Inbound Queue buffer pointers */
735 void *imq_base[TSI721_IMSGD_RING_SIZE];
736
737 u32 rx_slot;
738 void *dev_id;
739 u32 fq_wrptr;
740 u32 desc_rdptr;
741 spinlock_t lock;
742};
743
744struct tsi721_omsg_ring {
745 u32 size;
746 /* VA/PA of OB Msg descriptors */
747 void *omd_base;
748 dma_addr_t omd_phys;
749 /* VA/PA of OB Msg data buffers */
750 void *omq_base[TSI721_OMSGD_RING_SIZE];
751 dma_addr_t omq_phys[TSI721_OMSGD_RING_SIZE];
752 /* VA/PA of OB Msg descriptor status FIFO */
753 void *sts_base;
754 dma_addr_t sts_phys;
755 u32 sts_size; /* # of allocated status entries */
756 u32 sts_rdptr;
757
758 u32 tx_slot;
759 void *dev_id;
760 u32 wr_count;
761 spinlock_t lock;
762};
763
764enum tsi721_flags {
765 TSI721_USING_MSI = (1 << 0),
766 TSI721_USING_MSIX = (1 << 1),
767 TSI721_IMSGID_SET = (1 << 2),
768};
769
770#ifdef CONFIG_PCI_MSI
771/*
772 * MSI-X Table Entries (0 ... 69)
773 */
774#define TSI721_MSIX_DMACH_DONE(x) (0 + (x))
775#define TSI721_MSIX_DMACH_INT(x) (8 + (x))
776#define TSI721_MSIX_BDMA_INT 16
777#define TSI721_MSIX_OMSG_DONE(x) (17 + (x))
778#define TSI721_MSIX_OMSG_INT(x) (25 + (x))
779#define TSI721_MSIX_IMSG_DQ_RCV(x) (33 + (x))
780#define TSI721_MSIX_IMSG_INT(x) (41 + (x))
781#define TSI721_MSIX_MSG_INT 49
782#define TSI721_MSIX_SR2PC_IDBQ_RCV(x) (50 + (x))
783#define TSI721_MSIX_SR2PC_CH_INT(x) (58 + (x))
784#define TSI721_MSIX_SR2PC_INT 66
785#define TSI721_MSIX_PC2SR_INT 67
786#define TSI721_MSIX_SRIO_MAC_INT 68
787#define TSI721_MSIX_I2C_INT 69
788
789/* MSI-X vector and init table entry indexes */
790enum tsi721_msix_vect {
791 TSI721_VECT_IDB,
792 TSI721_VECT_PWRX, /* PW_RX is part of SRIO MAC Interrupt reporting */
793 TSI721_VECT_OMB0_DONE,
794 TSI721_VECT_OMB1_DONE,
795 TSI721_VECT_OMB2_DONE,
796 TSI721_VECT_OMB3_DONE,
797 TSI721_VECT_OMB0_INT,
798 TSI721_VECT_OMB1_INT,
799 TSI721_VECT_OMB2_INT,
800 TSI721_VECT_OMB3_INT,
801 TSI721_VECT_IMB0_RCV,
802 TSI721_VECT_IMB1_RCV,
803 TSI721_VECT_IMB2_RCV,
804 TSI721_VECT_IMB3_RCV,
805 TSI721_VECT_IMB0_INT,
806 TSI721_VECT_IMB1_INT,
807 TSI721_VECT_IMB2_INT,
808 TSI721_VECT_IMB3_INT,
809#ifdef CONFIG_RAPIDIO_DMA_ENGINE
810 TSI721_VECT_DMA0_DONE,
811 TSI721_VECT_DMA1_DONE,
812 TSI721_VECT_DMA2_DONE,
813 TSI721_VECT_DMA3_DONE,
814 TSI721_VECT_DMA4_DONE,
815 TSI721_VECT_DMA5_DONE,
816 TSI721_VECT_DMA6_DONE,
817 TSI721_VECT_DMA7_DONE,
818 TSI721_VECT_DMA0_INT,
819 TSI721_VECT_DMA1_INT,
820 TSI721_VECT_DMA2_INT,
821 TSI721_VECT_DMA3_INT,
822 TSI721_VECT_DMA4_INT,
823 TSI721_VECT_DMA5_INT,
824 TSI721_VECT_DMA6_INT,
825 TSI721_VECT_DMA7_INT,
826#endif /* CONFIG_RAPIDIO_DMA_ENGINE */
827 TSI721_VECT_MAX
828};
829
830#define IRQ_DEVICE_NAME_MAX 64
831
832struct msix_irq {
833 u16 vector;
834 char irq_name[IRQ_DEVICE_NAME_MAX];
835};
836#endif /* CONFIG_PCI_MSI */
837
838struct tsi721_ib_win_mapping {
839 struct list_head node;
840 dma_addr_t lstart;
841};
842
843struct tsi721_ib_win {
844 u64 rstart;
845 u32 size;
846 dma_addr_t lstart;
847 bool active;
848 bool xlat;
849 struct list_head mappings;
850};
851
852struct tsi721_obw_bar {
853 u64 base;
854 u64 size;
855 u64 free;
856};
857
858struct tsi721_ob_win {
859 u64 base;
860 u32 size;
861 u16 destid;
862 u64 rstart;
863 bool active;
864 struct tsi721_obw_bar *pbar;
865};
866
867struct tsi721_device {
868 struct pci_dev *pdev;
869 struct rio_mport mport;
870 u32 flags;
871 void __iomem *regs;
872#ifdef CONFIG_PCI_MSI
873 struct msix_irq msix[TSI721_VECT_MAX];
874#endif
875 /* Doorbells */
876 void __iomem *odb_base;
877 void *idb_base;
878 dma_addr_t idb_dma;
879 struct work_struct idb_work;
880 u32 db_discard_count;
881
882 /* Inbound Port-Write */
883 struct work_struct pw_work;
884 struct kfifo pw_fifo;
885 spinlock_t pw_fifo_lock;
886 u32 pw_discard_count;
887
888 /* BDMA Engine */
889 struct tsi721_bdma_maint mdma; /* Maintenance rd/wr request channel */
890
891#ifdef CONFIG_RAPIDIO_DMA_ENGINE
892 struct tsi721_bdma_chan bdma[TSI721_DMA_CHNUM];
893#endif
894
895 /* Inbound Messaging */
896 int imsg_init[TSI721_IMSG_CHNUM];
897 struct tsi721_imsg_ring imsg_ring[TSI721_IMSG_CHNUM];
898
899 /* Outbound Messaging */
900 int omsg_init[TSI721_OMSG_CHNUM];
901 struct tsi721_omsg_ring omsg_ring[TSI721_OMSG_CHNUM];
902
903 /* Inbound Mapping Windows */
904 struct tsi721_ib_win ib_win[TSI721_IBWIN_NUM];
905 int ibwin_cnt;
906
907 /* Outbound Mapping Windows */
908 struct tsi721_obw_bar p2r_bar[2];
909 struct tsi721_ob_win ob_win[TSI721_OBWIN_NUM];
910 int obwin_cnt;
911};
912
913#ifdef CONFIG_RAPIDIO_DMA_ENGINE
914extern void tsi721_bdma_handler(struct tsi721_bdma_chan *bdma_chan);
915extern int tsi721_register_dma(struct tsi721_device *priv);
916extern void tsi721_unregister_dma(struct tsi721_device *priv);
917extern void tsi721_dma_stop_all(struct tsi721_device *priv);
918#else
919#define tsi721_dma_stop_all(priv) do {} while (0)
920#define tsi721_unregister_dma(priv) do {} while (0)
921#endif
922
923#endif
924

source code of linux/drivers/rapidio/devices/tsi721.h