1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (C) 2018 Intel Corporation */ |
3 | |
4 | #ifndef __IPU3_CSS_FW_H |
5 | #define __IPU3_CSS_FW_H |
6 | |
7 | /******************* Firmware file definitions *******************/ |
8 | |
9 | #define IMGU_FW_NAME "intel/ipu3-fw.bin" |
10 | #define IMGU_FW_NAME_20161208 \ |
11 | "intel/irci_irci_ecr-master_20161208_0213_20170112_1500.bin" |
12 | |
13 | typedef u32 imgu_fw_ptr; |
14 | |
15 | enum imgu_fw_type { |
16 | IMGU_FW_SP_FIRMWARE, /* Firmware for the SP */ |
17 | IMGU_FW_SP1_FIRMWARE, /* Firmware for the SP1 */ |
18 | IMGU_FW_ISP_FIRMWARE, /* Firmware for the ISP */ |
19 | IMGU_FW_BOOTLOADER_FIRMWARE, /* Firmware for the BootLoader */ |
20 | IMGU_FW_ACC_FIRMWARE /* Firmware for accelerations */ |
21 | }; |
22 | |
23 | enum imgu_fw_acc_type { |
24 | IMGU_FW_ACC_NONE, /* Normal binary */ |
25 | IMGU_FW_ACC_OUTPUT, /* Accelerator stage on output frame */ |
26 | IMGU_FW_ACC_VIEWFINDER, /* Accelerator stage on viewfinder frame */ |
27 | IMGU_FW_ACC_STANDALONE, /* Stand-alone acceleration */ |
28 | }; |
29 | |
30 | struct imgu_fw_isp_parameter { |
31 | u32 offset; /* Offset in isp_<mem> config, params, etc. */ |
32 | u32 size; /* Disabled if 0 */ |
33 | }; |
34 | |
35 | struct imgu_fw_param_memory_offsets { |
36 | struct { |
37 | struct imgu_fw_isp_parameter lin; /* lin_vmem_params */ |
38 | struct imgu_fw_isp_parameter tnr3; /* tnr3_vmem_params */ |
39 | struct imgu_fw_isp_parameter xnr3; /* xnr3_vmem_params */ |
40 | } vmem; |
41 | struct { |
42 | struct imgu_fw_isp_parameter tnr; |
43 | struct imgu_fw_isp_parameter tnr3; /* tnr3_params */ |
44 | struct imgu_fw_isp_parameter xnr3; /* xnr3_params */ |
45 | struct imgu_fw_isp_parameter plane_io_config; /* 192 bytes */ |
46 | struct imgu_fw_isp_parameter rgbir; /* rgbir_params */ |
47 | } dmem; |
48 | }; |
49 | |
50 | struct imgu_fw_config_memory_offsets { |
51 | struct { |
52 | struct imgu_fw_isp_parameter iterator; |
53 | struct imgu_fw_isp_parameter dvs; |
54 | struct imgu_fw_isp_parameter output; |
55 | struct imgu_fw_isp_parameter raw; |
56 | struct imgu_fw_isp_parameter input_yuv; |
57 | struct imgu_fw_isp_parameter tnr; |
58 | struct imgu_fw_isp_parameter tnr3; |
59 | struct imgu_fw_isp_parameter ref; |
60 | } dmem; |
61 | }; |
62 | |
63 | struct imgu_fw_state_memory_offsets { |
64 | struct { |
65 | struct imgu_fw_isp_parameter tnr; |
66 | struct imgu_fw_isp_parameter tnr3; |
67 | struct imgu_fw_isp_parameter ref; |
68 | } dmem; |
69 | }; |
70 | |
71 | union imgu_fw_all_memory_offsets { |
72 | struct { |
73 | u64 imgu_fw_mem_offsets[3]; /* params, config, state */ |
74 | } offsets; |
75 | struct { |
76 | u64 ptr; |
77 | } array[IMGU_ABI_PARAM_CLASS_NUM]; |
78 | }; |
79 | |
80 | struct imgu_fw_binary_xinfo { |
81 | /* Part that is of interest to the SP. */ |
82 | struct imgu_abi_binary_info sp; |
83 | |
84 | /* Rest of the binary info, only interesting to the host. */ |
85 | u32 type; /* enum imgu_fw_acc_type */ |
86 | |
87 | u32 num_output_formats __aligned(8); |
88 | u32 output_formats[IMGU_ABI_FRAME_FORMAT_NUM]; /* enum frame_format */ |
89 | |
90 | /* number of supported vf formats */ |
91 | u32 num_vf_formats __aligned(8); |
92 | /* types of supported vf formats */ |
93 | u32 vf_formats[IMGU_ABI_FRAME_FORMAT_NUM]; /* enum frame_format */ |
94 | u8 num_output_pins; |
95 | imgu_fw_ptr xmem_addr; |
96 | |
97 | u64 imgu_fw_blob_descr_ptr __aligned(8); |
98 | u32 blob_index __aligned(8); |
99 | union imgu_fw_all_memory_offsets mem_offsets __aligned(8); |
100 | struct imgu_fw_binary_xinfo *next __aligned(8); |
101 | }; |
102 | |
103 | struct imgu_fw_sp_info { |
104 | u32 init_dmem_data; /* data sect config, stored to dmem */ |
105 | u32 per_frame_data; /* Per frame data, stored to dmem */ |
106 | u32 group; /* Per pipeline data, loaded by dma */ |
107 | u32 output; /* SP output data, loaded by dmem */ |
108 | u32 host_sp_queue; /* Host <-> SP queues */ |
109 | u32 host_sp_com; /* Host <-> SP commands */ |
110 | u32 isp_started; /* P'ed from sensor thread, csim only */ |
111 | u32 sw_state; /* Polled from css, enum imgu_abi_sp_swstate */ |
112 | u32 host_sp_queues_initialized; /* Polled from the SP */ |
113 | u32 sleep_mode; /* different mode to halt SP */ |
114 | u32 invalidate_tlb; /* inform SP to invalidate mmu TLB */ |
115 | u32 debug_buffer_ddr_address; /* the addr of DDR debug queue */ |
116 | |
117 | /* input system perf count array */ |
118 | u32 perf_counter_input_system_error; |
119 | u32 threads_stack; /* sp thread's stack pointers */ |
120 | u32 threads_stack_size; /* sp thread's stack sizes */ |
121 | u32 curr_binary_id; /* current binary id */ |
122 | u32 raw_copy_line_count; /* raw copy line counter */ |
123 | u32 ddr_parameter_address; /* acc param ddrptr, sp dmem */ |
124 | u32 ddr_parameter_size; /* acc param size, sp dmem */ |
125 | /* Entry functions */ |
126 | u32 sp_entry; /* The SP entry function */ |
127 | u32 tagger_frames_addr; /* Base address of tagger state */ |
128 | }; |
129 | |
130 | struct imgu_fw_bl_info { |
131 | u32 num_dma_cmds; /* Number of cmds sent by CSS */ |
132 | u32 dma_cmd_list; /* Dma command list sent by CSS */ |
133 | u32 sw_state; /* Polled from css, enum imgu_abi_bl_swstate */ |
134 | /* Entry functions */ |
135 | u32 bl_entry; /* The SP entry function */ |
136 | }; |
137 | |
138 | struct imgu_fw_acc_info { |
139 | u32 per_frame_data; /* Dummy for now */ |
140 | }; |
141 | |
142 | union imgu_fw_union { |
143 | struct imgu_fw_binary_xinfo isp; /* ISP info */ |
144 | struct imgu_fw_sp_info sp; /* SP info */ |
145 | struct imgu_fw_sp_info sp1; /* SP1 info */ |
146 | struct imgu_fw_bl_info bl; /* Bootloader info */ |
147 | struct imgu_fw_acc_info acc; /* Accelerator info */ |
148 | }; |
149 | |
150 | struct imgu_fw_info { |
151 | size_t ; /* size of fw header */ |
152 | u32 type __aligned(8); /* enum imgu_fw_type */ |
153 | |
154 | union imgu_fw_union info; /* Binary info */ |
155 | struct imgu_abi_blob_info blob; /* Blob info */ |
156 | /* Dynamic part */ |
157 | u64 next; |
158 | |
159 | u32 loaded __aligned(8); /* Firmware has been loaded */ |
160 | const u64 isp_code __aligned(8); /* ISP pointer to code */ |
161 | /* Firmware handle between user space and kernel */ |
162 | u32 handle __aligned(8); |
163 | /* Sections to copy from/to ISP */ |
164 | struct imgu_abi_isp_param_segments mem_initializers; |
165 | /* Initializer for local ISP memories */ |
166 | }; |
167 | |
168 | struct imgu_fw_bi_file_h { |
169 | char version[64]; /* branch tag + week day + time */ |
170 | int binary_nr; /* Number of binaries */ |
171 | unsigned int h_size; /* sizeof(struct imgu_fw_bi_file_h) */ |
172 | }; |
173 | |
174 | struct { |
175 | struct imgu_fw_bi_file_h ; |
176 | struct imgu_fw_info []; /* binary_nr items */ |
177 | }; |
178 | |
179 | /******************* Firmware functions *******************/ |
180 | |
181 | int imgu_css_fw_init(struct imgu_css *css); |
182 | void imgu_css_fw_cleanup(struct imgu_css *css); |
183 | |
184 | unsigned int imgu_css_fw_obgrid_size(const struct imgu_fw_info *bi); |
185 | void *imgu_css_fw_pipeline_params(struct imgu_css *css, unsigned int pipe, |
186 | enum imgu_abi_param_class cls, |
187 | enum imgu_abi_memories mem, |
188 | struct imgu_fw_isp_parameter *par, |
189 | size_t par_size, void *binary_params); |
190 | |
191 | #endif |
192 | |