1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (C) 2018 Intel Corporation */ |
3 | |
4 | #ifndef __IPU3_CSS_H |
5 | #define __IPU3_CSS_H |
6 | |
7 | #include <linux/videodev2.h> |
8 | #include <linux/types.h> |
9 | |
10 | #include "ipu3-abi.h" |
11 | #include "ipu3-css-pool.h" |
12 | |
13 | /* 2 stages for split isp pipeline, 1 for scaling */ |
14 | #define IMGU_NUM_SP 2 |
15 | #define IMGU_MAX_PIPELINE_NUM 20 |
16 | #define IMGU_MAX_PIPE_NUM 2 |
17 | |
18 | /* For DVS etc., format FRAME_FMT_YUV420_16 */ |
19 | #define IPU3_CSS_AUX_FRAME_REF 0 |
20 | /* For temporal noise reduction DVS etc., format FRAME_FMT_YUV_LINE */ |
21 | #define IPU3_CSS_AUX_FRAME_TNR 1 |
22 | #define IPU3_CSS_AUX_FRAME_TYPES 2 /* REF and TNR */ |
23 | #define IPU3_CSS_AUX_FRAMES 2 /* 2 for REF and 2 for TNR */ |
24 | |
25 | #define IPU3_CSS_QUEUE_IN 0 |
26 | #define IPU3_CSS_QUEUE_PARAMS 1 |
27 | #define IPU3_CSS_QUEUE_OUT 2 |
28 | #define IPU3_CSS_QUEUE_VF 3 |
29 | #define IPU3_CSS_QUEUE_STAT_3A 4 |
30 | #define IPU3_CSS_QUEUES 5 |
31 | |
32 | #define IPU3_CSS_RECT_EFFECTIVE 0 /* Effective resolution */ |
33 | #define IPU3_CSS_RECT_BDS 1 /* Resolution after BDS */ |
34 | #define IPU3_CSS_RECT_ENVELOPE 2 /* DVS envelope size */ |
35 | #define IPU3_CSS_RECT_GDC 3 /* gdc output res */ |
36 | #define IPU3_CSS_RECTS 4 /* number of rects */ |
37 | |
38 | #define IA_CSS_BINARY_MODE_PRIMARY 2 |
39 | #define IA_CSS_BINARY_MODE_VIDEO 3 |
40 | #define IPU3_CSS_DEFAULT_BINARY 3 /* default binary index */ |
41 | |
42 | /* |
43 | * The pipe id type, distinguishes the kind of pipes that |
44 | * can be run in parallel. |
45 | */ |
46 | enum imgu_css_pipe_id { |
47 | IPU3_CSS_PIPE_ID_PREVIEW, |
48 | IPU3_CSS_PIPE_ID_COPY, |
49 | IPU3_CSS_PIPE_ID_VIDEO, |
50 | IPU3_CSS_PIPE_ID_CAPTURE, |
51 | IPU3_CSS_PIPE_ID_YUVPP, |
52 | IPU3_CSS_PIPE_ID_ACC, |
53 | IPU3_CSS_PIPE_ID_NUM |
54 | }; |
55 | |
56 | struct imgu_css_resolution { |
57 | u32 w; |
58 | u32 h; |
59 | }; |
60 | |
61 | enum imgu_css_buffer_state { |
62 | IPU3_CSS_BUFFER_NEW, /* Not yet queued */ |
63 | IPU3_CSS_BUFFER_QUEUED, /* Queued, waiting to be filled */ |
64 | IPU3_CSS_BUFFER_DONE, /* Finished processing, removed from queue */ |
65 | IPU3_CSS_BUFFER_FAILED, /* Was not processed, removed from queue */ |
66 | }; |
67 | |
68 | struct imgu_css_buffer { |
69 | /* Private fields: user doesn't touch */ |
70 | dma_addr_t daddr; |
71 | unsigned int queue; |
72 | enum imgu_css_buffer_state state; |
73 | struct list_head list; |
74 | u8 queue_pos; |
75 | unsigned int pipe; |
76 | }; |
77 | |
78 | struct imgu_css_format { |
79 | u32 pixelformat; |
80 | enum v4l2_colorspace colorspace; |
81 | enum imgu_abi_frame_format frame_format; |
82 | enum imgu_abi_bayer_order bayer_order; |
83 | enum imgu_abi_osys_format osys_format; |
84 | enum imgu_abi_osys_tiling osys_tiling; |
85 | u8 bit_depth; /* Effective bits per pixel */ |
86 | u8 chroma_decim; /* Chroma plane decimation, 0=no chroma plane */ |
87 | u8 width_align; /* Alignment requirement for width_pad */ |
88 | u8 flags; |
89 | }; |
90 | |
91 | struct imgu_css_queue { |
92 | union { |
93 | struct v4l2_pix_format_mplane mpix; |
94 | struct v4l2_meta_format meta; |
95 | |
96 | } fmt; |
97 | const struct imgu_css_format *css_fmt; |
98 | unsigned int width_pad; |
99 | struct list_head bufs; |
100 | }; |
101 | |
102 | struct imgu_css_pipe { |
103 | enum imgu_css_pipe_id pipe_id; |
104 | unsigned int bindex; |
105 | |
106 | struct imgu_css_queue queue[IPU3_CSS_QUEUES]; |
107 | struct v4l2_rect rect[IPU3_CSS_RECTS]; |
108 | |
109 | bool vf_output_en; |
110 | /* Protect access to queue[IPU3_CSS_QUEUES] */ |
111 | spinlock_t qlock; |
112 | |
113 | /* Data structures shared with IMGU and driver, always allocated */ |
114 | struct imgu_css_map sp_ddr_ptrs; |
115 | struct imgu_css_map xmem_sp_stage_ptrs[IPU3_CSS_PIPE_ID_NUM] |
116 | [IMGU_ABI_MAX_STAGES]; |
117 | struct imgu_css_map xmem_isp_stage_ptrs[IPU3_CSS_PIPE_ID_NUM] |
118 | [IMGU_ABI_MAX_STAGES]; |
119 | |
120 | /* |
121 | * Data structures shared with IMGU and driver, binary specific. |
122 | * PARAM_CLASS_CONFIG and PARAM_CLASS_STATE parameters. |
123 | */ |
124 | struct imgu_css_map binary_params_cs[IMGU_ABI_PARAM_CLASS_NUM - 1] |
125 | [IMGU_ABI_NUM_MEMORIES]; |
126 | |
127 | struct { |
128 | struct imgu_css_map mem[IPU3_CSS_AUX_FRAMES]; |
129 | unsigned int width; |
130 | unsigned int height; |
131 | unsigned int bytesperline; |
132 | unsigned int bytesperpixel; |
133 | } aux_frames[IPU3_CSS_AUX_FRAME_TYPES]; |
134 | |
135 | struct { |
136 | struct imgu_css_pool parameter_set_info; |
137 | struct imgu_css_pool acc; |
138 | struct imgu_css_pool gdc; |
139 | struct imgu_css_pool obgrid; |
140 | /* PARAM_CLASS_PARAM parameters for binding while streaming */ |
141 | struct imgu_css_pool binary_params_p[IMGU_ABI_NUM_MEMORIES]; |
142 | } pool; |
143 | |
144 | struct imgu_css_map abi_buffers[IPU3_CSS_QUEUES] |
145 | [IMGU_ABI_HOST2SP_BUFQ_SIZE]; |
146 | }; |
147 | |
148 | /* IPU3 Camera Sub System structure */ |
149 | struct imgu_css { |
150 | struct device *dev; |
151 | void __iomem *base; |
152 | const struct firmware *fw; |
153 | struct imgu_fw_header *fwp; |
154 | int iomem_length; |
155 | int fw_bl, fw_sp[IMGU_NUM_SP]; /* Indices of bl and SP binaries */ |
156 | struct imgu_css_map *binary; /* fw binaries mapped to device */ |
157 | bool streaming; /* true when streaming is enabled */ |
158 | |
159 | struct imgu_css_pipe pipes[IMGU_MAX_PIPE_NUM]; |
160 | struct imgu_css_map xmem_sp_group_ptrs; |
161 | |
162 | /* enabled pipe(s) */ |
163 | DECLARE_BITMAP(enabled_pipes, IMGU_MAX_PIPE_NUM); |
164 | }; |
165 | |
166 | /******************* css v4l *******************/ |
167 | int imgu_css_init(struct device *dev, struct imgu_css *css, |
168 | void __iomem *base, int length); |
169 | void imgu_css_cleanup(struct imgu_css *css); |
170 | int imgu_css_fmt_try(struct imgu_css *css, |
171 | struct v4l2_pix_format_mplane *fmts[IPU3_CSS_QUEUES], |
172 | struct v4l2_rect *rects[IPU3_CSS_RECTS], |
173 | unsigned int pipe); |
174 | int imgu_css_fmt_set(struct imgu_css *css, |
175 | struct v4l2_pix_format_mplane *fmts[IPU3_CSS_QUEUES], |
176 | struct v4l2_rect *rects[IPU3_CSS_RECTS], |
177 | unsigned int pipe); |
178 | int imgu_css_meta_fmt_set(struct v4l2_meta_format *fmt); |
179 | int imgu_css_buf_queue(struct imgu_css *css, unsigned int pipe, |
180 | struct imgu_css_buffer *b); |
181 | struct imgu_css_buffer *imgu_css_buf_dequeue(struct imgu_css *css); |
182 | int imgu_css_start_streaming(struct imgu_css *css); |
183 | void imgu_css_stop_streaming(struct imgu_css *css); |
184 | bool imgu_css_queue_empty(struct imgu_css *css); |
185 | bool imgu_css_is_streaming(struct imgu_css *css); |
186 | bool imgu_css_pipe_queue_empty(struct imgu_css *css, unsigned int pipe); |
187 | |
188 | /******************* css hw *******************/ |
189 | int imgu_css_set_powerup(struct device *dev, void __iomem *base, |
190 | unsigned int freq); |
191 | void imgu_css_set_powerdown(struct device *dev, void __iomem *base); |
192 | int imgu_css_irq_ack(struct imgu_css *css); |
193 | |
194 | /******************* set parameters ************/ |
195 | int imgu_css_set_parameters(struct imgu_css *css, unsigned int pipe, |
196 | struct ipu3_uapi_params *set_params); |
197 | |
198 | /******************* auxiliary helpers *******************/ |
199 | static inline enum imgu_css_buffer_state |
200 | imgu_css_buf_state(struct imgu_css_buffer *b) |
201 | { |
202 | return b->state; |
203 | } |
204 | |
205 | /* Initialize given buffer. May be called several times. */ |
206 | static inline void imgu_css_buf_init(struct imgu_css_buffer *b, |
207 | unsigned int queue, dma_addr_t daddr) |
208 | { |
209 | b->state = IPU3_CSS_BUFFER_NEW; |
210 | b->queue = queue; |
211 | b->daddr = daddr; |
212 | } |
213 | #endif |
214 | |