1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Enhanced Host Controller Interface (EHCI) driver for USB.
4 *
5 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 *
7 * Copyright (c) 2000-2004 by David Brownell
8 */
9
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/dmapool.h>
13#include <linux/kernel.h>
14#include <linux/delay.h>
15#include <linux/ioport.h>
16#include <linux/sched.h>
17#include <linux/vmalloc.h>
18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/hrtimer.h>
21#include <linux/list.h>
22#include <linux/interrupt.h>
23#include <linux/usb.h>
24#include <linux/usb/hcd.h>
25#include <linux/usb/otg.h>
26#include <linux/moduleparam.h>
27#include <linux/dma-mapping.h>
28#include <linux/debugfs.h>
29#include <linux/platform_device.h>
30#include <linux/slab.h>
31
32#include <asm/byteorder.h>
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/unaligned.h>
36
37#if defined(CONFIG_PPC_PS3)
38#include <asm/firmware.h>
39#endif
40
41/*-------------------------------------------------------------------------*/
42
43/*
44 * EHCI hc_driver implementation ... experimental, incomplete.
45 * Based on the final 1.0 register interface specification.
46 *
47 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
48 * First was PCMCIA, like ISA; then CardBus, which is PCI.
49 * Next comes "CardBay", using USB 2.0 signals.
50 *
51 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
52 * Special thanks to Intel and VIA for providing host controllers to
53 * test this driver on, and Cypress (including In-System Design) for
54 * providing early devices for those host controllers to talk to!
55 */
56
57#define DRIVER_AUTHOR "David Brownell"
58#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
59
60static const char hcd_name [] = "ehci_hcd";
61
62
63#undef EHCI_URB_TRACE
64
65/* magic numbers that can affect system performance */
66#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
67#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
68#define EHCI_TUNE_RL_TT 0
69#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
70#define EHCI_TUNE_MULT_TT 1
71/*
72 * Some drivers think it's safe to schedule isochronous transfers more than
73 * 256 ms into the future (partly as a result of an old bug in the scheduling
74 * code). In an attempt to avoid trouble, we will use a minimum scheduling
75 * length of 512 frames instead of 256.
76 */
77#define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
78
79/* Initial IRQ latency: faster than hw default */
80static int log2_irq_thresh; // 0 to 6
81module_param (log2_irq_thresh, int, S_IRUGO);
82MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
83
84/* initial park setting: slower than hw default */
85static unsigned park;
86module_param (park, uint, S_IRUGO);
87MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
88
89/* for flakey hardware, ignore overcurrent indicators */
90static bool ignore_oc;
91module_param (ignore_oc, bool, S_IRUGO);
92MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
93
94#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
95
96/*-------------------------------------------------------------------------*/
97
98#include "ehci.h"
99#include "pci-quirks.h"
100
101static void compute_tt_budget(u8 budget_table[EHCI_BANDWIDTH_SIZE],
102 struct ehci_tt *tt);
103
104/*
105 * The MosChip MCS9990 controller updates its microframe counter
106 * a little before the frame counter, and occasionally we will read
107 * the invalid intermediate value. Avoid problems by checking the
108 * microframe number (the low-order 3 bits); if they are 0 then
109 * re-read the register to get the correct value.
110 */
111static unsigned ehci_moschip_read_frame_index(struct ehci_hcd *ehci)
112{
113 unsigned uf;
114
115 uf = ehci_readl(ehci, regs: &ehci->regs->frame_index);
116 if (unlikely((uf & 7) == 0))
117 uf = ehci_readl(ehci, regs: &ehci->regs->frame_index);
118 return uf;
119}
120
121static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
122{
123 if (ehci->frame_index_bug)
124 return ehci_moschip_read_frame_index(ehci);
125 return ehci_readl(ehci, regs: &ehci->regs->frame_index);
126}
127
128#include "ehci-dbg.c"
129
130/*-------------------------------------------------------------------------*/
131
132/*
133 * ehci_handshake - spin reading hc until handshake completes or fails
134 * @ptr: address of hc register to be read
135 * @mask: bits to look at in result of read
136 * @done: value of those bits when handshake succeeds
137 * @usec: timeout in microseconds
138 *
139 * Returns negative errno, or zero on success
140 *
141 * Success happens when the "mask" bits have the specified value (hardware
142 * handshake done). There are two failure modes: "usec" have passed (major
143 * hardware flakeout), or the register reads as all-ones (hardware removed).
144 *
145 * That last failure should_only happen in cases like physical cardbus eject
146 * before driver shutdown. But it also seems to be caused by bugs in cardbus
147 * bridge shutdown: shutting down the bridge before the devices using it.
148 */
149int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
150 u32 mask, u32 done, int usec)
151{
152 u32 result;
153
154 do {
155 result = ehci_readl(ehci, regs: ptr);
156 if (result == ~(u32)0) /* card removed */
157 return -ENODEV;
158 result &= mask;
159 if (result == done)
160 return 0;
161 udelay (1);
162 usec--;
163 } while (usec > 0);
164 return -ETIMEDOUT;
165}
166EXPORT_SYMBOL_GPL(ehci_handshake);
167
168/* check TDI/ARC silicon is in host mode */
169static int tdi_in_host_mode (struct ehci_hcd *ehci)
170{
171 u32 tmp;
172
173 tmp = ehci_readl(ehci, regs: &ehci->regs->usbmode);
174 return (tmp & 3) == USBMODE_CM_HC;
175}
176
177/*
178 * Force HC to halt state from unknown (EHCI spec section 2.3).
179 * Must be called with interrupts enabled and the lock not held.
180 */
181static int ehci_halt (struct ehci_hcd *ehci)
182{
183 u32 temp;
184
185 spin_lock_irq(lock: &ehci->lock);
186
187 /* disable any irqs left enabled by previous code */
188 ehci_writel(ehci, val: 0, regs: &ehci->regs->intr_enable);
189
190 if (ehci_is_TDI(ehci) && !tdi_in_host_mode(ehci)) {
191 spin_unlock_irq(lock: &ehci->lock);
192 return 0;
193 }
194
195 /*
196 * This routine gets called during probe before ehci->command
197 * has been initialized, so we can't rely on its value.
198 */
199 ehci->command &= ~CMD_RUN;
200 temp = ehci_readl(ehci, regs: &ehci->regs->command);
201 temp &= ~(CMD_RUN | CMD_IAAD);
202 ehci_writel(ehci, val: temp, regs: &ehci->regs->command);
203
204 spin_unlock_irq(lock: &ehci->lock);
205 synchronize_irq(irq: ehci_to_hcd(ehci)->irq);
206
207 return ehci_handshake(ehci, &ehci->regs->status,
208 STS_HALT, STS_HALT, 16 * 125);
209}
210
211/* put TDI/ARC silicon into EHCI mode */
212static void tdi_reset (struct ehci_hcd *ehci)
213{
214 u32 tmp;
215
216 tmp = ehci_readl(ehci, regs: &ehci->regs->usbmode);
217 tmp |= USBMODE_CM_HC;
218 /* The default byte access to MMR space is LE after
219 * controller reset. Set the required endian mode
220 * for transfer buffers to match the host microprocessor
221 */
222 if (ehci_big_endian_mmio(ehci))
223 tmp |= USBMODE_BE;
224 ehci_writel(ehci, val: tmp, regs: &ehci->regs->usbmode);
225}
226
227/*
228 * Reset a non-running (STS_HALT == 1) controller.
229 * Must be called with interrupts enabled and the lock not held.
230 */
231int ehci_reset(struct ehci_hcd *ehci)
232{
233 int retval;
234 u32 command = ehci_readl(ehci, regs: &ehci->regs->command);
235
236 /* If the EHCI debug controller is active, special care must be
237 * taken before and after a host controller reset */
238 if (ehci->debug && !dbgp_reset_prep(ehci_to_hcd(ehci)))
239 ehci->debug = NULL;
240
241 command |= CMD_RESET;
242 dbg_cmd (ehci, label: "reset", command);
243 ehci_writel(ehci, val: command, regs: &ehci->regs->command);
244 ehci->rh_state = EHCI_RH_HALTED;
245 ehci->next_statechange = jiffies;
246 retval = ehci_handshake(ehci, &ehci->regs->command,
247 CMD_RESET, 0, 250 * 1000);
248
249 if (ehci->has_hostpc) {
250 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
251 regs: &ehci->regs->usbmode_ex);
252 ehci_writel(ehci, TXFIFO_DEFAULT, regs: &ehci->regs->txfill_tuning);
253 }
254 if (retval)
255 return retval;
256
257 if (ehci_is_TDI(ehci))
258 tdi_reset (ehci);
259
260 if (ehci->debug)
261 dbgp_external_startup(ehci_to_hcd(ehci));
262
263 ehci->port_c_suspend = ehci->suspended_ports =
264 ehci->resuming_ports = 0;
265 return retval;
266}
267EXPORT_SYMBOL_GPL(ehci_reset);
268
269/*
270 * Idle the controller (turn off the schedules).
271 * Must be called with interrupts enabled and the lock not held.
272 */
273static void ehci_quiesce (struct ehci_hcd *ehci)
274{
275 u32 temp;
276
277 if (ehci->rh_state != EHCI_RH_RUNNING)
278 return;
279
280 /* wait for any schedule enables/disables to take effect */
281 temp = (ehci->command << 10) & (STS_ASS | STS_PSS);
282 ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, temp,
283 16 * 125);
284
285 /* then disable anything that's still active */
286 spin_lock_irq(lock: &ehci->lock);
287 ehci->command &= ~(CMD_ASE | CMD_PSE);
288 ehci_writel(ehci, val: ehci->command, regs: &ehci->regs->command);
289 spin_unlock_irq(lock: &ehci->lock);
290
291 /* hardware can take 16 microframes to turn off ... */
292 ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, 0,
293 16 * 125);
294}
295
296/*-------------------------------------------------------------------------*/
297
298static void end_iaa_cycle(struct ehci_hcd *ehci);
299static void end_unlink_async(struct ehci_hcd *ehci);
300static void unlink_empty_async(struct ehci_hcd *ehci);
301static void ehci_work(struct ehci_hcd *ehci);
302static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
303static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
304static int ehci_port_power(struct ehci_hcd *ehci, int portnum, bool enable);
305
306#include "ehci-timer.c"
307#include "ehci-hub.c"
308#include "ehci-mem.c"
309#include "ehci-q.c"
310#include "ehci-sched.c"
311#include "ehci-sysfs.c"
312
313/*-------------------------------------------------------------------------*/
314
315/* On some systems, leaving remote wakeup enabled prevents system shutdown.
316 * The firmware seems to think that powering off is a wakeup event!
317 * This routine turns off remote wakeup and everything else, on all ports.
318 */
319static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
320{
321 int port = HCS_N_PORTS(ehci->hcs_params);
322
323 while (port--) {
324 spin_unlock_irq(lock: &ehci->lock);
325 ehci_port_power(ehci, portnum: port, enable: false);
326 spin_lock_irq(lock: &ehci->lock);
327 ehci_writel(ehci, PORT_RWC_BITS,
328 regs: &ehci->regs->port_status[port]);
329 }
330}
331
332/*
333 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
334 * Must be called with interrupts enabled and the lock not held.
335 */
336static void ehci_silence_controller(struct ehci_hcd *ehci)
337{
338 ehci_halt(ehci);
339
340 spin_lock_irq(lock: &ehci->lock);
341 ehci->rh_state = EHCI_RH_HALTED;
342 ehci_turn_off_all_ports(ehci);
343
344 /* make BIOS/etc use companion controller during reboot */
345 ehci_writel(ehci, val: 0, regs: &ehci->regs->configured_flag);
346
347 /* unblock posted writes */
348 ehci_readl(ehci, regs: &ehci->regs->configured_flag);
349 spin_unlock_irq(lock: &ehci->lock);
350}
351
352/* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
353 * This forcibly disables dma and IRQs, helping kexec and other cases
354 * where the next system software may expect clean state.
355 */
356static void ehci_shutdown(struct usb_hcd *hcd)
357{
358 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
359
360 /**
361 * Protect the system from crashing at system shutdown in cases where
362 * usb host is not added yet from OTG controller driver.
363 * As ehci_setup() not done yet, so stop accessing registers or
364 * variables initialized in ehci_setup()
365 */
366 if (!ehci->sbrn)
367 return;
368
369 spin_lock_irq(lock: &ehci->lock);
370 ehci->shutdown = true;
371 ehci->rh_state = EHCI_RH_STOPPING;
372 ehci->enabled_hrtimer_events = 0;
373 spin_unlock_irq(lock: &ehci->lock);
374
375 ehci_silence_controller(ehci);
376
377 hrtimer_cancel(timer: &ehci->hrtimer);
378}
379
380/*-------------------------------------------------------------------------*/
381
382/*
383 * ehci_work is called from some interrupts, timers, and so on.
384 * it calls driver completion functions, after dropping ehci->lock.
385 */
386static void ehci_work (struct ehci_hcd *ehci)
387{
388 /* another CPU may drop ehci->lock during a schedule scan while
389 * it reports urb completions. this flag guards against bogus
390 * attempts at re-entrant schedule scanning.
391 */
392 if (ehci->scanning) {
393 ehci->need_rescan = true;
394 return;
395 }
396 ehci->scanning = true;
397
398 rescan:
399 ehci->need_rescan = false;
400 if (ehci->async_count)
401 scan_async(ehci);
402 if (ehci->intr_count > 0)
403 scan_intr(ehci);
404 if (ehci->isoc_count > 0)
405 scan_isoc(ehci);
406 if (ehci->need_rescan)
407 goto rescan;
408 ehci->scanning = false;
409
410 /* the IO watchdog guards against hardware or driver bugs that
411 * misplace IRQs, and should let us run completely without IRQs.
412 * such lossage has been observed on both VT6202 and VT8235.
413 */
414 turn_on_io_watchdog(ehci);
415}
416
417/*
418 * Called when the ehci_hcd module is removed.
419 */
420static void ehci_stop (struct usb_hcd *hcd)
421{
422 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
423
424 ehci_dbg (ehci, "stop\n");
425
426 /* no more interrupts ... */
427
428 spin_lock_irq(lock: &ehci->lock);
429 ehci->enabled_hrtimer_events = 0;
430 spin_unlock_irq(lock: &ehci->lock);
431
432 ehci_quiesce(ehci);
433 ehci_silence_controller(ehci);
434 ehci_reset (ehci);
435
436 hrtimer_cancel(timer: &ehci->hrtimer);
437 remove_sysfs_files(ehci);
438 remove_debug_files (ehci);
439
440 /* root hub is shut down separately (first, when possible) */
441 spin_lock_irq (lock: &ehci->lock);
442 end_free_itds(ehci);
443 spin_unlock_irq (lock: &ehci->lock);
444 ehci_mem_cleanup (ehci);
445
446 if (ehci->amd_pll_fix == 1)
447 usb_amd_dev_put();
448
449 dbg_status (ehci, label: "ehci_stop completed",
450 status: ehci_readl(ehci, regs: &ehci->regs->status));
451}
452
453/* one-time init, only for memory state */
454static int ehci_init(struct usb_hcd *hcd)
455{
456 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
457 u32 temp;
458 int retval;
459 u32 hcc_params;
460 struct ehci_qh_hw *hw;
461
462 spin_lock_init(&ehci->lock);
463
464 /*
465 * keep io watchdog by default, those good HCDs could turn off it later
466 */
467 ehci->need_io_watchdog = 1;
468
469 hrtimer_init(timer: &ehci->hrtimer, CLOCK_MONOTONIC, mode: HRTIMER_MODE_ABS);
470 ehci->hrtimer.function = ehci_hrtimer_func;
471 ehci->next_hrtimer_event = EHCI_HRTIMER_NO_EVENT;
472
473 hcc_params = ehci_readl(ehci, regs: &ehci->caps->hcc_params);
474
475 /*
476 * by default set standard 80% (== 100 usec/uframe) max periodic
477 * bandwidth as required by USB 2.0
478 */
479 ehci->uframe_periodic_max = 100;
480
481 /*
482 * hw default: 1K periodic list heads, one per frame.
483 * periodic_size can shrink by USBCMD update if hcc_params allows.
484 */
485 ehci->periodic_size = DEFAULT_I_TDPS;
486 INIT_LIST_HEAD(list: &ehci->async_unlink);
487 INIT_LIST_HEAD(list: &ehci->async_idle);
488 INIT_LIST_HEAD(list: &ehci->intr_unlink_wait);
489 INIT_LIST_HEAD(list: &ehci->intr_unlink);
490 INIT_LIST_HEAD(list: &ehci->intr_qh_list);
491 INIT_LIST_HEAD(list: &ehci->cached_itd_list);
492 INIT_LIST_HEAD(list: &ehci->cached_sitd_list);
493 INIT_LIST_HEAD(list: &ehci->tt_list);
494
495 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
496 /* periodic schedule size can be smaller than default */
497 switch (EHCI_TUNE_FLS) {
498 case 0: ehci->periodic_size = 1024; break;
499 case 1: ehci->periodic_size = 512; break;
500 case 2: ehci->periodic_size = 256; break;
501 default: BUG();
502 }
503 }
504 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
505 return retval;
506
507 /* controllers may cache some of the periodic schedule ... */
508 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
509 ehci->i_thresh = 0;
510 else // N microframes cached
511 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
512
513 /*
514 * dedicate a qh for the async ring head, since we couldn't unlink
515 * a 'real' qh without stopping the async schedule [4.8]. use it
516 * as the 'reclamation list head' too.
517 * its dummy is used in hw_alt_next of many tds, to prevent the qh
518 * from automatically advancing to the next td after short reads.
519 */
520 ehci->async->qh_next.qh = NULL;
521 hw = ehci->async->hw;
522 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
523 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
524#if defined(CONFIG_PPC_PS3)
525 hw->hw_info1 |= cpu_to_hc32(ehci, QH_INACTIVATE);
526#endif
527 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
528 hw->hw_qtd_next = EHCI_LIST_END(ehci);
529 ehci->async->qh_state = QH_STATE_LINKED;
530 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
531
532 /* clear interrupt enables, set irq latency */
533 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
534 log2_irq_thresh = 0;
535 temp = 1 << (16 + log2_irq_thresh);
536 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
537 ehci->has_ppcd = 1;
538 ehci_dbg(ehci, "enable per-port change event\n");
539 temp |= CMD_PPCEE;
540 }
541 if (HCC_CANPARK(hcc_params)) {
542 /* HW default park == 3, on hardware that supports it (like
543 * NVidia and ALI silicon), maximizes throughput on the async
544 * schedule by avoiding QH fetches between transfers.
545 *
546 * With fast usb storage devices and NForce2, "park" seems to
547 * make problems: throughput reduction (!), data errors...
548 */
549 if (park) {
550 park = min(park, (unsigned) 3);
551 temp |= CMD_PARK;
552 temp |= park << 8;
553 }
554 ehci_dbg(ehci, "park %d\n", park);
555 }
556 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
557 /* periodic schedule size can be smaller than default */
558 temp &= ~(3 << 2);
559 temp |= (EHCI_TUNE_FLS << 2);
560 }
561 ehci->command = temp;
562
563 /* Accept arbitrarily long scatter-gather lists */
564 if (!hcd->localmem_pool)
565 hcd->self.sg_tablesize = ~0;
566
567 /* Prepare for unlinking active QHs */
568 ehci->old_current = ~0;
569 return 0;
570}
571
572/* start HC running; it's halted, ehci_init() has been run (once) */
573static int ehci_run (struct usb_hcd *hcd)
574{
575 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
576 u32 temp;
577 u32 hcc_params;
578 int rc;
579
580 hcd->uses_new_polling = 1;
581
582 /* EHCI spec section 4.1 */
583
584 ehci_writel(ehci, val: ehci->periodic_dma, regs: &ehci->regs->frame_list);
585 ehci_writel(ehci, val: (u32)ehci->async->qh_dma, regs: &ehci->regs->async_next);
586
587 /*
588 * hcc_params controls whether ehci->regs->segment must (!!!)
589 * be used; it constrains QH/ITD/SITD and QTD locations.
590 * dma_pool consistent memory always uses segment zero.
591 * streaming mappings for I/O buffers, like dma_map_single(),
592 * can return segments above 4GB, if the device allows.
593 *
594 * NOTE: the dma mask is visible through dev->dma_mask, so
595 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
596 * Scsi_Host.highmem_io, and so forth. It's readonly to all
597 * host side drivers though.
598 */
599 hcc_params = ehci_readl(ehci, regs: &ehci->caps->hcc_params);
600 if (HCC_64BIT_ADDR(hcc_params)) {
601 ehci_writel(ehci, val: 0, regs: &ehci->regs->segment);
602#if 0
603// this is deeply broken on almost all architectures
604 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
605 ehci_info(ehci, "enabled 64bit DMA\n");
606#endif
607 }
608
609
610 // Philips, Intel, and maybe others need CMD_RUN before the
611 // root hub will detect new devices (why?); NEC doesn't
612 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
613 ehci->command |= CMD_RUN;
614 ehci_writel(ehci, val: ehci->command, regs: &ehci->regs->command);
615 dbg_cmd (ehci, label: "init", command: ehci->command);
616
617 /*
618 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
619 * are explicitly handed to companion controller(s), so no TT is
620 * involved with the root hub. (Except where one is integrated,
621 * and there's no companion controller unless maybe for USB OTG.)
622 *
623 * Turning on the CF flag will transfer ownership of all ports
624 * from the companions to the EHCI controller. If any of the
625 * companions are in the middle of a port reset at the time, it
626 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
627 * guarantees that no resets are in progress. After we set CF,
628 * a short delay lets the hardware catch up; new resets shouldn't
629 * be started before the port switching actions could complete.
630 */
631 down_write(sem: &ehci_cf_port_reset_rwsem);
632 ehci->rh_state = EHCI_RH_RUNNING;
633 ehci_writel(ehci, FLAG_CF, regs: &ehci->regs->configured_flag);
634
635 /* Wait until HC become operational */
636 ehci_readl(ehci, regs: &ehci->regs->command); /* unblock posted writes */
637 msleep(msecs: 5);
638
639 /* For Aspeed, STS_HALT also depends on ASS/PSS status.
640 * Check CMD_RUN instead.
641 */
642 if (ehci->is_aspeed)
643 rc = ehci_handshake(ehci, &ehci->regs->command, CMD_RUN,
644 1, 100 * 1000);
645 else
646 rc = ehci_handshake(ehci, &ehci->regs->status, STS_HALT,
647 0, 100 * 1000);
648
649 up_write(sem: &ehci_cf_port_reset_rwsem);
650
651 if (rc) {
652 ehci_err(ehci, "USB %x.%x, controller refused to start: %d\n",
653 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), rc);
654 return rc;
655 }
656
657 ehci->last_periodic_enable = ktime_get_real();
658
659 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
660 ehci_info (ehci,
661 "USB %x.%x started, EHCI %x.%02x%s\n",
662 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
663 temp >> 8, temp & 0xff,
664 (ignore_oc || ehci->spurious_oc) ? ", overcurrent ignored" : "");
665
666 ehci_writel(ehci, INTR_MASK,
667 regs: &ehci->regs->intr_enable); /* Turn On Interrupts */
668
669 /* GRR this is run-once init(), being done every time the HC starts.
670 * So long as they're part of class devices, we can't do it init()
671 * since the class device isn't created that early.
672 */
673 create_debug_files(ehci);
674 create_sysfs_files(ehci);
675
676 return 0;
677}
678
679int ehci_setup(struct usb_hcd *hcd)
680{
681 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
682 int retval;
683
684 ehci->regs = (void __iomem *)ehci->caps +
685 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
686 dbg_hcs_params(ehci, label: "reset");
687 dbg_hcc_params(ehci, label: "reset");
688
689 /* cache this readonly data; minimize chip reads */
690 ehci->hcs_params = ehci_readl(ehci, regs: &ehci->caps->hcs_params);
691
692 ehci->sbrn = HCD_USB2;
693
694 /* data structure init */
695 retval = ehci_init(hcd);
696 if (retval)
697 return retval;
698
699 retval = ehci_halt(ehci);
700 if (retval) {
701 ehci_mem_cleanup(ehci);
702 return retval;
703 }
704
705 ehci_reset(ehci);
706
707 return 0;
708}
709EXPORT_SYMBOL_GPL(ehci_setup);
710
711/*-------------------------------------------------------------------------*/
712
713static irqreturn_t ehci_irq (struct usb_hcd *hcd)
714{
715 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
716 u32 status, current_status, masked_status, pcd_status = 0;
717 u32 cmd;
718 int bh;
719
720 spin_lock(lock: &ehci->lock);
721
722 status = 0;
723 current_status = ehci_readl(ehci, regs: &ehci->regs->status);
724restart:
725
726 /* e.g. cardbus physical eject */
727 if (current_status == ~(u32) 0) {
728 ehci_dbg (ehci, "device removed\n");
729 goto dead;
730 }
731 status |= current_status;
732
733 /*
734 * We don't use STS_FLR, but some controllers don't like it to
735 * remain on, so mask it out along with the other status bits.
736 */
737 masked_status = current_status & (INTR_MASK | STS_FLR);
738
739 /* Shared IRQ? */
740 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
741 spin_unlock(lock: &ehci->lock);
742 return IRQ_NONE;
743 }
744
745 /* clear (just) interrupts */
746 ehci_writel(ehci, val: masked_status, regs: &ehci->regs->status);
747
748 /* For edge interrupts, don't race with an interrupt bit being raised */
749 current_status = ehci_readl(ehci, regs: &ehci->regs->status);
750 if (current_status & INTR_MASK)
751 goto restart;
752
753 cmd = ehci_readl(ehci, regs: &ehci->regs->command);
754 bh = 0;
755
756 /* normal [4.15.1.2] or error [4.15.1.1] completion */
757 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
758 if (likely ((status & STS_ERR) == 0)) {
759 INCR(ehci->stats.normal);
760 } else {
761 /* Force to check port status */
762 if (ehci->has_ci_pec_bug)
763 status |= STS_PCD;
764 INCR(ehci->stats.error);
765 }
766 bh = 1;
767 }
768
769 /* complete the unlinking of some qh [4.15.2.3] */
770 if (status & STS_IAA) {
771
772 /* Turn off the IAA watchdog */
773 ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_IAA_WATCHDOG);
774
775 /*
776 * Mild optimization: Allow another IAAD to reset the
777 * hrtimer, if one occurs before the next expiration.
778 * In theory we could always cancel the hrtimer, but
779 * tests show that about half the time it will be reset
780 * for some other event anyway.
781 */
782 if (ehci->next_hrtimer_event == EHCI_HRTIMER_IAA_WATCHDOG)
783 ++ehci->next_hrtimer_event;
784
785 /* guard against (alleged) silicon errata */
786 if (cmd & CMD_IAAD)
787 ehci_dbg(ehci, "IAA with IAAD still set?\n");
788 if (ehci->iaa_in_progress)
789 INCR(ehci->stats.iaa);
790 end_iaa_cycle(ehci);
791 }
792
793 /* remote wakeup [4.3.1] */
794 if (status & STS_PCD) {
795 unsigned i = HCS_N_PORTS (ehci->hcs_params);
796 u32 ppcd = ~0;
797
798 /* kick root hub later */
799 pcd_status = status;
800
801 /* resume root hub? */
802 if (ehci->rh_state == EHCI_RH_SUSPENDED)
803 usb_hcd_resume_root_hub(hcd);
804
805 /* get per-port change detect bits */
806 if (ehci->has_ppcd)
807 ppcd = status >> 16;
808
809 while (i--) {
810 int pstatus;
811
812 /* leverage per-port change bits feature */
813 if (!(ppcd & (1 << i)))
814 continue;
815 pstatus = ehci_readl(ehci,
816 regs: &ehci->regs->port_status[i]);
817
818 if (pstatus & PORT_OWNER)
819 continue;
820 if (!(test_bit(i, &ehci->suspended_ports) &&
821 ((pstatus & PORT_RESUME) ||
822 !(pstatus & PORT_SUSPEND)) &&
823 (pstatus & PORT_PE) &&
824 ehci->reset_done[i] == 0))
825 continue;
826
827 /* start USB_RESUME_TIMEOUT msec resume signaling from
828 * this port, and make hub_wq collect
829 * PORT_STAT_C_SUSPEND to stop that signaling.
830 */
831 ehci->reset_done[i] = jiffies +
832 msecs_to_jiffies(USB_RESUME_TIMEOUT);
833 set_bit(nr: i, addr: &ehci->resuming_ports);
834 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
835 usb_hcd_start_port_resume(bus: &hcd->self, portnum: i);
836 mod_timer(timer: &hcd->rh_timer, expires: ehci->reset_done[i]);
837 }
838 }
839
840 /* PCI errors [4.15.2.4] */
841 if (unlikely ((status & STS_FATAL) != 0)) {
842 ehci_err(ehci, "fatal error\n");
843 dbg_cmd(ehci, label: "fatal", command: cmd);
844 dbg_status(ehci, label: "fatal", status);
845dead:
846 usb_hc_died(hcd);
847
848 /* Don't let the controller do anything more */
849 ehci->shutdown = true;
850 ehci->rh_state = EHCI_RH_STOPPING;
851 ehci->command &= ~(CMD_RUN | CMD_ASE | CMD_PSE);
852 ehci_writel(ehci, val: ehci->command, regs: &ehci->regs->command);
853 ehci_writel(ehci, val: 0, regs: &ehci->regs->intr_enable);
854 ehci_handle_controller_death(ehci);
855
856 /* Handle completions when the controller stops */
857 bh = 0;
858 }
859
860 if (bh)
861 ehci_work (ehci);
862 spin_unlock(lock: &ehci->lock);
863 if (pcd_status)
864 usb_hcd_poll_rh_status(hcd);
865 return IRQ_HANDLED;
866}
867
868/*-------------------------------------------------------------------------*/
869
870/*
871 * non-error returns are a promise to giveback() the urb later
872 * we drop ownership so next owner (or urb unlink) can get it
873 *
874 * urb + dev is in hcd.self.controller.urb_list
875 * we're queueing TDs onto software and hardware lists
876 *
877 * hcd-specific init for hcpriv hasn't been done yet
878 *
879 * NOTE: control, bulk, and interrupt share the same code to append TDs
880 * to a (possibly active) QH, and the same QH scanning code.
881 */
882static int ehci_urb_enqueue (
883 struct usb_hcd *hcd,
884 struct urb *urb,
885 gfp_t mem_flags
886) {
887 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
888 struct list_head qtd_list;
889
890 INIT_LIST_HEAD (list: &qtd_list);
891
892 switch (usb_pipetype (urb->pipe)) {
893 case PIPE_CONTROL:
894 /* qh_completions() code doesn't handle all the fault cases
895 * in multi-TD control transfers. Even 1KB is rare anyway.
896 */
897 if (urb->transfer_buffer_length > (16 * 1024))
898 return -EMSGSIZE;
899 fallthrough;
900 /* case PIPE_BULK: */
901 default:
902 if (!qh_urb_transaction (ehci, urb, head: &qtd_list, flags: mem_flags))
903 return -ENOMEM;
904 return submit_async(ehci, urb, qtd_list: &qtd_list, mem_flags);
905
906 case PIPE_INTERRUPT:
907 if (!qh_urb_transaction (ehci, urb, head: &qtd_list, flags: mem_flags))
908 return -ENOMEM;
909 return intr_submit(ehci, urb, qtd_list: &qtd_list, mem_flags);
910
911 case PIPE_ISOCHRONOUS:
912 if (urb->dev->speed == USB_SPEED_HIGH)
913 return itd_submit (ehci, urb, mem_flags);
914 else
915 return sitd_submit (ehci, urb, mem_flags);
916 }
917}
918
919/* remove from hardware lists
920 * completions normally happen asynchronously
921 */
922
923static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
924{
925 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
926 struct ehci_qh *qh;
927 unsigned long flags;
928 int rc;
929
930 spin_lock_irqsave (&ehci->lock, flags);
931 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
932 if (rc)
933 goto done;
934
935 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
936 /*
937 * We don't expedite dequeue for isochronous URBs.
938 * Just wait until they complete normally or their
939 * time slot expires.
940 */
941 } else {
942 qh = (struct ehci_qh *) urb->hcpriv;
943 qh->unlink_reason |= QH_UNLINK_REQUESTED;
944 switch (qh->qh_state) {
945 case QH_STATE_LINKED:
946 if (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)
947 start_unlink_intr(ehci, qh);
948 else
949 start_unlink_async(ehci, qh);
950 break;
951 case QH_STATE_COMPLETING:
952 qh->dequeue_during_giveback = 1;
953 break;
954 case QH_STATE_UNLINK:
955 case QH_STATE_UNLINK_WAIT:
956 /* already started */
957 break;
958 case QH_STATE_IDLE:
959 /* QH might be waiting for a Clear-TT-Buffer */
960 qh_completions(ehci, qh);
961 break;
962 }
963 }
964done:
965 spin_unlock_irqrestore (lock: &ehci->lock, flags);
966 return rc;
967}
968
969/*-------------------------------------------------------------------------*/
970
971// bulk qh holds the data toggle
972
973static void
974ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
975{
976 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
977 unsigned long flags;
978 struct ehci_qh *qh;
979
980 /* ASSERT: any requests/urbs are being unlinked */
981 /* ASSERT: nobody can be submitting urbs for this any more */
982
983rescan:
984 spin_lock_irqsave (&ehci->lock, flags);
985 qh = ep->hcpriv;
986 if (!qh)
987 goto done;
988
989 /* endpoints can be iso streams. for now, we don't
990 * accelerate iso completions ... so spin a while.
991 */
992 if (qh->hw == NULL) {
993 struct ehci_iso_stream *stream = ep->hcpriv;
994
995 if (!list_empty(head: &stream->td_list))
996 goto idle_timeout;
997
998 /* BUG_ON(!list_empty(&stream->free_list)); */
999 reserve_release_iso_bandwidth(ehci, stream, sign: -1);
1000 kfree(objp: stream);
1001 goto done;
1002 }
1003
1004 qh->unlink_reason |= QH_UNLINK_REQUESTED;
1005 switch (qh->qh_state) {
1006 case QH_STATE_LINKED:
1007 if (list_empty(head: &qh->qtd_list))
1008 qh->unlink_reason |= QH_UNLINK_QUEUE_EMPTY;
1009 else
1010 WARN_ON(1);
1011 if (usb_endpoint_type(epd: &ep->desc) != USB_ENDPOINT_XFER_INT)
1012 start_unlink_async(ehci, qh);
1013 else
1014 start_unlink_intr(ehci, qh);
1015 fallthrough;
1016 case QH_STATE_COMPLETING: /* already in unlinking */
1017 case QH_STATE_UNLINK: /* wait for hw to finish? */
1018 case QH_STATE_UNLINK_WAIT:
1019idle_timeout:
1020 spin_unlock_irqrestore (lock: &ehci->lock, flags);
1021 schedule_timeout_uninterruptible(timeout: 1);
1022 goto rescan;
1023 case QH_STATE_IDLE: /* fully unlinked */
1024 if (qh->clearing_tt)
1025 goto idle_timeout;
1026 if (list_empty (head: &qh->qtd_list)) {
1027 if (qh->ps.bw_uperiod)
1028 reserve_release_intr_bandwidth(ehci, qh, sign: -1);
1029 qh_destroy(ehci, qh);
1030 break;
1031 }
1032 fallthrough;
1033 default:
1034 /* caller was supposed to have unlinked any requests;
1035 * that's not our job. just leak this memory.
1036 */
1037 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1038 qh, ep->desc.bEndpointAddress, qh->qh_state,
1039 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1040 break;
1041 }
1042 done:
1043 ep->hcpriv = NULL;
1044 spin_unlock_irqrestore (lock: &ehci->lock, flags);
1045}
1046
1047static void
1048ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1049{
1050 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1051 struct ehci_qh *qh;
1052 int eptype = usb_endpoint_type(epd: &ep->desc);
1053 int epnum = usb_endpoint_num(epd: &ep->desc);
1054 int is_out = usb_endpoint_dir_out(epd: &ep->desc);
1055 unsigned long flags;
1056
1057 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1058 return;
1059
1060 spin_lock_irqsave(&ehci->lock, flags);
1061 qh = ep->hcpriv;
1062
1063 /* For Bulk and Interrupt endpoints we maintain the toggle state
1064 * in the hardware; the toggle bits in udev aren't used at all.
1065 * When an endpoint is reset by usb_clear_halt() we must reset
1066 * the toggle bit in the QH.
1067 */
1068 if (qh) {
1069 if (!list_empty(head: &qh->qtd_list)) {
1070 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1071 } else {
1072 /* The toggle value in the QH can't be updated
1073 * while the QH is active. Unlink it now;
1074 * re-linking will call qh_refresh().
1075 */
1076 usb_settoggle(qh->ps.udev, epnum, is_out, 0);
1077 qh->unlink_reason |= QH_UNLINK_REQUESTED;
1078 if (eptype == USB_ENDPOINT_XFER_BULK)
1079 start_unlink_async(ehci, qh);
1080 else
1081 start_unlink_intr(ehci, qh);
1082 }
1083 }
1084 spin_unlock_irqrestore(lock: &ehci->lock, flags);
1085}
1086
1087static int ehci_get_frame (struct usb_hcd *hcd)
1088{
1089 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1090 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
1091}
1092
1093/*-------------------------------------------------------------------------*/
1094
1095/* Device addition and removal */
1096
1097static void ehci_remove_device(struct usb_hcd *hcd, struct usb_device *udev)
1098{
1099 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1100
1101 spin_lock_irq(lock: &ehci->lock);
1102 drop_tt(udev);
1103 spin_unlock_irq(lock: &ehci->lock);
1104}
1105
1106/*-------------------------------------------------------------------------*/
1107
1108#ifdef CONFIG_PM
1109
1110/* Clear wakeup signal locked in zhaoxin platform when device plug in. */
1111static void ehci_zx_wakeup_clear(struct ehci_hcd *ehci)
1112{
1113 u32 __iomem *reg = &ehci->regs->port_status[4];
1114 u32 t1 = ehci_readl(ehci, regs: reg);
1115
1116 t1 &= (u32)~0xf0000;
1117 t1 |= PORT_TEST_FORCE;
1118 ehci_writel(ehci, val: t1, regs: reg);
1119 t1 = ehci_readl(ehci, regs: reg);
1120 msleep(msecs: 1);
1121 t1 &= (u32)~0xf0000;
1122 ehci_writel(ehci, val: t1, regs: reg);
1123 ehci_readl(ehci, regs: reg);
1124 msleep(msecs: 1);
1125 t1 = ehci_readl(ehci, regs: reg);
1126 ehci_writel(ehci, val: t1 | PORT_CSC, regs: reg);
1127 ehci_readl(ehci, regs: reg);
1128}
1129
1130/* suspend/resume, section 4.3 */
1131
1132/* These routines handle the generic parts of controller suspend/resume */
1133
1134int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1135{
1136 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1137
1138 if (time_before(jiffies, ehci->next_statechange))
1139 msleep(msecs: 10);
1140
1141 /*
1142 * Root hub was already suspended. Disable IRQ emission and
1143 * mark HW unaccessible. The PM and USB cores make sure that
1144 * the root hub is either suspended or stopped.
1145 */
1146 ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
1147
1148 spin_lock_irq(lock: &ehci->lock);
1149 ehci_writel(ehci, val: 0, regs: &ehci->regs->intr_enable);
1150 (void) ehci_readl(ehci, regs: &ehci->regs->intr_enable);
1151
1152 clear_bit(HCD_FLAG_HW_ACCESSIBLE, addr: &hcd->flags);
1153 spin_unlock_irq(lock: &ehci->lock);
1154
1155 synchronize_irq(irq: hcd->irq);
1156
1157 /* Check for race with a wakeup request */
1158 if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
1159 ehci_resume(hcd, force_reset: false);
1160 return -EBUSY;
1161 }
1162
1163 return 0;
1164}
1165EXPORT_SYMBOL_GPL(ehci_suspend);
1166
1167/* Returns 0 if power was preserved, 1 if power was lost */
1168int ehci_resume(struct usb_hcd *hcd, bool force_reset)
1169{
1170 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1171
1172 if (time_before(jiffies, ehci->next_statechange))
1173 msleep(msecs: 100);
1174
1175 /* Mark hardware accessible again as we are back to full power by now */
1176 set_bit(HCD_FLAG_HW_ACCESSIBLE, addr: &hcd->flags);
1177
1178 if (ehci->shutdown)
1179 return 0; /* Controller is dead */
1180
1181 if (ehci->zx_wakeup_clear_needed)
1182 ehci_zx_wakeup_clear(ehci);
1183
1184 /*
1185 * If CF is still set and reset isn't forced
1186 * then we maintained suspend power.
1187 * Just undo the effect of ehci_suspend().
1188 */
1189 if (ehci_readl(ehci, regs: &ehci->regs->configured_flag) == FLAG_CF &&
1190 !force_reset) {
1191 int mask = INTR_MASK;
1192
1193 ehci_prepare_ports_for_controller_resume(ehci);
1194
1195 spin_lock_irq(lock: &ehci->lock);
1196 if (ehci->shutdown)
1197 goto skip;
1198
1199 if (!hcd->self.root_hub->do_remote_wakeup)
1200 mask &= ~STS_PCD;
1201 ehci_writel(ehci, val: mask, regs: &ehci->regs->intr_enable);
1202 ehci_readl(ehci, regs: &ehci->regs->intr_enable);
1203 skip:
1204 spin_unlock_irq(lock: &ehci->lock);
1205 return 0;
1206 }
1207
1208 /*
1209 * Else reset, to cope with power loss or resume from hibernation
1210 * having let the firmware kick in during reboot.
1211 */
1212 usb_root_hub_lost_power(rhdev: hcd->self.root_hub);
1213 (void) ehci_halt(ehci);
1214 (void) ehci_reset(ehci);
1215
1216 spin_lock_irq(lock: &ehci->lock);
1217 if (ehci->shutdown)
1218 goto skip;
1219
1220 ehci_writel(ehci, val: ehci->command, regs: &ehci->regs->command);
1221 ehci_writel(ehci, FLAG_CF, regs: &ehci->regs->configured_flag);
1222 ehci_readl(ehci, regs: &ehci->regs->command); /* unblock posted writes */
1223
1224 ehci->rh_state = EHCI_RH_SUSPENDED;
1225 spin_unlock_irq(lock: &ehci->lock);
1226
1227 return 1;
1228}
1229EXPORT_SYMBOL_GPL(ehci_resume);
1230
1231#endif
1232
1233/*-------------------------------------------------------------------------*/
1234
1235/*
1236 * Generic structure: This gets copied for platform drivers so that
1237 * individual entries can be overridden as needed.
1238 */
1239
1240static const struct hc_driver ehci_hc_driver = {
1241 .description = hcd_name,
1242 .product_desc = "EHCI Host Controller",
1243 .hcd_priv_size = sizeof(struct ehci_hcd),
1244
1245 /*
1246 * generic hardware linkage
1247 */
1248 .irq = ehci_irq,
1249 .flags = HCD_MEMORY | HCD_DMA | HCD_USB2 | HCD_BH,
1250
1251 /*
1252 * basic lifecycle operations
1253 */
1254 .reset = ehci_setup,
1255 .start = ehci_run,
1256 .stop = ehci_stop,
1257 .shutdown = ehci_shutdown,
1258
1259 /*
1260 * managing i/o requests and associated device resources
1261 */
1262 .urb_enqueue = ehci_urb_enqueue,
1263 .urb_dequeue = ehci_urb_dequeue,
1264 .endpoint_disable = ehci_endpoint_disable,
1265 .endpoint_reset = ehci_endpoint_reset,
1266 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
1267
1268 /*
1269 * scheduling support
1270 */
1271 .get_frame_number = ehci_get_frame,
1272
1273 /*
1274 * root hub support
1275 */
1276 .hub_status_data = ehci_hub_status_data,
1277 .hub_control = ehci_hub_control,
1278 .bus_suspend = ehci_bus_suspend,
1279 .bus_resume = ehci_bus_resume,
1280 .relinquish_port = ehci_relinquish_port,
1281 .port_handed_over = ehci_port_handed_over,
1282 .get_resuming_ports = ehci_get_resuming_ports,
1283
1284 /*
1285 * device support
1286 */
1287 .free_dev = ehci_remove_device,
1288#ifdef CONFIG_USB_HCD_TEST_MODE
1289 /* EH SINGLE_STEP_SET_FEATURE test support */
1290 .submit_single_step_set_feature = ehci_submit_single_step_set_feature,
1291#endif
1292};
1293
1294void ehci_init_driver(struct hc_driver *drv,
1295 const struct ehci_driver_overrides *over)
1296{
1297 /* Copy the generic table to drv and then apply the overrides */
1298 *drv = ehci_hc_driver;
1299
1300 if (over) {
1301 drv->hcd_priv_size += over->extra_priv_size;
1302 if (over->reset)
1303 drv->reset = over->reset;
1304 if (over->port_power)
1305 drv->port_power = over->port_power;
1306 }
1307}
1308EXPORT_SYMBOL_GPL(ehci_init_driver);
1309
1310/*-------------------------------------------------------------------------*/
1311
1312MODULE_DESCRIPTION(DRIVER_DESC);
1313MODULE_AUTHOR (DRIVER_AUTHOR);
1314MODULE_LICENSE ("GPL");
1315
1316#ifdef CONFIG_USB_EHCI_SH
1317#include "ehci-sh.c"
1318#endif
1319
1320#ifdef CONFIG_PPC_PS3
1321#include "ehci-ps3.c"
1322#endif
1323
1324#ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1325#include "ehci-ppc-of.c"
1326#endif
1327
1328#ifdef CONFIG_XPS_USB_HCD_XILINX
1329#include "ehci-xilinx-of.c"
1330#endif
1331
1332#ifdef CONFIG_SPARC_LEON
1333#include "ehci-grlib.c"
1334#endif
1335
1336static struct platform_driver * const platform_drivers[] = {
1337#ifdef CONFIG_USB_EHCI_SH
1338 &ehci_hcd_sh_driver,
1339#endif
1340#ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1341 &ehci_hcd_ppc_of_driver,
1342#endif
1343#ifdef CONFIG_XPS_USB_HCD_XILINX
1344 &ehci_hcd_xilinx_of_driver,
1345#endif
1346#ifdef CONFIG_SPARC_LEON
1347 &ehci_grlib_driver,
1348#endif
1349};
1350
1351static int __init ehci_hcd_init(void)
1352{
1353 int retval = 0;
1354
1355 if (usb_disabled())
1356 return -ENODEV;
1357
1358 set_bit(USB_EHCI_LOADED, addr: &usb_hcds_loaded);
1359 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1360 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1361 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1362 " before uhci_hcd and ohci_hcd, not after\n");
1363
1364 pr_debug("%s: block sizes: qh %zd qtd %zd itd %zd sitd %zd\n",
1365 hcd_name,
1366 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1367 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1368
1369#ifdef CONFIG_DYNAMIC_DEBUG
1370 ehci_debug_root = debugfs_create_dir(name: "ehci", parent: usb_debug_root);
1371#endif
1372
1373 retval = platform_register_drivers(platform_drivers, ARRAY_SIZE(platform_drivers));
1374 if (retval < 0)
1375 goto clean0;
1376
1377#ifdef CONFIG_PPC_PS3
1378 retval = ps3_ehci_driver_register(&ps3_ehci_driver);
1379 if (retval < 0)
1380 goto clean1;
1381#endif
1382
1383 return 0;
1384
1385#ifdef CONFIG_PPC_PS3
1386clean1:
1387#endif
1388 platform_unregister_drivers(drivers: platform_drivers, ARRAY_SIZE(platform_drivers));
1389clean0:
1390#ifdef CONFIG_DYNAMIC_DEBUG
1391 debugfs_remove(dentry: ehci_debug_root);
1392 ehci_debug_root = NULL;
1393#endif
1394 clear_bit(USB_EHCI_LOADED, addr: &usb_hcds_loaded);
1395 return retval;
1396}
1397module_init(ehci_hcd_init);
1398
1399static void __exit ehci_hcd_cleanup(void)
1400{
1401#ifdef CONFIG_PPC_PS3
1402 ps3_ehci_driver_unregister(&ps3_ehci_driver);
1403#endif
1404 platform_unregister_drivers(drivers: platform_drivers, ARRAY_SIZE(platform_drivers));
1405#ifdef CONFIG_DYNAMIC_DEBUG
1406 debugfs_remove(dentry: ehci_debug_root);
1407#endif
1408 clear_bit(USB_EHCI_LOADED, addr: &usb_hcds_loaded);
1409}
1410module_exit(ehci_hcd_cleanup);
1411

source code of linux/drivers/usb/host/ehci-hcd.c