1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * PolarFire SoC (MPFS) MUSB Glue Layer |
4 | * |
5 | * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved. |
6 | * Based on {omap2430,tusb6010,ux500}.c |
7 | * |
8 | */ |
9 | |
10 | #include <linux/clk.h> |
11 | #include <linux/dma-mapping.h> |
12 | #include <linux/err.h> |
13 | #include <linux/io.h> |
14 | #include <linux/kernel.h> |
15 | #include <linux/module.h> |
16 | #include <linux/of.h> |
17 | #include <linux/platform_device.h> |
18 | #include <linux/usb/usb_phy_generic.h> |
19 | #include "musb_core.h" |
20 | #include "musb_dma.h" |
21 | |
22 | #define MPFS_MUSB_MAX_EP_NUM 8 |
23 | #define MPFS_MUSB_RAM_BITS 12 |
24 | |
25 | struct mpfs_glue { |
26 | struct device *dev; |
27 | struct platform_device *musb; |
28 | struct platform_device *phy; |
29 | struct clk *clk; |
30 | }; |
31 | |
32 | static struct musb_fifo_cfg mpfs_musb_mode_cfg[] = { |
33 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
34 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, |
35 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, |
36 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, |
37 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, |
38 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, |
39 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 1024, }, |
40 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 4096, }, |
41 | }; |
42 | |
43 | static const struct musb_hdrc_config mpfs_musb_hdrc_config = { |
44 | .fifo_cfg = mpfs_musb_mode_cfg, |
45 | .fifo_cfg_size = ARRAY_SIZE(mpfs_musb_mode_cfg), |
46 | .multipoint = true, |
47 | .dyn_fifo = true, |
48 | .num_eps = MPFS_MUSB_MAX_EP_NUM, |
49 | .ram_bits = MPFS_MUSB_RAM_BITS, |
50 | }; |
51 | |
52 | static irqreturn_t mpfs_musb_interrupt(int irq, void *__hci) |
53 | { |
54 | unsigned long flags; |
55 | irqreturn_t ret = IRQ_NONE; |
56 | struct musb *musb = __hci; |
57 | |
58 | spin_lock_irqsave(&musb->lock, flags); |
59 | |
60 | musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); |
61 | musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); |
62 | musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); |
63 | |
64 | if (musb->int_usb || musb->int_tx || musb->int_rx) { |
65 | musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb); |
66 | musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx); |
67 | musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx); |
68 | ret = musb_interrupt(musb); |
69 | } |
70 | |
71 | spin_unlock_irqrestore(lock: &musb->lock, flags); |
72 | |
73 | return ret; |
74 | } |
75 | |
76 | static void mpfs_musb_set_vbus(struct musb *musb, int is_on) |
77 | { |
78 | u8 devctl; |
79 | |
80 | /* |
81 | * HDRC controls CPEN, but beware current surges during device |
82 | * connect. They can trigger transient overcurrent conditions |
83 | * that must be ignored. |
84 | */ |
85 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); |
86 | |
87 | if (is_on) { |
88 | musb->is_active = 1; |
89 | musb->xceiv->otg->default_a = 1; |
90 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; |
91 | devctl |= MUSB_DEVCTL_SESSION; |
92 | MUSB_HST_MODE(musb); |
93 | } else { |
94 | musb->is_active = 0; |
95 | |
96 | /* |
97 | * NOTE: skipping A_WAIT_VFALL -> A_IDLE and |
98 | * jumping right to B_IDLE... |
99 | */ |
100 | musb->xceiv->otg->default_a = 0; |
101 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
102 | devctl &= ~MUSB_DEVCTL_SESSION; |
103 | |
104 | MUSB_DEV_MODE(musb); |
105 | } |
106 | |
107 | musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); |
108 | |
109 | dev_dbg(musb->controller, "VBUS %s, devctl %02x\n" , |
110 | usb_otg_state_string(musb->xceiv->otg->state), |
111 | musb_readb(musb->mregs, MUSB_DEVCTL)); |
112 | } |
113 | |
114 | static int mpfs_musb_init(struct musb *musb) |
115 | { |
116 | struct device *dev = musb->controller; |
117 | |
118 | musb->xceiv = devm_usb_get_phy(dev, type: USB_PHY_TYPE_USB2); |
119 | if (IS_ERR(ptr: musb->xceiv)) { |
120 | dev_err(dev, "HS UDC: no transceiver configured\n" ); |
121 | return PTR_ERR(ptr: musb->xceiv); |
122 | } |
123 | |
124 | musb->dyn_fifo = true; |
125 | musb->isr = mpfs_musb_interrupt; |
126 | |
127 | musb_platform_set_vbus(musb, is_on: 1); |
128 | |
129 | return 0; |
130 | } |
131 | |
132 | static const struct musb_platform_ops mpfs_ops = { |
133 | .quirks = MUSB_DMA_INVENTRA, |
134 | .init = mpfs_musb_init, |
135 | .fifo_mode = 2, |
136 | #ifdef CONFIG_USB_INVENTRA_DMA |
137 | .dma_init = musbhs_dma_controller_create, |
138 | .dma_exit = musbhs_dma_controller_destroy, |
139 | #endif |
140 | .set_vbus = mpfs_musb_set_vbus |
141 | }; |
142 | |
143 | static int mpfs_probe(struct platform_device *pdev) |
144 | { |
145 | struct musb_hdrc_platform_data *pdata = dev_get_platdata(dev: &pdev->dev); |
146 | struct mpfs_glue *glue; |
147 | struct platform_device *musb_pdev; |
148 | struct device *dev = &pdev->dev; |
149 | struct clk *clk; |
150 | int ret; |
151 | |
152 | glue = devm_kzalloc(dev, size: sizeof(*glue), GFP_KERNEL); |
153 | if (!glue) |
154 | return -ENOMEM; |
155 | |
156 | musb_pdev = platform_device_alloc(name: "musb-hdrc" , PLATFORM_DEVID_AUTO); |
157 | if (!musb_pdev) { |
158 | dev_err(dev, "failed to allocate musb device\n" ); |
159 | return -ENOMEM; |
160 | } |
161 | |
162 | clk = devm_clk_get(dev: &pdev->dev, NULL); |
163 | if (IS_ERR(ptr: clk)) { |
164 | dev_err(&pdev->dev, "failed to get clock\n" ); |
165 | ret = PTR_ERR(ptr: clk); |
166 | goto err_phy_release; |
167 | } |
168 | |
169 | ret = clk_prepare_enable(clk); |
170 | if (ret) { |
171 | dev_err(&pdev->dev, "failed to enable clock\n" ); |
172 | goto err_phy_release; |
173 | } |
174 | |
175 | musb_pdev->dev.parent = dev; |
176 | musb_pdev->dev.coherent_dma_mask = DMA_BIT_MASK(39); |
177 | musb_pdev->dev.dma_mask = &musb_pdev->dev.coherent_dma_mask; |
178 | device_set_of_node_from_dev(dev: &musb_pdev->dev, dev2: dev); |
179 | |
180 | glue->dev = dev; |
181 | glue->musb = musb_pdev; |
182 | glue->clk = clk; |
183 | |
184 | pdata = devm_kzalloc(dev, size: sizeof(*pdata), GFP_KERNEL); |
185 | if (!pdata) { |
186 | ret = -ENOMEM; |
187 | goto err_clk_disable; |
188 | } |
189 | |
190 | pdata->config = &mpfs_musb_hdrc_config; |
191 | pdata->platform_ops = &mpfs_ops; |
192 | |
193 | pdata->mode = usb_get_dr_mode(dev); |
194 | if (pdata->mode == USB_DR_MODE_UNKNOWN) { |
195 | dev_info(dev, "No dr_mode property found, defaulting to otg\n" ); |
196 | pdata->mode = USB_DR_MODE_OTG; |
197 | } |
198 | |
199 | glue->phy = usb_phy_generic_register(); |
200 | if (IS_ERR(ptr: glue->phy)) { |
201 | dev_err(dev, "failed to register usb-phy %ld\n" , |
202 | PTR_ERR(glue->phy)); |
203 | ret = PTR_ERR(ptr: glue->phy); |
204 | goto err_clk_disable; |
205 | } |
206 | |
207 | platform_set_drvdata(pdev, data: glue); |
208 | |
209 | ret = platform_device_add_resources(pdev: musb_pdev, res: pdev->resource, num: pdev->num_resources); |
210 | if (ret) { |
211 | dev_err(dev, "failed to add resources\n" ); |
212 | goto err_clk_disable; |
213 | } |
214 | |
215 | ret = platform_device_add_data(pdev: musb_pdev, data: pdata, size: sizeof(*pdata)); |
216 | if (ret) { |
217 | dev_err(dev, "failed to add platform_data\n" ); |
218 | goto err_clk_disable; |
219 | } |
220 | |
221 | ret = platform_device_add(pdev: musb_pdev); |
222 | if (ret) { |
223 | dev_err(dev, "failed to register musb device\n" ); |
224 | goto err_clk_disable; |
225 | } |
226 | |
227 | dev_info(&pdev->dev, "Registered MPFS MUSB driver\n" ); |
228 | return 0; |
229 | |
230 | err_clk_disable: |
231 | clk_disable_unprepare(clk); |
232 | |
233 | err_phy_release: |
234 | usb_phy_generic_unregister(glue->phy); |
235 | platform_device_put(pdev: musb_pdev); |
236 | return ret; |
237 | } |
238 | |
239 | static void mpfs_remove(struct platform_device *pdev) |
240 | { |
241 | struct mpfs_glue *glue = platform_get_drvdata(pdev); |
242 | |
243 | clk_disable_unprepare(clk: glue->clk); |
244 | platform_device_unregister(glue->musb); |
245 | usb_phy_generic_unregister(pdev); |
246 | } |
247 | |
248 | #ifdef CONFIG_OF |
249 | static const struct of_device_id mpfs_id_table[] = { |
250 | { .compatible = "microchip,mpfs-musb" }, |
251 | { } |
252 | }; |
253 | MODULE_DEVICE_TABLE(of, mpfs_id_table); |
254 | #endif |
255 | |
256 | static struct platform_driver mpfs_musb_driver = { |
257 | .probe = mpfs_probe, |
258 | .remove_new = mpfs_remove, |
259 | .driver = { |
260 | .name = "mpfs-musb" , |
261 | .of_match_table = of_match_ptr(mpfs_id_table) |
262 | }, |
263 | }; |
264 | |
265 | module_platform_driver(mpfs_musb_driver); |
266 | |
267 | MODULE_DESCRIPTION("PolarFire SoC MUSB Glue Layer" ); |
268 | MODULE_LICENSE("GPL" ); |
269 | |