1 | /* |
2 | * drivers/video/asiliantfb.c |
3 | * frame buffer driver for Asiliant 69000 chip |
4 | * Copyright (C) 2001-2003 Saito.K & Jeanne |
5 | * |
6 | * from driver/video/chipsfb.c and, |
7 | * |
8 | * drivers/video/asiliantfb.c -- frame buffer device for |
9 | * Asiliant 69030 chip (formerly Intel, formerly Chips & Technologies) |
10 | * Author: apc@agelectronics.co.uk |
11 | * Copyright (C) 2000 AG Electronics |
12 | * Note: the data sheets don't seem to be available from Asiliant. |
13 | * They are available by searching developer.intel.com, but are not otherwise |
14 | * linked to. |
15 | * |
16 | * This driver should be portable with minimal effort to the 69000 display |
17 | * chip, and to the twin-display mode of the 69030. |
18 | * Contains code from Thomas Hhenleitner <th@visuelle-maschinen.de> (thanks) |
19 | * |
20 | * Derived from the CT65550 driver chipsfb.c: |
21 | * Copyright (C) 1998 Paul Mackerras |
22 | * ...which was derived from the Powermac "chips" driver: |
23 | * Copyright (C) 1997 Fabio Riccardi. |
24 | * And from the frame buffer device for Open Firmware-initialized devices: |
25 | * Copyright (C) 1997 Geert Uytterhoeven. |
26 | * |
27 | * This file is subject to the terms and conditions of the GNU General Public |
28 | * License. See the file COPYING in the main directory of this archive for |
29 | * more details. |
30 | */ |
31 | |
32 | #include <linux/aperture.h> |
33 | #include <linux/module.h> |
34 | #include <linux/kernel.h> |
35 | #include <linux/errno.h> |
36 | #include <linux/string.h> |
37 | #include <linux/mm.h> |
38 | #include <linux/vmalloc.h> |
39 | #include <linux/delay.h> |
40 | #include <linux/interrupt.h> |
41 | #include <linux/fb.h> |
42 | #include <linux/init.h> |
43 | #include <linux/pci.h> |
44 | #include <asm/io.h> |
45 | |
46 | /* Built in clock of the 69030 */ |
47 | static const unsigned Fref = 14318180; |
48 | |
49 | #define mmio_base (p->screen_base + 0x400000) |
50 | |
51 | #define mm_write_ind(num, val, ap, dp) do { \ |
52 | writeb((num), mmio_base + (ap)); writeb((val), mmio_base + (dp)); \ |
53 | } while (0) |
54 | |
55 | static void mm_write_xr(struct fb_info *p, u8 reg, u8 data) |
56 | { |
57 | mm_write_ind(reg, data, 0x7ac, 0x7ad); |
58 | } |
59 | #define write_xr(num, val) mm_write_xr(p, num, val) |
60 | |
61 | static void mm_write_fr(struct fb_info *p, u8 reg, u8 data) |
62 | { |
63 | mm_write_ind(reg, data, 0x7a0, 0x7a1); |
64 | } |
65 | #define write_fr(num, val) mm_write_fr(p, num, val) |
66 | |
67 | static void mm_write_cr(struct fb_info *p, u8 reg, u8 data) |
68 | { |
69 | mm_write_ind(reg, data, 0x7a8, 0x7a9); |
70 | } |
71 | #define write_cr(num, val) mm_write_cr(p, num, val) |
72 | |
73 | static void mm_write_gr(struct fb_info *p, u8 reg, u8 data) |
74 | { |
75 | mm_write_ind(reg, data, 0x79c, 0x79d); |
76 | } |
77 | #define write_gr(num, val) mm_write_gr(p, num, val) |
78 | |
79 | static void mm_write_sr(struct fb_info *p, u8 reg, u8 data) |
80 | { |
81 | mm_write_ind(reg, data, 0x788, 0x789); |
82 | } |
83 | #define write_sr(num, val) mm_write_sr(p, num, val) |
84 | |
85 | static void mm_write_ar(struct fb_info *p, u8 reg, u8 data) |
86 | { |
87 | readb(mmio_base + 0x7b4); |
88 | mm_write_ind(reg, data, 0x780, 0x780); |
89 | } |
90 | #define write_ar(num, val) mm_write_ar(p, num, val) |
91 | |
92 | static int asiliantfb_pci_init(struct pci_dev *dp, const struct pci_device_id *); |
93 | static int asiliantfb_check_var(struct fb_var_screeninfo *var, |
94 | struct fb_info *info); |
95 | static int asiliantfb_set_par(struct fb_info *info); |
96 | static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, |
97 | u_int transp, struct fb_info *info); |
98 | |
99 | static const struct fb_ops asiliantfb_ops = { |
100 | .owner = THIS_MODULE, |
101 | FB_DEFAULT_IOMEM_OPS, |
102 | .fb_check_var = asiliantfb_check_var, |
103 | .fb_set_par = asiliantfb_set_par, |
104 | .fb_setcolreg = asiliantfb_setcolreg, |
105 | }; |
106 | |
107 | /* Calculate the ratios for the dot clocks without using a single long long |
108 | * value */ |
109 | static void asiliant_calc_dclk2(u32 *ppixclock, u8 *dclk2_m, u8 *dclk2_n, u8 *dclk2_div) |
110 | { |
111 | unsigned pixclock = *ppixclock; |
112 | unsigned Ftarget; |
113 | unsigned n; |
114 | unsigned best_error = 0xffffffff; |
115 | unsigned best_m = 0xffffffff, |
116 | best_n = 0xffffffff; |
117 | unsigned ratio; |
118 | unsigned remainder; |
119 | unsigned char divisor = 0; |
120 | |
121 | /* Calculate the frequency required. This is hard enough. */ |
122 | ratio = 1000000 / pixclock; |
123 | remainder = 1000000 % pixclock; |
124 | Ftarget = 1000000 * ratio + (1000000 * remainder) / pixclock; |
125 | |
126 | while (Ftarget < 100000000) { |
127 | divisor += 0x10; |
128 | Ftarget <<= 1; |
129 | } |
130 | |
131 | ratio = Ftarget / Fref; |
132 | remainder = Ftarget % Fref; |
133 | |
134 | /* This expresses the constraint that 150kHz <= Fref/n <= 5Mhz, |
135 | * together with 3 <= n <= 257. */ |
136 | for (n = 3; n <= 257; n++) { |
137 | unsigned m = n * ratio + (n * remainder) / Fref; |
138 | |
139 | /* 3 <= m <= 257 */ |
140 | if (m >= 3 && m <= 257) { |
141 | unsigned new_error = Ftarget * n >= Fref * m ? |
142 | ((Ftarget * n) - (Fref * m)) : ((Fref * m) - (Ftarget * n)); |
143 | if (new_error < best_error) { |
144 | best_n = n; |
145 | best_m = m; |
146 | best_error = new_error; |
147 | } |
148 | } |
149 | /* But if VLD = 4, then 4m <= 1028 */ |
150 | else if (m <= 1028) { |
151 | /* remember there are still only 8-bits of precision in m, so |
152 | * avoid over-optimistic error calculations */ |
153 | unsigned new_error = Ftarget * n >= Fref * (m & ~3) ? |
154 | ((Ftarget * n) - (Fref * (m & ~3))) : ((Fref * (m & ~3)) - (Ftarget * n)); |
155 | if (new_error < best_error) { |
156 | best_n = n; |
157 | best_m = m; |
158 | best_error = new_error; |
159 | } |
160 | } |
161 | } |
162 | if (best_m > 257) |
163 | best_m >>= 2; /* divide m by 4, and leave VCO loop divide at 4 */ |
164 | else |
165 | divisor |= 4; /* or set VCO loop divide to 1 */ |
166 | *dclk2_m = best_m - 2; |
167 | *dclk2_n = best_n - 2; |
168 | *dclk2_div = divisor; |
169 | *ppixclock = pixclock; |
170 | return; |
171 | } |
172 | |
173 | static void asiliant_set_timing(struct fb_info *p) |
174 | { |
175 | unsigned hd = p->var.xres / 8; |
176 | unsigned hs = (p->var.xres + p->var.right_margin) / 8; |
177 | unsigned he = (p->var.xres + p->var.right_margin + p->var.hsync_len) / 8; |
178 | unsigned ht = (p->var.left_margin + p->var.xres + p->var.right_margin + p->var.hsync_len) / 8; |
179 | unsigned vd = p->var.yres; |
180 | unsigned vs = p->var.yres + p->var.lower_margin; |
181 | unsigned ve = p->var.yres + p->var.lower_margin + p->var.vsync_len; |
182 | unsigned vt = p->var.upper_margin + p->var.yres + p->var.lower_margin + p->var.vsync_len; |
183 | unsigned wd = (p->var.xres_virtual * ((p->var.bits_per_pixel+7)/8)) / 8; |
184 | |
185 | if ((p->var.xres == 640) && (p->var.yres == 480) && (p->var.pixclock == 39722)) { |
186 | write_fr(0x01, 0x02); /* LCD */ |
187 | } else { |
188 | write_fr(0x01, 0x01); /* CRT */ |
189 | } |
190 | |
191 | write_cr(0x11, (ve - 1) & 0x0f); |
192 | write_cr(0x00, (ht - 5) & 0xff); |
193 | write_cr(0x01, hd - 1); |
194 | write_cr(0x02, hd); |
195 | write_cr(0x03, ((ht - 1) & 0x1f) | 0x80); |
196 | write_cr(0x04, hs); |
197 | write_cr(0x05, (((ht - 1) & 0x20) <<2) | (he & 0x1f)); |
198 | write_cr(0x3c, (ht - 1) & 0xc0); |
199 | write_cr(0x06, (vt - 2) & 0xff); |
200 | write_cr(0x30, (vt - 2) >> 8); |
201 | write_cr(0x07, 0x00); |
202 | write_cr(0x08, 0x00); |
203 | write_cr(0x09, 0x00); |
204 | write_cr(0x10, (vs - 1) & 0xff); |
205 | write_cr(0x32, ((vs - 1) >> 8) & 0xf); |
206 | write_cr(0x11, ((ve - 1) & 0x0f) | 0x80); |
207 | write_cr(0x12, (vd - 1) & 0xff); |
208 | write_cr(0x31, ((vd - 1) & 0xf00) >> 8); |
209 | write_cr(0x13, wd & 0xff); |
210 | write_cr(0x41, (wd & 0xf00) >> 8); |
211 | write_cr(0x15, (vs - 1) & 0xff); |
212 | write_cr(0x33, ((vs - 1) >> 8) & 0xf); |
213 | write_cr(0x38, ((ht - 5) & 0x100) >> 8); |
214 | write_cr(0x16, (vt - 1) & 0xff); |
215 | write_cr(0x18, 0x00); |
216 | |
217 | if (p->var.xres == 640) { |
218 | writeb(val: 0xc7, mmio_base + 0x784); /* set misc output reg */ |
219 | } else { |
220 | writeb(val: 0x07, mmio_base + 0x784); /* set misc output reg */ |
221 | } |
222 | } |
223 | |
224 | static int asiliantfb_check_var(struct fb_var_screeninfo *var, |
225 | struct fb_info *p) |
226 | { |
227 | unsigned long Ftarget, ratio, remainder; |
228 | |
229 | if (!var->pixclock) |
230 | return -EINVAL; |
231 | |
232 | ratio = 1000000 / var->pixclock; |
233 | remainder = 1000000 % var->pixclock; |
234 | Ftarget = 1000000 * ratio + (1000000 * remainder) / var->pixclock; |
235 | |
236 | /* First check the constraint that the maximum post-VCO divisor is 32, |
237 | * and the maximum Fvco is 220MHz */ |
238 | if (Ftarget > 220000000 || Ftarget < 3125000) { |
239 | printk(KERN_ERR "asiliantfb dotclock must be between 3.125 and 220MHz\n" ); |
240 | return -ENXIO; |
241 | } |
242 | var->xres_virtual = var->xres; |
243 | var->yres_virtual = var->yres; |
244 | |
245 | if (var->bits_per_pixel == 24) { |
246 | var->red.offset = 16; |
247 | var->green.offset = 8; |
248 | var->blue.offset = 0; |
249 | var->red.length = var->blue.length = var->green.length = 8; |
250 | } else if (var->bits_per_pixel == 16) { |
251 | switch (var->red.offset) { |
252 | case 11: |
253 | var->green.length = 6; |
254 | break; |
255 | case 10: |
256 | var->green.length = 5; |
257 | break; |
258 | default: |
259 | return -EINVAL; |
260 | } |
261 | var->green.offset = 5; |
262 | var->blue.offset = 0; |
263 | var->red.length = var->blue.length = 5; |
264 | } else if (var->bits_per_pixel == 8) { |
265 | var->red.offset = var->green.offset = var->blue.offset = 0; |
266 | var->red.length = var->green.length = var->blue.length = 8; |
267 | } |
268 | return 0; |
269 | } |
270 | |
271 | static int asiliantfb_set_par(struct fb_info *p) |
272 | { |
273 | u8 dclk2_m; /* Holds m-2 value for register */ |
274 | u8 dclk2_n; /* Holds n-2 value for register */ |
275 | u8 dclk2_div; /* Holds divisor bitmask */ |
276 | |
277 | /* Set pixclock */ |
278 | asiliant_calc_dclk2(ppixclock: &p->var.pixclock, dclk2_m: &dclk2_m, dclk2_n: &dclk2_n, dclk2_div: &dclk2_div); |
279 | |
280 | /* Set color depth */ |
281 | if (p->var.bits_per_pixel == 24) { |
282 | write_xr(0x81, 0x16); /* 24 bit packed color mode */ |
283 | write_xr(0x82, 0x00); /* Disable palettes */ |
284 | write_xr(0x20, 0x20); /* 24 bit blitter mode */ |
285 | } else if (p->var.bits_per_pixel == 16) { |
286 | if (p->var.red.offset == 11) |
287 | write_xr(0x81, 0x15); /* 16 bit color mode */ |
288 | else |
289 | write_xr(0x81, 0x14); /* 15 bit color mode */ |
290 | write_xr(0x82, 0x00); /* Disable palettes */ |
291 | write_xr(0x20, 0x10); /* 16 bit blitter mode */ |
292 | } else if (p->var.bits_per_pixel == 8) { |
293 | write_xr(0x0a, 0x02); /* Linear */ |
294 | write_xr(0x81, 0x12); /* 8 bit color mode */ |
295 | write_xr(0x82, 0x00); /* Graphics gamma enable */ |
296 | write_xr(0x20, 0x00); /* 8 bit blitter mode */ |
297 | } |
298 | p->fix.line_length = p->var.xres * (p->var.bits_per_pixel >> 3); |
299 | p->fix.visual = (p->var.bits_per_pixel == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; |
300 | write_xr(0xc4, dclk2_m); |
301 | write_xr(0xc5, dclk2_n); |
302 | write_xr(0xc7, dclk2_div); |
303 | /* Set up the CR registers */ |
304 | asiliant_set_timing(p); |
305 | return 0; |
306 | } |
307 | |
308 | static int asiliantfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, |
309 | u_int transp, struct fb_info *p) |
310 | { |
311 | if (regno > 255) |
312 | return 1; |
313 | red >>= 8; |
314 | green >>= 8; |
315 | blue >>= 8; |
316 | |
317 | /* Set hardware palete */ |
318 | writeb(val: regno, mmio_base + 0x790); |
319 | udelay(1); |
320 | writeb(val: red, mmio_base + 0x791); |
321 | writeb(val: green, mmio_base + 0x791); |
322 | writeb(val: blue, mmio_base + 0x791); |
323 | |
324 | if (regno < 16) { |
325 | switch(p->var.red.offset) { |
326 | case 10: /* RGB 555 */ |
327 | ((u32 *)(p->pseudo_palette))[regno] = |
328 | ((red & 0xf8) << 7) | |
329 | ((green & 0xf8) << 2) | |
330 | ((blue & 0xf8) >> 3); |
331 | break; |
332 | case 11: /* RGB 565 */ |
333 | ((u32 *)(p->pseudo_palette))[regno] = |
334 | ((red & 0xf8) << 8) | |
335 | ((green & 0xfc) << 3) | |
336 | ((blue & 0xf8) >> 3); |
337 | break; |
338 | case 16: /* RGB 888 */ |
339 | ((u32 *)(p->pseudo_palette))[regno] = |
340 | (red << 16) | |
341 | (green << 8) | |
342 | (blue); |
343 | break; |
344 | } |
345 | } |
346 | |
347 | return 0; |
348 | } |
349 | |
350 | struct chips_init_reg { |
351 | unsigned char addr; |
352 | unsigned char data; |
353 | }; |
354 | |
355 | static struct chips_init_reg chips_init_sr[] = |
356 | { |
357 | {0x00, 0x03}, /* Reset register */ |
358 | {0x01, 0x01}, /* Clocking mode */ |
359 | {0x02, 0x0f}, /* Plane mask */ |
360 | {0x04, 0x0e} /* Memory mode */ |
361 | }; |
362 | |
363 | static struct chips_init_reg chips_init_gr[] = |
364 | { |
365 | {0x03, 0x00}, /* Data rotate */ |
366 | {0x05, 0x00}, /* Graphics mode */ |
367 | {0x06, 0x01}, /* Miscellaneous */ |
368 | {0x08, 0x00} /* Bit mask */ |
369 | }; |
370 | |
371 | static struct chips_init_reg chips_init_ar[] = |
372 | { |
373 | {0x10, 0x01}, /* Mode control */ |
374 | {0x11, 0x00}, /* Overscan */ |
375 | {0x12, 0x0f}, /* Memory plane enable */ |
376 | {0x13, 0x00} /* Horizontal pixel panning */ |
377 | }; |
378 | |
379 | static struct chips_init_reg chips_init_cr[] = |
380 | { |
381 | {0x0c, 0x00}, /* Start address high */ |
382 | {0x0d, 0x00}, /* Start address low */ |
383 | {0x40, 0x00}, /* Extended Start Address */ |
384 | {0x41, 0x00}, /* Extended Start Address */ |
385 | {0x14, 0x00}, /* Underline location */ |
386 | {0x17, 0xe3}, /* CRT mode control */ |
387 | {0x70, 0x00} /* Interlace control */ |
388 | }; |
389 | |
390 | |
391 | static struct chips_init_reg chips_init_fr[] = |
392 | { |
393 | {0x01, 0x02}, |
394 | {0x03, 0x08}, |
395 | {0x08, 0xcc}, |
396 | {0x0a, 0x08}, |
397 | {0x18, 0x00}, |
398 | {0x1e, 0x80}, |
399 | {0x40, 0x83}, |
400 | {0x41, 0x00}, |
401 | {0x48, 0x13}, |
402 | {0x4d, 0x60}, |
403 | {0x4e, 0x0f}, |
404 | |
405 | {0x0b, 0x01}, |
406 | |
407 | {0x21, 0x51}, |
408 | {0x22, 0x1d}, |
409 | {0x23, 0x5f}, |
410 | {0x20, 0x4f}, |
411 | {0x34, 0x00}, |
412 | {0x24, 0x51}, |
413 | {0x25, 0x00}, |
414 | {0x27, 0x0b}, |
415 | {0x26, 0x00}, |
416 | {0x37, 0x80}, |
417 | {0x33, 0x0b}, |
418 | {0x35, 0x11}, |
419 | {0x36, 0x02}, |
420 | {0x31, 0xea}, |
421 | {0x32, 0x0c}, |
422 | {0x30, 0xdf}, |
423 | {0x10, 0x0c}, |
424 | {0x11, 0xe0}, |
425 | {0x12, 0x50}, |
426 | {0x13, 0x00}, |
427 | {0x16, 0x03}, |
428 | {0x17, 0xbd}, |
429 | {0x1a, 0x00}, |
430 | }; |
431 | |
432 | |
433 | static struct chips_init_reg chips_init_xr[] = |
434 | { |
435 | {0xce, 0x00}, /* set default memory clock */ |
436 | {0xcc, 200 }, /* MCLK ratio M */ |
437 | {0xcd, 18 }, /* MCLK ratio N */ |
438 | {0xce, 0x90}, /* MCLK divisor = 2 */ |
439 | |
440 | {0xc4, 209 }, |
441 | {0xc5, 118 }, |
442 | {0xc7, 32 }, |
443 | {0xcf, 0x06}, |
444 | {0x09, 0x01}, /* IO Control - CRT controller extensions */ |
445 | {0x0a, 0x02}, /* Frame buffer mapping */ |
446 | {0x0b, 0x01}, /* PCI burst write */ |
447 | {0x40, 0x03}, /* Memory access control */ |
448 | {0x80, 0x82}, /* Pixel pipeline configuration 0 */ |
449 | {0x81, 0x12}, /* Pixel pipeline configuration 1 */ |
450 | {0x82, 0x08}, /* Pixel pipeline configuration 2 */ |
451 | |
452 | {0xd0, 0x0f}, |
453 | {0xd1, 0x01}, |
454 | }; |
455 | |
456 | static void chips_hw_init(struct fb_info *p) |
457 | { |
458 | int i; |
459 | |
460 | for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i) |
461 | write_xr(chips_init_xr[i].addr, chips_init_xr[i].data); |
462 | write_xr(0x81, 0x12); |
463 | write_xr(0x82, 0x08); |
464 | write_xr(0x20, 0x00); |
465 | for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i) |
466 | write_sr(chips_init_sr[i].addr, chips_init_sr[i].data); |
467 | for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i) |
468 | write_gr(chips_init_gr[i].addr, chips_init_gr[i].data); |
469 | for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i) |
470 | write_ar(chips_init_ar[i].addr, chips_init_ar[i].data); |
471 | /* Enable video output in attribute index register */ |
472 | writeb(val: 0x20, mmio_base + 0x780); |
473 | for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i) |
474 | write_cr(chips_init_cr[i].addr, chips_init_cr[i].data); |
475 | for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i) |
476 | write_fr(chips_init_fr[i].addr, chips_init_fr[i].data); |
477 | } |
478 | |
479 | static const struct fb_fix_screeninfo asiliantfb_fix = { |
480 | .id = "Asiliant 69000" , |
481 | .type = FB_TYPE_PACKED_PIXELS, |
482 | .visual = FB_VISUAL_PSEUDOCOLOR, |
483 | .accel = FB_ACCEL_NONE, |
484 | .line_length = 640, |
485 | .smem_len = 0x200000, /* 2MB */ |
486 | }; |
487 | |
488 | static const struct fb_var_screeninfo asiliantfb_var = { |
489 | .xres = 640, |
490 | .yres = 480, |
491 | .xres_virtual = 640, |
492 | .yres_virtual = 480, |
493 | .bits_per_pixel = 8, |
494 | .red = { .length = 8 }, |
495 | .green = { .length = 8 }, |
496 | .blue = { .length = 8 }, |
497 | .height = -1, |
498 | .width = -1, |
499 | .vmode = FB_VMODE_NONINTERLACED, |
500 | .pixclock = 39722, |
501 | .left_margin = 48, |
502 | .right_margin = 16, |
503 | .upper_margin = 33, |
504 | .lower_margin = 10, |
505 | .hsync_len = 96, |
506 | .vsync_len = 2, |
507 | }; |
508 | |
509 | static int init_asiliant(struct fb_info *p, unsigned long addr) |
510 | { |
511 | int err; |
512 | |
513 | p->fix = asiliantfb_fix; |
514 | p->fix.smem_start = addr; |
515 | p->var = asiliantfb_var; |
516 | p->fbops = &asiliantfb_ops; |
517 | |
518 | err = fb_alloc_cmap(cmap: &p->cmap, len: 256, transp: 0); |
519 | if (err) { |
520 | printk(KERN_ERR "C&T 69000 fb failed to alloc cmap memory\n" ); |
521 | return err; |
522 | } |
523 | |
524 | err = register_framebuffer(fb_info: p); |
525 | if (err < 0) { |
526 | printk(KERN_ERR "C&T 69000 framebuffer failed to register\n" ); |
527 | fb_dealloc_cmap(cmap: &p->cmap); |
528 | return err; |
529 | } |
530 | |
531 | fb_info(p, "Asiliant 69000 frame buffer (%dK RAM detected)\n" , |
532 | p->fix.smem_len / 1024); |
533 | |
534 | writeb(val: 0xff, mmio_base + 0x78c); |
535 | chips_hw_init(p); |
536 | return 0; |
537 | } |
538 | |
539 | static int asiliantfb_pci_init(struct pci_dev *dp, |
540 | const struct pci_device_id *ent) |
541 | { |
542 | unsigned long addr, size; |
543 | struct fb_info *p; |
544 | int err; |
545 | |
546 | err = aperture_remove_conflicting_pci_devices(pdev: dp, name: "asiliantfb" ); |
547 | if (err) |
548 | return err; |
549 | |
550 | if ((dp->resource[0].flags & IORESOURCE_MEM) == 0) |
551 | return -ENODEV; |
552 | addr = pci_resource_start(dp, 0); |
553 | size = pci_resource_len(dp, 0); |
554 | if (addr == 0) |
555 | return -ENODEV; |
556 | if (!request_mem_region(addr, size, "asiliantfb" )) |
557 | return -EBUSY; |
558 | |
559 | p = framebuffer_alloc(size: sizeof(u32) * 16, dev: &dp->dev); |
560 | if (!p) { |
561 | release_mem_region(addr, size); |
562 | return -ENOMEM; |
563 | } |
564 | p->pseudo_palette = p->par; |
565 | p->par = NULL; |
566 | |
567 | p->screen_base = ioremap(offset: addr, size: 0x800000); |
568 | if (p->screen_base == NULL) { |
569 | release_mem_region(addr, size); |
570 | framebuffer_release(info: p); |
571 | return -ENOMEM; |
572 | } |
573 | |
574 | pci_write_config_dword(dev: dp, where: 4, val: 0x02800083); |
575 | writeb(val: 3, addr: p->screen_base + 0x400784); |
576 | |
577 | err = init_asiliant(p, addr); |
578 | if (err) { |
579 | iounmap(addr: p->screen_base); |
580 | release_mem_region(addr, size); |
581 | framebuffer_release(info: p); |
582 | return err; |
583 | } |
584 | |
585 | pci_set_drvdata(pdev: dp, data: p); |
586 | return 0; |
587 | } |
588 | |
589 | static void asiliantfb_remove(struct pci_dev *dp) |
590 | { |
591 | struct fb_info *p = pci_get_drvdata(pdev: dp); |
592 | |
593 | unregister_framebuffer(fb_info: p); |
594 | fb_dealloc_cmap(cmap: &p->cmap); |
595 | iounmap(addr: p->screen_base); |
596 | release_mem_region(pci_resource_start(dp, 0), pci_resource_len(dp, 0)); |
597 | framebuffer_release(info: p); |
598 | } |
599 | |
600 | static const struct pci_device_id asiliantfb_pci_tbl[] = { |
601 | { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000, PCI_ANY_ID, PCI_ANY_ID }, |
602 | { 0 } |
603 | }; |
604 | |
605 | MODULE_DEVICE_TABLE(pci, asiliantfb_pci_tbl); |
606 | |
607 | static struct pci_driver asiliantfb_driver = { |
608 | .name = "asiliantfb" , |
609 | .id_table = asiliantfb_pci_tbl, |
610 | .probe = asiliantfb_pci_init, |
611 | .remove = asiliantfb_remove, |
612 | }; |
613 | |
614 | static int __init asiliantfb_init(void) |
615 | { |
616 | if (fb_modesetting_disabled(drvname: "asiliantfb" )) |
617 | return -ENODEV; |
618 | |
619 | if (fb_get_options(name: "asiliantfb" , NULL)) |
620 | return -ENODEV; |
621 | |
622 | return pci_register_driver(&asiliantfb_driver); |
623 | } |
624 | |
625 | module_init(asiliantfb_init); |
626 | |
627 | static void __exit asiliantfb_exit(void) |
628 | { |
629 | pci_unregister_driver(dev: &asiliantfb_driver); |
630 | } |
631 | |
632 | MODULE_LICENSE("GPL" ); |
633 | |