1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * mach-davinci/nand.h |
4 | * |
5 | * Copyright © 2006 Texas Instruments. |
6 | * |
7 | * Ported to 2.6.23 Copyright © 2008 by |
8 | * Sander Huijsen <Shuijsen@optelecom-nkf.com> |
9 | * Troy Kisky <troy.kisky@boundarydevices.com> |
10 | * Dirk Behme <Dirk.Behme@gmail.com> |
11 | * |
12 | * -------------------------------------------------------------------------- |
13 | */ |
14 | |
15 | #ifndef __ARCH_ARM_DAVINCI_NAND_H |
16 | #define __ARCH_ARM_DAVINCI_NAND_H |
17 | |
18 | #include <linux/mtd/rawnand.h> |
19 | |
20 | #define NANDFCR_OFFSET 0x60 |
21 | #define NANDFSR_OFFSET 0x64 |
22 | #define NANDF1ECC_OFFSET 0x70 |
23 | |
24 | /* 4-bit ECC syndrome registers */ |
25 | #define NAND_4BIT_ECC_LOAD_OFFSET 0xbc |
26 | #define NAND_4BIT_ECC1_OFFSET 0xc0 |
27 | #define NAND_4BIT_ECC2_OFFSET 0xc4 |
28 | #define NAND_4BIT_ECC3_OFFSET 0xc8 |
29 | #define NAND_4BIT_ECC4_OFFSET 0xcc |
30 | #define NAND_ERR_ADD1_OFFSET 0xd0 |
31 | #define NAND_ERR_ADD2_OFFSET 0xd4 |
32 | #define NAND_ERR_ERRVAL1_OFFSET 0xd8 |
33 | #define NAND_ERR_ERRVAL2_OFFSET 0xdc |
34 | |
35 | /* NOTE: boards don't need to use these address bits |
36 | * for ALE/CLE unless they support booting from NAND. |
37 | * They're used unless platform data overrides them. |
38 | */ |
39 | #define MASK_ALE 0x08 |
40 | #define MASK_CLE 0x10 |
41 | |
42 | struct davinci_nand_pdata { /* platform_data */ |
43 | uint32_t mask_ale; |
44 | uint32_t mask_cle; |
45 | |
46 | /* |
47 | * 0-indexed chip-select number of the asynchronous |
48 | * interface to which the NAND device has been connected. |
49 | * |
50 | * So, if you have NAND connected to CS3 of DA850, you |
51 | * will pass '1' here. Since the asynchronous interface |
52 | * on DA850 starts from CS2. |
53 | */ |
54 | uint32_t core_chipsel; |
55 | |
56 | /* for packages using two chipselects */ |
57 | uint32_t mask_chipsel; |
58 | |
59 | /* board's default static partition info */ |
60 | struct mtd_partition *parts; |
61 | unsigned nr_parts; |
62 | |
63 | /* none == NAND_ECC_ENGINE_TYPE_NONE (strongly *not* advised!!) |
64 | * soft == NAND_ECC_ENGINE_TYPE_SOFT |
65 | * else == NAND_ECC_ENGINE_TYPE_ON_HOST, according to ecc_bits |
66 | * |
67 | * All DaVinci-family chips support 1-bit hardware ECC. |
68 | * Newer ones also support 4-bit ECC, but are awkward |
69 | * using it with large page chips. |
70 | */ |
71 | enum nand_ecc_engine_type engine_type; |
72 | enum nand_ecc_placement ecc_placement; |
73 | u8 ecc_bits; |
74 | |
75 | /* e.g. NAND_BUSWIDTH_16 */ |
76 | unsigned options; |
77 | /* e.g. NAND_BBT_USE_FLASH */ |
78 | unsigned bbt_options; |
79 | |
80 | /* Main and mirror bbt descriptor overrides */ |
81 | struct nand_bbt_descr *bbt_td; |
82 | struct nand_bbt_descr *bbt_md; |
83 | |
84 | /* Access timings */ |
85 | struct davinci_aemif_timing *timing; |
86 | }; |
87 | |
88 | #endif /* __ARCH_ARM_DAVINCI_NAND_H */ |
89 | |