1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * cs42l42.c -- CS42L42 ALSA SoC audio driver |
4 | * |
5 | * Copyright 2016 Cirrus Logic, Inc. |
6 | * |
7 | * Author: James Schulman <james.schulman@cirrus.com> |
8 | * Author: Brian Austin <brian.austin@cirrus.com> |
9 | * Author: Michael White <michael.white@cirrus.com> |
10 | */ |
11 | |
12 | #include <linux/module.h> |
13 | #include <linux/moduleparam.h> |
14 | #include <linux/version.h> |
15 | #include <linux/types.h> |
16 | #include <linux/init.h> |
17 | #include <linux/delay.h> |
18 | #include <linux/regmap.h> |
19 | #include <linux/slab.h> |
20 | #include <linux/acpi.h> |
21 | #include <linux/platform_device.h> |
22 | #include <linux/pm_runtime.h> |
23 | #include <linux/property.h> |
24 | #include <linux/regulator/consumer.h> |
25 | #include <linux/gpio/consumer.h> |
26 | #include <sound/core.h> |
27 | #include <sound/pcm.h> |
28 | #include <sound/pcm_params.h> |
29 | #include <sound/soc.h> |
30 | #include <sound/soc-dapm.h> |
31 | #include <sound/initval.h> |
32 | #include <sound/tlv.h> |
33 | #include <dt-bindings/sound/cs42l42.h> |
34 | |
35 | #include "cs42l42.h" |
36 | #include "cirrus_legacy.h" |
37 | |
38 | static const char * const cs42l42_supply_names[] = { |
39 | "VA" , |
40 | "VP" , |
41 | "VCP" , |
42 | "VD_FILT" , |
43 | "VL" , |
44 | }; |
45 | |
46 | static const struct reg_default cs42l42_reg_defaults[] = { |
47 | { CS42L42_FRZ_CTL, 0x00 }, |
48 | { CS42L42_SRC_CTL, 0x10 }, |
49 | { CS42L42_MCLK_CTL, 0x02 }, |
50 | { CS42L42_SFTRAMP_RATE, 0xA4 }, |
51 | { CS42L42_SLOW_START_ENABLE, 0x70 }, |
52 | { CS42L42_I2C_DEBOUNCE, 0x88 }, |
53 | { CS42L42_I2C_STRETCH, 0x03 }, |
54 | { CS42L42_I2C_TIMEOUT, 0xB7 }, |
55 | { CS42L42_PWR_CTL1, 0xFF }, |
56 | { CS42L42_PWR_CTL2, 0x84 }, |
57 | { CS42L42_PWR_CTL3, 0x20 }, |
58 | { CS42L42_RSENSE_CTL1, 0x40 }, |
59 | { CS42L42_RSENSE_CTL2, 0x00 }, |
60 | { CS42L42_OSC_SWITCH, 0x00 }, |
61 | { CS42L42_RSENSE_CTL3, 0x1B }, |
62 | { CS42L42_TSENSE_CTL, 0x1B }, |
63 | { CS42L42_TSRS_INT_DISABLE, 0x00 }, |
64 | { CS42L42_HSDET_CTL1, 0x77 }, |
65 | { CS42L42_HSDET_CTL2, 0x00 }, |
66 | { CS42L42_HS_SWITCH_CTL, 0xF3 }, |
67 | { CS42L42_HS_CLAMP_DISABLE, 0x00 }, |
68 | { CS42L42_MCLK_SRC_SEL, 0x00 }, |
69 | { CS42L42_SPDIF_CLK_CFG, 0x00 }, |
70 | { CS42L42_FSYNC_PW_LOWER, 0x00 }, |
71 | { CS42L42_FSYNC_PW_UPPER, 0x00 }, |
72 | { CS42L42_FSYNC_P_LOWER, 0xF9 }, |
73 | { CS42L42_FSYNC_P_UPPER, 0x00 }, |
74 | { CS42L42_ASP_CLK_CFG, 0x00 }, |
75 | { CS42L42_ASP_FRM_CFG, 0x10 }, |
76 | { CS42L42_FS_RATE_EN, 0x00 }, |
77 | { CS42L42_IN_ASRC_CLK, 0x00 }, |
78 | { CS42L42_OUT_ASRC_CLK, 0x00 }, |
79 | { CS42L42_PLL_DIV_CFG1, 0x00 }, |
80 | { CS42L42_ADC_OVFL_INT_MASK, 0x01 }, |
81 | { CS42L42_MIXER_INT_MASK, 0x0F }, |
82 | { CS42L42_SRC_INT_MASK, 0x0F }, |
83 | { CS42L42_ASP_RX_INT_MASK, 0x1F }, |
84 | { CS42L42_ASP_TX_INT_MASK, 0x0F }, |
85 | { CS42L42_CODEC_INT_MASK, 0x03 }, |
86 | { CS42L42_SRCPL_INT_MASK, 0x7F }, |
87 | { CS42L42_VPMON_INT_MASK, 0x01 }, |
88 | { CS42L42_PLL_LOCK_INT_MASK, 0x01 }, |
89 | { CS42L42_TSRS_PLUG_INT_MASK, 0x0F }, |
90 | { CS42L42_PLL_CTL1, 0x00 }, |
91 | { CS42L42_PLL_DIV_FRAC0, 0x00 }, |
92 | { CS42L42_PLL_DIV_FRAC1, 0x00 }, |
93 | { CS42L42_PLL_DIV_FRAC2, 0x00 }, |
94 | { CS42L42_PLL_DIV_INT, 0x40 }, |
95 | { CS42L42_PLL_CTL3, 0x10 }, |
96 | { CS42L42_PLL_CAL_RATIO, 0x80 }, |
97 | { CS42L42_PLL_CTL4, 0x03 }, |
98 | { CS42L42_LOAD_DET_EN, 0x00 }, |
99 | { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 }, |
100 | { CS42L42_WAKE_CTL, 0xC0 }, |
101 | { CS42L42_ADC_DISABLE_MUTE, 0x00 }, |
102 | { CS42L42_TIPSENSE_CTL, 0x02 }, |
103 | { CS42L42_MISC_DET_CTL, 0x03 }, |
104 | { CS42L42_MIC_DET_CTL1, 0x1F }, |
105 | { CS42L42_MIC_DET_CTL2, 0x2F }, |
106 | { CS42L42_DET_INT1_MASK, 0xE0 }, |
107 | { CS42L42_DET_INT2_MASK, 0xFF }, |
108 | { CS42L42_HS_BIAS_CTL, 0xC2 }, |
109 | { CS42L42_ADC_CTL, 0x00 }, |
110 | { CS42L42_ADC_VOLUME, 0x00 }, |
111 | { CS42L42_ADC_WNF_HPF_CTL, 0x71 }, |
112 | { CS42L42_DAC_CTL1, 0x00 }, |
113 | { CS42L42_DAC_CTL2, 0x02 }, |
114 | { CS42L42_HP_CTL, 0x0D }, |
115 | { CS42L42_CLASSH_CTL, 0x07 }, |
116 | { CS42L42_MIXER_CHA_VOL, 0x3F }, |
117 | { CS42L42_MIXER_ADC_VOL, 0x3F }, |
118 | { CS42L42_MIXER_CHB_VOL, 0x3F }, |
119 | { CS42L42_EQ_COEF_IN0, 0x00 }, |
120 | { CS42L42_EQ_COEF_IN1, 0x00 }, |
121 | { CS42L42_EQ_COEF_IN2, 0x00 }, |
122 | { CS42L42_EQ_COEF_IN3, 0x00 }, |
123 | { CS42L42_EQ_COEF_RW, 0x00 }, |
124 | { CS42L42_EQ_COEF_OUT0, 0x00 }, |
125 | { CS42L42_EQ_COEF_OUT1, 0x00 }, |
126 | { CS42L42_EQ_COEF_OUT2, 0x00 }, |
127 | { CS42L42_EQ_COEF_OUT3, 0x00 }, |
128 | { CS42L42_EQ_INIT_STAT, 0x00 }, |
129 | { CS42L42_EQ_START_FILT, 0x00 }, |
130 | { CS42L42_EQ_MUTE_CTL, 0x00 }, |
131 | { CS42L42_SP_RX_CH_SEL, 0x04 }, |
132 | { CS42L42_SP_RX_ISOC_CTL, 0x04 }, |
133 | { CS42L42_SP_RX_FS, 0x8C }, |
134 | { CS42l42_SPDIF_CH_SEL, 0x0E }, |
135 | { CS42L42_SP_TX_ISOC_CTL, 0x04 }, |
136 | { CS42L42_SP_TX_FS, 0xCC }, |
137 | { CS42L42_SPDIF_SW_CTL1, 0x3F }, |
138 | { CS42L42_SRC_SDIN_FS, 0x40 }, |
139 | { CS42L42_SRC_SDOUT_FS, 0x40 }, |
140 | { CS42L42_SPDIF_CTL1, 0x01 }, |
141 | { CS42L42_SPDIF_CTL2, 0x00 }, |
142 | { CS42L42_SPDIF_CTL3, 0x00 }, |
143 | { CS42L42_SPDIF_CTL4, 0x42 }, |
144 | { CS42L42_ASP_TX_SZ_EN, 0x00 }, |
145 | { CS42L42_ASP_TX_CH_EN, 0x00 }, |
146 | { CS42L42_ASP_TX_CH_AP_RES, 0x0F }, |
147 | { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 }, |
148 | { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 }, |
149 | { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 }, |
150 | { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 }, |
151 | { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 }, |
152 | { CS42L42_ASP_RX_DAI0_EN, 0x00 }, |
153 | { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 }, |
154 | { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 }, |
155 | { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 }, |
156 | { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 }, |
157 | { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 }, |
158 | { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 }, |
159 | { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 }, |
160 | { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 }, |
161 | { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 }, |
162 | { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 }, |
163 | { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 }, |
164 | { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 }, |
165 | { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 }, |
166 | { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 }, |
167 | { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 }, |
168 | { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 }, |
169 | { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 }, |
170 | { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 }, |
171 | }; |
172 | |
173 | bool cs42l42_readable_register(struct device *dev, unsigned int reg) |
174 | { |
175 | switch (reg) { |
176 | case CS42L42_PAGE_REGISTER: |
177 | case CS42L42_DEVID_AB: |
178 | case CS42L42_DEVID_CD: |
179 | case CS42L42_DEVID_E: |
180 | case CS42L42_FABID: |
181 | case CS42L42_REVID: |
182 | case CS42L42_FRZ_CTL: |
183 | case CS42L42_SRC_CTL: |
184 | case CS42L42_MCLK_STATUS: |
185 | case CS42L42_MCLK_CTL: |
186 | case CS42L42_SFTRAMP_RATE: |
187 | case CS42L42_SLOW_START_ENABLE: |
188 | case CS42L42_I2C_DEBOUNCE: |
189 | case CS42L42_I2C_STRETCH: |
190 | case CS42L42_I2C_TIMEOUT: |
191 | case CS42L42_PWR_CTL1: |
192 | case CS42L42_PWR_CTL2: |
193 | case CS42L42_PWR_CTL3: |
194 | case CS42L42_RSENSE_CTL1: |
195 | case CS42L42_RSENSE_CTL2: |
196 | case CS42L42_OSC_SWITCH: |
197 | case CS42L42_OSC_SWITCH_STATUS: |
198 | case CS42L42_RSENSE_CTL3: |
199 | case CS42L42_TSENSE_CTL: |
200 | case CS42L42_TSRS_INT_DISABLE: |
201 | case CS42L42_TRSENSE_STATUS: |
202 | case CS42L42_HSDET_CTL1: |
203 | case CS42L42_HSDET_CTL2: |
204 | case CS42L42_HS_SWITCH_CTL: |
205 | case CS42L42_HS_DET_STATUS: |
206 | case CS42L42_HS_CLAMP_DISABLE: |
207 | case CS42L42_MCLK_SRC_SEL: |
208 | case CS42L42_SPDIF_CLK_CFG: |
209 | case CS42L42_FSYNC_PW_LOWER: |
210 | case CS42L42_FSYNC_PW_UPPER: |
211 | case CS42L42_FSYNC_P_LOWER: |
212 | case CS42L42_FSYNC_P_UPPER: |
213 | case CS42L42_ASP_CLK_CFG: |
214 | case CS42L42_ASP_FRM_CFG: |
215 | case CS42L42_FS_RATE_EN: |
216 | case CS42L42_IN_ASRC_CLK: |
217 | case CS42L42_OUT_ASRC_CLK: |
218 | case CS42L42_PLL_DIV_CFG1: |
219 | case CS42L42_ADC_OVFL_STATUS: |
220 | case CS42L42_MIXER_STATUS: |
221 | case CS42L42_SRC_STATUS: |
222 | case CS42L42_ASP_RX_STATUS: |
223 | case CS42L42_ASP_TX_STATUS: |
224 | case CS42L42_CODEC_STATUS: |
225 | case CS42L42_DET_INT_STATUS1: |
226 | case CS42L42_DET_INT_STATUS2: |
227 | case CS42L42_SRCPL_INT_STATUS: |
228 | case CS42L42_VPMON_STATUS: |
229 | case CS42L42_PLL_LOCK_STATUS: |
230 | case CS42L42_TSRS_PLUG_STATUS: |
231 | case CS42L42_ADC_OVFL_INT_MASK: |
232 | case CS42L42_MIXER_INT_MASK: |
233 | case CS42L42_SRC_INT_MASK: |
234 | case CS42L42_ASP_RX_INT_MASK: |
235 | case CS42L42_ASP_TX_INT_MASK: |
236 | case CS42L42_CODEC_INT_MASK: |
237 | case CS42L42_SRCPL_INT_MASK: |
238 | case CS42L42_VPMON_INT_MASK: |
239 | case CS42L42_PLL_LOCK_INT_MASK: |
240 | case CS42L42_TSRS_PLUG_INT_MASK: |
241 | case CS42L42_PLL_CTL1: |
242 | case CS42L42_PLL_DIV_FRAC0: |
243 | case CS42L42_PLL_DIV_FRAC1: |
244 | case CS42L42_PLL_DIV_FRAC2: |
245 | case CS42L42_PLL_DIV_INT: |
246 | case CS42L42_PLL_CTL3: |
247 | case CS42L42_PLL_CAL_RATIO: |
248 | case CS42L42_PLL_CTL4: |
249 | case CS42L42_LOAD_DET_RCSTAT: |
250 | case CS42L42_LOAD_DET_DONE: |
251 | case CS42L42_LOAD_DET_EN: |
252 | case CS42L42_HSBIAS_SC_AUTOCTL: |
253 | case CS42L42_WAKE_CTL: |
254 | case CS42L42_ADC_DISABLE_MUTE: |
255 | case CS42L42_TIPSENSE_CTL: |
256 | case CS42L42_MISC_DET_CTL: |
257 | case CS42L42_MIC_DET_CTL1: |
258 | case CS42L42_MIC_DET_CTL2: |
259 | case CS42L42_DET_STATUS1: |
260 | case CS42L42_DET_STATUS2: |
261 | case CS42L42_DET_INT1_MASK: |
262 | case CS42L42_DET_INT2_MASK: |
263 | case CS42L42_HS_BIAS_CTL: |
264 | case CS42L42_ADC_CTL: |
265 | case CS42L42_ADC_VOLUME: |
266 | case CS42L42_ADC_WNF_HPF_CTL: |
267 | case CS42L42_DAC_CTL1: |
268 | case CS42L42_DAC_CTL2: |
269 | case CS42L42_HP_CTL: |
270 | case CS42L42_CLASSH_CTL: |
271 | case CS42L42_MIXER_CHA_VOL: |
272 | case CS42L42_MIXER_ADC_VOL: |
273 | case CS42L42_MIXER_CHB_VOL: |
274 | case CS42L42_EQ_COEF_IN0: |
275 | case CS42L42_EQ_COEF_IN1: |
276 | case CS42L42_EQ_COEF_IN2: |
277 | case CS42L42_EQ_COEF_IN3: |
278 | case CS42L42_EQ_COEF_RW: |
279 | case CS42L42_EQ_COEF_OUT0: |
280 | case CS42L42_EQ_COEF_OUT1: |
281 | case CS42L42_EQ_COEF_OUT2: |
282 | case CS42L42_EQ_COEF_OUT3: |
283 | case CS42L42_EQ_INIT_STAT: |
284 | case CS42L42_EQ_START_FILT: |
285 | case CS42L42_EQ_MUTE_CTL: |
286 | case CS42L42_SP_RX_CH_SEL: |
287 | case CS42L42_SP_RX_ISOC_CTL: |
288 | case CS42L42_SP_RX_FS: |
289 | case CS42l42_SPDIF_CH_SEL: |
290 | case CS42L42_SP_TX_ISOC_CTL: |
291 | case CS42L42_SP_TX_FS: |
292 | case CS42L42_SPDIF_SW_CTL1: |
293 | case CS42L42_SRC_SDIN_FS: |
294 | case CS42L42_SRC_SDOUT_FS: |
295 | case CS42L42_SOFT_RESET_REBOOT: |
296 | case CS42L42_SPDIF_CTL1: |
297 | case CS42L42_SPDIF_CTL2: |
298 | case CS42L42_SPDIF_CTL3: |
299 | case CS42L42_SPDIF_CTL4: |
300 | case CS42L42_ASP_TX_SZ_EN: |
301 | case CS42L42_ASP_TX_CH_EN: |
302 | case CS42L42_ASP_TX_CH_AP_RES: |
303 | case CS42L42_ASP_TX_CH1_BIT_MSB: |
304 | case CS42L42_ASP_TX_CH1_BIT_LSB: |
305 | case CS42L42_ASP_TX_HIZ_DLY_CFG: |
306 | case CS42L42_ASP_TX_CH2_BIT_MSB: |
307 | case CS42L42_ASP_TX_CH2_BIT_LSB: |
308 | case CS42L42_ASP_RX_DAI0_EN: |
309 | case CS42L42_ASP_RX_DAI0_CH1_AP_RES: |
310 | case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB: |
311 | case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB: |
312 | case CS42L42_ASP_RX_DAI0_CH2_AP_RES: |
313 | case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB: |
314 | case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB: |
315 | case CS42L42_ASP_RX_DAI0_CH3_AP_RES: |
316 | case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB: |
317 | case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB: |
318 | case CS42L42_ASP_RX_DAI0_CH4_AP_RES: |
319 | case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB: |
320 | case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB: |
321 | case CS42L42_ASP_RX_DAI1_CH1_AP_RES: |
322 | case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB: |
323 | case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB: |
324 | case CS42L42_ASP_RX_DAI1_CH2_AP_RES: |
325 | case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB: |
326 | case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB: |
327 | case CS42L42_SUB_REVID: |
328 | return true; |
329 | default: |
330 | return false; |
331 | } |
332 | } |
333 | EXPORT_SYMBOL_NS_GPL(cs42l42_readable_register, SND_SOC_CS42L42_CORE); |
334 | |
335 | bool cs42l42_volatile_register(struct device *dev, unsigned int reg) |
336 | { |
337 | switch (reg) { |
338 | case CS42L42_DEVID_AB: |
339 | case CS42L42_DEVID_CD: |
340 | case CS42L42_DEVID_E: |
341 | case CS42L42_MCLK_STATUS: |
342 | case CS42L42_OSC_SWITCH_STATUS: |
343 | case CS42L42_TRSENSE_STATUS: |
344 | case CS42L42_HS_DET_STATUS: |
345 | case CS42L42_ADC_OVFL_STATUS: |
346 | case CS42L42_MIXER_STATUS: |
347 | case CS42L42_SRC_STATUS: |
348 | case CS42L42_ASP_RX_STATUS: |
349 | case CS42L42_ASP_TX_STATUS: |
350 | case CS42L42_CODEC_STATUS: |
351 | case CS42L42_DET_INT_STATUS1: |
352 | case CS42L42_DET_INT_STATUS2: |
353 | case CS42L42_SRCPL_INT_STATUS: |
354 | case CS42L42_VPMON_STATUS: |
355 | case CS42L42_PLL_LOCK_STATUS: |
356 | case CS42L42_TSRS_PLUG_STATUS: |
357 | case CS42L42_LOAD_DET_RCSTAT: |
358 | case CS42L42_LOAD_DET_DONE: |
359 | case CS42L42_DET_STATUS1: |
360 | case CS42L42_DET_STATUS2: |
361 | case CS42L42_SOFT_RESET_REBOOT: |
362 | return true; |
363 | default: |
364 | return false; |
365 | } |
366 | } |
367 | EXPORT_SYMBOL_NS_GPL(cs42l42_volatile_register, SND_SOC_CS42L42_CORE); |
368 | |
369 | const struct regmap_range_cfg cs42l42_page_range = { |
370 | .name = "Pages" , |
371 | .range_min = 0, |
372 | .range_max = CS42L42_MAX_REGISTER, |
373 | .selector_reg = CS42L42_PAGE_REGISTER, |
374 | .selector_mask = 0xff, |
375 | .selector_shift = 0, |
376 | .window_start = 0, |
377 | .window_len = 256, |
378 | }; |
379 | EXPORT_SYMBOL_NS_GPL(cs42l42_page_range, SND_SOC_CS42L42_CORE); |
380 | |
381 | const struct regmap_config cs42l42_regmap = { |
382 | .reg_bits = 8, |
383 | .val_bits = 8, |
384 | |
385 | .readable_reg = cs42l42_readable_register, |
386 | .volatile_reg = cs42l42_volatile_register, |
387 | |
388 | .ranges = &cs42l42_page_range, |
389 | .num_ranges = 1, |
390 | |
391 | .max_register = CS42L42_MAX_REGISTER, |
392 | .reg_defaults = cs42l42_reg_defaults, |
393 | .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults), |
394 | .cache_type = REGCACHE_MAPLE, |
395 | |
396 | .use_single_read = true, |
397 | .use_single_write = true, |
398 | }; |
399 | EXPORT_SYMBOL_NS_GPL(cs42l42_regmap, SND_SOC_CS42L42_CORE); |
400 | |
401 | static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true); |
402 | static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true); |
403 | |
404 | static int cs42l42_slow_start_put(struct snd_kcontrol *kcontrol, |
405 | struct snd_ctl_elem_value *ucontrol) |
406 | { |
407 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
408 | u8 val; |
409 | |
410 | /* all bits of SLOW_START_EN must change together */ |
411 | switch (ucontrol->value.integer.value[0]) { |
412 | case 0: |
413 | val = 0; |
414 | break; |
415 | case 1: |
416 | val = CS42L42_SLOW_START_EN_MASK; |
417 | break; |
418 | default: |
419 | return -EINVAL; |
420 | } |
421 | |
422 | return snd_soc_component_update_bits(component, CS42L42_SLOW_START_ENABLE, |
423 | CS42L42_SLOW_START_EN_MASK, val); |
424 | } |
425 | |
426 | static const char * const cs42l42_hpf_freq_text[] = { |
427 | "1.86Hz" , "120Hz" , "235Hz" , "466Hz" |
428 | }; |
429 | |
430 | static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL, |
431 | CS42L42_ADC_HPF_CF_SHIFT, |
432 | cs42l42_hpf_freq_text); |
433 | |
434 | static const char * const cs42l42_wnf3_freq_text[] = { |
435 | "160Hz" , "180Hz" , "200Hz" , "220Hz" , |
436 | "240Hz" , "260Hz" , "280Hz" , "300Hz" |
437 | }; |
438 | |
439 | static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL, |
440 | CS42L42_ADC_WNF_CF_SHIFT, |
441 | cs42l42_wnf3_freq_text); |
442 | |
443 | static const struct snd_kcontrol_new cs42l42_snd_controls[] = { |
444 | /* ADC Volume and Filter Controls */ |
445 | SOC_SINGLE("ADC Notch Switch" , CS42L42_ADC_CTL, |
446 | CS42L42_ADC_NOTCH_DIS_SHIFT, true, true), |
447 | SOC_SINGLE("ADC Weak Force Switch" , CS42L42_ADC_CTL, |
448 | CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false), |
449 | SOC_SINGLE("ADC Invert Switch" , CS42L42_ADC_CTL, |
450 | CS42L42_ADC_INV_SHIFT, true, false), |
451 | SOC_SINGLE("ADC Boost Switch" , CS42L42_ADC_CTL, |
452 | CS42L42_ADC_DIG_BOOST_SHIFT, true, false), |
453 | SOC_SINGLE_S8_TLV("ADC Volume" , CS42L42_ADC_VOLUME, -97, 12, adc_tlv), |
454 | SOC_SINGLE("ADC WNF Switch" , CS42L42_ADC_WNF_HPF_CTL, |
455 | CS42L42_ADC_WNF_EN_SHIFT, true, false), |
456 | SOC_SINGLE("ADC HPF Switch" , CS42L42_ADC_WNF_HPF_CTL, |
457 | CS42L42_ADC_HPF_EN_SHIFT, true, false), |
458 | SOC_ENUM("HPF Corner Freq" , cs42l42_hpf_freq_enum), |
459 | SOC_ENUM("WNF 3dB Freq" , cs42l42_wnf3_freq_enum), |
460 | |
461 | /* DAC Volume and Filter Controls */ |
462 | SOC_SINGLE("DACA Invert Switch" , CS42L42_DAC_CTL1, |
463 | CS42L42_DACA_INV_SHIFT, true, false), |
464 | SOC_SINGLE("DACB Invert Switch" , CS42L42_DAC_CTL1, |
465 | CS42L42_DACB_INV_SHIFT, true, false), |
466 | SOC_SINGLE("DAC HPF Switch" , CS42L42_DAC_CTL2, |
467 | CS42L42_DAC_HPF_EN_SHIFT, true, false), |
468 | SOC_DOUBLE_R_TLV("Mixer Volume" , CS42L42_MIXER_CHA_VOL, |
469 | CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT, |
470 | 0x3f, 1, mixer_tlv), |
471 | |
472 | SOC_SINGLE_EXT("Slow Start Switch" , CS42L42_SLOW_START_ENABLE, |
473 | CS42L42_SLOW_START_EN_SHIFT, true, false, |
474 | snd_soc_get_volsw, cs42l42_slow_start_put), |
475 | }; |
476 | |
477 | static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w, |
478 | struct snd_kcontrol *kcontrol, int event) |
479 | { |
480 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
481 | struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(c: component); |
482 | |
483 | switch (event) { |
484 | case SND_SOC_DAPM_PRE_PMU: |
485 | cs42l42->hp_adc_up_pending = true; |
486 | break; |
487 | case SND_SOC_DAPM_POST_PMU: |
488 | /* Only need one delay if HP and ADC are both powering-up */ |
489 | if (cs42l42->hp_adc_up_pending) { |
490 | usleep_range(CS42L42_HP_ADC_EN_TIME_US, |
491 | CS42L42_HP_ADC_EN_TIME_US + 1000); |
492 | cs42l42->hp_adc_up_pending = false; |
493 | } |
494 | break; |
495 | default: |
496 | break; |
497 | } |
498 | |
499 | return 0; |
500 | } |
501 | |
502 | static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = { |
503 | /* Playback Path */ |
504 | SND_SOC_DAPM_OUTPUT("HP" ), |
505 | SND_SOC_DAPM_DAC_E("DAC" , NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1, |
506 | cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), |
507 | SND_SOC_DAPM_MIXER("MIXER" , CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0), |
508 | SND_SOC_DAPM_AIF_IN("SDIN1" , NULL, 0, SND_SOC_NOPM, 0, 0), |
509 | SND_SOC_DAPM_AIF_IN("SDIN2" , NULL, 1, SND_SOC_NOPM, 0, 0), |
510 | |
511 | /* Playback Requirements */ |
512 | SND_SOC_DAPM_SUPPLY("ASP DAI0" , CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0), |
513 | |
514 | /* Capture Path */ |
515 | SND_SOC_DAPM_INPUT("HS" ), |
516 | SND_SOC_DAPM_ADC_E("ADC" , NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1, |
517 | cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU), |
518 | SND_SOC_DAPM_AIF_OUT("SDOUT1" , NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0), |
519 | SND_SOC_DAPM_AIF_OUT("SDOUT2" , NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0), |
520 | |
521 | /* Capture Requirements */ |
522 | SND_SOC_DAPM_SUPPLY("ASP DAO0" , CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0), |
523 | SND_SOC_DAPM_SUPPLY("ASP TX EN" , CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0), |
524 | |
525 | /* Playback/Capture Requirements */ |
526 | SND_SOC_DAPM_SUPPLY("SCLK" , CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0), |
527 | |
528 | /* Soundwire SRC power control */ |
529 | SND_SOC_DAPM_PGA("DACSRC" , CS42L42_PWR_CTL2, CS42L42_DAC_SRC_PDNB_SHIFT, 0, NULL, 0), |
530 | SND_SOC_DAPM_PGA("ADCSRC" , CS42L42_PWR_CTL2, CS42L42_ADC_SRC_PDNB_SHIFT, 0, NULL, 0), |
531 | }; |
532 | |
533 | static const struct snd_soc_dapm_route cs42l42_audio_map[] = { |
534 | /* Playback Path */ |
535 | {"HP" , NULL, "DAC" }, |
536 | {"DAC" , NULL, "MIXER" }, |
537 | {"MIXER" , NULL, "SDIN1" }, |
538 | {"MIXER" , NULL, "SDIN2" }, |
539 | {"SDIN1" , NULL, "Playback" }, |
540 | {"SDIN2" , NULL, "Playback" }, |
541 | |
542 | /* Playback Requirements */ |
543 | {"SDIN1" , NULL, "ASP DAI0" }, |
544 | {"SDIN2" , NULL, "ASP DAI0" }, |
545 | {"SDIN1" , NULL, "SCLK" }, |
546 | {"SDIN2" , NULL, "SCLK" }, |
547 | |
548 | /* Capture Path */ |
549 | {"ADC" , NULL, "HS" }, |
550 | { "SDOUT1" , NULL, "ADC" }, |
551 | { "SDOUT2" , NULL, "ADC" }, |
552 | { "Capture" , NULL, "SDOUT1" }, |
553 | { "Capture" , NULL, "SDOUT2" }, |
554 | |
555 | /* Capture Requirements */ |
556 | { "SDOUT1" , NULL, "ASP DAO0" }, |
557 | { "SDOUT2" , NULL, "ASP DAO0" }, |
558 | { "SDOUT1" , NULL, "SCLK" }, |
559 | { "SDOUT2" , NULL, "SCLK" }, |
560 | { "SDOUT1" , NULL, "ASP TX EN" }, |
561 | { "SDOUT2" , NULL, "ASP TX EN" }, |
562 | }; |
563 | |
564 | static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d) |
565 | { |
566 | struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(c: component); |
567 | |
568 | /* Prevent race with interrupt handler */ |
569 | mutex_lock(&cs42l42->irq_lock); |
570 | cs42l42->jack = jk; |
571 | |
572 | if (jk) { |
573 | switch (cs42l42->hs_type) { |
574 | case CS42L42_PLUG_CTIA: |
575 | case CS42L42_PLUG_OMTP: |
576 | snd_soc_jack_report(jack: jk, status: SND_JACK_HEADSET, mask: SND_JACK_HEADSET); |
577 | break; |
578 | case CS42L42_PLUG_HEADPHONE: |
579 | snd_soc_jack_report(jack: jk, status: SND_JACK_HEADPHONE, mask: SND_JACK_HEADPHONE); |
580 | break; |
581 | default: |
582 | break; |
583 | } |
584 | } |
585 | mutex_unlock(lock: &cs42l42->irq_lock); |
586 | |
587 | return 0; |
588 | } |
589 | |
590 | const struct snd_soc_component_driver cs42l42_soc_component = { |
591 | .set_jack = cs42l42_set_jack, |
592 | .dapm_widgets = cs42l42_dapm_widgets, |
593 | .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets), |
594 | .dapm_routes = cs42l42_audio_map, |
595 | .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map), |
596 | .controls = cs42l42_snd_controls, |
597 | .num_controls = ARRAY_SIZE(cs42l42_snd_controls), |
598 | .endianness = 1, |
599 | }; |
600 | EXPORT_SYMBOL_NS_GPL(cs42l42_soc_component, SND_SOC_CS42L42_CORE); |
601 | |
602 | /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */ |
603 | static const struct reg_sequence cs42l42_to_sclk_seq[] = { |
604 | { |
605 | .reg = CS42L42_OSC_SWITCH, |
606 | .def = CS42L42_SCLK_PRESENT_MASK, |
607 | .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, |
608 | }, |
609 | }; |
610 | |
611 | /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */ |
612 | static const struct reg_sequence cs42l42_to_osc_seq[] = { |
613 | { |
614 | .reg = CS42L42_OSC_SWITCH, |
615 | .def = 0, |
616 | .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US, |
617 | }, |
618 | }; |
619 | |
620 | struct cs42l42_pll_params { |
621 | u32 sclk; |
622 | u8 mclk_src_sel; |
623 | u8 sclk_prediv; |
624 | u8 pll_div_int; |
625 | u32 pll_div_frac; |
626 | u8 pll_mode; |
627 | u8 pll_divout; |
628 | u32 mclk_int; |
629 | u8 pll_cal_ratio; |
630 | u8 n; |
631 | }; |
632 | |
633 | /* |
634 | * Common PLL Settings for given SCLK |
635 | * Table 4-5 from the Datasheet |
636 | */ |
637 | static const struct cs42l42_pll_params pll_ratio_table[] = { |
638 | { 1411200, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2}, |
639 | { 1536000, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2}, |
640 | { 2304000, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2}, |
641 | { 2400000, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, |
642 | { 2822400, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, |
643 | { 3000000, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, |
644 | { 3072000, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, |
645 | { 4000000, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96, 1}, |
646 | { 4096000, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94, 1}, |
647 | { 4800000, 1, 0x01, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, |
648 | { 4800000, 1, 0x01, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2}, |
649 | { 5644800, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, |
650 | { 6000000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, |
651 | { 6144000, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1}, |
652 | { 6144000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}, |
653 | { 9600000, 1, 0x02, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, |
654 | { 9600000, 1, 0x02, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2}, |
655 | { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1}, |
656 | { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1}, |
657 | { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1}, |
658 | { 19200000, 1, 0x03, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2}, |
659 | { 19200000, 1, 0x03, 0x50, 0x000000, 0x01, 0x10, 12288000, 82, 2}, |
660 | { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1}, |
661 | { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1}, |
662 | { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1} |
663 | }; |
664 | |
665 | int cs42l42_pll_config(struct snd_soc_component *component, unsigned int clk, |
666 | unsigned int sample_rate) |
667 | { |
668 | struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(c: component); |
669 | int i; |
670 | |
671 | /* Don't reconfigure if there is an audio stream running */ |
672 | if (cs42l42->stream_use) { |
673 | if (pll_ratio_table[cs42l42->pll_config].sclk == clk) |
674 | return 0; |
675 | else |
676 | return -EBUSY; |
677 | } |
678 | |
679 | for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { |
680 | /* MCLKint must be a multiple of the sample rate */ |
681 | if (pll_ratio_table[i].mclk_int % sample_rate) |
682 | continue; |
683 | |
684 | if (pll_ratio_table[i].sclk == clk) { |
685 | cs42l42->pll_config = i; |
686 | |
687 | /* Configure the internal sample rate */ |
688 | snd_soc_component_update_bits(component, CS42L42_MCLK_CTL, |
689 | CS42L42_INTERNAL_FS_MASK, |
690 | val: ((pll_ratio_table[i].mclk_int != |
691 | 12000000) && |
692 | (pll_ratio_table[i].mclk_int != |
693 | 24000000)) << |
694 | CS42L42_INTERNAL_FS_SHIFT); |
695 | if (pll_ratio_table[i].mclk_src_sel == 0) { |
696 | /* Pass the clock straight through */ |
697 | snd_soc_component_update_bits(component, |
698 | CS42L42_PLL_CTL1, |
699 | CS42L42_PLL_START_MASK, val: 0); |
700 | } else { |
701 | /* Configure PLL per table 4-5 */ |
702 | snd_soc_component_update_bits(component, |
703 | CS42L42_PLL_DIV_CFG1, |
704 | CS42L42_SCLK_PREDIV_MASK, |
705 | val: pll_ratio_table[i].sclk_prediv |
706 | << CS42L42_SCLK_PREDIV_SHIFT); |
707 | snd_soc_component_update_bits(component, |
708 | CS42L42_PLL_DIV_INT, |
709 | CS42L42_PLL_DIV_INT_MASK, |
710 | val: pll_ratio_table[i].pll_div_int |
711 | << CS42L42_PLL_DIV_INT_SHIFT); |
712 | snd_soc_component_update_bits(component, |
713 | CS42L42_PLL_DIV_FRAC0, |
714 | CS42L42_PLL_DIV_FRAC_MASK, |
715 | CS42L42_FRAC0_VAL( |
716 | pll_ratio_table[i].pll_div_frac) |
717 | << CS42L42_PLL_DIV_FRAC_SHIFT); |
718 | snd_soc_component_update_bits(component, |
719 | CS42L42_PLL_DIV_FRAC1, |
720 | CS42L42_PLL_DIV_FRAC_MASK, |
721 | CS42L42_FRAC1_VAL( |
722 | pll_ratio_table[i].pll_div_frac) |
723 | << CS42L42_PLL_DIV_FRAC_SHIFT); |
724 | snd_soc_component_update_bits(component, |
725 | CS42L42_PLL_DIV_FRAC2, |
726 | CS42L42_PLL_DIV_FRAC_MASK, |
727 | CS42L42_FRAC2_VAL( |
728 | pll_ratio_table[i].pll_div_frac) |
729 | << CS42L42_PLL_DIV_FRAC_SHIFT); |
730 | snd_soc_component_update_bits(component, |
731 | CS42L42_PLL_CTL4, |
732 | CS42L42_PLL_MODE_MASK, |
733 | val: pll_ratio_table[i].pll_mode |
734 | << CS42L42_PLL_MODE_SHIFT); |
735 | snd_soc_component_update_bits(component, |
736 | CS42L42_PLL_CTL3, |
737 | CS42L42_PLL_DIVOUT_MASK, |
738 | val: (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n) |
739 | << CS42L42_PLL_DIVOUT_SHIFT); |
740 | snd_soc_component_update_bits(component, |
741 | CS42L42_PLL_CAL_RATIO, |
742 | CS42L42_PLL_CAL_RATIO_MASK, |
743 | val: pll_ratio_table[i].pll_cal_ratio |
744 | << CS42L42_PLL_CAL_RATIO_SHIFT); |
745 | } |
746 | return 0; |
747 | } |
748 | } |
749 | |
750 | return -EINVAL; |
751 | } |
752 | EXPORT_SYMBOL_NS_GPL(cs42l42_pll_config, SND_SOC_CS42L42_CORE); |
753 | |
754 | void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate) |
755 | { |
756 | struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(c: component); |
757 | unsigned int fs; |
758 | |
759 | /* Don't reconfigure if there is an audio stream running */ |
760 | if (cs42l42->stream_use) |
761 | return; |
762 | |
763 | /* SRC MCLK must be as close as possible to 125 * sample rate */ |
764 | if (sample_rate <= 48000) |
765 | fs = CS42L42_CLK_IASRC_SEL_6; |
766 | else |
767 | fs = CS42L42_CLK_IASRC_SEL_12; |
768 | |
769 | /* Set the sample rates (96k or lower) */ |
770 | snd_soc_component_update_bits(component, |
771 | CS42L42_FS_RATE_EN, |
772 | CS42L42_FS_EN_MASK, |
773 | val: (CS42L42_FS_EN_IASRC_96K | |
774 | CS42L42_FS_EN_OASRC_96K) << |
775 | CS42L42_FS_EN_SHIFT); |
776 | |
777 | snd_soc_component_update_bits(component, |
778 | CS42L42_IN_ASRC_CLK, |
779 | CS42L42_CLK_IASRC_SEL_MASK, |
780 | val: fs << CS42L42_CLK_IASRC_SEL_SHIFT); |
781 | snd_soc_component_update_bits(component, |
782 | CS42L42_OUT_ASRC_CLK, |
783 | CS42L42_CLK_OASRC_SEL_MASK, |
784 | val: fs << CS42L42_CLK_OASRC_SEL_SHIFT); |
785 | } |
786 | EXPORT_SYMBOL_NS_GPL(cs42l42_src_config, SND_SOC_CS42L42_CORE); |
787 | |
788 | static int cs42l42_asp_config(struct snd_soc_component *component, |
789 | unsigned int sclk, unsigned int sample_rate) |
790 | { |
791 | u32 fsync = sclk / sample_rate; |
792 | |
793 | /* Set up the LRCLK */ |
794 | if (((fsync * sample_rate) != sclk) || ((fsync % 2) != 0)) { |
795 | dev_err(component->dev, |
796 | "Unsupported sclk %d/sample rate %d\n" , |
797 | sclk, |
798 | sample_rate); |
799 | return -EINVAL; |
800 | } |
801 | /* Set the LRCLK period */ |
802 | snd_soc_component_update_bits(component, |
803 | CS42L42_FSYNC_P_LOWER, |
804 | CS42L42_FSYNC_PERIOD_MASK, |
805 | CS42L42_FRAC0_VAL(fsync - 1) << |
806 | CS42L42_FSYNC_PERIOD_SHIFT); |
807 | snd_soc_component_update_bits(component, |
808 | CS42L42_FSYNC_P_UPPER, |
809 | CS42L42_FSYNC_PERIOD_MASK, |
810 | CS42L42_FRAC1_VAL(fsync - 1) << |
811 | CS42L42_FSYNC_PERIOD_SHIFT); |
812 | /* Set the LRCLK to 50% duty cycle */ |
813 | fsync = fsync / 2; |
814 | snd_soc_component_update_bits(component, |
815 | CS42L42_FSYNC_PW_LOWER, |
816 | CS42L42_FSYNC_PULSE_WIDTH_MASK, |
817 | CS42L42_FRAC0_VAL(fsync - 1) << |
818 | CS42L42_FSYNC_PULSE_WIDTH_SHIFT); |
819 | snd_soc_component_update_bits(component, |
820 | CS42L42_FSYNC_PW_UPPER, |
821 | CS42L42_FSYNC_PULSE_WIDTH_MASK, |
822 | CS42L42_FRAC1_VAL(fsync - 1) << |
823 | CS42L42_FSYNC_PULSE_WIDTH_SHIFT); |
824 | |
825 | return 0; |
826 | } |
827 | |
828 | static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) |
829 | { |
830 | struct snd_soc_component *component = codec_dai->component; |
831 | u32 asp_cfg_val = 0; |
832 | |
833 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
834 | case SND_SOC_DAIFMT_CBS_CFM: |
835 | asp_cfg_val |= CS42L42_ASP_MASTER_MODE << |
836 | CS42L42_ASP_MODE_SHIFT; |
837 | break; |
838 | case SND_SOC_DAIFMT_CBS_CFS: |
839 | asp_cfg_val |= CS42L42_ASP_SLAVE_MODE << |
840 | CS42L42_ASP_MODE_SHIFT; |
841 | break; |
842 | default: |
843 | return -EINVAL; |
844 | } |
845 | |
846 | /* interface format */ |
847 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
848 | case SND_SOC_DAIFMT_I2S: |
849 | /* |
850 | * 5050 mode, frame starts on falling edge of LRCLK, |
851 | * frame delayed by 1.0 SCLKs |
852 | */ |
853 | snd_soc_component_update_bits(component, |
854 | CS42L42_ASP_FRM_CFG, |
855 | CS42L42_ASP_STP_MASK | |
856 | CS42L42_ASP_5050_MASK | |
857 | CS42L42_ASP_FSD_MASK, |
858 | CS42L42_ASP_5050_MASK | |
859 | (CS42L42_ASP_FSD_1_0 << |
860 | CS42L42_ASP_FSD_SHIFT)); |
861 | break; |
862 | default: |
863 | return -EINVAL; |
864 | } |
865 | |
866 | /* Bitclock/frame inversion */ |
867 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
868 | case SND_SOC_DAIFMT_NB_NF: |
869 | asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; |
870 | break; |
871 | case SND_SOC_DAIFMT_NB_IF: |
872 | asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT; |
873 | asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; |
874 | break; |
875 | case SND_SOC_DAIFMT_IB_NF: |
876 | break; |
877 | case SND_SOC_DAIFMT_IB_IF: |
878 | asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT; |
879 | break; |
880 | } |
881 | |
882 | snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK | |
883 | CS42L42_ASP_SCPOL_MASK | |
884 | CS42L42_ASP_LCPOL_MASK, |
885 | val: asp_cfg_val); |
886 | |
887 | return 0; |
888 | } |
889 | |
890 | static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) |
891 | { |
892 | struct snd_soc_component *component = dai->component; |
893 | struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(c: component); |
894 | |
895 | /* |
896 | * Sample rates < 44.1 kHz would produce an out-of-range SCLK with |
897 | * a standard I2S frame. If the machine driver sets SCLK it must be |
898 | * legal. |
899 | */ |
900 | if (cs42l42->sclk) |
901 | return 0; |
902 | |
903 | /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */ |
904 | return snd_pcm_hw_constraint_minmax(runtime: substream->runtime, |
905 | SNDRV_PCM_HW_PARAM_RATE, |
906 | min: 44100, max: 96000); |
907 | } |
908 | |
909 | static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream, |
910 | struct snd_pcm_hw_params *params, |
911 | struct snd_soc_dai *dai) |
912 | { |
913 | struct snd_soc_component *component = dai->component; |
914 | struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(c: component); |
915 | unsigned int channels = params_channels(p: params); |
916 | unsigned int width = (params_width(p: params) / 8) - 1; |
917 | unsigned int sample_rate = params_rate(p: params); |
918 | unsigned int slot_width = 0; |
919 | unsigned int val = 0; |
920 | unsigned int bclk; |
921 | int ret; |
922 | |
923 | if (cs42l42->bclk_ratio) { |
924 | /* machine driver has set the BCLK/samp-rate ratio */ |
925 | bclk = cs42l42->bclk_ratio * params_rate(p: params); |
926 | } else if (cs42l42->sclk) { |
927 | /* machine driver has set the SCLK */ |
928 | bclk = cs42l42->sclk; |
929 | } else { |
930 | /* |
931 | * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being |
932 | * more than assumed (which would result in overclocking). |
933 | */ |
934 | if (params_width(p: params) == 24) |
935 | slot_width = 32; |
936 | |
937 | /* I2S frame always has multiple of 2 channels */ |
938 | bclk = snd_soc_tdm_params_to_bclk(params, tdm_width: slot_width, tdm_slots: 0, slot_multiple: 2); |
939 | } |
940 | |
941 | switch (substream->stream) { |
942 | case SNDRV_PCM_STREAM_CAPTURE: |
943 | /* channel 2 on high LRCLK */ |
944 | val = CS42L42_ASP_TX_CH2_AP_MASK | |
945 | (width << CS42L42_ASP_TX_CH2_RES_SHIFT) | |
946 | (width << CS42L42_ASP_TX_CH1_RES_SHIFT); |
947 | |
948 | snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES, |
949 | CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK | |
950 | CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val); |
951 | break; |
952 | case SNDRV_PCM_STREAM_PLAYBACK: |
953 | val |= width << CS42L42_ASP_RX_CH_RES_SHIFT; |
954 | /* channel 1 on low LRCLK */ |
955 | snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES, |
956 | CS42L42_ASP_RX_CH_AP_MASK | |
957 | CS42L42_ASP_RX_CH_RES_MASK, val); |
958 | /* Channel 2 on high LRCLK */ |
959 | val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT; |
960 | snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES, |
961 | CS42L42_ASP_RX_CH_AP_MASK | |
962 | CS42L42_ASP_RX_CH_RES_MASK, val); |
963 | |
964 | /* Channel B comes from the last active channel */ |
965 | snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL, |
966 | CS42L42_SP_RX_CHB_SEL_MASK, |
967 | val: (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT); |
968 | |
969 | /* Both LRCLK slots must be enabled */ |
970 | snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN, |
971 | CS42L42_ASP_RX0_CH_EN_MASK, |
972 | BIT(CS42L42_ASP_RX0_CH1_SHIFT) | |
973 | BIT(CS42L42_ASP_RX0_CH2_SHIFT)); |
974 | break; |
975 | default: |
976 | break; |
977 | } |
978 | |
979 | ret = cs42l42_pll_config(component, bclk, sample_rate); |
980 | if (ret) |
981 | return ret; |
982 | |
983 | ret = cs42l42_asp_config(component, sclk: bclk, sample_rate); |
984 | if (ret) |
985 | return ret; |
986 | |
987 | cs42l42_src_config(component, sample_rate); |
988 | |
989 | return 0; |
990 | } |
991 | |
992 | static int cs42l42_set_sysclk(struct snd_soc_dai *dai, |
993 | int clk_id, unsigned int freq, int dir) |
994 | { |
995 | struct snd_soc_component *component = dai->component; |
996 | struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(c: component); |
997 | int i; |
998 | |
999 | if (freq == 0) { |
1000 | cs42l42->sclk = 0; |
1001 | return 0; |
1002 | } |
1003 | |
1004 | for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { |
1005 | if (pll_ratio_table[i].sclk == freq) { |
1006 | cs42l42->sclk = freq; |
1007 | return 0; |
1008 | } |
1009 | } |
1010 | |
1011 | dev_err(component->dev, "SCLK %u not supported\n" , freq); |
1012 | |
1013 | return -EINVAL; |
1014 | } |
1015 | |
1016 | static int cs42l42_set_bclk_ratio(struct snd_soc_dai *dai, |
1017 | unsigned int bclk_ratio) |
1018 | { |
1019 | struct snd_soc_component *component = dai->component; |
1020 | struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(c: component); |
1021 | |
1022 | cs42l42->bclk_ratio = bclk_ratio; |
1023 | |
1024 | return 0; |
1025 | } |
1026 | |
1027 | int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) |
1028 | { |
1029 | struct snd_soc_component *component = dai->component; |
1030 | struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(c: component); |
1031 | unsigned int regval; |
1032 | int ret; |
1033 | |
1034 | if (mute) { |
1035 | /* Mute the headphone */ |
1036 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
1037 | snd_soc_component_update_bits(component, CS42L42_HP_CTL, |
1038 | CS42L42_HP_ANA_AMUTE_MASK | |
1039 | CS42L42_HP_ANA_BMUTE_MASK, |
1040 | CS42L42_HP_ANA_AMUTE_MASK | |
1041 | CS42L42_HP_ANA_BMUTE_MASK); |
1042 | |
1043 | cs42l42->stream_use &= ~(1 << stream); |
1044 | if (!cs42l42->stream_use) { |
1045 | /* |
1046 | * Switch to the internal oscillator. |
1047 | * SCLK must remain running until after this clock switch. |
1048 | * Without a source of clock the I2C bus doesn't work. |
1049 | */ |
1050 | regmap_multi_reg_write(map: cs42l42->regmap, regs: cs42l42_to_osc_seq, |
1051 | ARRAY_SIZE(cs42l42_to_osc_seq)); |
1052 | |
1053 | /* Must disconnect PLL before stopping it */ |
1054 | snd_soc_component_update_bits(component, |
1055 | CS42L42_MCLK_SRC_SEL, |
1056 | CS42L42_MCLK_SRC_SEL_MASK, |
1057 | val: 0); |
1058 | usleep_range(min: 100, max: 200); |
1059 | |
1060 | snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, |
1061 | CS42L42_PLL_START_MASK, val: 0); |
1062 | } |
1063 | } else { |
1064 | if (!cs42l42->stream_use) { |
1065 | /* SCLK must be running before codec unmute. |
1066 | * |
1067 | * PLL must not be started with ADC and HP both off |
1068 | * otherwise the FILT+ supply will not charge properly. |
1069 | * DAPM widgets power-up before stream unmute so at least |
1070 | * one of the "DAC" or "ADC" widgets will already have |
1071 | * powered-up. |
1072 | */ |
1073 | if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) { |
1074 | snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, |
1075 | CS42L42_PLL_START_MASK, val: 1); |
1076 | |
1077 | if (pll_ratio_table[cs42l42->pll_config].n > 1) { |
1078 | usleep_range(CS42L42_PLL_DIVOUT_TIME_US, |
1079 | CS42L42_PLL_DIVOUT_TIME_US * 2); |
1080 | regval = pll_ratio_table[cs42l42->pll_config].pll_divout; |
1081 | snd_soc_component_update_bits(component, CS42L42_PLL_CTL3, |
1082 | CS42L42_PLL_DIVOUT_MASK, |
1083 | val: regval << |
1084 | CS42L42_PLL_DIVOUT_SHIFT); |
1085 | } |
1086 | |
1087 | ret = regmap_read_poll_timeout(cs42l42->regmap, |
1088 | CS42L42_PLL_LOCK_STATUS, |
1089 | regval, |
1090 | (regval & 1), |
1091 | CS42L42_PLL_LOCK_POLL_US, |
1092 | CS42L42_PLL_LOCK_TIMEOUT_US); |
1093 | if (ret < 0) |
1094 | dev_warn(component->dev, "PLL failed to lock: %d\n" , ret); |
1095 | |
1096 | /* PLL must be running to drive glitchless switch logic */ |
1097 | snd_soc_component_update_bits(component, |
1098 | CS42L42_MCLK_SRC_SEL, |
1099 | CS42L42_MCLK_SRC_SEL_MASK, |
1100 | CS42L42_MCLK_SRC_SEL_MASK); |
1101 | } |
1102 | |
1103 | /* Mark SCLK as present, turn off internal oscillator */ |
1104 | regmap_multi_reg_write(map: cs42l42->regmap, regs: cs42l42_to_sclk_seq, |
1105 | ARRAY_SIZE(cs42l42_to_sclk_seq)); |
1106 | } |
1107 | cs42l42->stream_use |= 1 << stream; |
1108 | |
1109 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
1110 | /* Un-mute the headphone */ |
1111 | snd_soc_component_update_bits(component, CS42L42_HP_CTL, |
1112 | CS42L42_HP_ANA_AMUTE_MASK | |
1113 | CS42L42_HP_ANA_BMUTE_MASK, |
1114 | val: 0); |
1115 | } |
1116 | } |
1117 | |
1118 | return 0; |
1119 | } |
1120 | EXPORT_SYMBOL_NS_GPL(cs42l42_mute_stream, SND_SOC_CS42L42_CORE); |
1121 | |
1122 | #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
1123 | SNDRV_PCM_FMTBIT_S24_LE |\ |
1124 | SNDRV_PCM_FMTBIT_S32_LE) |
1125 | |
1126 | static const struct snd_soc_dai_ops cs42l42_ops = { |
1127 | .startup = cs42l42_dai_startup, |
1128 | .hw_params = cs42l42_pcm_hw_params, |
1129 | .set_fmt = cs42l42_set_dai_fmt, |
1130 | .set_sysclk = cs42l42_set_sysclk, |
1131 | .set_bclk_ratio = cs42l42_set_bclk_ratio, |
1132 | .mute_stream = cs42l42_mute_stream, |
1133 | }; |
1134 | |
1135 | struct snd_soc_dai_driver cs42l42_dai = { |
1136 | .name = "cs42l42" , |
1137 | .playback = { |
1138 | .stream_name = "Playback" , |
1139 | .channels_min = 1, |
1140 | .channels_max = 2, |
1141 | .rates = SNDRV_PCM_RATE_8000_96000, |
1142 | .formats = CS42L42_FORMATS, |
1143 | }, |
1144 | .capture = { |
1145 | .stream_name = "Capture" , |
1146 | .channels_min = 1, |
1147 | .channels_max = 2, |
1148 | .rates = SNDRV_PCM_RATE_8000_96000, |
1149 | .formats = CS42L42_FORMATS, |
1150 | }, |
1151 | .symmetric_rate = 1, |
1152 | .symmetric_sample_bits = 1, |
1153 | .ops = &cs42l42_ops, |
1154 | }; |
1155 | EXPORT_SYMBOL_NS_GPL(cs42l42_dai, SND_SOC_CS42L42_CORE); |
1156 | |
1157 | static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42) |
1158 | { |
1159 | unsigned int hs_det_status; |
1160 | unsigned int hs_det_comp1; |
1161 | unsigned int hs_det_comp2; |
1162 | unsigned int hs_det_sw; |
1163 | |
1164 | /* Set hs detect to manual, active mode */ |
1165 | regmap_update_bits(map: cs42l42->regmap, |
1166 | CS42L42_HSDET_CTL2, |
1167 | CS42L42_HSDET_CTRL_MASK | |
1168 | CS42L42_HSDET_SET_MASK | |
1169 | CS42L42_HSBIAS_REF_MASK | |
1170 | CS42L42_HSDET_AUTO_TIME_MASK, |
1171 | val: (1 << CS42L42_HSDET_CTRL_SHIFT) | |
1172 | (0 << CS42L42_HSDET_SET_SHIFT) | |
1173 | (0 << CS42L42_HSBIAS_REF_SHIFT) | |
1174 | (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); |
1175 | |
1176 | /* Configure HS DET comparator reference levels. */ |
1177 | regmap_update_bits(map: cs42l42->regmap, |
1178 | CS42L42_HSDET_CTL1, |
1179 | CS42L42_HSDET_COMP1_LVL_MASK | |
1180 | CS42L42_HSDET_COMP2_LVL_MASK, |
1181 | val: (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) | |
1182 | (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT)); |
1183 | |
1184 | /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */ |
1185 | regmap_write(map: cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1); |
1186 | |
1187 | msleep(msecs: 100); |
1188 | |
1189 | regmap_read(map: cs42l42->regmap, CS42L42_HS_DET_STATUS, val: &hs_det_status); |
1190 | |
1191 | hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> |
1192 | CS42L42_HSDET_COMP1_OUT_SHIFT; |
1193 | hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> |
1194 | CS42L42_HSDET_COMP2_OUT_SHIFT; |
1195 | |
1196 | /* Close the SW_HSB_HS3 switch for a Type 2 headset. */ |
1197 | regmap_write(map: cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2); |
1198 | |
1199 | msleep(msecs: 100); |
1200 | |
1201 | regmap_read(map: cs42l42->regmap, CS42L42_HS_DET_STATUS, val: &hs_det_status); |
1202 | |
1203 | hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> |
1204 | CS42L42_HSDET_COMP1_OUT_SHIFT) << 1; |
1205 | hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> |
1206 | CS42L42_HSDET_COMP2_OUT_SHIFT) << 1; |
1207 | |
1208 | /* Use Comparator 1 with 1.25V Threshold. */ |
1209 | switch (hs_det_comp1) { |
1210 | case CS42L42_HSDET_COMP_TYPE1: |
1211 | cs42l42->hs_type = CS42L42_PLUG_CTIA; |
1212 | hs_det_sw = CS42L42_HSDET_SW_TYPE1; |
1213 | break; |
1214 | case CS42L42_HSDET_COMP_TYPE2: |
1215 | cs42l42->hs_type = CS42L42_PLUG_OMTP; |
1216 | hs_det_sw = CS42L42_HSDET_SW_TYPE2; |
1217 | break; |
1218 | default: |
1219 | /* Fallback to Comparator 2 with 1.75V Threshold. */ |
1220 | switch (hs_det_comp2) { |
1221 | case CS42L42_HSDET_COMP_TYPE1: |
1222 | cs42l42->hs_type = CS42L42_PLUG_CTIA; |
1223 | hs_det_sw = CS42L42_HSDET_SW_TYPE1; |
1224 | break; |
1225 | case CS42L42_HSDET_COMP_TYPE2: |
1226 | cs42l42->hs_type = CS42L42_PLUG_OMTP; |
1227 | hs_det_sw = CS42L42_HSDET_SW_TYPE2; |
1228 | break; |
1229 | /* Detect Type 3 and Type 4 Headsets as Headphones */ |
1230 | default: |
1231 | cs42l42->hs_type = CS42L42_PLUG_HEADPHONE; |
1232 | hs_det_sw = CS42L42_HSDET_SW_TYPE3; |
1233 | break; |
1234 | } |
1235 | } |
1236 | |
1237 | /* Set Switches */ |
1238 | regmap_write(map: cs42l42->regmap, CS42L42_HS_SWITCH_CTL, val: hs_det_sw); |
1239 | |
1240 | /* Set HSDET mode to Manual—Disabled */ |
1241 | regmap_update_bits(map: cs42l42->regmap, |
1242 | CS42L42_HSDET_CTL2, |
1243 | CS42L42_HSDET_CTRL_MASK | |
1244 | CS42L42_HSDET_SET_MASK | |
1245 | CS42L42_HSBIAS_REF_MASK | |
1246 | CS42L42_HSDET_AUTO_TIME_MASK, |
1247 | val: (0 << CS42L42_HSDET_CTRL_SHIFT) | |
1248 | (0 << CS42L42_HSDET_SET_SHIFT) | |
1249 | (0 << CS42L42_HSBIAS_REF_SHIFT) | |
1250 | (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); |
1251 | |
1252 | /* Configure HS DET comparator reference levels. */ |
1253 | regmap_update_bits(map: cs42l42->regmap, |
1254 | CS42L42_HSDET_CTL1, |
1255 | CS42L42_HSDET_COMP1_LVL_MASK | |
1256 | CS42L42_HSDET_COMP2_LVL_MASK, |
1257 | val: (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) | |
1258 | (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT)); |
1259 | } |
1260 | |
1261 | static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42) |
1262 | { |
1263 | unsigned int hs_det_status; |
1264 | unsigned int int_status; |
1265 | |
1266 | /* Read and save the hs detection result */ |
1267 | regmap_read(map: cs42l42->regmap, CS42L42_HS_DET_STATUS, val: &hs_det_status); |
1268 | |
1269 | /* Mask the auto detect interrupt */ |
1270 | regmap_update_bits(map: cs42l42->regmap, |
1271 | CS42L42_CODEC_INT_MASK, |
1272 | CS42L42_PDN_DONE_MASK | |
1273 | CS42L42_HSDET_AUTO_DONE_MASK, |
1274 | val: (1 << CS42L42_PDN_DONE_SHIFT) | |
1275 | (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); |
1276 | |
1277 | |
1278 | cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >> |
1279 | CS42L42_HSDET_TYPE_SHIFT; |
1280 | |
1281 | /* Set hs detect to automatic, disabled mode */ |
1282 | regmap_update_bits(map: cs42l42->regmap, |
1283 | CS42L42_HSDET_CTL2, |
1284 | CS42L42_HSDET_CTRL_MASK | |
1285 | CS42L42_HSDET_SET_MASK | |
1286 | CS42L42_HSBIAS_REF_MASK | |
1287 | CS42L42_HSDET_AUTO_TIME_MASK, |
1288 | val: (2 << CS42L42_HSDET_CTRL_SHIFT) | |
1289 | (2 << CS42L42_HSDET_SET_SHIFT) | |
1290 | (0 << CS42L42_HSBIAS_REF_SHIFT) | |
1291 | (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); |
1292 | |
1293 | /* Run Manual detection if auto detect has not found a headset. |
1294 | * We Re-Run with Manual Detection if the original detection was invalid or headphones, |
1295 | * to ensure that a headset mic is detected in all cases. |
1296 | */ |
1297 | if (cs42l42->hs_type == CS42L42_PLUG_INVALID || |
1298 | cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) { |
1299 | dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n" ); |
1300 | cs42l42_manual_hs_type_detect(cs42l42); |
1301 | } |
1302 | |
1303 | /* Set up button detection */ |
1304 | if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) || |
1305 | (cs42l42->hs_type == CS42L42_PLUG_OMTP)) { |
1306 | /* Set auto HS bias settings to default */ |
1307 | regmap_update_bits(map: cs42l42->regmap, |
1308 | CS42L42_HSBIAS_SC_AUTOCTL, |
1309 | CS42L42_HSBIAS_SENSE_EN_MASK | |
1310 | CS42L42_AUTO_HSBIAS_HIZ_MASK | |
1311 | CS42L42_TIP_SENSE_EN_MASK | |
1312 | CS42L42_HSBIAS_SENSE_TRIP_MASK, |
1313 | val: (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | |
1314 | (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | |
1315 | (0 << CS42L42_TIP_SENSE_EN_SHIFT) | |
1316 | (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); |
1317 | |
1318 | /* Set up hs detect level sensitivity */ |
1319 | regmap_update_bits(map: cs42l42->regmap, |
1320 | CS42L42_MIC_DET_CTL1, |
1321 | CS42L42_LATCH_TO_VP_MASK | |
1322 | CS42L42_EVENT_STAT_SEL_MASK | |
1323 | CS42L42_HS_DET_LEVEL_MASK, |
1324 | val: (1 << CS42L42_LATCH_TO_VP_SHIFT) | |
1325 | (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | |
1326 | (cs42l42->bias_thresholds[0] << |
1327 | CS42L42_HS_DET_LEVEL_SHIFT)); |
1328 | |
1329 | /* Set auto HS bias settings to default */ |
1330 | regmap_update_bits(map: cs42l42->regmap, |
1331 | CS42L42_HSBIAS_SC_AUTOCTL, |
1332 | CS42L42_HSBIAS_SENSE_EN_MASK | |
1333 | CS42L42_AUTO_HSBIAS_HIZ_MASK | |
1334 | CS42L42_TIP_SENSE_EN_MASK | |
1335 | CS42L42_HSBIAS_SENSE_TRIP_MASK, |
1336 | val: (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) | |
1337 | (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | |
1338 | (0 << CS42L42_TIP_SENSE_EN_SHIFT) | |
1339 | (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); |
1340 | |
1341 | /* Turn on level detect circuitry */ |
1342 | regmap_update_bits(map: cs42l42->regmap, |
1343 | CS42L42_MISC_DET_CTL, |
1344 | CS42L42_HSBIAS_CTL_MASK | |
1345 | CS42L42_PDN_MIC_LVL_DET_MASK, |
1346 | val: (3 << CS42L42_HSBIAS_CTL_SHIFT) | |
1347 | (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); |
1348 | |
1349 | msleep(msecs: cs42l42->btn_det_init_dbnce); |
1350 | |
1351 | /* Clear any button interrupts before unmasking them */ |
1352 | regmap_read(map: cs42l42->regmap, CS42L42_DET_INT_STATUS2, |
1353 | val: &int_status); |
1354 | |
1355 | /* Unmask button detect interrupts */ |
1356 | regmap_update_bits(map: cs42l42->regmap, |
1357 | CS42L42_DET_INT2_MASK, |
1358 | CS42L42_M_DETECT_TF_MASK | |
1359 | CS42L42_M_DETECT_FT_MASK | |
1360 | CS42L42_M_HSBIAS_HIZ_MASK | |
1361 | CS42L42_M_SHORT_RLS_MASK | |
1362 | CS42L42_M_SHORT_DET_MASK, |
1363 | val: (0 << CS42L42_M_DETECT_TF_SHIFT) | |
1364 | (0 << CS42L42_M_DETECT_FT_SHIFT) | |
1365 | (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | |
1366 | (1 << CS42L42_M_SHORT_RLS_SHIFT) | |
1367 | (1 << CS42L42_M_SHORT_DET_SHIFT)); |
1368 | } else { |
1369 | /* Make sure button detect and HS bias circuits are off */ |
1370 | regmap_update_bits(map: cs42l42->regmap, |
1371 | CS42L42_MISC_DET_CTL, |
1372 | CS42L42_HSBIAS_CTL_MASK | |
1373 | CS42L42_PDN_MIC_LVL_DET_MASK, |
1374 | val: (1 << CS42L42_HSBIAS_CTL_SHIFT) | |
1375 | (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); |
1376 | } |
1377 | |
1378 | regmap_update_bits(map: cs42l42->regmap, |
1379 | CS42L42_DAC_CTL2, |
1380 | CS42L42_HPOUT_PULLDOWN_MASK | |
1381 | CS42L42_HPOUT_LOAD_MASK | |
1382 | CS42L42_HPOUT_CLAMP_MASK | |
1383 | CS42L42_DAC_HPF_EN_MASK | |
1384 | CS42L42_DAC_MON_EN_MASK, |
1385 | val: (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) | |
1386 | (0 << CS42L42_HPOUT_LOAD_SHIFT) | |
1387 | (0 << CS42L42_HPOUT_CLAMP_SHIFT) | |
1388 | (1 << CS42L42_DAC_HPF_EN_SHIFT) | |
1389 | (0 << CS42L42_DAC_MON_EN_SHIFT)); |
1390 | |
1391 | /* Unmask tip sense interrupts */ |
1392 | regmap_update_bits(map: cs42l42->regmap, |
1393 | CS42L42_TSRS_PLUG_INT_MASK, |
1394 | CS42L42_TS_PLUG_MASK | |
1395 | CS42L42_TS_UNPLUG_MASK, |
1396 | val: (0 << CS42L42_TS_PLUG_SHIFT) | |
1397 | (0 << CS42L42_TS_UNPLUG_SHIFT)); |
1398 | } |
1399 | |
1400 | static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42) |
1401 | { |
1402 | /* Mask tip sense interrupts */ |
1403 | regmap_update_bits(map: cs42l42->regmap, |
1404 | CS42L42_TSRS_PLUG_INT_MASK, |
1405 | CS42L42_TS_PLUG_MASK | |
1406 | CS42L42_TS_UNPLUG_MASK, |
1407 | val: (1 << CS42L42_TS_PLUG_SHIFT) | |
1408 | (1 << CS42L42_TS_UNPLUG_SHIFT)); |
1409 | |
1410 | /* Make sure button detect and HS bias circuits are off */ |
1411 | regmap_update_bits(map: cs42l42->regmap, |
1412 | CS42L42_MISC_DET_CTL, |
1413 | CS42L42_HSBIAS_CTL_MASK | |
1414 | CS42L42_PDN_MIC_LVL_DET_MASK, |
1415 | val: (1 << CS42L42_HSBIAS_CTL_SHIFT) | |
1416 | (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); |
1417 | |
1418 | /* Set auto HS bias settings to default */ |
1419 | regmap_update_bits(map: cs42l42->regmap, |
1420 | CS42L42_HSBIAS_SC_AUTOCTL, |
1421 | CS42L42_HSBIAS_SENSE_EN_MASK | |
1422 | CS42L42_AUTO_HSBIAS_HIZ_MASK | |
1423 | CS42L42_TIP_SENSE_EN_MASK | |
1424 | CS42L42_HSBIAS_SENSE_TRIP_MASK, |
1425 | val: (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | |
1426 | (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | |
1427 | (0 << CS42L42_TIP_SENSE_EN_SHIFT) | |
1428 | (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); |
1429 | |
1430 | /* Set hs detect to manual, disabled mode */ |
1431 | regmap_update_bits(map: cs42l42->regmap, |
1432 | CS42L42_HSDET_CTL2, |
1433 | CS42L42_HSDET_CTRL_MASK | |
1434 | CS42L42_HSDET_SET_MASK | |
1435 | CS42L42_HSBIAS_REF_MASK | |
1436 | CS42L42_HSDET_AUTO_TIME_MASK, |
1437 | val: (0 << CS42L42_HSDET_CTRL_SHIFT) | |
1438 | (2 << CS42L42_HSDET_SET_SHIFT) | |
1439 | (0 << CS42L42_HSBIAS_REF_SHIFT) | |
1440 | (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); |
1441 | |
1442 | regmap_update_bits(map: cs42l42->regmap, |
1443 | CS42L42_DAC_CTL2, |
1444 | CS42L42_HPOUT_PULLDOWN_MASK | |
1445 | CS42L42_HPOUT_LOAD_MASK | |
1446 | CS42L42_HPOUT_CLAMP_MASK | |
1447 | CS42L42_DAC_HPF_EN_MASK | |
1448 | CS42L42_DAC_MON_EN_MASK, |
1449 | val: (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) | |
1450 | (0 << CS42L42_HPOUT_LOAD_SHIFT) | |
1451 | (1 << CS42L42_HPOUT_CLAMP_SHIFT) | |
1452 | (1 << CS42L42_DAC_HPF_EN_SHIFT) | |
1453 | (1 << CS42L42_DAC_MON_EN_SHIFT)); |
1454 | |
1455 | /* Power up HS bias to 2.7V */ |
1456 | regmap_update_bits(map: cs42l42->regmap, |
1457 | CS42L42_MISC_DET_CTL, |
1458 | CS42L42_HSBIAS_CTL_MASK | |
1459 | CS42L42_PDN_MIC_LVL_DET_MASK, |
1460 | val: (3 << CS42L42_HSBIAS_CTL_SHIFT) | |
1461 | (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); |
1462 | |
1463 | /* Wait for HS bias to ramp up */ |
1464 | msleep(msecs: cs42l42->hs_bias_ramp_time); |
1465 | |
1466 | /* Unmask auto detect interrupt */ |
1467 | regmap_update_bits(map: cs42l42->regmap, |
1468 | CS42L42_CODEC_INT_MASK, |
1469 | CS42L42_PDN_DONE_MASK | |
1470 | CS42L42_HSDET_AUTO_DONE_MASK, |
1471 | val: (1 << CS42L42_PDN_DONE_SHIFT) | |
1472 | (0 << CS42L42_HSDET_AUTO_DONE_SHIFT)); |
1473 | |
1474 | /* Set hs detect to automatic, enabled mode */ |
1475 | regmap_update_bits(map: cs42l42->regmap, |
1476 | CS42L42_HSDET_CTL2, |
1477 | CS42L42_HSDET_CTRL_MASK | |
1478 | CS42L42_HSDET_SET_MASK | |
1479 | CS42L42_HSBIAS_REF_MASK | |
1480 | CS42L42_HSDET_AUTO_TIME_MASK, |
1481 | val: (3 << CS42L42_HSDET_CTRL_SHIFT) | |
1482 | (2 << CS42L42_HSDET_SET_SHIFT) | |
1483 | (0 << CS42L42_HSBIAS_REF_SHIFT) | |
1484 | (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); |
1485 | } |
1486 | |
1487 | static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42) |
1488 | { |
1489 | /* Mask button detect interrupts */ |
1490 | regmap_update_bits(map: cs42l42->regmap, |
1491 | CS42L42_DET_INT2_MASK, |
1492 | CS42L42_M_DETECT_TF_MASK | |
1493 | CS42L42_M_DETECT_FT_MASK | |
1494 | CS42L42_M_HSBIAS_HIZ_MASK | |
1495 | CS42L42_M_SHORT_RLS_MASK | |
1496 | CS42L42_M_SHORT_DET_MASK, |
1497 | val: (1 << CS42L42_M_DETECT_TF_SHIFT) | |
1498 | (1 << CS42L42_M_DETECT_FT_SHIFT) | |
1499 | (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | |
1500 | (1 << CS42L42_M_SHORT_RLS_SHIFT) | |
1501 | (1 << CS42L42_M_SHORT_DET_SHIFT)); |
1502 | |
1503 | /* Ground HS bias */ |
1504 | regmap_update_bits(map: cs42l42->regmap, |
1505 | CS42L42_MISC_DET_CTL, |
1506 | CS42L42_HSBIAS_CTL_MASK | |
1507 | CS42L42_PDN_MIC_LVL_DET_MASK, |
1508 | val: (1 << CS42L42_HSBIAS_CTL_SHIFT) | |
1509 | (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)); |
1510 | |
1511 | /* Set auto HS bias settings to default */ |
1512 | regmap_update_bits(map: cs42l42->regmap, |
1513 | CS42L42_HSBIAS_SC_AUTOCTL, |
1514 | CS42L42_HSBIAS_SENSE_EN_MASK | |
1515 | CS42L42_AUTO_HSBIAS_HIZ_MASK | |
1516 | CS42L42_TIP_SENSE_EN_MASK | |
1517 | CS42L42_HSBIAS_SENSE_TRIP_MASK, |
1518 | val: (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) | |
1519 | (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) | |
1520 | (0 << CS42L42_TIP_SENSE_EN_SHIFT) | |
1521 | (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)); |
1522 | |
1523 | /* Set hs detect to manual, disabled mode */ |
1524 | regmap_update_bits(map: cs42l42->regmap, |
1525 | CS42L42_HSDET_CTL2, |
1526 | CS42L42_HSDET_CTRL_MASK | |
1527 | CS42L42_HSDET_SET_MASK | |
1528 | CS42L42_HSBIAS_REF_MASK | |
1529 | CS42L42_HSDET_AUTO_TIME_MASK, |
1530 | val: (0 << CS42L42_HSDET_CTRL_SHIFT) | |
1531 | (2 << CS42L42_HSDET_SET_SHIFT) | |
1532 | (0 << CS42L42_HSBIAS_REF_SHIFT) | |
1533 | (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)); |
1534 | } |
1535 | |
1536 | static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42) |
1537 | { |
1538 | int bias_level; |
1539 | unsigned int detect_status; |
1540 | |
1541 | /* Mask button detect interrupts */ |
1542 | regmap_update_bits(map: cs42l42->regmap, |
1543 | CS42L42_DET_INT2_MASK, |
1544 | CS42L42_M_DETECT_TF_MASK | |
1545 | CS42L42_M_DETECT_FT_MASK | |
1546 | CS42L42_M_HSBIAS_HIZ_MASK | |
1547 | CS42L42_M_SHORT_RLS_MASK | |
1548 | CS42L42_M_SHORT_DET_MASK, |
1549 | val: (1 << CS42L42_M_DETECT_TF_SHIFT) | |
1550 | (1 << CS42L42_M_DETECT_FT_SHIFT) | |
1551 | (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | |
1552 | (1 << CS42L42_M_SHORT_RLS_SHIFT) | |
1553 | (1 << CS42L42_M_SHORT_DET_SHIFT)); |
1554 | |
1555 | usleep_range(min: cs42l42->btn_det_event_dbnce * 1000, |
1556 | max: cs42l42->btn_det_event_dbnce * 2000); |
1557 | |
1558 | /* Test all 4 level detect biases */ |
1559 | bias_level = 1; |
1560 | do { |
1561 | /* Adjust button detect level sensitivity */ |
1562 | regmap_update_bits(map: cs42l42->regmap, |
1563 | CS42L42_MIC_DET_CTL1, |
1564 | CS42L42_LATCH_TO_VP_MASK | |
1565 | CS42L42_EVENT_STAT_SEL_MASK | |
1566 | CS42L42_HS_DET_LEVEL_MASK, |
1567 | val: (1 << CS42L42_LATCH_TO_VP_SHIFT) | |
1568 | (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | |
1569 | (cs42l42->bias_thresholds[bias_level] << |
1570 | CS42L42_HS_DET_LEVEL_SHIFT)); |
1571 | |
1572 | regmap_read(map: cs42l42->regmap, CS42L42_DET_STATUS2, |
1573 | val: &detect_status); |
1574 | } while ((detect_status & CS42L42_HS_TRUE_MASK) && |
1575 | (++bias_level < CS42L42_NUM_BIASES)); |
1576 | |
1577 | switch (bias_level) { |
1578 | case 1: /* Function C button press */ |
1579 | bias_level = SND_JACK_BTN_2; |
1580 | dev_dbg(cs42l42->dev, "Function C button press\n" ); |
1581 | break; |
1582 | case 2: /* Function B button press */ |
1583 | bias_level = SND_JACK_BTN_1; |
1584 | dev_dbg(cs42l42->dev, "Function B button press\n" ); |
1585 | break; |
1586 | case 3: /* Function D button press */ |
1587 | bias_level = SND_JACK_BTN_3; |
1588 | dev_dbg(cs42l42->dev, "Function D button press\n" ); |
1589 | break; |
1590 | case 4: /* Function A button press */ |
1591 | bias_level = SND_JACK_BTN_0; |
1592 | dev_dbg(cs42l42->dev, "Function A button press\n" ); |
1593 | break; |
1594 | default: |
1595 | bias_level = 0; |
1596 | break; |
1597 | } |
1598 | |
1599 | /* Set button detect level sensitivity back to default */ |
1600 | regmap_update_bits(map: cs42l42->regmap, |
1601 | CS42L42_MIC_DET_CTL1, |
1602 | CS42L42_LATCH_TO_VP_MASK | |
1603 | CS42L42_EVENT_STAT_SEL_MASK | |
1604 | CS42L42_HS_DET_LEVEL_MASK, |
1605 | val: (1 << CS42L42_LATCH_TO_VP_SHIFT) | |
1606 | (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | |
1607 | (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT)); |
1608 | |
1609 | /* Clear any button interrupts before unmasking them */ |
1610 | regmap_read(map: cs42l42->regmap, CS42L42_DET_INT_STATUS2, |
1611 | val: &detect_status); |
1612 | |
1613 | /* Unmask button detect interrupts */ |
1614 | regmap_update_bits(map: cs42l42->regmap, |
1615 | CS42L42_DET_INT2_MASK, |
1616 | CS42L42_M_DETECT_TF_MASK | |
1617 | CS42L42_M_DETECT_FT_MASK | |
1618 | CS42L42_M_HSBIAS_HIZ_MASK | |
1619 | CS42L42_M_SHORT_RLS_MASK | |
1620 | CS42L42_M_SHORT_DET_MASK, |
1621 | val: (0 << CS42L42_M_DETECT_TF_SHIFT) | |
1622 | (0 << CS42L42_M_DETECT_FT_SHIFT) | |
1623 | (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) | |
1624 | (1 << CS42L42_M_SHORT_RLS_SHIFT) | |
1625 | (1 << CS42L42_M_SHORT_DET_SHIFT)); |
1626 | |
1627 | return bias_level; |
1628 | } |
1629 | |
1630 | struct cs42l42_irq_params { |
1631 | u16 status_addr; |
1632 | u16 mask_addr; |
1633 | u8 mask; |
1634 | }; |
1635 | |
1636 | static const struct cs42l42_irq_params irq_params_table[] = { |
1637 | {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK, |
1638 | CS42L42_ADC_OVFL_VAL_MASK}, |
1639 | {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK, |
1640 | CS42L42_MIXER_VAL_MASK}, |
1641 | {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK, |
1642 | CS42L42_SRC_VAL_MASK}, |
1643 | {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK, |
1644 | CS42L42_ASP_RX_VAL_MASK}, |
1645 | {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK, |
1646 | CS42L42_ASP_TX_VAL_MASK}, |
1647 | {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK, |
1648 | CS42L42_CODEC_VAL_MASK}, |
1649 | {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK, |
1650 | CS42L42_DET_INT_VAL1_MASK}, |
1651 | {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK, |
1652 | CS42L42_DET_INT_VAL2_MASK}, |
1653 | {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK, |
1654 | CS42L42_SRCPL_VAL_MASK}, |
1655 | {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK, |
1656 | CS42L42_VPMON_VAL_MASK}, |
1657 | {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK, |
1658 | CS42L42_PLL_LOCK_VAL_MASK}, |
1659 | {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK, |
1660 | CS42L42_TSRS_PLUG_VAL_MASK} |
1661 | }; |
1662 | |
1663 | irqreturn_t cs42l42_irq_thread(int irq, void *data) |
1664 | { |
1665 | struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data; |
1666 | unsigned int stickies[12]; |
1667 | unsigned int masks[12]; |
1668 | unsigned int current_plug_status; |
1669 | unsigned int current_button_status; |
1670 | unsigned int i; |
1671 | |
1672 | pm_runtime_get_sync(dev: cs42l42->dev); |
1673 | mutex_lock(&cs42l42->irq_lock); |
1674 | if (cs42l42->suspended || !cs42l42->init_done) { |
1675 | mutex_unlock(lock: &cs42l42->irq_lock); |
1676 | pm_runtime_put_autosuspend(dev: cs42l42->dev); |
1677 | return IRQ_NONE; |
1678 | } |
1679 | |
1680 | /* Read sticky registers to clear interurpt */ |
1681 | for (i = 0; i < ARRAY_SIZE(stickies); i++) { |
1682 | regmap_read(map: cs42l42->regmap, reg: irq_params_table[i].status_addr, |
1683 | val: &(stickies[i])); |
1684 | regmap_read(map: cs42l42->regmap, reg: irq_params_table[i].mask_addr, |
1685 | val: &(masks[i])); |
1686 | stickies[i] = stickies[i] & (~masks[i]) & |
1687 | irq_params_table[i].mask; |
1688 | } |
1689 | |
1690 | /* Read tip sense status before handling type detect */ |
1691 | current_plug_status = (stickies[11] & |
1692 | (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> |
1693 | CS42L42_TS_PLUG_SHIFT; |
1694 | |
1695 | /* Read button sense status */ |
1696 | current_button_status = stickies[7] & |
1697 | (CS42L42_M_DETECT_TF_MASK | |
1698 | CS42L42_M_DETECT_FT_MASK | |
1699 | CS42L42_M_HSBIAS_HIZ_MASK); |
1700 | |
1701 | /* |
1702 | * Check auto-detect status. Don't assume a previous unplug event has |
1703 | * cleared the flags. If the jack is unplugged and plugged during |
1704 | * system suspend there won't have been an unplug event. |
1705 | */ |
1706 | if ((~masks[5]) & irq_params_table[5].mask) { |
1707 | if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) { |
1708 | cs42l42_process_hs_type_detect(cs42l42); |
1709 | switch (cs42l42->hs_type) { |
1710 | case CS42L42_PLUG_CTIA: |
1711 | case CS42L42_PLUG_OMTP: |
1712 | snd_soc_jack_report(jack: cs42l42->jack, status: SND_JACK_HEADSET, |
1713 | mask: SND_JACK_HEADSET | |
1714 | SND_JACK_BTN_0 | SND_JACK_BTN_1 | |
1715 | SND_JACK_BTN_2 | SND_JACK_BTN_3); |
1716 | break; |
1717 | case CS42L42_PLUG_HEADPHONE: |
1718 | snd_soc_jack_report(jack: cs42l42->jack, status: SND_JACK_HEADPHONE, |
1719 | mask: SND_JACK_HEADSET | |
1720 | SND_JACK_BTN_0 | SND_JACK_BTN_1 | |
1721 | SND_JACK_BTN_2 | SND_JACK_BTN_3); |
1722 | break; |
1723 | default: |
1724 | break; |
1725 | } |
1726 | dev_dbg(cs42l42->dev, "Auto detect done (%d)\n" , cs42l42->hs_type); |
1727 | } |
1728 | } |
1729 | |
1730 | /* Check tip sense status */ |
1731 | if ((~masks[11]) & irq_params_table[11].mask) { |
1732 | switch (current_plug_status) { |
1733 | case CS42L42_TS_PLUG: |
1734 | if (cs42l42->plug_state != CS42L42_TS_PLUG) { |
1735 | cs42l42->plug_state = CS42L42_TS_PLUG; |
1736 | cs42l42_init_hs_type_detect(cs42l42); |
1737 | } |
1738 | break; |
1739 | |
1740 | case CS42L42_TS_UNPLUG: |
1741 | if (cs42l42->plug_state != CS42L42_TS_UNPLUG) { |
1742 | cs42l42->plug_state = CS42L42_TS_UNPLUG; |
1743 | cs42l42_cancel_hs_type_detect(cs42l42); |
1744 | |
1745 | snd_soc_jack_report(jack: cs42l42->jack, status: 0, |
1746 | mask: SND_JACK_HEADSET | |
1747 | SND_JACK_BTN_0 | SND_JACK_BTN_1 | |
1748 | SND_JACK_BTN_2 | SND_JACK_BTN_3); |
1749 | |
1750 | dev_dbg(cs42l42->dev, "Unplug event\n" ); |
1751 | } |
1752 | break; |
1753 | |
1754 | default: |
1755 | cs42l42->plug_state = CS42L42_TS_TRANS; |
1756 | } |
1757 | } |
1758 | |
1759 | /* Check button detect status */ |
1760 | if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) { |
1761 | if (!(current_button_status & |
1762 | CS42L42_M_HSBIAS_HIZ_MASK)) { |
1763 | |
1764 | if (current_button_status & CS42L42_M_DETECT_TF_MASK) { |
1765 | dev_dbg(cs42l42->dev, "Button released\n" ); |
1766 | snd_soc_jack_report(jack: cs42l42->jack, status: 0, |
1767 | mask: SND_JACK_BTN_0 | SND_JACK_BTN_1 | |
1768 | SND_JACK_BTN_2 | SND_JACK_BTN_3); |
1769 | } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) { |
1770 | snd_soc_jack_report(jack: cs42l42->jack, |
1771 | status: cs42l42_handle_button_press(cs42l42), |
1772 | mask: SND_JACK_BTN_0 | SND_JACK_BTN_1 | |
1773 | SND_JACK_BTN_2 | SND_JACK_BTN_3); |
1774 | } |
1775 | } |
1776 | } |
1777 | |
1778 | mutex_unlock(lock: &cs42l42->irq_lock); |
1779 | pm_runtime_mark_last_busy(dev: cs42l42->dev); |
1780 | pm_runtime_put_autosuspend(dev: cs42l42->dev); |
1781 | |
1782 | return IRQ_HANDLED; |
1783 | } |
1784 | EXPORT_SYMBOL_NS_GPL(cs42l42_irq_thread, SND_SOC_CS42L42_CORE); |
1785 | |
1786 | static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42) |
1787 | { |
1788 | regmap_update_bits(map: cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK, |
1789 | CS42L42_ADC_OVFL_MASK, |
1790 | val: (1 << CS42L42_ADC_OVFL_SHIFT)); |
1791 | |
1792 | regmap_update_bits(map: cs42l42->regmap, CS42L42_MIXER_INT_MASK, |
1793 | CS42L42_MIX_CHB_OVFL_MASK | |
1794 | CS42L42_MIX_CHA_OVFL_MASK | |
1795 | CS42L42_EQ_OVFL_MASK | |
1796 | CS42L42_EQ_BIQUAD_OVFL_MASK, |
1797 | val: (1 << CS42L42_MIX_CHB_OVFL_SHIFT) | |
1798 | (1 << CS42L42_MIX_CHA_OVFL_SHIFT) | |
1799 | (1 << CS42L42_EQ_OVFL_SHIFT) | |
1800 | (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)); |
1801 | |
1802 | regmap_update_bits(map: cs42l42->regmap, CS42L42_SRC_INT_MASK, |
1803 | CS42L42_SRC_ILK_MASK | |
1804 | CS42L42_SRC_OLK_MASK | |
1805 | CS42L42_SRC_IUNLK_MASK | |
1806 | CS42L42_SRC_OUNLK_MASK, |
1807 | val: (1 << CS42L42_SRC_ILK_SHIFT) | |
1808 | (1 << CS42L42_SRC_OLK_SHIFT) | |
1809 | (1 << CS42L42_SRC_IUNLK_SHIFT) | |
1810 | (1 << CS42L42_SRC_OUNLK_SHIFT)); |
1811 | |
1812 | regmap_update_bits(map: cs42l42->regmap, CS42L42_ASP_RX_INT_MASK, |
1813 | CS42L42_ASPRX_NOLRCK_MASK | |
1814 | CS42L42_ASPRX_EARLY_MASK | |
1815 | CS42L42_ASPRX_LATE_MASK | |
1816 | CS42L42_ASPRX_ERROR_MASK | |
1817 | CS42L42_ASPRX_OVLD_MASK, |
1818 | val: (1 << CS42L42_ASPRX_NOLRCK_SHIFT) | |
1819 | (1 << CS42L42_ASPRX_EARLY_SHIFT) | |
1820 | (1 << CS42L42_ASPRX_LATE_SHIFT) | |
1821 | (1 << CS42L42_ASPRX_ERROR_SHIFT) | |
1822 | (1 << CS42L42_ASPRX_OVLD_SHIFT)); |
1823 | |
1824 | regmap_update_bits(map: cs42l42->regmap, CS42L42_ASP_TX_INT_MASK, |
1825 | CS42L42_ASPTX_NOLRCK_MASK | |
1826 | CS42L42_ASPTX_EARLY_MASK | |
1827 | CS42L42_ASPTX_LATE_MASK | |
1828 | CS42L42_ASPTX_SMERROR_MASK, |
1829 | val: (1 << CS42L42_ASPTX_NOLRCK_SHIFT) | |
1830 | (1 << CS42L42_ASPTX_EARLY_SHIFT) | |
1831 | (1 << CS42L42_ASPTX_LATE_SHIFT) | |
1832 | (1 << CS42L42_ASPTX_SMERROR_SHIFT)); |
1833 | |
1834 | regmap_update_bits(map: cs42l42->regmap, CS42L42_CODEC_INT_MASK, |
1835 | CS42L42_PDN_DONE_MASK | |
1836 | CS42L42_HSDET_AUTO_DONE_MASK, |
1837 | val: (1 << CS42L42_PDN_DONE_SHIFT) | |
1838 | (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)); |
1839 | |
1840 | regmap_update_bits(map: cs42l42->regmap, CS42L42_SRCPL_INT_MASK, |
1841 | CS42L42_SRCPL_ADC_LK_MASK | |
1842 | CS42L42_SRCPL_DAC_LK_MASK | |
1843 | CS42L42_SRCPL_ADC_UNLK_MASK | |
1844 | CS42L42_SRCPL_DAC_UNLK_MASK, |
1845 | val: (1 << CS42L42_SRCPL_ADC_LK_SHIFT) | |
1846 | (1 << CS42L42_SRCPL_DAC_LK_SHIFT) | |
1847 | (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) | |
1848 | (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)); |
1849 | |
1850 | regmap_update_bits(map: cs42l42->regmap, CS42L42_DET_INT1_MASK, |
1851 | CS42L42_TIP_SENSE_UNPLUG_MASK | |
1852 | CS42L42_TIP_SENSE_PLUG_MASK | |
1853 | CS42L42_HSBIAS_SENSE_MASK, |
1854 | val: (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) | |
1855 | (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) | |
1856 | (1 << CS42L42_HSBIAS_SENSE_SHIFT)); |
1857 | |
1858 | regmap_update_bits(map: cs42l42->regmap, CS42L42_DET_INT2_MASK, |
1859 | CS42L42_M_DETECT_TF_MASK | |
1860 | CS42L42_M_DETECT_FT_MASK | |
1861 | CS42L42_M_HSBIAS_HIZ_MASK | |
1862 | CS42L42_M_SHORT_RLS_MASK | |
1863 | CS42L42_M_SHORT_DET_MASK, |
1864 | val: (1 << CS42L42_M_DETECT_TF_SHIFT) | |
1865 | (1 << CS42L42_M_DETECT_FT_SHIFT) | |
1866 | (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) | |
1867 | (1 << CS42L42_M_SHORT_RLS_SHIFT) | |
1868 | (1 << CS42L42_M_SHORT_DET_SHIFT)); |
1869 | |
1870 | regmap_update_bits(map: cs42l42->regmap, CS42L42_VPMON_INT_MASK, |
1871 | CS42L42_VPMON_MASK, |
1872 | val: (1 << CS42L42_VPMON_SHIFT)); |
1873 | |
1874 | regmap_update_bits(map: cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK, |
1875 | CS42L42_PLL_LOCK_MASK, |
1876 | val: (1 << CS42L42_PLL_LOCK_SHIFT)); |
1877 | |
1878 | regmap_update_bits(map: cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, |
1879 | CS42L42_RS_PLUG_MASK | |
1880 | CS42L42_RS_UNPLUG_MASK | |
1881 | CS42L42_TS_PLUG_MASK | |
1882 | CS42L42_TS_UNPLUG_MASK, |
1883 | val: (1 << CS42L42_RS_PLUG_SHIFT) | |
1884 | (1 << CS42L42_RS_UNPLUG_SHIFT) | |
1885 | (0 << CS42L42_TS_PLUG_SHIFT) | |
1886 | (0 << CS42L42_TS_UNPLUG_SHIFT)); |
1887 | } |
1888 | |
1889 | static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42) |
1890 | { |
1891 | unsigned int reg; |
1892 | |
1893 | cs42l42->hs_type = CS42L42_PLUG_INVALID; |
1894 | |
1895 | /* |
1896 | * DETECT_MODE must always be 0 with ADC and HP both off otherwise the |
1897 | * FILT+ supply will not charge properly. |
1898 | */ |
1899 | regmap_update_bits(map: cs42l42->regmap, CS42L42_MISC_DET_CTL, |
1900 | CS42L42_DETECT_MODE_MASK, val: 0); |
1901 | |
1902 | /* Latch analog controls to VP power domain */ |
1903 | regmap_update_bits(map: cs42l42->regmap, CS42L42_MIC_DET_CTL1, |
1904 | CS42L42_LATCH_TO_VP_MASK | |
1905 | CS42L42_EVENT_STAT_SEL_MASK | |
1906 | CS42L42_HS_DET_LEVEL_MASK, |
1907 | val: (1 << CS42L42_LATCH_TO_VP_SHIFT) | |
1908 | (0 << CS42L42_EVENT_STAT_SEL_SHIFT) | |
1909 | (cs42l42->bias_thresholds[0] << |
1910 | CS42L42_HS_DET_LEVEL_SHIFT)); |
1911 | |
1912 | /* Remove ground noise-suppression clamps */ |
1913 | regmap_update_bits(map: cs42l42->regmap, |
1914 | CS42L42_HS_CLAMP_DISABLE, |
1915 | CS42L42_HS_CLAMP_DISABLE_MASK, |
1916 | val: (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)); |
1917 | |
1918 | /* Enable the tip sense circuit */ |
1919 | regmap_update_bits(map: cs42l42->regmap, CS42L42_TSENSE_CTL, |
1920 | CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK); |
1921 | |
1922 | regmap_update_bits(map: cs42l42->regmap, CS42L42_TIPSENSE_CTL, |
1923 | CS42L42_TIP_SENSE_CTRL_MASK | |
1924 | CS42L42_TIP_SENSE_INV_MASK | |
1925 | CS42L42_TIP_SENSE_DEBOUNCE_MASK, |
1926 | val: (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) | |
1927 | (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) | |
1928 | (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)); |
1929 | |
1930 | /* Save the initial status of the tip sense */ |
1931 | regmap_read(map: cs42l42->regmap, |
1932 | CS42L42_TSRS_PLUG_STATUS, |
1933 | val: ®); |
1934 | cs42l42->plug_state = (((char) reg) & |
1935 | (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >> |
1936 | CS42L42_TS_PLUG_SHIFT; |
1937 | } |
1938 | |
1939 | static const unsigned int threshold_defaults[] = { |
1940 | CS42L42_HS_DET_LEVEL_15, |
1941 | CS42L42_HS_DET_LEVEL_8, |
1942 | CS42L42_HS_DET_LEVEL_4, |
1943 | CS42L42_HS_DET_LEVEL_1 |
1944 | }; |
1945 | |
1946 | static int cs42l42_handle_device_data(struct device *dev, |
1947 | struct cs42l42_private *cs42l42) |
1948 | { |
1949 | unsigned int val; |
1950 | u32 thresholds[CS42L42_NUM_BIASES]; |
1951 | int ret; |
1952 | int i; |
1953 | |
1954 | ret = device_property_read_u32(dev, propname: "cirrus,ts-inv" , val: &val); |
1955 | if (!ret) { |
1956 | switch (val) { |
1957 | case CS42L42_TS_INV_EN: |
1958 | case CS42L42_TS_INV_DIS: |
1959 | cs42l42->ts_inv = val; |
1960 | break; |
1961 | default: |
1962 | dev_err(dev, |
1963 | "Wrong cirrus,ts-inv DT value %d\n" , |
1964 | val); |
1965 | cs42l42->ts_inv = CS42L42_TS_INV_DIS; |
1966 | } |
1967 | } else { |
1968 | cs42l42->ts_inv = CS42L42_TS_INV_DIS; |
1969 | } |
1970 | |
1971 | ret = device_property_read_u32(dev, propname: "cirrus,ts-dbnc-rise" , val: &val); |
1972 | if (!ret) { |
1973 | switch (val) { |
1974 | case CS42L42_TS_DBNCE_0: |
1975 | case CS42L42_TS_DBNCE_125: |
1976 | case CS42L42_TS_DBNCE_250: |
1977 | case CS42L42_TS_DBNCE_500: |
1978 | case CS42L42_TS_DBNCE_750: |
1979 | case CS42L42_TS_DBNCE_1000: |
1980 | case CS42L42_TS_DBNCE_1250: |
1981 | case CS42L42_TS_DBNCE_1500: |
1982 | cs42l42->ts_dbnc_rise = val; |
1983 | break; |
1984 | default: |
1985 | dev_err(dev, |
1986 | "Wrong cirrus,ts-dbnc-rise DT value %d\n" , |
1987 | val); |
1988 | cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; |
1989 | } |
1990 | } else { |
1991 | cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000; |
1992 | } |
1993 | |
1994 | regmap_update_bits(map: cs42l42->regmap, CS42L42_TSENSE_CTL, |
1995 | CS42L42_TS_RISE_DBNCE_TIME_MASK, |
1996 | val: (cs42l42->ts_dbnc_rise << |
1997 | CS42L42_TS_RISE_DBNCE_TIME_SHIFT)); |
1998 | |
1999 | ret = device_property_read_u32(dev, propname: "cirrus,ts-dbnc-fall" , val: &val); |
2000 | if (!ret) { |
2001 | switch (val) { |
2002 | case CS42L42_TS_DBNCE_0: |
2003 | case CS42L42_TS_DBNCE_125: |
2004 | case CS42L42_TS_DBNCE_250: |
2005 | case CS42L42_TS_DBNCE_500: |
2006 | case CS42L42_TS_DBNCE_750: |
2007 | case CS42L42_TS_DBNCE_1000: |
2008 | case CS42L42_TS_DBNCE_1250: |
2009 | case CS42L42_TS_DBNCE_1500: |
2010 | cs42l42->ts_dbnc_fall = val; |
2011 | break; |
2012 | default: |
2013 | dev_err(dev, |
2014 | "Wrong cirrus,ts-dbnc-fall DT value %d\n" , |
2015 | val); |
2016 | cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; |
2017 | } |
2018 | } else { |
2019 | cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0; |
2020 | } |
2021 | |
2022 | regmap_update_bits(map: cs42l42->regmap, CS42L42_TSENSE_CTL, |
2023 | CS42L42_TS_FALL_DBNCE_TIME_MASK, |
2024 | val: (cs42l42->ts_dbnc_fall << |
2025 | CS42L42_TS_FALL_DBNCE_TIME_SHIFT)); |
2026 | |
2027 | ret = device_property_read_u32(dev, propname: "cirrus,btn-det-init-dbnce" , val: &val); |
2028 | if (!ret) { |
2029 | if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX) |
2030 | cs42l42->btn_det_init_dbnce = val; |
2031 | else { |
2032 | dev_err(dev, |
2033 | "Wrong cirrus,btn-det-init-dbnce DT value %d\n" , |
2034 | val); |
2035 | cs42l42->btn_det_init_dbnce = |
2036 | CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; |
2037 | } |
2038 | } else { |
2039 | cs42l42->btn_det_init_dbnce = |
2040 | CS42L42_BTN_DET_INIT_DBNCE_DEFAULT; |
2041 | } |
2042 | |
2043 | ret = device_property_read_u32(dev, propname: "cirrus,btn-det-event-dbnce" , val: &val); |
2044 | if (!ret) { |
2045 | if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX) |
2046 | cs42l42->btn_det_event_dbnce = val; |
2047 | else { |
2048 | dev_err(dev, |
2049 | "Wrong cirrus,btn-det-event-dbnce DT value %d\n" , val); |
2050 | cs42l42->btn_det_event_dbnce = |
2051 | CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; |
2052 | } |
2053 | } else { |
2054 | cs42l42->btn_det_event_dbnce = |
2055 | CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT; |
2056 | } |
2057 | |
2058 | ret = device_property_read_u32_array(dev, propname: "cirrus,bias-lvls" , |
2059 | val: thresholds, ARRAY_SIZE(thresholds)); |
2060 | if (!ret) { |
2061 | for (i = 0; i < CS42L42_NUM_BIASES; i++) { |
2062 | if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX) |
2063 | cs42l42->bias_thresholds[i] = thresholds[i]; |
2064 | else { |
2065 | dev_err(dev, |
2066 | "Wrong cirrus,bias-lvls[%d] DT value %d\n" , i, |
2067 | thresholds[i]); |
2068 | cs42l42->bias_thresholds[i] = threshold_defaults[i]; |
2069 | } |
2070 | } |
2071 | } else { |
2072 | for (i = 0; i < CS42L42_NUM_BIASES; i++) |
2073 | cs42l42->bias_thresholds[i] = threshold_defaults[i]; |
2074 | } |
2075 | |
2076 | ret = device_property_read_u32(dev, propname: "cirrus,hs-bias-ramp-rate" , val: &val); |
2077 | if (!ret) { |
2078 | switch (val) { |
2079 | case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL: |
2080 | cs42l42->hs_bias_ramp_rate = val; |
2081 | cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0; |
2082 | break; |
2083 | case CS42L42_HSBIAS_RAMP_FAST: |
2084 | cs42l42->hs_bias_ramp_rate = val; |
2085 | cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1; |
2086 | break; |
2087 | case CS42L42_HSBIAS_RAMP_SLOW: |
2088 | cs42l42->hs_bias_ramp_rate = val; |
2089 | cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; |
2090 | break; |
2091 | case CS42L42_HSBIAS_RAMP_SLOWEST: |
2092 | cs42l42->hs_bias_ramp_rate = val; |
2093 | cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3; |
2094 | break; |
2095 | default: |
2096 | dev_err(dev, |
2097 | "Wrong cirrus,hs-bias-ramp-rate DT value %d\n" , |
2098 | val); |
2099 | cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; |
2100 | cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; |
2101 | } |
2102 | } else { |
2103 | cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW; |
2104 | cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2; |
2105 | } |
2106 | |
2107 | regmap_update_bits(map: cs42l42->regmap, CS42L42_HS_BIAS_CTL, |
2108 | CS42L42_HSBIAS_RAMP_MASK, |
2109 | val: (cs42l42->hs_bias_ramp_rate << |
2110 | CS42L42_HSBIAS_RAMP_SHIFT)); |
2111 | |
2112 | if (device_property_read_bool(dev, propname: "cirrus,hs-bias-sense-disable" )) |
2113 | cs42l42->hs_bias_sense_en = 0; |
2114 | else |
2115 | cs42l42->hs_bias_sense_en = 1; |
2116 | |
2117 | return 0; |
2118 | } |
2119 | |
2120 | /* Datasheet suspend sequence */ |
2121 | static const struct reg_sequence __maybe_unused cs42l42_shutdown_seq[] = { |
2122 | REG_SEQ0(CS42L42_MIC_DET_CTL1, 0x9F), |
2123 | REG_SEQ0(CS42L42_ADC_OVFL_INT_MASK, 0x01), |
2124 | REG_SEQ0(CS42L42_MIXER_INT_MASK, 0x0F), |
2125 | REG_SEQ0(CS42L42_SRC_INT_MASK, 0x0F), |
2126 | REG_SEQ0(CS42L42_ASP_RX_INT_MASK, 0x1F), |
2127 | REG_SEQ0(CS42L42_ASP_TX_INT_MASK, 0x0F), |
2128 | REG_SEQ0(CS42L42_CODEC_INT_MASK, 0x03), |
2129 | REG_SEQ0(CS42L42_SRCPL_INT_MASK, 0x7F), |
2130 | REG_SEQ0(CS42L42_VPMON_INT_MASK, 0x01), |
2131 | REG_SEQ0(CS42L42_PLL_LOCK_INT_MASK, 0x01), |
2132 | REG_SEQ0(CS42L42_TSRS_PLUG_INT_MASK, 0x0F), |
2133 | REG_SEQ0(CS42L42_WAKE_CTL, 0xE1), |
2134 | REG_SEQ0(CS42L42_DET_INT1_MASK, 0xE0), |
2135 | REG_SEQ0(CS42L42_DET_INT2_MASK, 0xFF), |
2136 | REG_SEQ0(CS42L42_MIXER_CHA_VOL, 0x3F), |
2137 | REG_SEQ0(CS42L42_MIXER_ADC_VOL, 0x3F), |
2138 | REG_SEQ0(CS42L42_MIXER_CHB_VOL, 0x3F), |
2139 | REG_SEQ0(CS42L42_HP_CTL, 0x0F), |
2140 | REG_SEQ0(CS42L42_ASP_RX_DAI0_EN, 0x00), |
2141 | REG_SEQ0(CS42L42_ASP_CLK_CFG, 0x00), |
2142 | REG_SEQ0(CS42L42_HSDET_CTL2, 0x00), |
2143 | REG_SEQ0(CS42L42_PWR_CTL1, 0xFE), |
2144 | REG_SEQ0(CS42L42_PWR_CTL2, 0x8C), |
2145 | REG_SEQ0(CS42L42_DAC_CTL2, 0x02), |
2146 | REG_SEQ0(CS42L42_HS_CLAMP_DISABLE, 0x00), |
2147 | REG_SEQ0(CS42L42_MISC_DET_CTL, 0x03), |
2148 | REG_SEQ0(CS42L42_TIPSENSE_CTL, 0x02), |
2149 | REG_SEQ0(CS42L42_HSBIAS_SC_AUTOCTL, 0x03), |
2150 | REG_SEQ0(CS42L42_PWR_CTL1, 0xFF) |
2151 | }; |
2152 | |
2153 | int cs42l42_suspend(struct device *dev) |
2154 | { |
2155 | struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); |
2156 | unsigned int reg; |
2157 | u8 save_regs[ARRAY_SIZE(cs42l42_shutdown_seq)]; |
2158 | int i, ret; |
2159 | |
2160 | if (!cs42l42->init_done) |
2161 | return 0; |
2162 | |
2163 | /* |
2164 | * Wait for threaded irq handler to be idle and stop it processing |
2165 | * future interrupts. This ensures a safe disable if the interrupt |
2166 | * is shared. |
2167 | */ |
2168 | mutex_lock(&cs42l42->irq_lock); |
2169 | cs42l42->suspended = true; |
2170 | |
2171 | /* Save register values that will be overwritten by shutdown sequence */ |
2172 | for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) { |
2173 | regmap_read(map: cs42l42->regmap, reg: cs42l42_shutdown_seq[i].reg, val: ®); |
2174 | save_regs[i] = (u8)reg; |
2175 | } |
2176 | |
2177 | /* Shutdown codec */ |
2178 | regmap_multi_reg_write(map: cs42l42->regmap, |
2179 | regs: cs42l42_shutdown_seq, |
2180 | ARRAY_SIZE(cs42l42_shutdown_seq)); |
2181 | |
2182 | /* All interrupt sources are now disabled */ |
2183 | mutex_unlock(lock: &cs42l42->irq_lock); |
2184 | |
2185 | /* Wait for power-down complete */ |
2186 | msleep(CS42L42_PDN_DONE_TIME_MS); |
2187 | ret = regmap_read_poll_timeout(cs42l42->regmap, |
2188 | CS42L42_CODEC_STATUS, reg, |
2189 | (reg & CS42L42_PDN_DONE_MASK), |
2190 | CS42L42_PDN_DONE_POLL_US, |
2191 | CS42L42_PDN_DONE_TIMEOUT_US); |
2192 | if (ret) |
2193 | dev_warn(dev, "Failed to get PDN_DONE: %d\n" , ret); |
2194 | |
2195 | /* Discharge FILT+ */ |
2196 | regmap_update_bits(map: cs42l42->regmap, CS42L42_PWR_CTL2, |
2197 | CS42L42_DISCHARGE_FILT_MASK, CS42L42_DISCHARGE_FILT_MASK); |
2198 | |
2199 | regcache_cache_only(map: cs42l42->regmap, enable: true); |
2200 | gpiod_set_value_cansleep(desc: cs42l42->reset_gpio, value: 0); |
2201 | regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), consumers: cs42l42->supplies); |
2202 | |
2203 | /* Restore register values to the regmap cache */ |
2204 | for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) |
2205 | regmap_write(map: cs42l42->regmap, reg: cs42l42_shutdown_seq[i].reg, val: save_regs[i]); |
2206 | |
2207 | /* The cached address page register value is now stale */ |
2208 | regcache_drop_region(map: cs42l42->regmap, CS42L42_PAGE_REGISTER, CS42L42_PAGE_REGISTER); |
2209 | |
2210 | dev_dbg(dev, "System suspended\n" ); |
2211 | |
2212 | return 0; |
2213 | |
2214 | } |
2215 | EXPORT_SYMBOL_NS_GPL(cs42l42_suspend, SND_SOC_CS42L42_CORE); |
2216 | |
2217 | int cs42l42_resume(struct device *dev) |
2218 | { |
2219 | struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); |
2220 | int ret; |
2221 | |
2222 | if (!cs42l42->init_done) |
2223 | return 0; |
2224 | |
2225 | /* |
2226 | * If jack was unplugged and re-plugged during suspend it could |
2227 | * have changed type but the tip-sense state hasn't changed. |
2228 | * Force a plugged state to be re-evaluated. |
2229 | */ |
2230 | if (cs42l42->plug_state != CS42L42_TS_UNPLUG) |
2231 | cs42l42->plug_state = CS42L42_TS_TRANS; |
2232 | |
2233 | ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), consumers: cs42l42->supplies); |
2234 | if (ret != 0) { |
2235 | dev_err(dev, "Failed to enable supplies: %d\n" , ret); |
2236 | return ret; |
2237 | } |
2238 | |
2239 | gpiod_set_value_cansleep(desc: cs42l42->reset_gpio, value: 1); |
2240 | usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); |
2241 | |
2242 | dev_dbg(dev, "System resume powered up\n" ); |
2243 | |
2244 | return 0; |
2245 | } |
2246 | EXPORT_SYMBOL_NS_GPL(cs42l42_resume, SND_SOC_CS42L42_CORE); |
2247 | |
2248 | void cs42l42_resume_restore(struct device *dev) |
2249 | { |
2250 | struct cs42l42_private *cs42l42 = dev_get_drvdata(dev); |
2251 | |
2252 | regcache_cache_only(map: cs42l42->regmap, enable: false); |
2253 | regcache_mark_dirty(map: cs42l42->regmap); |
2254 | |
2255 | mutex_lock(&cs42l42->irq_lock); |
2256 | /* Sync LATCH_TO_VP first so the VP domain registers sync correctly */ |
2257 | regcache_sync_region(map: cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1); |
2258 | regcache_sync(map: cs42l42->regmap); |
2259 | |
2260 | cs42l42->suspended = false; |
2261 | mutex_unlock(lock: &cs42l42->irq_lock); |
2262 | |
2263 | dev_dbg(dev, "System resumed\n" ); |
2264 | } |
2265 | EXPORT_SYMBOL_NS_GPL(cs42l42_resume_restore, SND_SOC_CS42L42_CORE); |
2266 | |
2267 | static int __maybe_unused cs42l42_i2c_resume(struct device *dev) |
2268 | { |
2269 | int ret; |
2270 | |
2271 | ret = cs42l42_resume(dev); |
2272 | if (ret) |
2273 | return ret; |
2274 | |
2275 | cs42l42_resume_restore(dev); |
2276 | |
2277 | return 0; |
2278 | } |
2279 | |
2280 | int cs42l42_common_probe(struct cs42l42_private *cs42l42, |
2281 | const struct snd_soc_component_driver *component_drv, |
2282 | struct snd_soc_dai_driver *dai) |
2283 | { |
2284 | int ret, i; |
2285 | |
2286 | dev_set_drvdata(dev: cs42l42->dev, data: cs42l42); |
2287 | mutex_init(&cs42l42->irq_lock); |
2288 | |
2289 | BUILD_BUG_ON(ARRAY_SIZE(cs42l42_supply_names) != ARRAY_SIZE(cs42l42->supplies)); |
2290 | for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++) |
2291 | cs42l42->supplies[i].supply = cs42l42_supply_names[i]; |
2292 | |
2293 | ret = devm_regulator_bulk_get(dev: cs42l42->dev, |
2294 | ARRAY_SIZE(cs42l42->supplies), |
2295 | consumers: cs42l42->supplies); |
2296 | if (ret != 0) { |
2297 | dev_err(cs42l42->dev, |
2298 | "Failed to request supplies: %d\n" , ret); |
2299 | return ret; |
2300 | } |
2301 | |
2302 | ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), |
2303 | consumers: cs42l42->supplies); |
2304 | if (ret != 0) { |
2305 | dev_err(cs42l42->dev, |
2306 | "Failed to enable supplies: %d\n" , ret); |
2307 | return ret; |
2308 | } |
2309 | |
2310 | /* Reset the Device */ |
2311 | cs42l42->reset_gpio = devm_gpiod_get_optional(dev: cs42l42->dev, |
2312 | con_id: "reset" , flags: GPIOD_OUT_LOW); |
2313 | if (IS_ERR(ptr: cs42l42->reset_gpio)) { |
2314 | ret = PTR_ERR(ptr: cs42l42->reset_gpio); |
2315 | goto err_disable_noreset; |
2316 | } |
2317 | |
2318 | if (cs42l42->reset_gpio) { |
2319 | dev_dbg(cs42l42->dev, "Found reset GPIO\n" ); |
2320 | |
2321 | /* |
2322 | * ACPI can override the default GPIO state we requested |
2323 | * so ensure that we start with RESET low. |
2324 | */ |
2325 | gpiod_set_value_cansleep(desc: cs42l42->reset_gpio, value: 0); |
2326 | |
2327 | /* Ensure minimum reset pulse width */ |
2328 | usleep_range(min: 10, max: 500); |
2329 | |
2330 | /* |
2331 | * On SoundWire keep the chip in reset until we get an UNATTACH |
2332 | * notification from the SoundWire core. This acts as a |
2333 | * synchronization point to reject stale ATTACH notifications |
2334 | * if the chip was already enumerated before we reset it. |
2335 | */ |
2336 | if (cs42l42->sdw_peripheral) |
2337 | cs42l42->sdw_waiting_first_unattach = true; |
2338 | else |
2339 | gpiod_set_value_cansleep(desc: cs42l42->reset_gpio, value: 1); |
2340 | } |
2341 | usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2); |
2342 | |
2343 | /* Request IRQ if one was specified */ |
2344 | if (cs42l42->irq) { |
2345 | ret = request_threaded_irq(irq: cs42l42->irq, |
2346 | NULL, thread_fn: cs42l42_irq_thread, |
2347 | IRQF_ONESHOT | IRQF_TRIGGER_LOW, |
2348 | name: "cs42l42" , dev: cs42l42); |
2349 | if (ret) { |
2350 | dev_err_probe(dev: cs42l42->dev, err: ret, |
2351 | fmt: "Failed to request IRQ\n" ); |
2352 | goto err_disable_noirq; |
2353 | } |
2354 | } |
2355 | |
2356 | /* Register codec now so it can EPROBE_DEFER */ |
2357 | ret = devm_snd_soc_register_component(dev: cs42l42->dev, component_driver: component_drv, dai_drv: dai, num_dai: 1); |
2358 | if (ret < 0) |
2359 | goto err; |
2360 | |
2361 | return 0; |
2362 | |
2363 | err: |
2364 | if (cs42l42->irq) |
2365 | free_irq(cs42l42->irq, cs42l42); |
2366 | |
2367 | err_disable_noirq: |
2368 | gpiod_set_value_cansleep(desc: cs42l42->reset_gpio, value: 0); |
2369 | err_disable_noreset: |
2370 | regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), consumers: cs42l42->supplies); |
2371 | |
2372 | return ret; |
2373 | } |
2374 | EXPORT_SYMBOL_NS_GPL(cs42l42_common_probe, SND_SOC_CS42L42_CORE); |
2375 | |
2376 | int cs42l42_init(struct cs42l42_private *cs42l42) |
2377 | { |
2378 | unsigned int reg; |
2379 | int devid, ret; |
2380 | |
2381 | /* initialize codec */ |
2382 | devid = cirrus_read_device_id(regmap: cs42l42->regmap, CS42L42_DEVID_AB); |
2383 | if (devid < 0) { |
2384 | ret = devid; |
2385 | dev_err(cs42l42->dev, "Failed to read device ID: %d\n" , ret); |
2386 | goto err_disable; |
2387 | } |
2388 | |
2389 | if (devid != cs42l42->devid) { |
2390 | ret = -ENODEV; |
2391 | dev_err(cs42l42->dev, |
2392 | "CS42L%x Device ID (%X). Expected %X\n" , |
2393 | cs42l42->devid & 0xff, devid, cs42l42->devid); |
2394 | goto err_disable; |
2395 | } |
2396 | |
2397 | ret = regmap_read(map: cs42l42->regmap, CS42L42_REVID, val: ®); |
2398 | if (ret < 0) { |
2399 | dev_err(cs42l42->dev, "Get Revision ID failed\n" ); |
2400 | goto err_shutdown; |
2401 | } |
2402 | |
2403 | dev_info(cs42l42->dev, |
2404 | "Cirrus Logic CS42L%x, Revision: %02X\n" , |
2405 | cs42l42->devid & 0xff, reg & 0xFF); |
2406 | |
2407 | /* Power up the codec */ |
2408 | regmap_update_bits(map: cs42l42->regmap, CS42L42_PWR_CTL1, |
2409 | CS42L42_ASP_DAO_PDN_MASK | |
2410 | CS42L42_ASP_DAI_PDN_MASK | |
2411 | CS42L42_MIXER_PDN_MASK | |
2412 | CS42L42_EQ_PDN_MASK | |
2413 | CS42L42_HP_PDN_MASK | |
2414 | CS42L42_ADC_PDN_MASK | |
2415 | CS42L42_PDN_ALL_MASK, |
2416 | val: (1 << CS42L42_ASP_DAO_PDN_SHIFT) | |
2417 | (1 << CS42L42_ASP_DAI_PDN_SHIFT) | |
2418 | (1 << CS42L42_MIXER_PDN_SHIFT) | |
2419 | (1 << CS42L42_EQ_PDN_SHIFT) | |
2420 | (1 << CS42L42_HP_PDN_SHIFT) | |
2421 | (1 << CS42L42_ADC_PDN_SHIFT) | |
2422 | (0 << CS42L42_PDN_ALL_SHIFT)); |
2423 | |
2424 | ret = cs42l42_handle_device_data(dev: cs42l42->dev, cs42l42); |
2425 | if (ret != 0) |
2426 | goto err_shutdown; |
2427 | |
2428 | /* |
2429 | * SRC power is linked to ASP power so doesn't work in Soundwire mode. |
2430 | * Override it and use DAPM to control SRC power for Soundwire. |
2431 | */ |
2432 | if (cs42l42->sdw_peripheral) { |
2433 | regmap_update_bits(map: cs42l42->regmap, CS42L42_PWR_CTL2, |
2434 | CS42L42_SRC_PDN_OVERRIDE_MASK | |
2435 | CS42L42_DAC_SRC_PDNB_MASK | |
2436 | CS42L42_ADC_SRC_PDNB_MASK, |
2437 | CS42L42_SRC_PDN_OVERRIDE_MASK); |
2438 | } |
2439 | |
2440 | /* Setup headset detection */ |
2441 | cs42l42_setup_hs_type_detect(cs42l42); |
2442 | |
2443 | /* |
2444 | * Set init_done before unmasking interrupts so any triggered |
2445 | * immediately will be handled. |
2446 | */ |
2447 | cs42l42->init_done = true; |
2448 | |
2449 | /* Mask/Unmask Interrupts */ |
2450 | cs42l42_set_interrupt_masks(cs42l42); |
2451 | |
2452 | return 0; |
2453 | |
2454 | err_shutdown: |
2455 | regmap_write(map: cs42l42->regmap, CS42L42_CODEC_INT_MASK, val: 0xff); |
2456 | regmap_write(map: cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, val: 0xff); |
2457 | regmap_write(map: cs42l42->regmap, CS42L42_PWR_CTL1, val: 0xff); |
2458 | |
2459 | err_disable: |
2460 | if (cs42l42->irq) |
2461 | free_irq(cs42l42->irq, cs42l42); |
2462 | |
2463 | gpiod_set_value_cansleep(desc: cs42l42->reset_gpio, value: 0); |
2464 | regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), |
2465 | consumers: cs42l42->supplies); |
2466 | return ret; |
2467 | } |
2468 | EXPORT_SYMBOL_NS_GPL(cs42l42_init, SND_SOC_CS42L42_CORE); |
2469 | |
2470 | void cs42l42_common_remove(struct cs42l42_private *cs42l42) |
2471 | { |
2472 | if (cs42l42->irq) |
2473 | free_irq(cs42l42->irq, cs42l42); |
2474 | |
2475 | /* |
2476 | * The driver might not have control of reset and power supplies, |
2477 | * so ensure that the chip internals are powered down. |
2478 | */ |
2479 | if (cs42l42->init_done) { |
2480 | regmap_write(map: cs42l42->regmap, CS42L42_CODEC_INT_MASK, val: 0xff); |
2481 | regmap_write(map: cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, val: 0xff); |
2482 | regmap_write(map: cs42l42->regmap, CS42L42_PWR_CTL1, val: 0xff); |
2483 | } |
2484 | |
2485 | gpiod_set_value_cansleep(desc: cs42l42->reset_gpio, value: 0); |
2486 | regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), consumers: cs42l42->supplies); |
2487 | } |
2488 | EXPORT_SYMBOL_NS_GPL(cs42l42_common_remove, SND_SOC_CS42L42_CORE); |
2489 | |
2490 | MODULE_DESCRIPTION("ASoC CS42L42 driver" ); |
2491 | MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>" ); |
2492 | MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>" ); |
2493 | MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>" ); |
2494 | MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>" ); |
2495 | MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>" ); |
2496 | MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>" ); |
2497 | MODULE_LICENSE("GPL" ); |
2498 | |