1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * cs43130.c -- CS43130 ALSA Soc Audio driver |
4 | * |
5 | * Copyright 2017 Cirrus Logic, Inc. |
6 | * |
7 | * Authors: Li Xu <li.xu@cirrus.com> |
8 | */ |
9 | #include <linux/module.h> |
10 | #include <linux/moduleparam.h> |
11 | #include <linux/kernel.h> |
12 | #include <linux/init.h> |
13 | #include <linux/delay.h> |
14 | #include <linux/gpio/consumer.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/pm.h> |
17 | #include <linux/i2c.h> |
18 | #include <linux/property.h> |
19 | #include <linux/regmap.h> |
20 | #include <linux/slab.h> |
21 | #include <sound/core.h> |
22 | #include <sound/pcm.h> |
23 | #include <sound/pcm_params.h> |
24 | #include <sound/soc.h> |
25 | #include <sound/soc-dapm.h> |
26 | #include <sound/initval.h> |
27 | #include <sound/tlv.h> |
28 | #include <linux/regulator/consumer.h> |
29 | #include <linux/pm_runtime.h> |
30 | #include <linux/completion.h> |
31 | #include <linux/mutex.h> |
32 | #include <linux/workqueue.h> |
33 | #include <sound/jack.h> |
34 | |
35 | #include "cs43130.h" |
36 | #include "cirrus_legacy.h" |
37 | |
38 | static const struct reg_default cs43130_reg_defaults[] = { |
39 | {CS43130_SYS_CLK_CTL_1, 0x06}, |
40 | {CS43130_SP_SRATE, 0x01}, |
41 | {CS43130_SP_BITSIZE, 0x05}, |
42 | {CS43130_PAD_INT_CFG, 0x03}, |
43 | {CS43130_PWDN_CTL, 0xFE}, |
44 | {CS43130_CRYSTAL_SET, 0x04}, |
45 | {CS43130_PLL_SET_1, 0x00}, |
46 | {CS43130_PLL_SET_2, 0x00}, |
47 | {CS43130_PLL_SET_3, 0x00}, |
48 | {CS43130_PLL_SET_4, 0x00}, |
49 | {CS43130_PLL_SET_5, 0x40}, |
50 | {CS43130_PLL_SET_6, 0x10}, |
51 | {CS43130_PLL_SET_7, 0x80}, |
52 | {CS43130_PLL_SET_8, 0x03}, |
53 | {CS43130_PLL_SET_9, 0x02}, |
54 | {CS43130_PLL_SET_10, 0x02}, |
55 | {CS43130_CLKOUT_CTL, 0x00}, |
56 | {CS43130_ASP_NUM_1, 0x01}, |
57 | {CS43130_ASP_NUM_2, 0x00}, |
58 | {CS43130_ASP_DEN_1, 0x08}, |
59 | {CS43130_ASP_DEN_2, 0x00}, |
60 | {CS43130_ASP_LRCK_HI_TIME_1, 0x1F}, |
61 | {CS43130_ASP_LRCK_HI_TIME_2, 0x00}, |
62 | {CS43130_ASP_LRCK_PERIOD_1, 0x3F}, |
63 | {CS43130_ASP_LRCK_PERIOD_2, 0x00}, |
64 | {CS43130_ASP_CLOCK_CONF, 0x0C}, |
65 | {CS43130_ASP_FRAME_CONF, 0x0A}, |
66 | {CS43130_XSP_NUM_1, 0x01}, |
67 | {CS43130_XSP_NUM_2, 0x00}, |
68 | {CS43130_XSP_DEN_1, 0x02}, |
69 | {CS43130_XSP_DEN_2, 0x00}, |
70 | {CS43130_XSP_LRCK_HI_TIME_1, 0x1F}, |
71 | {CS43130_XSP_LRCK_HI_TIME_2, 0x00}, |
72 | {CS43130_XSP_LRCK_PERIOD_1, 0x3F}, |
73 | {CS43130_XSP_LRCK_PERIOD_2, 0x00}, |
74 | {CS43130_XSP_CLOCK_CONF, 0x0C}, |
75 | {CS43130_XSP_FRAME_CONF, 0x0A}, |
76 | {CS43130_ASP_CH_1_LOC, 0x00}, |
77 | {CS43130_ASP_CH_2_LOC, 0x00}, |
78 | {CS43130_ASP_CH_1_SZ_EN, 0x06}, |
79 | {CS43130_ASP_CH_2_SZ_EN, 0x0E}, |
80 | {CS43130_XSP_CH_1_LOC, 0x00}, |
81 | {CS43130_XSP_CH_2_LOC, 0x00}, |
82 | {CS43130_XSP_CH_1_SZ_EN, 0x06}, |
83 | {CS43130_XSP_CH_2_SZ_EN, 0x0E}, |
84 | {CS43130_DSD_VOL_B, 0x78}, |
85 | {CS43130_DSD_VOL_A, 0x78}, |
86 | {CS43130_DSD_PATH_CTL_1, 0xA8}, |
87 | {CS43130_DSD_INT_CFG, 0x00}, |
88 | {CS43130_DSD_PATH_CTL_2, 0x02}, |
89 | {CS43130_DSD_PCM_MIX_CTL, 0x00}, |
90 | {CS43130_DSD_PATH_CTL_3, 0x40}, |
91 | {CS43130_HP_OUT_CTL_1, 0x30}, |
92 | {CS43130_PCM_FILT_OPT, 0x02}, |
93 | {CS43130_PCM_VOL_B, 0x78}, |
94 | {CS43130_PCM_VOL_A, 0x78}, |
95 | {CS43130_PCM_PATH_CTL_1, 0xA8}, |
96 | {CS43130_PCM_PATH_CTL_2, 0x00}, |
97 | {CS43130_CLASS_H_CTL, 0x1E}, |
98 | {CS43130_HP_DETECT, 0x04}, |
99 | {CS43130_HP_LOAD_1, 0x00}, |
100 | {CS43130_HP_MEAS_LOAD_1, 0x00}, |
101 | {CS43130_HP_MEAS_LOAD_2, 0x00}, |
102 | {CS43130_INT_MASK_1, 0xFF}, |
103 | {CS43130_INT_MASK_2, 0xFF}, |
104 | {CS43130_INT_MASK_3, 0xFF}, |
105 | {CS43130_INT_MASK_4, 0xFF}, |
106 | {CS43130_INT_MASK_5, 0xFF}, |
107 | }; |
108 | |
109 | static bool cs43130_volatile_register(struct device *dev, unsigned int reg) |
110 | { |
111 | switch (reg) { |
112 | case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5: |
113 | case CS43130_HP_DC_STAT_1 ... CS43130_HP_DC_STAT_2: |
114 | case CS43130_HP_AC_STAT_1 ... CS43130_HP_AC_STAT_2: |
115 | return true; |
116 | default: |
117 | return false; |
118 | } |
119 | } |
120 | |
121 | static bool cs43130_readable_register(struct device *dev, unsigned int reg) |
122 | { |
123 | switch (reg) { |
124 | case CS43130_DEVID_AB ... CS43130_SYS_CLK_CTL_1: |
125 | case CS43130_SP_SRATE ... CS43130_PAD_INT_CFG: |
126 | case CS43130_PWDN_CTL: |
127 | case CS43130_CRYSTAL_SET: |
128 | case CS43130_PLL_SET_1 ... CS43130_PLL_SET_5: |
129 | case CS43130_PLL_SET_6: |
130 | case CS43130_PLL_SET_7: |
131 | case CS43130_PLL_SET_8: |
132 | case CS43130_PLL_SET_9: |
133 | case CS43130_PLL_SET_10: |
134 | case CS43130_CLKOUT_CTL: |
135 | case CS43130_ASP_NUM_1 ... CS43130_ASP_FRAME_CONF: |
136 | case CS43130_XSP_NUM_1 ... CS43130_XSP_FRAME_CONF: |
137 | case CS43130_ASP_CH_1_LOC: |
138 | case CS43130_ASP_CH_2_LOC: |
139 | case CS43130_ASP_CH_1_SZ_EN: |
140 | case CS43130_ASP_CH_2_SZ_EN: |
141 | case CS43130_XSP_CH_1_LOC: |
142 | case CS43130_XSP_CH_2_LOC: |
143 | case CS43130_XSP_CH_1_SZ_EN: |
144 | case CS43130_XSP_CH_2_SZ_EN: |
145 | case CS43130_DSD_VOL_B ... CS43130_DSD_PATH_CTL_3: |
146 | case CS43130_HP_OUT_CTL_1: |
147 | case CS43130_PCM_FILT_OPT ... CS43130_PCM_PATH_CTL_2: |
148 | case CS43130_CLASS_H_CTL: |
149 | case CS43130_HP_DETECT: |
150 | case CS43130_HP_STATUS: |
151 | case CS43130_HP_LOAD_1: |
152 | case CS43130_HP_MEAS_LOAD_1: |
153 | case CS43130_HP_MEAS_LOAD_2: |
154 | case CS43130_HP_DC_STAT_1: |
155 | case CS43130_HP_DC_STAT_2: |
156 | case CS43130_HP_AC_STAT_1: |
157 | case CS43130_HP_AC_STAT_2: |
158 | case CS43130_HP_LOAD_STAT: |
159 | case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5: |
160 | case CS43130_INT_MASK_1 ... CS43130_INT_MASK_5: |
161 | return true; |
162 | default: |
163 | return false; |
164 | } |
165 | } |
166 | |
167 | static bool cs43130_precious_register(struct device *dev, unsigned int reg) |
168 | { |
169 | switch (reg) { |
170 | case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5: |
171 | return true; |
172 | default: |
173 | return false; |
174 | } |
175 | } |
176 | |
177 | struct cs43130_pll_params { |
178 | unsigned int pll_in; |
179 | u8 sclk_prediv; |
180 | u8 pll_div_int; |
181 | u32 pll_div_frac; |
182 | u8 pll_mode; |
183 | u8 pll_divout; |
184 | unsigned int pll_out; |
185 | u8 pll_cal_ratio; |
186 | }; |
187 | |
188 | static const struct cs43130_pll_params pll_ratio_table[] = { |
189 | {9600000, 0x02, 0x49, 0x800000, 0x00, 0x08, 22579200, 151}, |
190 | {9600000, 0x02, 0x50, 0x000000, 0x00, 0x08, 24576000, 164}, |
191 | |
192 | {11289600, 0x02, 0X40, 0, 0x01, 0x08, 22579200, 128}, |
193 | {11289600, 0x02, 0x44, 0x06F700, 0x0, 0x08, 24576000, 139}, |
194 | |
195 | {12000000, 0x02, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120}, |
196 | {12000000, 0x02, 0x40, 0x000000, 0x00, 0x08, 24576000, 131}, |
197 | |
198 | {12288000, 0x02, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118}, |
199 | {12288000, 0x02, 0x40, 0x000000, 0x01, 0x08, 24576000, 128}, |
200 | |
201 | {13000000, 0x02, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111}, |
202 | {13000000, 0x02, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121}, |
203 | |
204 | {19200000, 0x03, 0x49, 0x800000, 0x00, 0x08, 22579200, 151}, |
205 | {19200000, 0x03, 0x50, 0x000000, 0x00, 0x08, 24576000, 164}, |
206 | |
207 | {22579200, 0, 0, 0, 0, 0, 22579200, 0}, |
208 | {22579200, 0x03, 0x44, 0x06F700, 0x00, 0x08, 24576000, 139}, |
209 | |
210 | {24000000, 0x03, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120}, |
211 | {24000000, 0x03, 0x40, 0x000000, 0x00, 0x08, 24576000, 131}, |
212 | |
213 | {24576000, 0x03, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118}, |
214 | {24576000, 0, 0, 0, 0, 0, 24576000, 0}, |
215 | |
216 | {26000000, 0x03, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111}, |
217 | {26000000, 0x03, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121}, |
218 | }; |
219 | |
220 | static const struct cs43130_pll_params *cs43130_get_pll_table( |
221 | unsigned int freq_in, unsigned int freq_out) |
222 | { |
223 | int i; |
224 | |
225 | for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) { |
226 | if (pll_ratio_table[i].pll_in == freq_in && |
227 | pll_ratio_table[i].pll_out == freq_out) |
228 | return &pll_ratio_table[i]; |
229 | } |
230 | |
231 | return NULL; |
232 | } |
233 | |
234 | static int cs43130_pll_config(struct snd_soc_component *component) |
235 | { |
236 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
237 | const struct cs43130_pll_params *pll_entry; |
238 | |
239 | dev_dbg(cs43130->dev, "cs43130->mclk = %u, cs43130->mclk_int = %u\n" , |
240 | cs43130->mclk, cs43130->mclk_int); |
241 | |
242 | pll_entry = cs43130_get_pll_table(freq_in: cs43130->mclk, freq_out: cs43130->mclk_int); |
243 | if (!pll_entry) |
244 | return -EINVAL; |
245 | |
246 | if (pll_entry->pll_cal_ratio == 0) { |
247 | regmap_update_bits(map: cs43130->regmap, CS43130_PLL_SET_1, |
248 | CS43130_PLL_START_MASK, val: 0); |
249 | |
250 | cs43130->pll_bypass = true; |
251 | return 0; |
252 | } |
253 | |
254 | cs43130->pll_bypass = false; |
255 | |
256 | regmap_update_bits(map: cs43130->regmap, CS43130_PLL_SET_2, |
257 | CS43130_PLL_DIV_DATA_MASK, |
258 | val: pll_entry->pll_div_frac >> |
259 | CS43130_PLL_DIV_FRAC_0_DATA_SHIFT); |
260 | regmap_update_bits(map: cs43130->regmap, CS43130_PLL_SET_3, |
261 | CS43130_PLL_DIV_DATA_MASK, |
262 | val: pll_entry->pll_div_frac >> |
263 | CS43130_PLL_DIV_FRAC_1_DATA_SHIFT); |
264 | regmap_update_bits(map: cs43130->regmap, CS43130_PLL_SET_4, |
265 | CS43130_PLL_DIV_DATA_MASK, |
266 | val: pll_entry->pll_div_frac >> |
267 | CS43130_PLL_DIV_FRAC_2_DATA_SHIFT); |
268 | regmap_write(map: cs43130->regmap, CS43130_PLL_SET_5, |
269 | val: pll_entry->pll_div_int); |
270 | regmap_write(map: cs43130->regmap, CS43130_PLL_SET_6, val: pll_entry->pll_divout); |
271 | regmap_write(map: cs43130->regmap, CS43130_PLL_SET_7, |
272 | val: pll_entry->pll_cal_ratio); |
273 | regmap_update_bits(map: cs43130->regmap, CS43130_PLL_SET_8, |
274 | CS43130_PLL_MODE_MASK, |
275 | val: pll_entry->pll_mode << CS43130_PLL_MODE_SHIFT); |
276 | regmap_write(map: cs43130->regmap, CS43130_PLL_SET_9, |
277 | val: pll_entry->sclk_prediv); |
278 | regmap_update_bits(map: cs43130->regmap, CS43130_PLL_SET_1, |
279 | CS43130_PLL_START_MASK, val: 1); |
280 | |
281 | return 0; |
282 | } |
283 | |
284 | static int cs43130_set_pll(struct snd_soc_component *component, int pll_id, int source, |
285 | unsigned int freq_in, unsigned int freq_out) |
286 | { |
287 | int ret = 0; |
288 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
289 | |
290 | switch (freq_in) { |
291 | case 9600000: |
292 | case 11289600: |
293 | case 12000000: |
294 | case 12288000: |
295 | case 13000000: |
296 | case 19200000: |
297 | case 22579200: |
298 | case 24000000: |
299 | case 24576000: |
300 | case 26000000: |
301 | cs43130->mclk = freq_in; |
302 | break; |
303 | default: |
304 | dev_err(cs43130->dev, |
305 | "unsupported pll input reference clock:%d\n" , freq_in); |
306 | return -EINVAL; |
307 | } |
308 | |
309 | switch (freq_out) { |
310 | case 22579200: |
311 | cs43130->mclk_int = freq_out; |
312 | break; |
313 | case 24576000: |
314 | cs43130->mclk_int = freq_out; |
315 | break; |
316 | default: |
317 | dev_err(cs43130->dev, |
318 | "unsupported pll output ref clock: %u\n" , freq_out); |
319 | return -EINVAL; |
320 | } |
321 | |
322 | ret = cs43130_pll_config(component); |
323 | dev_dbg(cs43130->dev, "cs43130->pll_bypass = %d" , cs43130->pll_bypass); |
324 | return ret; |
325 | } |
326 | |
327 | static int cs43130_wait_for_completion(struct cs43130_private *cs43130, struct completion *to_poll, |
328 | int time) |
329 | { |
330 | int stickies, offset, flag, ret; |
331 | |
332 | if (cs43130->has_irq_line) { |
333 | ret = wait_for_completion_timeout(x: to_poll, timeout: msecs_to_jiffies(m: time)); |
334 | if (ret == 0) |
335 | return -ETIMEDOUT; |
336 | else |
337 | return 0; // Discard number of jiffies left till timeout and return success |
338 | } |
339 | |
340 | if (to_poll == &cs43130->xtal_rdy) { |
341 | offset = 0; |
342 | flag = CS43130_XTAL_RDY_INT; |
343 | } else if (to_poll == &cs43130->pll_rdy) { |
344 | offset = 0; |
345 | flag = CS43130_PLL_RDY_INT; |
346 | } else { |
347 | return -EINVAL; |
348 | } |
349 | |
350 | return regmap_read_poll_timeout(cs43130->regmap, CS43130_INT_STATUS_1 + offset, |
351 | stickies, (stickies & flag), |
352 | 1000, time * 1000); |
353 | } |
354 | |
355 | static int cs43130_change_clksrc(struct snd_soc_component *component, |
356 | enum cs43130_mclk_src_sel src) |
357 | { |
358 | int ret; |
359 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
360 | int mclk_int_decoded; |
361 | |
362 | if (src == cs43130->mclk_int_src) { |
363 | /* clk source has not changed */ |
364 | return 0; |
365 | } |
366 | |
367 | switch (cs43130->mclk_int) { |
368 | case CS43130_MCLK_22M: |
369 | mclk_int_decoded = CS43130_MCLK_22P5; |
370 | break; |
371 | case CS43130_MCLK_24M: |
372 | mclk_int_decoded = CS43130_MCLK_24P5; |
373 | break; |
374 | default: |
375 | dev_err(cs43130->dev, "Invalid MCLK INT freq: %u\n" , cs43130->mclk_int); |
376 | return -EINVAL; |
377 | } |
378 | |
379 | switch (src) { |
380 | case CS43130_MCLK_SRC_EXT: |
381 | cs43130->pll_bypass = true; |
382 | cs43130->mclk_int_src = CS43130_MCLK_SRC_EXT; |
383 | if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) { |
384 | regmap_update_bits(map: cs43130->regmap, CS43130_PWDN_CTL, |
385 | CS43130_PDN_XTAL_MASK, |
386 | val: 1 << CS43130_PDN_XTAL_SHIFT); |
387 | } else { |
388 | reinit_completion(x: &cs43130->xtal_rdy); |
389 | regmap_update_bits(map: cs43130->regmap, CS43130_INT_MASK_1, |
390 | CS43130_XTAL_RDY_INT_MASK, val: 0); |
391 | regmap_update_bits(map: cs43130->regmap, CS43130_PWDN_CTL, |
392 | CS43130_PDN_XTAL_MASK, val: 0); |
393 | ret = cs43130_wait_for_completion(cs43130, to_poll: &cs43130->xtal_rdy, time: 100); |
394 | regmap_update_bits(map: cs43130->regmap, CS43130_INT_MASK_1, |
395 | CS43130_XTAL_RDY_INT_MASK, |
396 | val: 1 << CS43130_XTAL_RDY_INT_SHIFT); |
397 | if (ret) { |
398 | dev_err(cs43130->dev, "Error waiting for XTAL_READY interrupt: %d\n" , ret); |
399 | return ret; |
400 | } |
401 | } |
402 | |
403 | regmap_update_bits(map: cs43130->regmap, CS43130_SYS_CLK_CTL_1, |
404 | CS43130_MCLK_SRC_SEL_MASK, |
405 | val: src << CS43130_MCLK_SRC_SEL_SHIFT); |
406 | regmap_update_bits(map: cs43130->regmap, CS43130_SYS_CLK_CTL_1, |
407 | CS43130_MCLK_INT_MASK, |
408 | val: mclk_int_decoded << CS43130_MCLK_INT_SHIFT); |
409 | usleep_range(min: 150, max: 200); |
410 | |
411 | regmap_update_bits(map: cs43130->regmap, CS43130_PWDN_CTL, |
412 | CS43130_PDN_PLL_MASK, |
413 | val: 1 << CS43130_PDN_PLL_SHIFT); |
414 | break; |
415 | case CS43130_MCLK_SRC_PLL: |
416 | cs43130->pll_bypass = false; |
417 | cs43130->mclk_int_src = CS43130_MCLK_SRC_PLL; |
418 | if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) { |
419 | regmap_update_bits(map: cs43130->regmap, CS43130_PWDN_CTL, |
420 | CS43130_PDN_XTAL_MASK, |
421 | val: 1 << CS43130_PDN_XTAL_SHIFT); |
422 | } else { |
423 | reinit_completion(x: &cs43130->xtal_rdy); |
424 | regmap_update_bits(map: cs43130->regmap, CS43130_INT_MASK_1, |
425 | CS43130_XTAL_RDY_INT_MASK, val: 0); |
426 | regmap_update_bits(map: cs43130->regmap, CS43130_PWDN_CTL, |
427 | CS43130_PDN_XTAL_MASK, val: 0); |
428 | ret = cs43130_wait_for_completion(cs43130, to_poll: &cs43130->xtal_rdy, time: 100); |
429 | regmap_update_bits(map: cs43130->regmap, CS43130_INT_MASK_1, |
430 | CS43130_XTAL_RDY_INT_MASK, |
431 | val: 1 << CS43130_XTAL_RDY_INT_SHIFT); |
432 | if (ret) { |
433 | dev_err(cs43130->dev, "Error waiting for XTAL_READY interrupt: %d\n" , ret); |
434 | return ret; |
435 | } |
436 | } |
437 | |
438 | reinit_completion(x: &cs43130->pll_rdy); |
439 | regmap_update_bits(map: cs43130->regmap, CS43130_INT_MASK_1, |
440 | CS43130_PLL_RDY_INT_MASK, val: 0); |
441 | regmap_update_bits(map: cs43130->regmap, CS43130_PWDN_CTL, |
442 | CS43130_PDN_PLL_MASK, val: 0); |
443 | ret = cs43130_wait_for_completion(cs43130, to_poll: &cs43130->pll_rdy, time: 100); |
444 | regmap_update_bits(map: cs43130->regmap, CS43130_INT_MASK_1, |
445 | CS43130_PLL_RDY_INT_MASK, |
446 | val: 1 << CS43130_PLL_RDY_INT_SHIFT); |
447 | if (ret) { |
448 | dev_err(cs43130->dev, "Error waiting for PLL_READY interrupt: %d\n" , ret); |
449 | return ret; |
450 | } |
451 | |
452 | regmap_update_bits(map: cs43130->regmap, CS43130_SYS_CLK_CTL_1, |
453 | CS43130_MCLK_SRC_SEL_MASK, |
454 | val: src << CS43130_MCLK_SRC_SEL_SHIFT); |
455 | regmap_update_bits(map: cs43130->regmap, CS43130_SYS_CLK_CTL_1, |
456 | CS43130_MCLK_INT_MASK, |
457 | val: mclk_int_decoded << CS43130_MCLK_INT_SHIFT); |
458 | usleep_range(min: 150, max: 200); |
459 | break; |
460 | case CS43130_MCLK_SRC_RCO: |
461 | cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO; |
462 | |
463 | regmap_update_bits(map: cs43130->regmap, CS43130_SYS_CLK_CTL_1, |
464 | CS43130_MCLK_SRC_SEL_MASK, |
465 | val: src << CS43130_MCLK_SRC_SEL_SHIFT); |
466 | regmap_update_bits(map: cs43130->regmap, CS43130_SYS_CLK_CTL_1, |
467 | CS43130_MCLK_INT_MASK, |
468 | val: CS43130_MCLK_22P5 << CS43130_MCLK_INT_SHIFT); |
469 | usleep_range(min: 150, max: 200); |
470 | |
471 | regmap_update_bits(map: cs43130->regmap, CS43130_PWDN_CTL, |
472 | CS43130_PDN_XTAL_MASK, |
473 | val: 1 << CS43130_PDN_XTAL_SHIFT); |
474 | regmap_update_bits(map: cs43130->regmap, CS43130_PWDN_CTL, |
475 | CS43130_PDN_PLL_MASK, |
476 | val: 1 << CS43130_PDN_PLL_SHIFT); |
477 | break; |
478 | default: |
479 | dev_err(cs43130->dev, "Invalid MCLK source value\n" ); |
480 | return -EINVAL; |
481 | } |
482 | |
483 | return 0; |
484 | } |
485 | |
486 | static const struct cs43130_bitwidth_map cs43130_bitwidth_table[] = { |
487 | {8, CS43130_SP_BIT_SIZE_8, CS43130_CH_BIT_SIZE_8}, |
488 | {16, CS43130_SP_BIT_SIZE_16, CS43130_CH_BIT_SIZE_16}, |
489 | {24, CS43130_SP_BIT_SIZE_24, CS43130_CH_BIT_SIZE_24}, |
490 | {32, CS43130_SP_BIT_SIZE_32, CS43130_CH_BIT_SIZE_32}, |
491 | }; |
492 | |
493 | static const struct cs43130_bitwidth_map *cs43130_get_bitwidth_table( |
494 | unsigned int bitwidth) |
495 | { |
496 | int i; |
497 | |
498 | for (i = 0; i < ARRAY_SIZE(cs43130_bitwidth_table); i++) { |
499 | if (cs43130_bitwidth_table[i].bitwidth == bitwidth) |
500 | return &cs43130_bitwidth_table[i]; |
501 | } |
502 | |
503 | return NULL; |
504 | } |
505 | |
506 | static int cs43130_set_bitwidth(int dai_id, unsigned int bitwidth_dai, |
507 | struct regmap *regmap) |
508 | { |
509 | const struct cs43130_bitwidth_map *bw_map; |
510 | |
511 | bw_map = cs43130_get_bitwidth_table(bitwidth: bitwidth_dai); |
512 | if (!bw_map) |
513 | return -EINVAL; |
514 | |
515 | switch (dai_id) { |
516 | case CS43130_ASP_PCM_DAI: |
517 | case CS43130_ASP_DOP_DAI: |
518 | regmap_update_bits(map: regmap, CS43130_ASP_CH_1_SZ_EN, |
519 | CS43130_CH_BITSIZE_MASK, val: bw_map->ch_bit); |
520 | regmap_update_bits(map: regmap, CS43130_ASP_CH_2_SZ_EN, |
521 | CS43130_CH_BITSIZE_MASK, val: bw_map->ch_bit); |
522 | regmap_update_bits(map: regmap, CS43130_SP_BITSIZE, |
523 | CS43130_ASP_BITSIZE_MASK, val: bw_map->sp_bit); |
524 | break; |
525 | case CS43130_XSP_DOP_DAI: |
526 | regmap_update_bits(map: regmap, CS43130_XSP_CH_1_SZ_EN, |
527 | CS43130_CH_BITSIZE_MASK, val: bw_map->ch_bit); |
528 | regmap_update_bits(map: regmap, CS43130_XSP_CH_2_SZ_EN, |
529 | CS43130_CH_BITSIZE_MASK, val: bw_map->ch_bit); |
530 | regmap_update_bits(map: regmap, CS43130_SP_BITSIZE, |
531 | CS43130_XSP_BITSIZE_MASK, val: bw_map->sp_bit << |
532 | CS43130_XSP_BITSIZE_SHIFT); |
533 | break; |
534 | default: |
535 | return -EINVAL; |
536 | } |
537 | |
538 | return 0; |
539 | } |
540 | |
541 | static const struct cs43130_rate_map cs43130_rate_table[] = { |
542 | {32000, CS43130_ASP_SPRATE_32K}, |
543 | {44100, CS43130_ASP_SPRATE_44_1K}, |
544 | {48000, CS43130_ASP_SPRATE_48K}, |
545 | {88200, CS43130_ASP_SPRATE_88_2K}, |
546 | {96000, CS43130_ASP_SPRATE_96K}, |
547 | {176400, CS43130_ASP_SPRATE_176_4K}, |
548 | {192000, CS43130_ASP_SPRATE_192K}, |
549 | {352800, CS43130_ASP_SPRATE_352_8K}, |
550 | {384000, CS43130_ASP_SPRATE_384K}, |
551 | }; |
552 | |
553 | static const struct cs43130_rate_map *cs43130_get_rate_table(int fs) |
554 | { |
555 | int i; |
556 | |
557 | for (i = 0; i < ARRAY_SIZE(cs43130_rate_table); i++) { |
558 | if (cs43130_rate_table[i].fs == fs) |
559 | return &cs43130_rate_table[i]; |
560 | } |
561 | |
562 | return NULL; |
563 | } |
564 | |
565 | static const struct cs43130_clk_gen *cs43130_get_clk_gen(int mclk_int, int fs, |
566 | const struct cs43130_clk_gen *clk_gen_table, int len_clk_gen_table) |
567 | { |
568 | int i; |
569 | |
570 | for (i = 0; i < len_clk_gen_table; i++) { |
571 | if (clk_gen_table[i].mclk_int == mclk_int && |
572 | clk_gen_table[i].fs == fs) |
573 | return &clk_gen_table[i]; |
574 | } |
575 | |
576 | return NULL; |
577 | } |
578 | |
579 | static int cs43130_set_sp_fmt(int dai_id, unsigned int bitwidth_sclk, |
580 | struct snd_pcm_hw_params *params, |
581 | struct cs43130_private *cs43130) |
582 | { |
583 | u16 frm_size; |
584 | u16 hi_size; |
585 | u8 frm_delay; |
586 | u8 frm_phase; |
587 | u8 frm_data; |
588 | u8 sclk_edge; |
589 | u8 lrck_edge; |
590 | u8 clk_data; |
591 | u8 loc_ch1; |
592 | u8 loc_ch2; |
593 | u8 dai_mode_val; |
594 | const struct cs43130_clk_gen *clk_gen; |
595 | |
596 | switch (cs43130->dais[dai_id].dai_format) { |
597 | case SND_SOC_DAIFMT_I2S: |
598 | hi_size = bitwidth_sclk; |
599 | frm_delay = 2; |
600 | frm_phase = 0; |
601 | break; |
602 | case SND_SOC_DAIFMT_LEFT_J: |
603 | hi_size = bitwidth_sclk; |
604 | frm_delay = 0; |
605 | frm_phase = 1; |
606 | break; |
607 | case SND_SOC_DAIFMT_DSP_A: |
608 | hi_size = 1; |
609 | frm_delay = 2; |
610 | frm_phase = 1; |
611 | break; |
612 | case SND_SOC_DAIFMT_DSP_B: |
613 | hi_size = 1; |
614 | frm_delay = 0; |
615 | frm_phase = 1; |
616 | break; |
617 | default: |
618 | return -EINVAL; |
619 | } |
620 | |
621 | switch (cs43130->dais[dai_id].dai_invert) { |
622 | case SND_SOC_DAIFMT_NB_NF: |
623 | sclk_edge = 1; |
624 | lrck_edge = 0; |
625 | break; |
626 | case SND_SOC_DAIFMT_IB_NF: |
627 | sclk_edge = 0; |
628 | lrck_edge = 0; |
629 | break; |
630 | case SND_SOC_DAIFMT_NB_IF: |
631 | sclk_edge = 1; |
632 | lrck_edge = 1; |
633 | break; |
634 | case SND_SOC_DAIFMT_IB_IF: |
635 | sclk_edge = 0; |
636 | lrck_edge = 1; |
637 | break; |
638 | default: |
639 | return -EINVAL; |
640 | } |
641 | |
642 | switch (cs43130->dais[dai_id].dai_mode) { |
643 | case SND_SOC_DAIFMT_CBS_CFS: |
644 | dai_mode_val = 0; |
645 | break; |
646 | case SND_SOC_DAIFMT_CBM_CFM: |
647 | dai_mode_val = 1; |
648 | break; |
649 | default: |
650 | return -EINVAL; |
651 | } |
652 | |
653 | frm_size = bitwidth_sclk * params_channels(p: params); |
654 | loc_ch1 = 0; |
655 | loc_ch2 = bitwidth_sclk * (params_channels(p: params) - 1); |
656 | |
657 | frm_data = frm_delay & CS43130_SP_FSD_MASK; |
658 | frm_data |= (frm_phase << CS43130_SP_STP_SHIFT) & CS43130_SP_STP_MASK; |
659 | |
660 | clk_data = lrck_edge & CS43130_SP_LCPOL_IN_MASK; |
661 | clk_data |= (lrck_edge << CS43130_SP_LCPOL_OUT_SHIFT) & |
662 | CS43130_SP_LCPOL_OUT_MASK; |
663 | clk_data |= (sclk_edge << CS43130_SP_SCPOL_IN_SHIFT) & |
664 | CS43130_SP_SCPOL_IN_MASK; |
665 | clk_data |= (sclk_edge << CS43130_SP_SCPOL_OUT_SHIFT) & |
666 | CS43130_SP_SCPOL_OUT_MASK; |
667 | clk_data |= (dai_mode_val << CS43130_SP_MODE_SHIFT) & |
668 | CS43130_SP_MODE_MASK; |
669 | |
670 | switch (dai_id) { |
671 | case CS43130_ASP_PCM_DAI: |
672 | case CS43130_ASP_DOP_DAI: |
673 | regmap_update_bits(map: cs43130->regmap, CS43130_ASP_LRCK_PERIOD_1, |
674 | CS43130_SP_LCPR_DATA_MASK, val: (frm_size - 1) >> |
675 | CS43130_SP_LCPR_LSB_DATA_SHIFT); |
676 | regmap_update_bits(map: cs43130->regmap, CS43130_ASP_LRCK_PERIOD_2, |
677 | CS43130_SP_LCPR_DATA_MASK, val: (frm_size - 1) >> |
678 | CS43130_SP_LCPR_MSB_DATA_SHIFT); |
679 | regmap_update_bits(map: cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_1, |
680 | CS43130_SP_LCHI_DATA_MASK, val: (hi_size - 1) >> |
681 | CS43130_SP_LCHI_LSB_DATA_SHIFT); |
682 | regmap_update_bits(map: cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_2, |
683 | CS43130_SP_LCHI_DATA_MASK, val: (hi_size - 1) >> |
684 | CS43130_SP_LCHI_MSB_DATA_SHIFT); |
685 | regmap_write(map: cs43130->regmap, CS43130_ASP_FRAME_CONF, val: frm_data); |
686 | regmap_write(map: cs43130->regmap, CS43130_ASP_CH_1_LOC, val: loc_ch1); |
687 | regmap_write(map: cs43130->regmap, CS43130_ASP_CH_2_LOC, val: loc_ch2); |
688 | regmap_update_bits(map: cs43130->regmap, CS43130_ASP_CH_1_SZ_EN, |
689 | CS43130_CH_EN_MASK, val: 1 << CS43130_CH_EN_SHIFT); |
690 | regmap_update_bits(map: cs43130->regmap, CS43130_ASP_CH_2_SZ_EN, |
691 | CS43130_CH_EN_MASK, val: 1 << CS43130_CH_EN_SHIFT); |
692 | regmap_write(map: cs43130->regmap, CS43130_ASP_CLOCK_CONF, val: clk_data); |
693 | break; |
694 | case CS43130_XSP_DOP_DAI: |
695 | regmap_update_bits(map: cs43130->regmap, CS43130_XSP_LRCK_PERIOD_1, |
696 | CS43130_SP_LCPR_DATA_MASK, val: (frm_size - 1) >> |
697 | CS43130_SP_LCPR_LSB_DATA_SHIFT); |
698 | regmap_update_bits(map: cs43130->regmap, CS43130_XSP_LRCK_PERIOD_2, |
699 | CS43130_SP_LCPR_DATA_MASK, val: (frm_size - 1) >> |
700 | CS43130_SP_LCPR_MSB_DATA_SHIFT); |
701 | regmap_update_bits(map: cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_1, |
702 | CS43130_SP_LCHI_DATA_MASK, val: (hi_size - 1) >> |
703 | CS43130_SP_LCHI_LSB_DATA_SHIFT); |
704 | regmap_update_bits(map: cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_2, |
705 | CS43130_SP_LCHI_DATA_MASK, val: (hi_size - 1) >> |
706 | CS43130_SP_LCHI_MSB_DATA_SHIFT); |
707 | regmap_write(map: cs43130->regmap, CS43130_XSP_FRAME_CONF, val: frm_data); |
708 | regmap_write(map: cs43130->regmap, CS43130_XSP_CH_1_LOC, val: loc_ch1); |
709 | regmap_write(map: cs43130->regmap, CS43130_XSP_CH_2_LOC, val: loc_ch2); |
710 | regmap_update_bits(map: cs43130->regmap, CS43130_XSP_CH_1_SZ_EN, |
711 | CS43130_CH_EN_MASK, val: 1 << CS43130_CH_EN_SHIFT); |
712 | regmap_update_bits(map: cs43130->regmap, CS43130_XSP_CH_2_SZ_EN, |
713 | CS43130_CH_EN_MASK, val: 1 << CS43130_CH_EN_SHIFT); |
714 | regmap_write(map: cs43130->regmap, CS43130_XSP_CLOCK_CONF, val: clk_data); |
715 | break; |
716 | default: |
717 | return -EINVAL; |
718 | } |
719 | |
720 | switch (frm_size) { |
721 | case 16: |
722 | clk_gen = cs43130_get_clk_gen(mclk_int: cs43130->mclk_int, |
723 | fs: params_rate(p: params), |
724 | clk_gen_table: cs43130_16_clk_gen, |
725 | ARRAY_SIZE(cs43130_16_clk_gen)); |
726 | break; |
727 | case 32: |
728 | clk_gen = cs43130_get_clk_gen(mclk_int: cs43130->mclk_int, |
729 | fs: params_rate(p: params), |
730 | clk_gen_table: cs43130_32_clk_gen, |
731 | ARRAY_SIZE(cs43130_32_clk_gen)); |
732 | break; |
733 | case 48: |
734 | clk_gen = cs43130_get_clk_gen(mclk_int: cs43130->mclk_int, |
735 | fs: params_rate(p: params), |
736 | clk_gen_table: cs43130_48_clk_gen, |
737 | ARRAY_SIZE(cs43130_48_clk_gen)); |
738 | break; |
739 | case 64: |
740 | clk_gen = cs43130_get_clk_gen(mclk_int: cs43130->mclk_int, |
741 | fs: params_rate(p: params), |
742 | clk_gen_table: cs43130_64_clk_gen, |
743 | ARRAY_SIZE(cs43130_64_clk_gen)); |
744 | break; |
745 | default: |
746 | return -EINVAL; |
747 | } |
748 | |
749 | if (!clk_gen) |
750 | return -EINVAL; |
751 | |
752 | switch (dai_id) { |
753 | case CS43130_ASP_PCM_DAI: |
754 | case CS43130_ASP_DOP_DAI: |
755 | regmap_write(map: cs43130->regmap, CS43130_ASP_DEN_1, |
756 | val: (clk_gen->v.denominator & CS43130_SP_M_LSB_DATA_MASK) >> |
757 | CS43130_SP_M_LSB_DATA_SHIFT); |
758 | regmap_write(map: cs43130->regmap, CS43130_ASP_DEN_2, |
759 | val: (clk_gen->v.denominator & CS43130_SP_M_MSB_DATA_MASK) >> |
760 | CS43130_SP_M_MSB_DATA_SHIFT); |
761 | regmap_write(map: cs43130->regmap, CS43130_ASP_NUM_1, |
762 | val: (clk_gen->v.numerator & CS43130_SP_N_LSB_DATA_MASK) >> |
763 | CS43130_SP_N_LSB_DATA_SHIFT); |
764 | regmap_write(map: cs43130->regmap, CS43130_ASP_NUM_2, |
765 | val: (clk_gen->v.numerator & CS43130_SP_N_MSB_DATA_MASK) >> |
766 | CS43130_SP_N_MSB_DATA_SHIFT); |
767 | break; |
768 | case CS43130_XSP_DOP_DAI: |
769 | regmap_write(map: cs43130->regmap, CS43130_XSP_DEN_1, |
770 | val: (clk_gen->v.denominator & CS43130_SP_M_LSB_DATA_MASK) >> |
771 | CS43130_SP_M_LSB_DATA_SHIFT); |
772 | regmap_write(map: cs43130->regmap, CS43130_XSP_DEN_2, |
773 | val: (clk_gen->v.denominator & CS43130_SP_M_MSB_DATA_MASK) >> |
774 | CS43130_SP_M_MSB_DATA_SHIFT); |
775 | regmap_write(map: cs43130->regmap, CS43130_XSP_NUM_1, |
776 | val: (clk_gen->v.numerator & CS43130_SP_N_LSB_DATA_MASK) >> |
777 | CS43130_SP_N_LSB_DATA_SHIFT); |
778 | regmap_write(map: cs43130->regmap, CS43130_XSP_NUM_2, |
779 | val: (clk_gen->v.numerator & CS43130_SP_N_MSB_DATA_MASK) >> |
780 | CS43130_SP_N_MSB_DATA_SHIFT); |
781 | break; |
782 | default: |
783 | return -EINVAL; |
784 | } |
785 | |
786 | return 0; |
787 | } |
788 | |
789 | static int cs43130_pcm_dsd_mix(bool en, struct regmap *regmap) |
790 | { |
791 | if (en) { |
792 | regmap_update_bits(map: regmap, CS43130_DSD_PCM_MIX_CTL, |
793 | CS43130_MIX_PCM_PREP_MASK, |
794 | val: 1 << CS43130_MIX_PCM_PREP_SHIFT); |
795 | usleep_range(min: 6000, max: 6050); |
796 | regmap_update_bits(map: regmap, CS43130_DSD_PCM_MIX_CTL, |
797 | CS43130_MIX_PCM_DSD_MASK, |
798 | val: 1 << CS43130_MIX_PCM_DSD_SHIFT); |
799 | } else { |
800 | regmap_update_bits(map: regmap, CS43130_DSD_PCM_MIX_CTL, |
801 | CS43130_MIX_PCM_DSD_MASK, |
802 | val: 0 << CS43130_MIX_PCM_DSD_SHIFT); |
803 | usleep_range(min: 1600, max: 1650); |
804 | regmap_update_bits(map: regmap, CS43130_DSD_PCM_MIX_CTL, |
805 | CS43130_MIX_PCM_PREP_MASK, |
806 | val: 0 << CS43130_MIX_PCM_PREP_SHIFT); |
807 | } |
808 | |
809 | return 0; |
810 | } |
811 | |
812 | static int cs43130_dsd_hw_params(struct snd_pcm_substream *substream, |
813 | struct snd_pcm_hw_params *params, |
814 | struct snd_soc_dai *dai) |
815 | { |
816 | struct snd_soc_component *component = dai->component; |
817 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
818 | unsigned int required_clk; |
819 | u8 dsd_speed; |
820 | |
821 | mutex_lock(&cs43130->clk_mutex); |
822 | if (!cs43130->clk_req) { |
823 | /* no DAI is currently using clk */ |
824 | if (!(CS43130_MCLK_22M % params_rate(p: params))) |
825 | required_clk = CS43130_MCLK_22M; |
826 | else |
827 | required_clk = CS43130_MCLK_24M; |
828 | |
829 | cs43130_set_pll(component, pll_id: 0, source: 0, freq_in: cs43130->mclk, freq_out: required_clk); |
830 | if (cs43130->pll_bypass) |
831 | cs43130_change_clksrc(component, src: CS43130_MCLK_SRC_EXT); |
832 | else |
833 | cs43130_change_clksrc(component, src: CS43130_MCLK_SRC_PLL); |
834 | } |
835 | |
836 | cs43130->clk_req++; |
837 | if (cs43130->clk_req == 2) |
838 | cs43130_pcm_dsd_mix(en: true, regmap: cs43130->regmap); |
839 | mutex_unlock(lock: &cs43130->clk_mutex); |
840 | |
841 | switch (params_rate(p: params)) { |
842 | case 176400: |
843 | dsd_speed = 0; |
844 | break; |
845 | case 352800: |
846 | dsd_speed = 1; |
847 | break; |
848 | default: |
849 | dev_err(cs43130->dev, "Rate(%u) not supported\n" , |
850 | params_rate(params)); |
851 | return -EINVAL; |
852 | } |
853 | |
854 | if (cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM) |
855 | regmap_update_bits(map: cs43130->regmap, CS43130_DSD_INT_CFG, |
856 | CS43130_DSD_MASTER, CS43130_DSD_MASTER); |
857 | else |
858 | regmap_update_bits(map: cs43130->regmap, CS43130_DSD_INT_CFG, |
859 | CS43130_DSD_MASTER, val: 0); |
860 | |
861 | regmap_update_bits(map: cs43130->regmap, CS43130_DSD_PATH_CTL_2, |
862 | CS43130_DSD_SPEED_MASK, |
863 | val: dsd_speed << CS43130_DSD_SPEED_SHIFT); |
864 | regmap_update_bits(map: cs43130->regmap, CS43130_DSD_PATH_CTL_2, |
865 | CS43130_DSD_SRC_MASK, val: CS43130_DSD_SRC_DSD << |
866 | CS43130_DSD_SRC_SHIFT); |
867 | |
868 | return 0; |
869 | } |
870 | |
871 | static int cs43130_hw_params(struct snd_pcm_substream *substream, |
872 | struct snd_pcm_hw_params *params, |
873 | struct snd_soc_dai *dai) |
874 | { |
875 | struct snd_soc_component *component = dai->component; |
876 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
877 | const struct cs43130_rate_map *rate_map; |
878 | unsigned int sclk = cs43130->dais[dai->id].sclk; |
879 | unsigned int bitwidth_sclk; |
880 | unsigned int bitwidth_dai = (unsigned int)(params_width(p: params)); |
881 | unsigned int required_clk; |
882 | u8 dsd_speed; |
883 | |
884 | mutex_lock(&cs43130->clk_mutex); |
885 | if (!cs43130->clk_req) { |
886 | /* no DAI is currently using clk */ |
887 | if (!(CS43130_MCLK_22M % params_rate(p: params))) |
888 | required_clk = CS43130_MCLK_22M; |
889 | else |
890 | required_clk = CS43130_MCLK_24M; |
891 | |
892 | cs43130_set_pll(component, pll_id: 0, source: 0, freq_in: cs43130->mclk, freq_out: required_clk); |
893 | if (cs43130->pll_bypass) |
894 | cs43130_change_clksrc(component, src: CS43130_MCLK_SRC_EXT); |
895 | else |
896 | cs43130_change_clksrc(component, src: CS43130_MCLK_SRC_PLL); |
897 | } |
898 | |
899 | cs43130->clk_req++; |
900 | if (cs43130->clk_req == 2) |
901 | cs43130_pcm_dsd_mix(en: true, regmap: cs43130->regmap); |
902 | mutex_unlock(lock: &cs43130->clk_mutex); |
903 | |
904 | switch (dai->id) { |
905 | case CS43130_ASP_DOP_DAI: |
906 | case CS43130_XSP_DOP_DAI: |
907 | /* DoP bitwidth is always 24-bit */ |
908 | bitwidth_dai = 24; |
909 | sclk = params_rate(p: params) * bitwidth_dai * |
910 | params_channels(p: params); |
911 | |
912 | switch (params_rate(p: params)) { |
913 | case 176400: |
914 | dsd_speed = 0; |
915 | break; |
916 | case 352800: |
917 | dsd_speed = 1; |
918 | break; |
919 | default: |
920 | dev_err(cs43130->dev, "Rate(%u) not supported\n" , |
921 | params_rate(params)); |
922 | return -EINVAL; |
923 | } |
924 | |
925 | regmap_update_bits(map: cs43130->regmap, CS43130_DSD_PATH_CTL_2, |
926 | CS43130_DSD_SPEED_MASK, |
927 | val: dsd_speed << CS43130_DSD_SPEED_SHIFT); |
928 | break; |
929 | case CS43130_ASP_PCM_DAI: |
930 | rate_map = cs43130_get_rate_table(fs: params_rate(p: params)); |
931 | if (!rate_map) |
932 | return -EINVAL; |
933 | |
934 | regmap_write(map: cs43130->regmap, CS43130_SP_SRATE, val: rate_map->val); |
935 | break; |
936 | default: |
937 | dev_err(cs43130->dev, "Invalid DAI (%d)\n" , dai->id); |
938 | return -EINVAL; |
939 | } |
940 | |
941 | switch (dai->id) { |
942 | case CS43130_ASP_DOP_DAI: |
943 | regmap_update_bits(map: cs43130->regmap, CS43130_DSD_PATH_CTL_2, |
944 | CS43130_DSD_SRC_MASK, val: CS43130_DSD_SRC_ASP << |
945 | CS43130_DSD_SRC_SHIFT); |
946 | break; |
947 | case CS43130_XSP_DOP_DAI: |
948 | regmap_update_bits(map: cs43130->regmap, CS43130_DSD_PATH_CTL_2, |
949 | CS43130_DSD_SRC_MASK, val: CS43130_DSD_SRC_XSP << |
950 | CS43130_DSD_SRC_SHIFT); |
951 | break; |
952 | } |
953 | |
954 | if (!sclk && cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM) |
955 | /* Calculate SCLK in master mode if unassigned */ |
956 | sclk = params_rate(p: params) * bitwidth_dai * |
957 | params_channels(p: params); |
958 | |
959 | if (!sclk) { |
960 | /* at this point, SCLK must be set */ |
961 | dev_err(cs43130->dev, "SCLK freq is not set\n" ); |
962 | return -EINVAL; |
963 | } |
964 | |
965 | bitwidth_sclk = (sclk / params_rate(p: params)) / params_channels(p: params); |
966 | if (bitwidth_sclk < bitwidth_dai) { |
967 | dev_err(cs43130->dev, "Format not supported: SCLK freq is too low\n" ); |
968 | return -EINVAL; |
969 | } |
970 | |
971 | dev_dbg(cs43130->dev, |
972 | "sclk = %u, fs = %d, bitwidth_dai = %u\n" , |
973 | sclk, params_rate(params), bitwidth_dai); |
974 | |
975 | dev_dbg(cs43130->dev, |
976 | "bitwidth_sclk = %u, num_ch = %u\n" , |
977 | bitwidth_sclk, params_channels(params)); |
978 | |
979 | cs43130_set_bitwidth(dai_id: dai->id, bitwidth_dai, regmap: cs43130->regmap); |
980 | cs43130_set_sp_fmt(dai_id: dai->id, bitwidth_sclk, params, cs43130); |
981 | |
982 | return 0; |
983 | } |
984 | |
985 | static int cs43130_hw_free(struct snd_pcm_substream *substream, |
986 | struct snd_soc_dai *dai) |
987 | { |
988 | struct snd_soc_component *component = dai->component; |
989 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
990 | |
991 | mutex_lock(&cs43130->clk_mutex); |
992 | cs43130->clk_req--; |
993 | if (!cs43130->clk_req) { |
994 | /* no DAI is currently using clk */ |
995 | cs43130_change_clksrc(component, src: CS43130_MCLK_SRC_RCO); |
996 | cs43130_pcm_dsd_mix(en: false, regmap: cs43130->regmap); |
997 | } |
998 | mutex_unlock(lock: &cs43130->clk_mutex); |
999 | |
1000 | return 0; |
1001 | } |
1002 | |
1003 | static const DECLARE_TLV_DB_SCALE(pcm_vol_tlv, -12750, 50, 1); |
1004 | |
1005 | static const char * const pcm_ch_text[] = { |
1006 | "Left-Right Ch" , |
1007 | "Left-Left Ch" , |
1008 | "Right-Left Ch" , |
1009 | "Right-Right Ch" , |
1010 | }; |
1011 | |
1012 | static const struct reg_sequence pcm_ch_en_seq[] = { |
1013 | {CS43130_DXD1, 0x99}, |
1014 | {0x180005, 0x8C}, |
1015 | {0x180007, 0xAB}, |
1016 | {0x180015, 0x31}, |
1017 | {0x180017, 0xB2}, |
1018 | {0x180025, 0x30}, |
1019 | {0x180027, 0x84}, |
1020 | {0x180035, 0x9C}, |
1021 | {0x180037, 0xAE}, |
1022 | {0x18000D, 0x24}, |
1023 | {0x18000F, 0xA3}, |
1024 | {0x18001D, 0x05}, |
1025 | {0x18001F, 0xD4}, |
1026 | {0x18002D, 0x0B}, |
1027 | {0x18002F, 0xC7}, |
1028 | {0x18003D, 0x71}, |
1029 | {0x18003F, 0xE7}, |
1030 | {CS43130_DXD1, 0}, |
1031 | }; |
1032 | |
1033 | static const struct reg_sequence pcm_ch_dis_seq[] = { |
1034 | {CS43130_DXD1, 0x99}, |
1035 | {0x180005, 0x24}, |
1036 | {0x180007, 0xA3}, |
1037 | {0x180015, 0x05}, |
1038 | {0x180017, 0xD4}, |
1039 | {0x180025, 0x0B}, |
1040 | {0x180027, 0xC7}, |
1041 | {0x180035, 0x71}, |
1042 | {0x180037, 0xE7}, |
1043 | {0x18000D, 0x8C}, |
1044 | {0x18000F, 0xAB}, |
1045 | {0x18001D, 0x31}, |
1046 | {0x18001F, 0xB2}, |
1047 | {0x18002D, 0x30}, |
1048 | {0x18002F, 0x84}, |
1049 | {0x18003D, 0x9C}, |
1050 | {0x18003F, 0xAE}, |
1051 | {CS43130_DXD1, 0}, |
1052 | }; |
1053 | |
1054 | static int cs43130_pcm_ch_get(struct snd_kcontrol *kcontrol, |
1055 | struct snd_ctl_elem_value *ucontrol) |
1056 | { |
1057 | return snd_soc_get_enum_double(kcontrol, ucontrol); |
1058 | } |
1059 | |
1060 | static int cs43130_pcm_ch_put(struct snd_kcontrol *kcontrol, |
1061 | struct snd_ctl_elem_value *ucontrol) |
1062 | { |
1063 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
1064 | unsigned int *item = ucontrol->value.enumerated.item; |
1065 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
1066 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
1067 | unsigned int val; |
1068 | |
1069 | if (item[0] >= e->items) |
1070 | return -EINVAL; |
1071 | val = snd_soc_enum_item_to_val(e, item: item[0]) << e->shift_l; |
1072 | |
1073 | switch (cs43130->dev_id) { |
1074 | case CS43131_CHIP_ID: |
1075 | case CS43198_CHIP_ID: |
1076 | if (val >= 2) |
1077 | regmap_multi_reg_write(map: cs43130->regmap, regs: pcm_ch_en_seq, |
1078 | ARRAY_SIZE(pcm_ch_en_seq)); |
1079 | else |
1080 | regmap_multi_reg_write(map: cs43130->regmap, regs: pcm_ch_dis_seq, |
1081 | ARRAY_SIZE(pcm_ch_dis_seq)); |
1082 | break; |
1083 | } |
1084 | |
1085 | return snd_soc_put_enum_double(kcontrol, ucontrol); |
1086 | } |
1087 | |
1088 | static SOC_ENUM_SINGLE_DECL(pcm_ch_enum, CS43130_PCM_PATH_CTL_2, 0, |
1089 | pcm_ch_text); |
1090 | |
1091 | static const char * const pcm_spd_texts[] = { |
1092 | "Fast" , |
1093 | "Slow" , |
1094 | }; |
1095 | |
1096 | static SOC_ENUM_SINGLE_DECL(pcm_spd_enum, CS43130_PCM_FILT_OPT, 7, |
1097 | pcm_spd_texts); |
1098 | |
1099 | static const char * const dsd_texts[] = { |
1100 | "Off" , |
1101 | "BCKA Mode" , |
1102 | "BCKD Mode" , |
1103 | }; |
1104 | |
1105 | static const unsigned int dsd_values[] = { |
1106 | CS43130_DSD_SRC_DSD, |
1107 | CS43130_DSD_SRC_ASP, |
1108 | CS43130_DSD_SRC_XSP, |
1109 | }; |
1110 | |
1111 | static SOC_VALUE_ENUM_SINGLE_DECL(dsd_enum, CS43130_DSD_INT_CFG, 0, 0x03, |
1112 | dsd_texts, dsd_values); |
1113 | |
1114 | static const struct snd_kcontrol_new cs43130_snd_controls[] = { |
1115 | SOC_DOUBLE_R_TLV("Master Playback Volume" , |
1116 | CS43130_PCM_VOL_A, CS43130_PCM_VOL_B, 0, 0xFF, 1, |
1117 | pcm_vol_tlv), |
1118 | SOC_DOUBLE_R_TLV("Master DSD Playback Volume" , |
1119 | CS43130_DSD_VOL_A, CS43130_DSD_VOL_B, 0, 0xFF, 1, |
1120 | pcm_vol_tlv), |
1121 | SOC_ENUM_EXT("PCM Ch Select" , pcm_ch_enum, cs43130_pcm_ch_get, |
1122 | cs43130_pcm_ch_put), |
1123 | SOC_ENUM("PCM Filter Speed" , pcm_spd_enum), |
1124 | SOC_SINGLE("PCM Phase Compensation" , CS43130_PCM_FILT_OPT, 6, 1, 0), |
1125 | SOC_SINGLE("PCM Nonoversample Emulate" , CS43130_PCM_FILT_OPT, 5, 1, 0), |
1126 | SOC_SINGLE("PCM High-pass Filter" , CS43130_PCM_FILT_OPT, 1, 1, 0), |
1127 | SOC_SINGLE("PCM De-emphasis Filter" , CS43130_PCM_FILT_OPT, 0, 1, 0), |
1128 | SOC_ENUM("DSD Phase Modulation" , dsd_enum), |
1129 | }; |
1130 | |
1131 | static const struct reg_sequence pcm_seq[] = { |
1132 | {CS43130_DXD1, 0x99}, |
1133 | {CS43130_DXD7, 0x01}, |
1134 | {CS43130_DXD8, 0}, |
1135 | {CS43130_DXD9, 0x01}, |
1136 | {CS43130_DXD3, 0x12}, |
1137 | {CS43130_DXD4, 0}, |
1138 | {CS43130_DXD10, 0x28}, |
1139 | {CS43130_DXD11, 0x28}, |
1140 | {CS43130_DXD1, 0}, |
1141 | }; |
1142 | |
1143 | static const struct reg_sequence dsd_seq[] = { |
1144 | {CS43130_DXD1, 0x99}, |
1145 | {CS43130_DXD7, 0x01}, |
1146 | {CS43130_DXD8, 0}, |
1147 | {CS43130_DXD9, 0x01}, |
1148 | {CS43130_DXD3, 0x12}, |
1149 | {CS43130_DXD4, 0}, |
1150 | {CS43130_DXD10, 0x1E}, |
1151 | {CS43130_DXD11, 0x20}, |
1152 | {CS43130_DXD1, 0}, |
1153 | }; |
1154 | |
1155 | static const struct reg_sequence pop_free_seq[] = { |
1156 | {CS43130_DXD1, 0x99}, |
1157 | {CS43130_DXD12, 0x0A}, |
1158 | {CS43130_DXD1, 0}, |
1159 | }; |
1160 | |
1161 | static const struct reg_sequence pop_free_seq2[] = { |
1162 | {CS43130_DXD1, 0x99}, |
1163 | {CS43130_DXD13, 0x20}, |
1164 | {CS43130_DXD1, 0}, |
1165 | }; |
1166 | |
1167 | static const struct reg_sequence mute_seq[] = { |
1168 | {CS43130_DXD1, 0x99}, |
1169 | {CS43130_DXD3, 0x12}, |
1170 | {CS43130_DXD5, 0x02}, |
1171 | {CS43130_DXD4, 0x12}, |
1172 | {CS43130_DXD1, 0}, |
1173 | }; |
1174 | |
1175 | static const struct reg_sequence unmute_seq[] = { |
1176 | {CS43130_DXD1, 0x99}, |
1177 | {CS43130_DXD3, 0x10}, |
1178 | {CS43130_DXD5, 0}, |
1179 | {CS43130_DXD4, 0x16}, |
1180 | {CS43130_DXD1, 0}, |
1181 | }; |
1182 | |
1183 | static int cs43130_dsd_event(struct snd_soc_dapm_widget *w, |
1184 | struct snd_kcontrol *kcontrol, int event) |
1185 | { |
1186 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1187 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
1188 | |
1189 | switch (event) { |
1190 | case SND_SOC_DAPM_PRE_PMU: |
1191 | switch (cs43130->dev_id) { |
1192 | case CS43130_CHIP_ID: |
1193 | case CS4399_CHIP_ID: |
1194 | regmap_multi_reg_write(map: cs43130->regmap, regs: dsd_seq, |
1195 | ARRAY_SIZE(dsd_seq)); |
1196 | break; |
1197 | } |
1198 | break; |
1199 | case SND_SOC_DAPM_POST_PMU: |
1200 | regmap_update_bits(map: cs43130->regmap, CS43130_DSD_PATH_CTL_1, |
1201 | CS43130_MUTE_MASK, val: 0); |
1202 | switch (cs43130->dev_id) { |
1203 | case CS43130_CHIP_ID: |
1204 | case CS4399_CHIP_ID: |
1205 | regmap_multi_reg_write(map: cs43130->regmap, regs: unmute_seq, |
1206 | ARRAY_SIZE(unmute_seq)); |
1207 | break; |
1208 | } |
1209 | break; |
1210 | case SND_SOC_DAPM_PRE_PMD: |
1211 | switch (cs43130->dev_id) { |
1212 | case CS43130_CHIP_ID: |
1213 | case CS4399_CHIP_ID: |
1214 | regmap_multi_reg_write(map: cs43130->regmap, regs: mute_seq, |
1215 | ARRAY_SIZE(mute_seq)); |
1216 | regmap_update_bits(map: cs43130->regmap, |
1217 | CS43130_DSD_PATH_CTL_1, |
1218 | CS43130_MUTE_MASK, CS43130_MUTE_EN); |
1219 | /* |
1220 | * DSD Power Down Sequence |
1221 | * According to Design, 130ms is preferred. |
1222 | */ |
1223 | msleep(msecs: 130); |
1224 | break; |
1225 | case CS43131_CHIP_ID: |
1226 | case CS43198_CHIP_ID: |
1227 | regmap_update_bits(map: cs43130->regmap, |
1228 | CS43130_DSD_PATH_CTL_1, |
1229 | CS43130_MUTE_MASK, CS43130_MUTE_EN); |
1230 | break; |
1231 | } |
1232 | break; |
1233 | default: |
1234 | dev_err(cs43130->dev, "Invalid event = 0x%x\n" , event); |
1235 | return -EINVAL; |
1236 | } |
1237 | return 0; |
1238 | } |
1239 | |
1240 | static int cs43130_pcm_event(struct snd_soc_dapm_widget *w, |
1241 | struct snd_kcontrol *kcontrol, int event) |
1242 | { |
1243 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1244 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
1245 | |
1246 | switch (event) { |
1247 | case SND_SOC_DAPM_PRE_PMU: |
1248 | switch (cs43130->dev_id) { |
1249 | case CS43130_CHIP_ID: |
1250 | case CS4399_CHIP_ID: |
1251 | regmap_multi_reg_write(map: cs43130->regmap, regs: pcm_seq, |
1252 | ARRAY_SIZE(pcm_seq)); |
1253 | break; |
1254 | } |
1255 | break; |
1256 | case SND_SOC_DAPM_POST_PMU: |
1257 | regmap_update_bits(map: cs43130->regmap, CS43130_PCM_PATH_CTL_1, |
1258 | CS43130_MUTE_MASK, val: 0); |
1259 | switch (cs43130->dev_id) { |
1260 | case CS43130_CHIP_ID: |
1261 | case CS4399_CHIP_ID: |
1262 | regmap_multi_reg_write(map: cs43130->regmap, regs: unmute_seq, |
1263 | ARRAY_SIZE(unmute_seq)); |
1264 | break; |
1265 | } |
1266 | break; |
1267 | case SND_SOC_DAPM_PRE_PMD: |
1268 | switch (cs43130->dev_id) { |
1269 | case CS43130_CHIP_ID: |
1270 | case CS4399_CHIP_ID: |
1271 | regmap_multi_reg_write(map: cs43130->regmap, regs: mute_seq, |
1272 | ARRAY_SIZE(mute_seq)); |
1273 | regmap_update_bits(map: cs43130->regmap, |
1274 | CS43130_PCM_PATH_CTL_1, |
1275 | CS43130_MUTE_MASK, CS43130_MUTE_EN); |
1276 | /* |
1277 | * PCM Power Down Sequence |
1278 | * According to Design, 130ms is preferred. |
1279 | */ |
1280 | msleep(msecs: 130); |
1281 | break; |
1282 | case CS43131_CHIP_ID: |
1283 | case CS43198_CHIP_ID: |
1284 | regmap_update_bits(map: cs43130->regmap, |
1285 | CS43130_PCM_PATH_CTL_1, |
1286 | CS43130_MUTE_MASK, CS43130_MUTE_EN); |
1287 | break; |
1288 | } |
1289 | break; |
1290 | default: |
1291 | dev_err(cs43130->dev, "Invalid event = 0x%x\n" , event); |
1292 | return -EINVAL; |
1293 | } |
1294 | return 0; |
1295 | } |
1296 | |
1297 | static const struct reg_sequence dac_postpmu_seq[] = { |
1298 | {CS43130_DXD9, 0x0C}, |
1299 | {CS43130_DXD3, 0x10}, |
1300 | {CS43130_DXD4, 0x20}, |
1301 | }; |
1302 | |
1303 | static const struct reg_sequence dac_postpmd_seq[] = { |
1304 | {CS43130_DXD1, 0x99}, |
1305 | {CS43130_DXD6, 0x01}, |
1306 | {CS43130_DXD1, 0}, |
1307 | }; |
1308 | |
1309 | static int cs43130_dac_event(struct snd_soc_dapm_widget *w, |
1310 | struct snd_kcontrol *kcontrol, int event) |
1311 | { |
1312 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1313 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
1314 | |
1315 | switch (event) { |
1316 | case SND_SOC_DAPM_PRE_PMU: |
1317 | switch (cs43130->dev_id) { |
1318 | case CS43130_CHIP_ID: |
1319 | case CS4399_CHIP_ID: |
1320 | regmap_multi_reg_write(map: cs43130->regmap, regs: pop_free_seq, |
1321 | ARRAY_SIZE(pop_free_seq)); |
1322 | break; |
1323 | case CS43131_CHIP_ID: |
1324 | case CS43198_CHIP_ID: |
1325 | regmap_multi_reg_write(map: cs43130->regmap, regs: pop_free_seq2, |
1326 | ARRAY_SIZE(pop_free_seq2)); |
1327 | break; |
1328 | } |
1329 | break; |
1330 | case SND_SOC_DAPM_POST_PMU: |
1331 | usleep_range(min: 10000, max: 10050); |
1332 | |
1333 | regmap_write(map: cs43130->regmap, CS43130_DXD1, val: 0x99); |
1334 | |
1335 | switch (cs43130->dev_id) { |
1336 | case CS43130_CHIP_ID: |
1337 | case CS4399_CHIP_ID: |
1338 | regmap_multi_reg_write(map: cs43130->regmap, regs: dac_postpmu_seq, |
1339 | ARRAY_SIZE(dac_postpmu_seq)); |
1340 | /* |
1341 | * Per datasheet, Sec. PCM Power-Up Sequence. |
1342 | * According to Design, CS43130_DXD12 must be 0 to meet |
1343 | * THDN and Dynamic Range spec. |
1344 | */ |
1345 | msleep(msecs: 1000); |
1346 | regmap_write(map: cs43130->regmap, CS43130_DXD12, val: 0); |
1347 | break; |
1348 | case CS43131_CHIP_ID: |
1349 | case CS43198_CHIP_ID: |
1350 | usleep_range(min: 12000, max: 12010); |
1351 | regmap_write(map: cs43130->regmap, CS43130_DXD13, val: 0); |
1352 | break; |
1353 | } |
1354 | |
1355 | regmap_write(map: cs43130->regmap, CS43130_DXD1, val: 0); |
1356 | break; |
1357 | case SND_SOC_DAPM_POST_PMD: |
1358 | switch (cs43130->dev_id) { |
1359 | case CS43130_CHIP_ID: |
1360 | case CS4399_CHIP_ID: |
1361 | regmap_multi_reg_write(map: cs43130->regmap, regs: dac_postpmd_seq, |
1362 | ARRAY_SIZE(dac_postpmd_seq)); |
1363 | break; |
1364 | } |
1365 | break; |
1366 | default: |
1367 | dev_err(cs43130->dev, "Invalid DAC event = 0x%x\n" , event); |
1368 | return -EINVAL; |
1369 | } |
1370 | return 0; |
1371 | } |
1372 | |
1373 | static const struct reg_sequence hpin_prepmd_seq[] = { |
1374 | {CS43130_DXD1, 0x99}, |
1375 | {CS43130_DXD15, 0x64}, |
1376 | {CS43130_DXD14, 0}, |
1377 | {CS43130_DXD2, 0}, |
1378 | {CS43130_DXD1, 0}, |
1379 | }; |
1380 | |
1381 | static const struct reg_sequence hpin_postpmu_seq[] = { |
1382 | {CS43130_DXD1, 0x99}, |
1383 | {CS43130_DXD2, 1}, |
1384 | {CS43130_DXD14, 0xDC}, |
1385 | {CS43130_DXD15, 0xE4}, |
1386 | {CS43130_DXD1, 0}, |
1387 | }; |
1388 | |
1389 | static int cs43130_hpin_event(struct snd_soc_dapm_widget *w, |
1390 | struct snd_kcontrol *kcontrol, int event) |
1391 | { |
1392 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
1393 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
1394 | |
1395 | switch (event) { |
1396 | case SND_SOC_DAPM_POST_PMD: |
1397 | regmap_multi_reg_write(map: cs43130->regmap, regs: hpin_prepmd_seq, |
1398 | ARRAY_SIZE(hpin_prepmd_seq)); |
1399 | break; |
1400 | case SND_SOC_DAPM_PRE_PMU: |
1401 | regmap_multi_reg_write(map: cs43130->regmap, regs: hpin_postpmu_seq, |
1402 | ARRAY_SIZE(hpin_postpmu_seq)); |
1403 | break; |
1404 | default: |
1405 | dev_err(cs43130->dev, "Invalid HPIN event = 0x%x\n" , event); |
1406 | return -EINVAL; |
1407 | } |
1408 | return 0; |
1409 | } |
1410 | |
1411 | static const char * const bypass_mux_text[] = { |
1412 | "Internal" , |
1413 | "Alternative" , |
1414 | }; |
1415 | static SOC_ENUM_SINGLE_DECL(bypass_enum, SND_SOC_NOPM, 0, bypass_mux_text); |
1416 | static const struct snd_kcontrol_new bypass_ctrl = SOC_DAPM_ENUM("Switch" , bypass_enum); |
1417 | |
1418 | static const struct snd_soc_dapm_widget digital_hp_widgets[] = { |
1419 | SND_SOC_DAPM_MUX("Bypass Switch" , SND_SOC_NOPM, 0, 0, &bypass_ctrl), |
1420 | SND_SOC_DAPM_OUTPUT("HPOUTA" ), |
1421 | SND_SOC_DAPM_OUTPUT("HPOUTB" ), |
1422 | |
1423 | SND_SOC_DAPM_AIF_IN_E("ASPIN PCM" , NULL, 0, CS43130_PWDN_CTL, |
1424 | CS43130_PDN_ASP_SHIFT, 1, cs43130_pcm_event, |
1425 | (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
1426 | SND_SOC_DAPM_PRE_PMD)), |
1427 | |
1428 | SND_SOC_DAPM_AIF_IN_E("ASPIN DoP" , NULL, 0, CS43130_PWDN_CTL, |
1429 | CS43130_PDN_ASP_SHIFT, 1, cs43130_dsd_event, |
1430 | (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
1431 | SND_SOC_DAPM_PRE_PMD)), |
1432 | |
1433 | SND_SOC_DAPM_AIF_IN_E("XSPIN DoP" , NULL, 0, CS43130_PWDN_CTL, |
1434 | CS43130_PDN_XSP_SHIFT, 1, cs43130_dsd_event, |
1435 | (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
1436 | SND_SOC_DAPM_PRE_PMD)), |
1437 | |
1438 | SND_SOC_DAPM_AIF_IN_E("XSPIN DSD" , NULL, 0, CS43130_PWDN_CTL, |
1439 | CS43130_PDN_DSDIF_SHIFT, 1, cs43130_dsd_event, |
1440 | (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
1441 | SND_SOC_DAPM_PRE_PMD)), |
1442 | |
1443 | SND_SOC_DAPM_DAC("DSD" , NULL, CS43130_DSD_PATH_CTL_2, |
1444 | CS43130_DSD_EN_SHIFT, 0), |
1445 | |
1446 | SND_SOC_DAPM_DAC_E("HiFi DAC" , NULL, CS43130_PWDN_CTL, |
1447 | CS43130_PDN_HP_SHIFT, 1, cs43130_dac_event, |
1448 | (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
1449 | SND_SOC_DAPM_POST_PMD)), |
1450 | }; |
1451 | |
1452 | static const struct snd_soc_dapm_widget analog_hp_widgets[] = { |
1453 | SND_SOC_DAPM_DAC_E("Analog Playback" , NULL, CS43130_HP_OUT_CTL_1, |
1454 | CS43130_HP_IN_EN_SHIFT, 0, cs43130_hpin_event, |
1455 | (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD)), |
1456 | }; |
1457 | |
1458 | static struct snd_soc_dapm_widget all_hp_widgets[ |
1459 | ARRAY_SIZE(digital_hp_widgets) + |
1460 | ARRAY_SIZE(analog_hp_widgets)]; |
1461 | |
1462 | static const struct snd_soc_dapm_route digital_hp_routes[] = { |
1463 | {"ASPIN PCM" , NULL, "ASP PCM Playback" }, |
1464 | {"ASPIN DoP" , NULL, "ASP DoP Playback" }, |
1465 | {"XSPIN DoP" , NULL, "XSP DoP Playback" }, |
1466 | {"XSPIN DSD" , NULL, "XSP DSD Playback" }, |
1467 | {"DSD" , NULL, "ASPIN DoP" }, |
1468 | {"DSD" , NULL, "XSPIN DoP" }, |
1469 | {"DSD" , NULL, "XSPIN DSD" }, |
1470 | {"HiFi DAC" , NULL, "ASPIN PCM" }, |
1471 | {"HiFi DAC" , NULL, "DSD" }, |
1472 | {"Bypass Switch" , "Internal" , "HiFi DAC" }, |
1473 | {"HPOUTA" , NULL, "Bypass Switch" }, |
1474 | {"HPOUTB" , NULL, "Bypass Switch" }, |
1475 | }; |
1476 | |
1477 | static const struct snd_soc_dapm_route analog_hp_routes[] = { |
1478 | {"Bypass Switch" , "Alternative" , "Analog Playback" }, |
1479 | }; |
1480 | |
1481 | static struct snd_soc_dapm_route all_hp_routes[ |
1482 | ARRAY_SIZE(digital_hp_routes) + |
1483 | ARRAY_SIZE(analog_hp_routes)]; |
1484 | |
1485 | static const unsigned int cs43130_asp_src_rates[] = { |
1486 | 32000, 44100, 48000, 88200, 96000, 176400, 192000, 352800, 384000 |
1487 | }; |
1488 | |
1489 | static const struct snd_pcm_hw_constraint_list cs43130_asp_constraints = { |
1490 | .count = ARRAY_SIZE(cs43130_asp_src_rates), |
1491 | .list = cs43130_asp_src_rates, |
1492 | }; |
1493 | |
1494 | static int cs43130_pcm_startup(struct snd_pcm_substream *substream, |
1495 | struct snd_soc_dai *dai) |
1496 | { |
1497 | return snd_pcm_hw_constraint_list(runtime: substream->runtime, cond: 0, |
1498 | SNDRV_PCM_HW_PARAM_RATE, |
1499 | l: &cs43130_asp_constraints); |
1500 | } |
1501 | |
1502 | static const unsigned int cs43130_dop_src_rates[] = { |
1503 | 176400, 352800, |
1504 | }; |
1505 | |
1506 | static const struct snd_pcm_hw_constraint_list cs43130_dop_constraints = { |
1507 | .count = ARRAY_SIZE(cs43130_dop_src_rates), |
1508 | .list = cs43130_dop_src_rates, |
1509 | }; |
1510 | |
1511 | static int cs43130_dop_startup(struct snd_pcm_substream *substream, |
1512 | struct snd_soc_dai *dai) |
1513 | { |
1514 | return snd_pcm_hw_constraint_list(runtime: substream->runtime, cond: 0, |
1515 | SNDRV_PCM_HW_PARAM_RATE, |
1516 | l: &cs43130_dop_constraints); |
1517 | } |
1518 | |
1519 | static int cs43130_pcm_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) |
1520 | { |
1521 | struct snd_soc_component *component = codec_dai->component; |
1522 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
1523 | |
1524 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
1525 | case SND_SOC_DAIFMT_CBS_CFS: |
1526 | cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS; |
1527 | break; |
1528 | case SND_SOC_DAIFMT_CBM_CFM: |
1529 | cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM; |
1530 | break; |
1531 | default: |
1532 | dev_err(cs43130->dev, "unsupported mode\n" ); |
1533 | return -EINVAL; |
1534 | } |
1535 | |
1536 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
1537 | case SND_SOC_DAIFMT_NB_NF: |
1538 | cs43130->dais[codec_dai->id].dai_invert = SND_SOC_DAIFMT_NB_NF; |
1539 | break; |
1540 | case SND_SOC_DAIFMT_IB_NF: |
1541 | cs43130->dais[codec_dai->id].dai_invert = SND_SOC_DAIFMT_IB_NF; |
1542 | break; |
1543 | case SND_SOC_DAIFMT_NB_IF: |
1544 | cs43130->dais[codec_dai->id].dai_invert = SND_SOC_DAIFMT_NB_IF; |
1545 | break; |
1546 | case SND_SOC_DAIFMT_IB_IF: |
1547 | cs43130->dais[codec_dai->id].dai_invert = SND_SOC_DAIFMT_IB_IF; |
1548 | break; |
1549 | default: |
1550 | dev_err(cs43130->dev, "Unsupported invert mode 0x%x\n" , |
1551 | fmt & SND_SOC_DAIFMT_INV_MASK); |
1552 | return -EINVAL; |
1553 | } |
1554 | |
1555 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
1556 | case SND_SOC_DAIFMT_I2S: |
1557 | cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_I2S; |
1558 | break; |
1559 | case SND_SOC_DAIFMT_LEFT_J: |
1560 | cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_LEFT_J; |
1561 | break; |
1562 | case SND_SOC_DAIFMT_DSP_A: |
1563 | cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_A; |
1564 | break; |
1565 | case SND_SOC_DAIFMT_DSP_B: |
1566 | cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_B; |
1567 | break; |
1568 | default: |
1569 | dev_err(cs43130->dev, |
1570 | "unsupported audio format\n" ); |
1571 | return -EINVAL; |
1572 | } |
1573 | |
1574 | dev_dbg(cs43130->dev, "dai_id = %d, dai_mode = %u, dai_format = %u\n" , |
1575 | codec_dai->id, |
1576 | cs43130->dais[codec_dai->id].dai_mode, |
1577 | cs43130->dais[codec_dai->id].dai_format); |
1578 | |
1579 | return 0; |
1580 | } |
1581 | |
1582 | static int cs43130_dsd_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) |
1583 | { |
1584 | struct snd_soc_component *component = codec_dai->component; |
1585 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
1586 | |
1587 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
1588 | case SND_SOC_DAIFMT_CBS_CFS: |
1589 | cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS; |
1590 | break; |
1591 | case SND_SOC_DAIFMT_CBM_CFM: |
1592 | cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM; |
1593 | break; |
1594 | default: |
1595 | dev_err(cs43130->dev, "Unsupported DAI format.\n" ); |
1596 | return -EINVAL; |
1597 | } |
1598 | |
1599 | dev_dbg(cs43130->dev, "dai_mode = 0x%x\n" , |
1600 | cs43130->dais[codec_dai->id].dai_mode); |
1601 | |
1602 | return 0; |
1603 | } |
1604 | |
1605 | static int cs43130_set_sysclk(struct snd_soc_dai *codec_dai, |
1606 | int clk_id, unsigned int freq, int dir) |
1607 | { |
1608 | struct snd_soc_component *component = codec_dai->component; |
1609 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
1610 | |
1611 | cs43130->dais[codec_dai->id].sclk = freq; |
1612 | dev_dbg(cs43130->dev, "dai_id = %d, sclk = %u\n" , codec_dai->id, |
1613 | cs43130->dais[codec_dai->id].sclk); |
1614 | |
1615 | return 0; |
1616 | } |
1617 | |
1618 | static const struct snd_soc_dai_ops cs43130_pcm_ops = { |
1619 | .startup = cs43130_pcm_startup, |
1620 | .hw_params = cs43130_hw_params, |
1621 | .hw_free = cs43130_hw_free, |
1622 | .set_sysclk = cs43130_set_sysclk, |
1623 | .set_fmt = cs43130_pcm_set_fmt, |
1624 | }; |
1625 | |
1626 | static const struct snd_soc_dai_ops cs43130_dop_ops = { |
1627 | .startup = cs43130_dop_startup, |
1628 | .hw_params = cs43130_hw_params, |
1629 | .hw_free = cs43130_hw_free, |
1630 | .set_sysclk = cs43130_set_sysclk, |
1631 | .set_fmt = cs43130_pcm_set_fmt, |
1632 | }; |
1633 | |
1634 | static const struct snd_soc_dai_ops cs43130_dsd_ops = { |
1635 | .startup = cs43130_dop_startup, |
1636 | .hw_params = cs43130_dsd_hw_params, |
1637 | .hw_free = cs43130_hw_free, |
1638 | .set_fmt = cs43130_dsd_set_fmt, |
1639 | }; |
1640 | |
1641 | static struct snd_soc_dai_driver cs43130_dai[] = { |
1642 | { |
1643 | .name = "cs43130-asp-pcm" , |
1644 | .id = CS43130_ASP_PCM_DAI, |
1645 | .playback = { |
1646 | .stream_name = "ASP PCM Playback" , |
1647 | .channels_min = 1, |
1648 | .channels_max = 2, |
1649 | .rates = SNDRV_PCM_RATE_KNOT, |
1650 | .formats = CS43130_PCM_FORMATS, |
1651 | }, |
1652 | .ops = &cs43130_pcm_ops, |
1653 | .symmetric_rate = 1, |
1654 | }, |
1655 | { |
1656 | .name = "cs43130-asp-dop" , |
1657 | .id = CS43130_ASP_DOP_DAI, |
1658 | .playback = { |
1659 | .stream_name = "ASP DoP Playback" , |
1660 | .channels_min = 1, |
1661 | .channels_max = 2, |
1662 | .rates = SNDRV_PCM_RATE_KNOT, |
1663 | .formats = CS43130_DOP_FORMATS, |
1664 | }, |
1665 | .ops = &cs43130_dop_ops, |
1666 | .symmetric_rate = 1, |
1667 | }, |
1668 | { |
1669 | .name = "cs43130-xsp-dop" , |
1670 | .id = CS43130_XSP_DOP_DAI, |
1671 | .playback = { |
1672 | .stream_name = "XSP DoP Playback" , |
1673 | .channels_min = 1, |
1674 | .channels_max = 2, |
1675 | .rates = SNDRV_PCM_RATE_KNOT, |
1676 | .formats = CS43130_DOP_FORMATS, |
1677 | }, |
1678 | .ops = &cs43130_dop_ops, |
1679 | .symmetric_rate = 1, |
1680 | }, |
1681 | { |
1682 | .name = "cs43130-xsp-dsd" , |
1683 | .id = CS43130_XSP_DSD_DAI, |
1684 | .playback = { |
1685 | .stream_name = "XSP DSD Playback" , |
1686 | .channels_min = 1, |
1687 | .channels_max = 2, |
1688 | .rates = SNDRV_PCM_RATE_KNOT, |
1689 | .formats = CS43130_DOP_FORMATS, |
1690 | }, |
1691 | .ops = &cs43130_dsd_ops, |
1692 | }, |
1693 | |
1694 | }; |
1695 | |
1696 | static int cs43130_component_set_sysclk(struct snd_soc_component *component, |
1697 | int clk_id, int source, unsigned int freq, |
1698 | int dir) |
1699 | { |
1700 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
1701 | |
1702 | dev_dbg(cs43130->dev, "clk_id = %d, source = %d, freq = %d, dir = %d\n" , |
1703 | clk_id, source, freq, dir); |
1704 | |
1705 | switch (freq) { |
1706 | case CS43130_MCLK_22M: |
1707 | case CS43130_MCLK_24M: |
1708 | cs43130->mclk = freq; |
1709 | break; |
1710 | default: |
1711 | dev_err(cs43130->dev, "Invalid MCLK INT freq: %u\n" , freq); |
1712 | return -EINVAL; |
1713 | } |
1714 | |
1715 | if (source == CS43130_MCLK_SRC_EXT) { |
1716 | cs43130->pll_bypass = true; |
1717 | } else { |
1718 | dev_err(cs43130->dev, "Invalid MCLK source\n" ); |
1719 | return -EINVAL; |
1720 | } |
1721 | |
1722 | return 0; |
1723 | } |
1724 | |
1725 | static inline u16 cs43130_get_ac_reg_val(u16 ac_freq) |
1726 | { |
1727 | /* AC freq is counted in 5.94Hz step. */ |
1728 | return ac_freq / 6; |
1729 | } |
1730 | |
1731 | static int cs43130_show_dc(struct device *dev, char *buf, u8 ch) |
1732 | { |
1733 | struct i2c_client *client = to_i2c_client(dev); |
1734 | struct cs43130_private *cs43130 = i2c_get_clientdata(client); |
1735 | |
1736 | if (!cs43130->hpload_done) |
1737 | return sysfs_emit(buf, fmt: "NO_HPLOAD\n" ); |
1738 | else |
1739 | return sysfs_emit(buf, fmt: "%u\n" , cs43130->hpload_dc[ch]); |
1740 | } |
1741 | |
1742 | static ssize_t hpload_dc_l_show(struct device *dev, |
1743 | struct device_attribute *attr, char *buf) |
1744 | { |
1745 | return cs43130_show_dc(dev, buf, HP_LEFT); |
1746 | } |
1747 | |
1748 | static ssize_t hpload_dc_r_show(struct device *dev, |
1749 | struct device_attribute *attr, char *buf) |
1750 | { |
1751 | return cs43130_show_dc(dev, buf, HP_RIGHT); |
1752 | } |
1753 | |
1754 | static const u16 cs43130_ac_freq[CS43130_AC_FREQ] = { |
1755 | 24, |
1756 | 43, |
1757 | 93, |
1758 | 200, |
1759 | 431, |
1760 | 928, |
1761 | 2000, |
1762 | 4309, |
1763 | 9283, |
1764 | 20000, |
1765 | }; |
1766 | |
1767 | static int cs43130_show_ac(struct device *dev, char *buf, u8 ch) |
1768 | { |
1769 | int i, j = 0, tmp; |
1770 | struct i2c_client *client = to_i2c_client(dev); |
1771 | struct cs43130_private *cs43130 = i2c_get_clientdata(client); |
1772 | |
1773 | if (cs43130->hpload_done && cs43130->ac_meas) { |
1774 | for (i = 0; i < ARRAY_SIZE(cs43130_ac_freq); i++) { |
1775 | tmp = sysfs_emit_at(buf, at: j, fmt: "%u\n" , |
1776 | cs43130->hpload_ac[i][ch]); |
1777 | if (!tmp) |
1778 | break; |
1779 | |
1780 | j += tmp; |
1781 | } |
1782 | |
1783 | return j; |
1784 | } else { |
1785 | return sysfs_emit(buf, fmt: "NO_HPLOAD\n" ); |
1786 | } |
1787 | } |
1788 | |
1789 | static ssize_t hpload_ac_l_show(struct device *dev, |
1790 | struct device_attribute *attr, char *buf) |
1791 | { |
1792 | return cs43130_show_ac(dev, buf, HP_LEFT); |
1793 | } |
1794 | |
1795 | static ssize_t hpload_ac_r_show(struct device *dev, |
1796 | struct device_attribute *attr, char *buf) |
1797 | { |
1798 | return cs43130_show_ac(dev, buf, HP_RIGHT); |
1799 | } |
1800 | |
1801 | static DEVICE_ATTR_RO(hpload_dc_l); |
1802 | static DEVICE_ATTR_RO(hpload_dc_r); |
1803 | static DEVICE_ATTR_RO(hpload_ac_l); |
1804 | static DEVICE_ATTR_RO(hpload_ac_r); |
1805 | |
1806 | static struct attribute *hpload_attrs[] = { |
1807 | &dev_attr_hpload_dc_l.attr, |
1808 | &dev_attr_hpload_dc_r.attr, |
1809 | &dev_attr_hpload_ac_l.attr, |
1810 | &dev_attr_hpload_ac_r.attr, |
1811 | }; |
1812 | ATTRIBUTE_GROUPS(hpload); |
1813 | |
1814 | static struct reg_sequence hp_en_cal_seq[] = { |
1815 | {CS43130_INT_MASK_4, CS43130_INT_MASK_ALL}, |
1816 | {CS43130_HP_MEAS_LOAD_1, 0}, |
1817 | {CS43130_HP_MEAS_LOAD_2, 0}, |
1818 | {CS43130_INT_MASK_4, 0}, |
1819 | {CS43130_DXD1, 0x99}, |
1820 | {CS43130_DXD16, 0xBB}, |
1821 | {CS43130_DXD12, 0x01}, |
1822 | {CS43130_DXD19, 0xCB}, |
1823 | {CS43130_DXD17, 0x95}, |
1824 | {CS43130_DXD18, 0x0B}, |
1825 | {CS43130_DXD1, 0}, |
1826 | {CS43130_HP_LOAD_1, 0x80}, |
1827 | }; |
1828 | |
1829 | static struct reg_sequence hp_en_cal_seq2[] = { |
1830 | {CS43130_INT_MASK_4, CS43130_INT_MASK_ALL}, |
1831 | {CS43130_HP_MEAS_LOAD_1, 0}, |
1832 | {CS43130_HP_MEAS_LOAD_2, 0}, |
1833 | {CS43130_INT_MASK_4, 0}, |
1834 | {CS43130_HP_LOAD_1, 0x80}, |
1835 | }; |
1836 | |
1837 | static struct reg_sequence hp_dis_cal_seq[] = { |
1838 | {CS43130_HP_LOAD_1, 0x80}, |
1839 | {CS43130_DXD1, 0x99}, |
1840 | {CS43130_DXD12, 0}, |
1841 | {CS43130_DXD1, 0}, |
1842 | {CS43130_HP_LOAD_1, 0}, |
1843 | }; |
1844 | |
1845 | static struct reg_sequence hp_dis_cal_seq2[] = { |
1846 | {CS43130_HP_LOAD_1, 0x80}, |
1847 | {CS43130_HP_LOAD_1, 0}, |
1848 | }; |
1849 | |
1850 | static struct reg_sequence hp_dc_ch_l_seq[] = { |
1851 | {CS43130_DXD1, 0x99}, |
1852 | {CS43130_DXD19, 0x0A}, |
1853 | {CS43130_DXD17, 0x93}, |
1854 | {CS43130_DXD18, 0x0A}, |
1855 | {CS43130_DXD1, 0}, |
1856 | {CS43130_HP_LOAD_1, 0x80}, |
1857 | {CS43130_HP_LOAD_1, 0x81}, |
1858 | }; |
1859 | |
1860 | static struct reg_sequence hp_dc_ch_l_seq2[] = { |
1861 | {CS43130_HP_LOAD_1, 0x80}, |
1862 | {CS43130_HP_LOAD_1, 0x81}, |
1863 | }; |
1864 | |
1865 | static struct reg_sequence hp_dc_ch_r_seq[] = { |
1866 | {CS43130_DXD1, 0x99}, |
1867 | {CS43130_DXD19, 0x8A}, |
1868 | {CS43130_DXD17, 0x15}, |
1869 | {CS43130_DXD18, 0x06}, |
1870 | {CS43130_DXD1, 0}, |
1871 | {CS43130_HP_LOAD_1, 0x90}, |
1872 | {CS43130_HP_LOAD_1, 0x91}, |
1873 | }; |
1874 | |
1875 | static struct reg_sequence hp_dc_ch_r_seq2[] = { |
1876 | {CS43130_HP_LOAD_1, 0x90}, |
1877 | {CS43130_HP_LOAD_1, 0x91}, |
1878 | }; |
1879 | |
1880 | static struct reg_sequence hp_ac_ch_l_seq[] = { |
1881 | {CS43130_DXD1, 0x99}, |
1882 | {CS43130_DXD19, 0x0A}, |
1883 | {CS43130_DXD17, 0x93}, |
1884 | {CS43130_DXD18, 0x0A}, |
1885 | {CS43130_DXD1, 0}, |
1886 | {CS43130_HP_LOAD_1, 0x80}, |
1887 | {CS43130_HP_LOAD_1, 0x82}, |
1888 | }; |
1889 | |
1890 | static struct reg_sequence hp_ac_ch_l_seq2[] = { |
1891 | {CS43130_HP_LOAD_1, 0x80}, |
1892 | {CS43130_HP_LOAD_1, 0x82}, |
1893 | }; |
1894 | |
1895 | static struct reg_sequence hp_ac_ch_r_seq[] = { |
1896 | {CS43130_DXD1, 0x99}, |
1897 | {CS43130_DXD19, 0x8A}, |
1898 | {CS43130_DXD17, 0x15}, |
1899 | {CS43130_DXD18, 0x06}, |
1900 | {CS43130_DXD1, 0}, |
1901 | {CS43130_HP_LOAD_1, 0x90}, |
1902 | {CS43130_HP_LOAD_1, 0x92}, |
1903 | }; |
1904 | |
1905 | static struct reg_sequence hp_ac_ch_r_seq2[] = { |
1906 | {CS43130_HP_LOAD_1, 0x90}, |
1907 | {CS43130_HP_LOAD_1, 0x92}, |
1908 | }; |
1909 | |
1910 | static struct reg_sequence hp_cln_seq[] = { |
1911 | {CS43130_INT_MASK_4, CS43130_INT_MASK_ALL}, |
1912 | {CS43130_HP_MEAS_LOAD_1, 0}, |
1913 | {CS43130_HP_MEAS_LOAD_2, 0}, |
1914 | }; |
1915 | |
1916 | struct reg_sequences { |
1917 | struct reg_sequence *seq; |
1918 | int size; |
1919 | unsigned int msk; |
1920 | }; |
1921 | |
1922 | static struct reg_sequences hpload_seq1[] = { |
1923 | { |
1924 | .seq = hp_en_cal_seq, |
1925 | .size = ARRAY_SIZE(hp_en_cal_seq), |
1926 | .msk = CS43130_HPLOAD_ON_INT, |
1927 | }, |
1928 | { |
1929 | .seq = hp_dc_ch_l_seq, |
1930 | .size = ARRAY_SIZE(hp_dc_ch_l_seq), |
1931 | .msk = CS43130_HPLOAD_DC_INT, |
1932 | }, |
1933 | { |
1934 | .seq = hp_ac_ch_l_seq, |
1935 | .size = ARRAY_SIZE(hp_ac_ch_l_seq), |
1936 | .msk = CS43130_HPLOAD_AC_INT, |
1937 | }, |
1938 | { |
1939 | .seq = hp_dis_cal_seq, |
1940 | .size = ARRAY_SIZE(hp_dis_cal_seq), |
1941 | .msk = CS43130_HPLOAD_OFF_INT, |
1942 | }, |
1943 | { |
1944 | .seq = hp_en_cal_seq, |
1945 | .size = ARRAY_SIZE(hp_en_cal_seq), |
1946 | .msk = CS43130_HPLOAD_ON_INT, |
1947 | }, |
1948 | { |
1949 | .seq = hp_dc_ch_r_seq, |
1950 | .size = ARRAY_SIZE(hp_dc_ch_r_seq), |
1951 | .msk = CS43130_HPLOAD_DC_INT, |
1952 | }, |
1953 | { |
1954 | .seq = hp_ac_ch_r_seq, |
1955 | .size = ARRAY_SIZE(hp_ac_ch_r_seq), |
1956 | .msk = CS43130_HPLOAD_AC_INT, |
1957 | }, |
1958 | }; |
1959 | |
1960 | static struct reg_sequences hpload_seq2[] = { |
1961 | { |
1962 | .seq = hp_en_cal_seq2, |
1963 | .size = ARRAY_SIZE(hp_en_cal_seq2), |
1964 | .msk = CS43130_HPLOAD_ON_INT, |
1965 | }, |
1966 | { |
1967 | .seq = hp_dc_ch_l_seq2, |
1968 | .size = ARRAY_SIZE(hp_dc_ch_l_seq2), |
1969 | .msk = CS43130_HPLOAD_DC_INT, |
1970 | }, |
1971 | { |
1972 | .seq = hp_ac_ch_l_seq2, |
1973 | .size = ARRAY_SIZE(hp_ac_ch_l_seq2), |
1974 | .msk = CS43130_HPLOAD_AC_INT, |
1975 | }, |
1976 | { |
1977 | .seq = hp_dis_cal_seq2, |
1978 | .size = ARRAY_SIZE(hp_dis_cal_seq2), |
1979 | .msk = CS43130_HPLOAD_OFF_INT, |
1980 | }, |
1981 | { |
1982 | .seq = hp_en_cal_seq2, |
1983 | .size = ARRAY_SIZE(hp_en_cal_seq2), |
1984 | .msk = CS43130_HPLOAD_ON_INT, |
1985 | }, |
1986 | { |
1987 | .seq = hp_dc_ch_r_seq2, |
1988 | .size = ARRAY_SIZE(hp_dc_ch_r_seq2), |
1989 | .msk = CS43130_HPLOAD_DC_INT, |
1990 | }, |
1991 | { |
1992 | .seq = hp_ac_ch_r_seq2, |
1993 | .size = ARRAY_SIZE(hp_ac_ch_r_seq2), |
1994 | .msk = CS43130_HPLOAD_AC_INT, |
1995 | }, |
1996 | }; |
1997 | |
1998 | static int cs43130_update_hpload(unsigned int msk, int ac_idx, |
1999 | struct cs43130_private *cs43130) |
2000 | { |
2001 | bool left_ch = true; |
2002 | unsigned int reg; |
2003 | u32 addr; |
2004 | u16 impedance; |
2005 | |
2006 | switch (msk) { |
2007 | case CS43130_HPLOAD_DC_INT: |
2008 | case CS43130_HPLOAD_AC_INT: |
2009 | break; |
2010 | default: |
2011 | return 0; |
2012 | } |
2013 | |
2014 | regmap_read(map: cs43130->regmap, CS43130_HP_LOAD_1, val: ®); |
2015 | if (reg & CS43130_HPLOAD_CHN_SEL) |
2016 | left_ch = false; |
2017 | |
2018 | if (msk == CS43130_HPLOAD_DC_INT) |
2019 | addr = CS43130_HP_DC_STAT_1; |
2020 | else |
2021 | addr = CS43130_HP_AC_STAT_1; |
2022 | |
2023 | regmap_read(map: cs43130->regmap, reg: addr, val: ®); |
2024 | impedance = reg >> 3; |
2025 | regmap_read(map: cs43130->regmap, reg: addr + 1, val: ®); |
2026 | impedance |= reg << 5; |
2027 | |
2028 | if (msk == CS43130_HPLOAD_DC_INT) { |
2029 | if (left_ch) |
2030 | cs43130->hpload_dc[HP_LEFT] = impedance; |
2031 | else |
2032 | cs43130->hpload_dc[HP_RIGHT] = impedance; |
2033 | |
2034 | dev_dbg(cs43130->dev, "HP DC impedance (Ch %u): %u\n" , !left_ch, |
2035 | impedance); |
2036 | } else { |
2037 | if (left_ch) |
2038 | cs43130->hpload_ac[ac_idx][HP_LEFT] = impedance; |
2039 | else |
2040 | cs43130->hpload_ac[ac_idx][HP_RIGHT] = impedance; |
2041 | |
2042 | dev_dbg(cs43130->dev, "HP AC (%u Hz) impedance (Ch %u): %u\n" , |
2043 | cs43130->ac_freq[ac_idx], !left_ch, impedance); |
2044 | } |
2045 | |
2046 | return 0; |
2047 | } |
2048 | |
2049 | static int cs43130_hpload_proc(struct cs43130_private *cs43130, |
2050 | struct reg_sequence *seq, int seq_size, |
2051 | unsigned int rslt_msk, int ac_idx) |
2052 | { |
2053 | int ret; |
2054 | unsigned int msk; |
2055 | u16 ac_reg_val; |
2056 | |
2057 | reinit_completion(x: &cs43130->hpload_evt); |
2058 | |
2059 | if (rslt_msk == CS43130_HPLOAD_AC_INT) { |
2060 | ac_reg_val = cs43130_get_ac_reg_val(ac_freq: cs43130->ac_freq[ac_idx]); |
2061 | regmap_update_bits(map: cs43130->regmap, CS43130_HP_LOAD_1, |
2062 | CS43130_HPLOAD_AC_START, val: 0); |
2063 | regmap_update_bits(map: cs43130->regmap, CS43130_HP_MEAS_LOAD_1, |
2064 | CS43130_HP_MEAS_LOAD_MASK, |
2065 | val: ac_reg_val >> CS43130_HP_MEAS_LOAD_1_SHIFT); |
2066 | regmap_update_bits(map: cs43130->regmap, CS43130_HP_MEAS_LOAD_2, |
2067 | CS43130_HP_MEAS_LOAD_MASK, |
2068 | val: ac_reg_val >> CS43130_HP_MEAS_LOAD_2_SHIFT); |
2069 | } |
2070 | |
2071 | regmap_multi_reg_write(map: cs43130->regmap, regs: seq, |
2072 | num_regs: seq_size); |
2073 | |
2074 | ret = wait_for_completion_timeout(x: &cs43130->hpload_evt, |
2075 | timeout: msecs_to_jiffies(m: 1000)); |
2076 | regmap_read(map: cs43130->regmap, CS43130_INT_MASK_4, val: &msk); |
2077 | if (!ret) { |
2078 | dev_err(cs43130->dev, "Timeout waiting for HPLOAD interrupt\n" ); |
2079 | return -ETIMEDOUT; |
2080 | } |
2081 | |
2082 | dev_dbg(cs43130->dev, "HP load stat: %x, INT_MASK_4: %x\n" , |
2083 | cs43130->hpload_stat, msk); |
2084 | if ((cs43130->hpload_stat & (CS43130_HPLOAD_NO_DC_INT | |
2085 | CS43130_HPLOAD_UNPLUG_INT | |
2086 | CS43130_HPLOAD_OOR_INT)) || |
2087 | !(cs43130->hpload_stat & rslt_msk)) { |
2088 | dev_dbg(cs43130->dev, "HP load measure failed\n" ); |
2089 | return -1; |
2090 | } |
2091 | |
2092 | return 0; |
2093 | } |
2094 | |
2095 | static const struct reg_sequence hv_seq[][2] = { |
2096 | { |
2097 | {CS43130_CLASS_H_CTL, 0x1C}, |
2098 | {CS43130_HP_OUT_CTL_1, 0x10}, |
2099 | }, |
2100 | { |
2101 | {CS43130_CLASS_H_CTL, 0x1E}, |
2102 | {CS43130_HP_OUT_CTL_1, 0x20}, |
2103 | }, |
2104 | { |
2105 | {CS43130_CLASS_H_CTL, 0x1E}, |
2106 | {CS43130_HP_OUT_CTL_1, 0x30}, |
2107 | }, |
2108 | }; |
2109 | |
2110 | static int cs43130_set_hv(struct regmap *regmap, u16 hpload_dc, |
2111 | const u16 *dc_threshold) |
2112 | { |
2113 | int i; |
2114 | |
2115 | for (i = 0; i < CS43130_DC_THRESHOLD; i++) { |
2116 | if (hpload_dc <= dc_threshold[i]) |
2117 | break; |
2118 | } |
2119 | |
2120 | regmap_multi_reg_write(map: regmap, regs: hv_seq[i], ARRAY_SIZE(hv_seq[i])); |
2121 | |
2122 | return 0; |
2123 | } |
2124 | |
2125 | static void cs43130_imp_meas(struct work_struct *wk) |
2126 | { |
2127 | unsigned int reg, seq_size; |
2128 | int i, ret, ac_idx; |
2129 | struct cs43130_private *cs43130; |
2130 | struct snd_soc_component *component; |
2131 | struct reg_sequences *hpload_seq; |
2132 | |
2133 | cs43130 = container_of(wk, struct cs43130_private, work); |
2134 | component = cs43130->component; |
2135 | |
2136 | if (!cs43130->mclk) |
2137 | return; |
2138 | |
2139 | cs43130->hpload_done = false; |
2140 | |
2141 | mutex_lock(&cs43130->clk_mutex); |
2142 | if (!cs43130->clk_req) { |
2143 | /* clk not in use */ |
2144 | cs43130_set_pll(component, pll_id: 0, source: 0, freq_in: cs43130->mclk, CS43130_MCLK_22M); |
2145 | if (cs43130->pll_bypass) |
2146 | cs43130_change_clksrc(component, src: CS43130_MCLK_SRC_EXT); |
2147 | else |
2148 | cs43130_change_clksrc(component, src: CS43130_MCLK_SRC_PLL); |
2149 | } |
2150 | |
2151 | cs43130->clk_req++; |
2152 | mutex_unlock(lock: &cs43130->clk_mutex); |
2153 | |
2154 | regmap_read(map: cs43130->regmap, CS43130_INT_STATUS_4, val: ®); |
2155 | |
2156 | switch (cs43130->dev_id) { |
2157 | case CS43130_CHIP_ID: |
2158 | hpload_seq = hpload_seq1; |
2159 | seq_size = ARRAY_SIZE(hpload_seq1); |
2160 | break; |
2161 | case CS43131_CHIP_ID: |
2162 | hpload_seq = hpload_seq2; |
2163 | seq_size = ARRAY_SIZE(hpload_seq2); |
2164 | break; |
2165 | default: |
2166 | WARN(1, "Invalid dev_id for meas: %d" , cs43130->dev_id); |
2167 | return; |
2168 | } |
2169 | |
2170 | i = 0; |
2171 | ac_idx = 0; |
2172 | while (i < seq_size) { |
2173 | ret = cs43130_hpload_proc(cs43130, seq: hpload_seq[i].seq, |
2174 | seq_size: hpload_seq[i].size, |
2175 | rslt_msk: hpload_seq[i].msk, ac_idx); |
2176 | if (ret < 0) |
2177 | goto exit; |
2178 | |
2179 | cs43130_update_hpload(msk: hpload_seq[i].msk, ac_idx, cs43130); |
2180 | |
2181 | if (cs43130->ac_meas && |
2182 | hpload_seq[i].msk == CS43130_HPLOAD_AC_INT && |
2183 | ac_idx < CS43130_AC_FREQ - 1) { |
2184 | ac_idx++; |
2185 | } else { |
2186 | ac_idx = 0; |
2187 | i++; |
2188 | } |
2189 | } |
2190 | cs43130->hpload_done = true; |
2191 | |
2192 | if (cs43130->hpload_dc[HP_LEFT] >= CS43130_LINEOUT_LOAD) |
2193 | snd_soc_jack_report(jack: &cs43130->jack, CS43130_JACK_LINEOUT, |
2194 | CS43130_JACK_MASK); |
2195 | else |
2196 | snd_soc_jack_report(jack: &cs43130->jack, CS43130_JACK_HEADPHONE, |
2197 | CS43130_JACK_MASK); |
2198 | |
2199 | dev_dbg(cs43130->dev, "Set HP output control. DC threshold\n" ); |
2200 | for (i = 0; i < CS43130_DC_THRESHOLD; i++) |
2201 | dev_dbg(cs43130->dev, "DC threshold[%d]: %u.\n" , i, |
2202 | cs43130->dc_threshold[i]); |
2203 | |
2204 | cs43130_set_hv(regmap: cs43130->regmap, hpload_dc: cs43130->hpload_dc[HP_LEFT], |
2205 | dc_threshold: cs43130->dc_threshold); |
2206 | |
2207 | exit: |
2208 | switch (cs43130->dev_id) { |
2209 | case CS43130_CHIP_ID: |
2210 | cs43130_hpload_proc(cs43130, seq: hp_dis_cal_seq, |
2211 | ARRAY_SIZE(hp_dis_cal_seq), |
2212 | CS43130_HPLOAD_OFF_INT, ac_idx); |
2213 | break; |
2214 | case CS43131_CHIP_ID: |
2215 | cs43130_hpload_proc(cs43130, seq: hp_dis_cal_seq2, |
2216 | ARRAY_SIZE(hp_dis_cal_seq2), |
2217 | CS43130_HPLOAD_OFF_INT, ac_idx); |
2218 | break; |
2219 | } |
2220 | |
2221 | regmap_multi_reg_write(map: cs43130->regmap, regs: hp_cln_seq, |
2222 | ARRAY_SIZE(hp_cln_seq)); |
2223 | |
2224 | mutex_lock(&cs43130->clk_mutex); |
2225 | cs43130->clk_req--; |
2226 | /* clk not in use */ |
2227 | if (!cs43130->clk_req) |
2228 | cs43130_change_clksrc(component, src: CS43130_MCLK_SRC_RCO); |
2229 | mutex_unlock(lock: &cs43130->clk_mutex); |
2230 | } |
2231 | |
2232 | static irqreturn_t cs43130_irq_thread(int irq, void *data) |
2233 | { |
2234 | struct cs43130_private *cs43130 = (struct cs43130_private *)data; |
2235 | unsigned int stickies[CS43130_NUM_INT]; |
2236 | unsigned int irq_occurrence = 0; |
2237 | unsigned int masks[CS43130_NUM_INT]; |
2238 | int i, j; |
2239 | |
2240 | for (i = 0; i < ARRAY_SIZE(stickies); i++) { |
2241 | regmap_read(map: cs43130->regmap, CS43130_INT_STATUS_1 + i, |
2242 | val: &stickies[i]); |
2243 | regmap_read(map: cs43130->regmap, CS43130_INT_MASK_1 + i, |
2244 | val: &masks[i]); |
2245 | } |
2246 | |
2247 | for (i = 0; i < ARRAY_SIZE(stickies); i++) { |
2248 | stickies[i] = stickies[i] & (~masks[i]); |
2249 | for (j = 0; j < 8; j++) |
2250 | irq_occurrence += (stickies[i] >> j) & 1; |
2251 | } |
2252 | |
2253 | if (!irq_occurrence) |
2254 | return IRQ_NONE; |
2255 | |
2256 | if (stickies[0] & CS43130_XTAL_RDY_INT) { |
2257 | complete(&cs43130->xtal_rdy); |
2258 | return IRQ_HANDLED; |
2259 | } |
2260 | |
2261 | if (stickies[0] & CS43130_PLL_RDY_INT) { |
2262 | complete(&cs43130->pll_rdy); |
2263 | return IRQ_HANDLED; |
2264 | } |
2265 | |
2266 | if (stickies[3] & CS43130_HPLOAD_NO_DC_INT) { |
2267 | cs43130->hpload_stat = stickies[3]; |
2268 | dev_err(cs43130->dev, |
2269 | "DC load has not completed before AC load (%x)\n" , |
2270 | cs43130->hpload_stat); |
2271 | complete(&cs43130->hpload_evt); |
2272 | return IRQ_HANDLED; |
2273 | } |
2274 | |
2275 | if (stickies[3] & CS43130_HPLOAD_UNPLUG_INT) { |
2276 | cs43130->hpload_stat = stickies[3]; |
2277 | dev_err(cs43130->dev, "HP unplugged during measurement (%x)\n" , |
2278 | cs43130->hpload_stat); |
2279 | complete(&cs43130->hpload_evt); |
2280 | return IRQ_HANDLED; |
2281 | } |
2282 | |
2283 | if (stickies[3] & CS43130_HPLOAD_OOR_INT) { |
2284 | cs43130->hpload_stat = stickies[3]; |
2285 | dev_err(cs43130->dev, "HP load out of range (%x)\n" , |
2286 | cs43130->hpload_stat); |
2287 | complete(&cs43130->hpload_evt); |
2288 | return IRQ_HANDLED; |
2289 | } |
2290 | |
2291 | if (stickies[3] & CS43130_HPLOAD_AC_INT) { |
2292 | cs43130->hpload_stat = stickies[3]; |
2293 | dev_dbg(cs43130->dev, "HP AC load measurement done (%x)\n" , |
2294 | cs43130->hpload_stat); |
2295 | complete(&cs43130->hpload_evt); |
2296 | return IRQ_HANDLED; |
2297 | } |
2298 | |
2299 | if (stickies[3] & CS43130_HPLOAD_DC_INT) { |
2300 | cs43130->hpload_stat = stickies[3]; |
2301 | dev_dbg(cs43130->dev, "HP DC load measurement done (%x)\n" , |
2302 | cs43130->hpload_stat); |
2303 | complete(&cs43130->hpload_evt); |
2304 | return IRQ_HANDLED; |
2305 | } |
2306 | |
2307 | if (stickies[3] & CS43130_HPLOAD_ON_INT) { |
2308 | cs43130->hpload_stat = stickies[3]; |
2309 | dev_dbg(cs43130->dev, "HP load state machine on done (%x)\n" , |
2310 | cs43130->hpload_stat); |
2311 | complete(&cs43130->hpload_evt); |
2312 | return IRQ_HANDLED; |
2313 | } |
2314 | |
2315 | if (stickies[3] & CS43130_HPLOAD_OFF_INT) { |
2316 | cs43130->hpload_stat = stickies[3]; |
2317 | dev_dbg(cs43130->dev, "HP load state machine off done (%x)\n" , |
2318 | cs43130->hpload_stat); |
2319 | complete(&cs43130->hpload_evt); |
2320 | return IRQ_HANDLED; |
2321 | } |
2322 | |
2323 | if (stickies[0] & CS43130_XTAL_ERR_INT) { |
2324 | dev_err(cs43130->dev, "Crystal err: clock is not running\n" ); |
2325 | return IRQ_HANDLED; |
2326 | } |
2327 | |
2328 | if (stickies[0] & CS43130_HP_UNPLUG_INT) { |
2329 | dev_dbg(cs43130->dev, "HP unplugged\n" ); |
2330 | cs43130->hpload_done = false; |
2331 | snd_soc_jack_report(jack: &cs43130->jack, status: 0, CS43130_JACK_MASK); |
2332 | return IRQ_HANDLED; |
2333 | } |
2334 | |
2335 | if (stickies[0] & CS43130_HP_PLUG_INT) { |
2336 | if (cs43130->dc_meas && !cs43130->hpload_done && |
2337 | !work_busy(work: &cs43130->work)) { |
2338 | dev_dbg(cs43130->dev, "HP load queue work\n" ); |
2339 | queue_work(wq: cs43130->wq, work: &cs43130->work); |
2340 | } |
2341 | |
2342 | snd_soc_jack_report(jack: &cs43130->jack, status: SND_JACK_MECHANICAL, |
2343 | CS43130_JACK_MASK); |
2344 | return IRQ_HANDLED; |
2345 | } |
2346 | |
2347 | return IRQ_NONE; |
2348 | } |
2349 | |
2350 | static int cs43130_probe(struct snd_soc_component *component) |
2351 | { |
2352 | int ret; |
2353 | struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(c: component); |
2354 | struct snd_soc_card *card = component->card; |
2355 | unsigned int reg; |
2356 | |
2357 | cs43130->component = component; |
2358 | |
2359 | if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) { |
2360 | regmap_update_bits(map: cs43130->regmap, CS43130_CRYSTAL_SET, |
2361 | CS43130_XTAL_IBIAS_MASK, |
2362 | val: cs43130->xtal_ibias); |
2363 | regmap_update_bits(map: cs43130->regmap, CS43130_INT_MASK_1, |
2364 | CS43130_XTAL_ERR_INT, val: 0); |
2365 | } |
2366 | |
2367 | ret = snd_soc_card_jack_new(card, id: "Headphone" , CS43130_JACK_MASK, |
2368 | jack: &cs43130->jack); |
2369 | if (ret < 0) { |
2370 | dev_err(cs43130->dev, "Cannot create jack\n" ); |
2371 | return ret; |
2372 | } |
2373 | |
2374 | cs43130->hpload_done = false; |
2375 | if (cs43130->dc_meas) { |
2376 | ret = sysfs_create_groups(kobj: &cs43130->dev->kobj, groups: hpload_groups); |
2377 | if (ret) |
2378 | return ret; |
2379 | |
2380 | cs43130->wq = create_singlethread_workqueue("cs43130_hp" ); |
2381 | if (!cs43130->wq) { |
2382 | sysfs_remove_groups(kobj: &cs43130->dev->kobj, groups: hpload_groups); |
2383 | return -ENOMEM; |
2384 | } |
2385 | INIT_WORK(&cs43130->work, cs43130_imp_meas); |
2386 | } |
2387 | |
2388 | regmap_read(map: cs43130->regmap, CS43130_INT_STATUS_1, val: ®); |
2389 | regmap_read(map: cs43130->regmap, CS43130_HP_STATUS, val: ®); |
2390 | regmap_update_bits(map: cs43130->regmap, CS43130_INT_MASK_1, |
2391 | CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT, val: 0); |
2392 | regmap_update_bits(map: cs43130->regmap, CS43130_HP_DETECT, |
2393 | CS43130_HP_DETECT_CTRL_MASK, val: 0); |
2394 | regmap_update_bits(map: cs43130->regmap, CS43130_HP_DETECT, |
2395 | CS43130_HP_DETECT_CTRL_MASK, |
2396 | CS43130_HP_DETECT_CTRL_MASK); |
2397 | |
2398 | return 0; |
2399 | } |
2400 | |
2401 | static struct snd_soc_component_driver soc_component_dev_cs43130 = { |
2402 | .probe = cs43130_probe, |
2403 | .controls = cs43130_snd_controls, |
2404 | .num_controls = ARRAY_SIZE(cs43130_snd_controls), |
2405 | .set_sysclk = cs43130_component_set_sysclk, |
2406 | .set_pll = cs43130_set_pll, |
2407 | .idle_bias_on = 1, |
2408 | .use_pmdown_time = 1, |
2409 | .endianness = 1, |
2410 | }; |
2411 | |
2412 | static const struct regmap_config cs43130_regmap = { |
2413 | .reg_bits = 24, |
2414 | .pad_bits = 8, |
2415 | .val_bits = 8, |
2416 | |
2417 | .max_register = CS43130_LASTREG, |
2418 | .reg_defaults = cs43130_reg_defaults, |
2419 | .num_reg_defaults = ARRAY_SIZE(cs43130_reg_defaults), |
2420 | .readable_reg = cs43130_readable_register, |
2421 | .precious_reg = cs43130_precious_register, |
2422 | .volatile_reg = cs43130_volatile_register, |
2423 | .cache_type = REGCACHE_MAPLE, |
2424 | /* needed for regcache_sync */ |
2425 | .use_single_read = true, |
2426 | .use_single_write = true, |
2427 | }; |
2428 | |
2429 | static const u16 cs43130_dc_threshold[CS43130_DC_THRESHOLD] = { |
2430 | 50, |
2431 | 120, |
2432 | }; |
2433 | |
2434 | static int cs43130_handle_device_data(struct cs43130_private *cs43130) |
2435 | { |
2436 | unsigned int val; |
2437 | int i; |
2438 | |
2439 | if (device_property_read_u32(dev: cs43130->dev, propname: "cirrus,xtal-ibias" , val: &val) < 0) { |
2440 | /* Crystal is unused. System clock is used for external MCLK */ |
2441 | cs43130->xtal_ibias = CS43130_XTAL_UNUSED; |
2442 | return 0; |
2443 | } |
2444 | |
2445 | switch (val) { |
2446 | case 1: |
2447 | cs43130->xtal_ibias = CS43130_XTAL_IBIAS_7_5UA; |
2448 | break; |
2449 | case 2: |
2450 | cs43130->xtal_ibias = CS43130_XTAL_IBIAS_12_5UA; |
2451 | break; |
2452 | case 3: |
2453 | cs43130->xtal_ibias = CS43130_XTAL_IBIAS_15UA; |
2454 | break; |
2455 | default: |
2456 | dev_err(cs43130->dev, |
2457 | "Invalid cirrus,xtal-ibias value: %d\n" , val); |
2458 | return -EINVAL; |
2459 | } |
2460 | |
2461 | cs43130->dc_meas = device_property_read_bool(dev: cs43130->dev, propname: "cirrus,dc-measure" ); |
2462 | cs43130->ac_meas = device_property_read_bool(dev: cs43130->dev, propname: "cirrus,ac-measure" ); |
2463 | |
2464 | if (!device_property_read_u16_array(dev: cs43130->dev, propname: "cirrus,ac-freq" , val: cs43130->ac_freq, |
2465 | CS43130_AC_FREQ)) { |
2466 | for (i = 0; i < CS43130_AC_FREQ; i++) |
2467 | cs43130->ac_freq[i] = cs43130_ac_freq[i]; |
2468 | } |
2469 | |
2470 | if (!device_property_read_u16_array(dev: cs43130->dev, propname: "cirrus,dc-threshold" , |
2471 | val: cs43130->dc_threshold, |
2472 | CS43130_DC_THRESHOLD)) { |
2473 | for (i = 0; i < CS43130_DC_THRESHOLD; i++) |
2474 | cs43130->dc_threshold[i] = cs43130_dc_threshold[i]; |
2475 | } |
2476 | |
2477 | return 0; |
2478 | } |
2479 | |
2480 | static int cs43130_i2c_probe(struct i2c_client *client) |
2481 | { |
2482 | struct cs43130_private *cs43130; |
2483 | int ret; |
2484 | unsigned int reg; |
2485 | int i, devid; |
2486 | |
2487 | cs43130 = devm_kzalloc(dev: &client->dev, size: sizeof(*cs43130), GFP_KERNEL); |
2488 | if (!cs43130) |
2489 | return -ENOMEM; |
2490 | |
2491 | cs43130->dev = &client->dev; |
2492 | |
2493 | i2c_set_clientdata(client, data: cs43130); |
2494 | |
2495 | cs43130->regmap = devm_regmap_init_i2c(client, &cs43130_regmap); |
2496 | if (IS_ERR(ptr: cs43130->regmap)) { |
2497 | ret = PTR_ERR(ptr: cs43130->regmap); |
2498 | return ret; |
2499 | } |
2500 | |
2501 | if (dev_fwnode(cs43130->dev)) { |
2502 | ret = cs43130_handle_device_data(cs43130); |
2503 | if (ret != 0) |
2504 | return ret; |
2505 | } |
2506 | |
2507 | for (i = 0; i < ARRAY_SIZE(cs43130->supplies); i++) |
2508 | cs43130->supplies[i].supply = cs43130_supply_names[i]; |
2509 | |
2510 | ret = devm_regulator_bulk_get(dev: cs43130->dev, |
2511 | ARRAY_SIZE(cs43130->supplies), |
2512 | consumers: cs43130->supplies); |
2513 | if (ret != 0) { |
2514 | dev_err(cs43130->dev, "Failed to request supplies: %d\n" , ret); |
2515 | return ret; |
2516 | } |
2517 | ret = regulator_bulk_enable(ARRAY_SIZE(cs43130->supplies), |
2518 | consumers: cs43130->supplies); |
2519 | if (ret != 0) { |
2520 | dev_err(cs43130->dev, "Failed to enable supplies: %d\n" , ret); |
2521 | return ret; |
2522 | } |
2523 | |
2524 | cs43130->reset_gpio = devm_gpiod_get_optional(dev: cs43130->dev, |
2525 | con_id: "reset" , flags: GPIOD_OUT_LOW); |
2526 | if (IS_ERR(ptr: cs43130->reset_gpio)) { |
2527 | ret = PTR_ERR(ptr: cs43130->reset_gpio); |
2528 | goto err_supplies; |
2529 | } |
2530 | |
2531 | gpiod_set_value_cansleep(desc: cs43130->reset_gpio, value: 1); |
2532 | |
2533 | usleep_range(min: 2000, max: 2050); |
2534 | |
2535 | devid = cirrus_read_device_id(regmap: cs43130->regmap, CS43130_DEVID_AB); |
2536 | if (devid < 0) { |
2537 | ret = devid; |
2538 | dev_err(cs43130->dev, "Failed to read device ID: %d\n" , ret); |
2539 | goto err; |
2540 | } |
2541 | |
2542 | switch (devid) { |
2543 | case CS43130_CHIP_ID: |
2544 | case CS4399_CHIP_ID: |
2545 | case CS43131_CHIP_ID: |
2546 | case CS43198_CHIP_ID: |
2547 | break; |
2548 | default: |
2549 | dev_err(cs43130->dev, |
2550 | "CS43130 Device ID %X. Expected ID %X, %X, %X or %X\n" , |
2551 | devid, CS43130_CHIP_ID, CS4399_CHIP_ID, |
2552 | CS43131_CHIP_ID, CS43198_CHIP_ID); |
2553 | ret = -ENODEV; |
2554 | goto err; |
2555 | } |
2556 | |
2557 | cs43130->dev_id = devid; |
2558 | ret = regmap_read(map: cs43130->regmap, CS43130_REV_ID, val: ®); |
2559 | if (ret < 0) { |
2560 | dev_err(cs43130->dev, "Get Revision ID failed\n" ); |
2561 | goto err; |
2562 | } |
2563 | |
2564 | dev_info(cs43130->dev, |
2565 | "Cirrus Logic CS43130 (%x), Revision: %02X\n" , devid, |
2566 | reg & 0xFF); |
2567 | |
2568 | mutex_init(&cs43130->clk_mutex); |
2569 | |
2570 | init_completion(x: &cs43130->xtal_rdy); |
2571 | init_completion(x: &cs43130->pll_rdy); |
2572 | init_completion(x: &cs43130->hpload_evt); |
2573 | |
2574 | if (!client->irq) { |
2575 | dev_dbg(cs43130->dev, "IRQ not found, will poll instead\n" ); |
2576 | cs43130->has_irq_line = 0; |
2577 | } else { |
2578 | ret = devm_request_threaded_irq(dev: cs43130->dev, irq: client->irq, |
2579 | NULL, thread_fn: cs43130_irq_thread, |
2580 | IRQF_ONESHOT | IRQF_TRIGGER_LOW, |
2581 | devname: "cs43130" , dev_id: cs43130); |
2582 | if (ret != 0) { |
2583 | dev_err(cs43130->dev, "Failed to request IRQ: %d\n" , ret); |
2584 | goto err; |
2585 | } |
2586 | cs43130->has_irq_line = 1; |
2587 | } |
2588 | |
2589 | cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO; |
2590 | |
2591 | pm_runtime_set_autosuspend_delay(dev: cs43130->dev, delay: 100); |
2592 | pm_runtime_use_autosuspend(dev: cs43130->dev); |
2593 | pm_runtime_set_active(dev: cs43130->dev); |
2594 | pm_runtime_enable(dev: cs43130->dev); |
2595 | |
2596 | switch (cs43130->dev_id) { |
2597 | case CS43130_CHIP_ID: |
2598 | case CS43131_CHIP_ID: |
2599 | memcpy(all_hp_widgets, digital_hp_widgets, |
2600 | sizeof(digital_hp_widgets)); |
2601 | memcpy(all_hp_widgets + ARRAY_SIZE(digital_hp_widgets), |
2602 | analog_hp_widgets, sizeof(analog_hp_widgets)); |
2603 | memcpy(all_hp_routes, digital_hp_routes, |
2604 | sizeof(digital_hp_routes)); |
2605 | memcpy(all_hp_routes + ARRAY_SIZE(digital_hp_routes), |
2606 | analog_hp_routes, sizeof(analog_hp_routes)); |
2607 | |
2608 | soc_component_dev_cs43130.dapm_widgets = |
2609 | all_hp_widgets; |
2610 | soc_component_dev_cs43130.num_dapm_widgets = |
2611 | ARRAY_SIZE(all_hp_widgets); |
2612 | soc_component_dev_cs43130.dapm_routes = |
2613 | all_hp_routes; |
2614 | soc_component_dev_cs43130.num_dapm_routes = |
2615 | ARRAY_SIZE(all_hp_routes); |
2616 | break; |
2617 | case CS43198_CHIP_ID: |
2618 | case CS4399_CHIP_ID: |
2619 | soc_component_dev_cs43130.dapm_widgets = |
2620 | digital_hp_widgets; |
2621 | soc_component_dev_cs43130.num_dapm_widgets = |
2622 | ARRAY_SIZE(digital_hp_widgets); |
2623 | soc_component_dev_cs43130.dapm_routes = |
2624 | digital_hp_routes; |
2625 | soc_component_dev_cs43130.num_dapm_routes = |
2626 | ARRAY_SIZE(digital_hp_routes); |
2627 | break; |
2628 | } |
2629 | |
2630 | ret = devm_snd_soc_register_component(dev: cs43130->dev, |
2631 | component_driver: &soc_component_dev_cs43130, |
2632 | dai_drv: cs43130_dai, ARRAY_SIZE(cs43130_dai)); |
2633 | if (ret < 0) { |
2634 | dev_err(cs43130->dev, |
2635 | "snd_soc_register_component failed with ret = %d\n" , ret); |
2636 | goto err; |
2637 | } |
2638 | |
2639 | regmap_update_bits(map: cs43130->regmap, CS43130_PAD_INT_CFG, |
2640 | CS43130_ASP_3ST_MASK, val: 0); |
2641 | regmap_update_bits(map: cs43130->regmap, CS43130_PAD_INT_CFG, |
2642 | CS43130_XSP_3ST_MASK, val: 0); |
2643 | |
2644 | return 0; |
2645 | |
2646 | err: |
2647 | gpiod_set_value_cansleep(desc: cs43130->reset_gpio, value: 0); |
2648 | err_supplies: |
2649 | regulator_bulk_disable(ARRAY_SIZE(cs43130->supplies), |
2650 | consumers: cs43130->supplies); |
2651 | |
2652 | return ret; |
2653 | } |
2654 | |
2655 | static void cs43130_i2c_remove(struct i2c_client *client) |
2656 | { |
2657 | struct cs43130_private *cs43130 = i2c_get_clientdata(client); |
2658 | |
2659 | if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) |
2660 | regmap_update_bits(map: cs43130->regmap, CS43130_INT_MASK_1, |
2661 | CS43130_XTAL_ERR_INT, |
2662 | val: 1 << CS43130_XTAL_ERR_INT_SHIFT); |
2663 | |
2664 | regmap_update_bits(map: cs43130->regmap, CS43130_INT_MASK_1, |
2665 | CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT, |
2666 | CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT); |
2667 | |
2668 | if (cs43130->dc_meas) { |
2669 | cancel_work_sync(work: &cs43130->work); |
2670 | flush_workqueue(cs43130->wq); |
2671 | |
2672 | device_remove_file(dev: cs43130->dev, attr: &dev_attr_hpload_dc_l); |
2673 | device_remove_file(dev: cs43130->dev, attr: &dev_attr_hpload_dc_r); |
2674 | device_remove_file(dev: cs43130->dev, attr: &dev_attr_hpload_ac_l); |
2675 | device_remove_file(dev: cs43130->dev, attr: &dev_attr_hpload_ac_r); |
2676 | } |
2677 | |
2678 | gpiod_set_value_cansleep(desc: cs43130->reset_gpio, value: 0); |
2679 | |
2680 | pm_runtime_disable(dev: cs43130->dev); |
2681 | regulator_bulk_disable(CS43130_NUM_SUPPLIES, consumers: cs43130->supplies); |
2682 | } |
2683 | |
2684 | static int __maybe_unused cs43130_runtime_suspend(struct device *dev) |
2685 | { |
2686 | struct cs43130_private *cs43130 = dev_get_drvdata(dev); |
2687 | |
2688 | if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) |
2689 | regmap_update_bits(map: cs43130->regmap, CS43130_INT_MASK_1, |
2690 | CS43130_XTAL_ERR_INT, |
2691 | val: 1 << CS43130_XTAL_ERR_INT_SHIFT); |
2692 | |
2693 | regcache_cache_only(map: cs43130->regmap, enable: true); |
2694 | regcache_mark_dirty(map: cs43130->regmap); |
2695 | |
2696 | gpiod_set_value_cansleep(desc: cs43130->reset_gpio, value: 0); |
2697 | |
2698 | regulator_bulk_disable(CS43130_NUM_SUPPLIES, consumers: cs43130->supplies); |
2699 | |
2700 | return 0; |
2701 | } |
2702 | |
2703 | static int __maybe_unused cs43130_runtime_resume(struct device *dev) |
2704 | { |
2705 | struct cs43130_private *cs43130 = dev_get_drvdata(dev); |
2706 | int ret; |
2707 | |
2708 | ret = regulator_bulk_enable(CS43130_NUM_SUPPLIES, consumers: cs43130->supplies); |
2709 | if (ret != 0) { |
2710 | dev_err(dev, "Failed to enable supplies: %d\n" , ret); |
2711 | return ret; |
2712 | } |
2713 | |
2714 | regcache_cache_only(map: cs43130->regmap, enable: false); |
2715 | |
2716 | gpiod_set_value_cansleep(desc: cs43130->reset_gpio, value: 1); |
2717 | |
2718 | usleep_range(min: 2000, max: 2050); |
2719 | |
2720 | ret = regcache_sync(map: cs43130->regmap); |
2721 | if (ret != 0) { |
2722 | dev_err(dev, "Failed to restore register cache\n" ); |
2723 | goto err; |
2724 | } |
2725 | |
2726 | if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) |
2727 | regmap_update_bits(map: cs43130->regmap, CS43130_INT_MASK_1, |
2728 | CS43130_XTAL_ERR_INT, val: 0); |
2729 | |
2730 | return 0; |
2731 | err: |
2732 | regcache_cache_only(map: cs43130->regmap, enable: true); |
2733 | regulator_bulk_disable(CS43130_NUM_SUPPLIES, consumers: cs43130->supplies); |
2734 | |
2735 | return ret; |
2736 | } |
2737 | |
2738 | static const struct dev_pm_ops cs43130_runtime_pm = { |
2739 | SET_RUNTIME_PM_OPS(cs43130_runtime_suspend, cs43130_runtime_resume, |
2740 | NULL) |
2741 | }; |
2742 | |
2743 | #if IS_ENABLED(CONFIG_OF) |
2744 | static const struct of_device_id cs43130_of_match[] = { |
2745 | {.compatible = "cirrus,cs43130" ,}, |
2746 | {.compatible = "cirrus,cs4399" ,}, |
2747 | {.compatible = "cirrus,cs43131" ,}, |
2748 | {.compatible = "cirrus,cs43198" ,}, |
2749 | {}, |
2750 | }; |
2751 | |
2752 | MODULE_DEVICE_TABLE(of, cs43130_of_match); |
2753 | #endif |
2754 | |
2755 | #if IS_ENABLED(CONFIG_ACPI) |
2756 | static const struct acpi_device_id cs43130_acpi_match[] = { |
2757 | { "CSC4399" , 0 }, |
2758 | {} |
2759 | }; |
2760 | |
2761 | MODULE_DEVICE_TABLE(acpi, cs43130_acpi_match); |
2762 | #endif |
2763 | |
2764 | |
2765 | static const struct i2c_device_id cs43130_i2c_id[] = { |
2766 | {"cs43130" , 0}, |
2767 | {"cs4399" , 0}, |
2768 | {"cs43131" , 0}, |
2769 | {"cs43198" , 0}, |
2770 | {} |
2771 | }; |
2772 | |
2773 | MODULE_DEVICE_TABLE(i2c, cs43130_i2c_id); |
2774 | |
2775 | static struct i2c_driver cs43130_i2c_driver = { |
2776 | .driver = { |
2777 | .name = "cs43130" , |
2778 | .of_match_table = of_match_ptr(cs43130_of_match), |
2779 | .acpi_match_table = ACPI_PTR(cs43130_acpi_match), |
2780 | .pm = &cs43130_runtime_pm, |
2781 | }, |
2782 | .id_table = cs43130_i2c_id, |
2783 | .probe = cs43130_i2c_probe, |
2784 | .remove = cs43130_i2c_remove, |
2785 | }; |
2786 | |
2787 | module_i2c_driver(cs43130_i2c_driver); |
2788 | |
2789 | MODULE_AUTHOR("Li Xu <li.xu@cirrus.com>" ); |
2790 | MODULE_DESCRIPTION("Cirrus Logic CS43130 ALSA SoC Codec Driver" ); |
2791 | MODULE_LICENSE("GPL" ); |
2792 | |