1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3
4#include <linux/module.h>
5#include <linux/init.h>
6#include <linux/io.h>
7#include <linux/platform_device.h>
8#include <linux/pm_runtime.h>
9#include <linux/clk.h>
10#include <sound/soc.h>
11#include <sound/pcm.h>
12#include <sound/pcm_params.h>
13#include <sound/soc-dapm.h>
14#include <sound/tlv.h>
15#include <linux/of_clk.h>
16#include <linux/clk-provider.h>
17
18#include "lpass-macro-common.h"
19
20#define CDC_RX_TOP_TOP_CFG0 (0x0000)
21#define CDC_RX_TOP_SWR_CTRL (0x0008)
22#define CDC_RX_TOP_DEBUG (0x000C)
23#define CDC_RX_TOP_DEBUG_BUS (0x0010)
24#define CDC_RX_TOP_DEBUG_EN0 (0x0014)
25#define CDC_RX_TOP_DEBUG_EN1 (0x0018)
26#define CDC_RX_TOP_DEBUG_EN2 (0x001C)
27#define CDC_RX_TOP_HPHL_COMP_WR_LSB (0x0020)
28#define CDC_RX_TOP_HPHL_COMP_WR_MSB (0x0024)
29#define CDC_RX_TOP_HPHL_COMP_LUT (0x0028)
30#define CDC_RX_TOP_HPH_LUT_BYPASS_MASK BIT(7)
31#define CDC_RX_TOP_HPHL_COMP_RD_LSB (0x002C)
32#define CDC_RX_TOP_HPHL_COMP_RD_MSB (0x0030)
33#define CDC_RX_TOP_HPHR_COMP_WR_LSB (0x0034)
34#define CDC_RX_TOP_HPHR_COMP_WR_MSB (0x0038)
35#define CDC_RX_TOP_HPHR_COMP_LUT (0x003C)
36#define CDC_RX_TOP_HPHR_COMP_RD_LSB (0x0040)
37#define CDC_RX_TOP_HPHR_COMP_RD_MSB (0x0044)
38#define CDC_RX_TOP_DSD0_DEBUG_CFG0 (0x0070)
39#define CDC_RX_TOP_DSD0_DEBUG_CFG1 (0x0074)
40#define CDC_RX_TOP_DSD0_DEBUG_CFG2 (0x0078)
41#define CDC_RX_TOP_DSD0_DEBUG_CFG3 (0x007C)
42#define CDC_RX_TOP_DSD1_DEBUG_CFG0 (0x0080)
43#define CDC_RX_TOP_DSD1_DEBUG_CFG1 (0x0084)
44#define CDC_RX_TOP_DSD1_DEBUG_CFG2 (0x0088)
45#define CDC_RX_TOP_DSD1_DEBUG_CFG3 (0x008C)
46#define CDC_RX_TOP_RX_I2S_CTL (0x0090)
47#define CDC_RX_TOP_TX_I2S2_CTL (0x0094)
48#define CDC_RX_TOP_I2S_CLK (0x0098)
49#define CDC_RX_TOP_I2S_RESET (0x009C)
50#define CDC_RX_TOP_I2S_MUX (0x00A0)
51#define CDC_RX_CLK_RST_CTRL_MCLK_CONTROL (0x0100)
52#define CDC_RX_CLK_MCLK_EN_MASK BIT(0)
53#define CDC_RX_CLK_MCLK_ENABLE BIT(0)
54#define CDC_RX_CLK_MCLK2_EN_MASK BIT(1)
55#define CDC_RX_CLK_MCLK2_ENABLE BIT(1)
56#define CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0104)
57#define CDC_RX_FS_MCLK_CNT_EN_MASK BIT(0)
58#define CDC_RX_FS_MCLK_CNT_ENABLE BIT(0)
59#define CDC_RX_FS_MCLK_CNT_CLR_MASK BIT(1)
60#define CDC_RX_FS_MCLK_CNT_CLR BIT(1)
61#define CDC_RX_CLK_RST_CTRL_SWR_CONTROL (0x0108)
62#define CDC_RX_SWR_CLK_EN_MASK BIT(0)
63#define CDC_RX_SWR_RESET_MASK BIT(1)
64#define CDC_RX_SWR_RESET BIT(1)
65#define CDC_RX_CLK_RST_CTRL_DSD_CONTROL (0x010C)
66#define CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL (0x0110)
67#define CDC_RX_SOFTCLIP_CRC (0x0140)
68#define CDC_RX_SOFTCLIP_CLK_EN_MASK BIT(0)
69#define CDC_RX_SOFTCLIP_SOFTCLIP_CTRL (0x0144)
70#define CDC_RX_SOFTCLIP_EN_MASK BIT(0)
71#define CDC_RX_INP_MUX_RX_INT0_CFG0 (0x0180)
72#define CDC_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(3, 0)
73#define CDC_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(7, 4)
74#define CDC_RX_INP_MUX_RX_INT0_CFG1 (0x0184)
75#define CDC_RX_INTX_2_SEL_MASK GENMASK(3, 0)
76#define CDC_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(7, 4)
77#define CDC_RX_INP_MUX_RX_INT1_CFG0 (0x0188)
78#define CDC_RX_INP_MUX_RX_INT1_CFG1 (0x018C)
79#define CDC_RX_INP_MUX_RX_INT2_CFG0 (0x0190)
80#define CDC_RX_INP_MUX_RX_INT2_CFG1 (0x0194)
81#define CDC_RX_INP_MUX_RX_MIX_CFG4 (0x0198)
82#define CDC_RX_INP_MUX_RX_MIX_CFG5 (0x019C)
83#define CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 (0x01A0)
84#define CDC_RX_CLSH_CRC (0x0200)
85#define CDC_RX_CLSH_CLK_EN_MASK BIT(0)
86#define CDC_RX_CLSH_DLY_CTRL (0x0204)
87#define CDC_RX_CLSH_DECAY_CTRL (0x0208)
88#define CDC_RX_CLSH_DECAY_RATE_MASK GENMASK(2, 0)
89#define CDC_RX_CLSH_HPH_V_PA (0x020C)
90#define CDC_RX_CLSH_HPH_V_PA_MIN_MASK GENMASK(5, 0)
91#define CDC_RX_CLSH_EAR_V_PA (0x0210)
92#define CDC_RX_CLSH_HPH_V_HD (0x0214)
93#define CDC_RX_CLSH_EAR_V_HD (0x0218)
94#define CDC_RX_CLSH_K1_MSB (0x021C)
95#define CDC_RX_CLSH_K1_MSB_COEFF_MASK GENMASK(3, 0)
96#define CDC_RX_CLSH_K1_LSB (0x0220)
97#define CDC_RX_CLSH_K2_MSB (0x0224)
98#define CDC_RX_CLSH_K2_LSB (0x0228)
99#define CDC_RX_CLSH_IDLE_CTRL (0x022C)
100#define CDC_RX_CLSH_IDLE_HPH (0x0230)
101#define CDC_RX_CLSH_IDLE_EAR (0x0234)
102#define CDC_RX_CLSH_TEST0 (0x0238)
103#define CDC_RX_CLSH_TEST1 (0x023C)
104#define CDC_RX_CLSH_OVR_VREF (0x0240)
105#define CDC_RX_CLSH_CLSG_CTL (0x0244)
106#define CDC_RX_CLSH_CLSG_CFG1 (0x0248)
107#define CDC_RX_CLSH_CLSG_CFG2 (0x024C)
108#define CDC_RX_BCL_VBAT_PATH_CTL (0x0280)
109#define CDC_RX_BCL_VBAT_CFG (0x0284)
110#define CDC_RX_BCL_VBAT_ADC_CAL1 (0x0288)
111#define CDC_RX_BCL_VBAT_ADC_CAL2 (0x028C)
112#define CDC_RX_BCL_VBAT_ADC_CAL3 (0x0290)
113#define CDC_RX_BCL_VBAT_PK_EST1 (0x0294)
114#define CDC_RX_BCL_VBAT_PK_EST2 (0x0298)
115#define CDC_RX_BCL_VBAT_PK_EST3 (0x029C)
116#define CDC_RX_BCL_VBAT_RF_PROC1 (0x02A0)
117#define CDC_RX_BCL_VBAT_RF_PROC2 (0x02A4)
118#define CDC_RX_BCL_VBAT_TAC1 (0x02A8)
119#define CDC_RX_BCL_VBAT_TAC2 (0x02AC)
120#define CDC_RX_BCL_VBAT_TAC3 (0x02B0)
121#define CDC_RX_BCL_VBAT_TAC4 (0x02B4)
122#define CDC_RX_BCL_VBAT_GAIN_UPD1 (0x02B8)
123#define CDC_RX_BCL_VBAT_GAIN_UPD2 (0x02BC)
124#define CDC_RX_BCL_VBAT_GAIN_UPD3 (0x02C0)
125#define CDC_RX_BCL_VBAT_GAIN_UPD4 (0x02C4)
126#define CDC_RX_BCL_VBAT_GAIN_UPD5 (0x02C8)
127#define CDC_RX_BCL_VBAT_DEBUG1 (0x02CC)
128#define CDC_RX_BCL_VBAT_GAIN_UPD_MON (0x02D0)
129#define CDC_RX_BCL_VBAT_GAIN_MON_VAL (0x02D4)
130#define CDC_RX_BCL_VBAT_BAN (0x02D8)
131#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD1 (0x02DC)
132#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD2 (0x02E0)
133#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD3 (0x02E4)
134#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD4 (0x02E8)
135#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD5 (0x02EC)
136#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD6 (0x02F0)
137#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD7 (0x02F4)
138#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD8 (0x02F8)
139#define CDC_RX_BCL_VBAT_BCL_GAIN_UPD9 (0x02FC)
140#define CDC_RX_BCL_VBAT_ATTN1 (0x0300)
141#define CDC_RX_BCL_VBAT_ATTN2 (0x0304)
142#define CDC_RX_BCL_VBAT_ATTN3 (0x0308)
143#define CDC_RX_BCL_VBAT_DECODE_CTL1 (0x030C)
144#define CDC_RX_BCL_VBAT_DECODE_CTL2 (0x0310)
145#define CDC_RX_BCL_VBAT_DECODE_CFG1 (0x0314)
146#define CDC_RX_BCL_VBAT_DECODE_CFG2 (0x0318)
147#define CDC_RX_BCL_VBAT_DECODE_CFG3 (0x031C)
148#define CDC_RX_BCL_VBAT_DECODE_CFG4 (0x0320)
149#define CDC_RX_BCL_VBAT_DECODE_ST (0x0324)
150#define CDC_RX_INTR_CTRL_CFG (0x0340)
151#define CDC_RX_INTR_CTRL_CLR_COMMIT (0x0344)
152#define CDC_RX_INTR_CTRL_PIN1_MASK0 (0x0360)
153#define CDC_RX_INTR_CTRL_PIN1_STATUS0 (0x0368)
154#define CDC_RX_INTR_CTRL_PIN1_CLEAR0 (0x0370)
155#define CDC_RX_INTR_CTRL_PIN2_MASK0 (0x0380)
156#define CDC_RX_INTR_CTRL_PIN2_STATUS0 (0x0388)
157#define CDC_RX_INTR_CTRL_PIN2_CLEAR0 (0x0390)
158#define CDC_RX_INTR_CTRL_LEVEL0 (0x03C0)
159#define CDC_RX_INTR_CTRL_BYPASS0 (0x03C8)
160#define CDC_RX_INTR_CTRL_SET0 (0x03D0)
161#define CDC_RX_RXn_RX_PATH_CTL(n) (0x0400 + 0x80 * n)
162#define CDC_RX_RX0_RX_PATH_CTL (0x0400)
163#define CDC_RX_PATH_RESET_EN_MASK BIT(6)
164#define CDC_RX_PATH_CLK_EN_MASK BIT(5)
165#define CDC_RX_PATH_CLK_ENABLE BIT(5)
166#define CDC_RX_PATH_PGA_MUTE_MASK BIT(4)
167#define CDC_RX_PATH_PGA_MUTE_ENABLE BIT(4)
168#define CDC_RX_PATH_PCM_RATE_MASK GENMASK(3, 0)
169#define CDC_RX_RXn_RX_PATH_CFG0(n) (0x0404 + 0x80 * n)
170#define CDC_RX_RXn_COMP_EN_MASK BIT(1)
171#define CDC_RX_RX0_RX_PATH_CFG0 (0x0404)
172#define CDC_RX_RXn_CLSH_EN_MASK BIT(6)
173#define CDC_RX_DLY_ZN_EN_MASK BIT(3)
174#define CDC_RX_DLY_ZN_ENABLE BIT(3)
175#define CDC_RX_RXn_HD2_EN_MASK BIT(2)
176#define CDC_RX_RXn_RX_PATH_CFG1(n) (0x0408 + 0x80 * n)
177#define CDC_RX_RXn_SIDETONE_EN_MASK BIT(4)
178#define CDC_RX_RX0_RX_PATH_CFG1 (0x0408)
179#define CDC_RX_RX0_HPH_L_EAR_SEL_MASK BIT(1)
180#define CDC_RX_RXn_RX_PATH_CFG2(n) (0x040C + 0x80 * n)
181#define CDC_RX_RXn_HPF_CUT_FREQ_MASK GENMASK(1, 0)
182#define CDC_RX_RX0_RX_PATH_CFG2 (0x040C)
183#define CDC_RX_RXn_RX_PATH_CFG3(n) (0x0410 + 0x80 * n)
184#define CDC_RX_RX0_RX_PATH_CFG3 (0x0410)
185#define CDC_RX_DC_COEFF_SEL_MASK GENMASK(1, 0)
186#define CDC_RX_DC_COEFF_SEL_TWO 0x2
187#define CDC_RX_RXn_RX_VOL_CTL(n) (0x0414 + 0x80 * n)
188#define CDC_RX_RX0_RX_VOL_CTL (0x0414)
189#define CDC_RX_RXn_RX_PATH_MIX_CTL(n) (0x0418 + 0x80 * n)
190#define CDC_RX_RXn_MIX_PCM_RATE_MASK GENMASK(3, 0)
191#define CDC_RX_RXn_MIX_RESET_MASK BIT(6)
192#define CDC_RX_RXn_MIX_RESET BIT(6)
193#define CDC_RX_RXn_MIX_CLK_EN_MASK BIT(5)
194#define CDC_RX_RX0_RX_PATH_MIX_CTL (0x0418)
195#define CDC_RX_RX0_RX_PATH_MIX_CFG (0x041C)
196#define CDC_RX_RXn_RX_VOL_MIX_CTL(n) (0x0420 + 0x80 * n)
197#define CDC_RX_RX0_RX_VOL_MIX_CTL (0x0420)
198#define CDC_RX_RX0_RX_PATH_SEC1 (0x0424)
199#define CDC_RX_RX0_RX_PATH_SEC2 (0x0428)
200#define CDC_RX_RX0_RX_PATH_SEC3 (0x042C)
201#define CDC_RX_RX0_RX_PATH_SEC4 (0x0430)
202#define CDC_RX_RX0_RX_PATH_SEC7 (0x0434)
203#define CDC_RX_DSM_OUT_DELAY_SEL_MASK GENMASK(2, 0)
204#define CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE 0x2
205#define CDC_RX_RX0_RX_PATH_MIX_SEC0 (0x0438)
206#define CDC_RX_RX0_RX_PATH_MIX_SEC1 (0x043C)
207#define CDC_RX_RXn_RX_PATH_DSM_CTL(n) (0x0440 + 0x80 * n)
208#define CDC_RX_RXn_DSM_CLK_EN_MASK BIT(0)
209#define CDC_RX_RX0_RX_PATH_DSM_CTL (0x0440)
210#define CDC_RX_RX0_RX_PATH_DSM_DATA1 (0x0444)
211#define CDC_RX_RX0_RX_PATH_DSM_DATA2 (0x0448)
212#define CDC_RX_RX0_RX_PATH_DSM_DATA3 (0x044C)
213#define CDC_RX_RX0_RX_PATH_DSM_DATA4 (0x0450)
214#define CDC_RX_RX0_RX_PATH_DSM_DATA5 (0x0454)
215#define CDC_RX_RX0_RX_PATH_DSM_DATA6 (0x0458)
216#define CDC_RX_RX1_RX_PATH_CTL (0x0480)
217#define CDC_RX_RX1_RX_PATH_CFG0 (0x0484)
218#define CDC_RX_RX1_RX_PATH_CFG1 (0x0488)
219#define CDC_RX_RX1_RX_PATH_CFG2 (0x048C)
220#define CDC_RX_RX1_RX_PATH_CFG3 (0x0490)
221#define CDC_RX_RX1_RX_VOL_CTL (0x0494)
222#define CDC_RX_RX1_RX_PATH_MIX_CTL (0x0498)
223#define CDC_RX_RX1_RX_PATH_MIX_CFG (0x049C)
224#define CDC_RX_RX1_RX_VOL_MIX_CTL (0x04A0)
225#define CDC_RX_RX1_RX_PATH_SEC1 (0x04A4)
226#define CDC_RX_RX1_RX_PATH_SEC2 (0x04A8)
227#define CDC_RX_RX1_RX_PATH_SEC3 (0x04AC)
228#define CDC_RX_RXn_HD2_ALPHA_MASK GENMASK(5, 2)
229#define CDC_RX_RX1_RX_PATH_SEC4 (0x04B0)
230#define CDC_RX_RX1_RX_PATH_SEC7 (0x04B4)
231#define CDC_RX_RX1_RX_PATH_MIX_SEC0 (0x04B8)
232#define CDC_RX_RX1_RX_PATH_MIX_SEC1 (0x04BC)
233#define CDC_RX_RX1_RX_PATH_DSM_CTL (0x04C0)
234#define CDC_RX_RX1_RX_PATH_DSM_DATA1 (0x04C4)
235#define CDC_RX_RX1_RX_PATH_DSM_DATA2 (0x04C8)
236#define CDC_RX_RX1_RX_PATH_DSM_DATA3 (0x04CC)
237#define CDC_RX_RX1_RX_PATH_DSM_DATA4 (0x04D0)
238#define CDC_RX_RX1_RX_PATH_DSM_DATA5 (0x04D4)
239#define CDC_RX_RX1_RX_PATH_DSM_DATA6 (0x04D8)
240#define CDC_RX_RX2_RX_PATH_CTL (0x0500)
241#define CDC_RX_RX2_RX_PATH_CFG0 (0x0504)
242#define CDC_RX_RX2_CLSH_EN_MASK BIT(4)
243#define CDC_RX_RX2_DLY_Z_EN_MASK BIT(3)
244#define CDC_RX_RX2_RX_PATH_CFG1 (0x0508)
245#define CDC_RX_RX2_RX_PATH_CFG2 (0x050C)
246#define CDC_RX_RX2_RX_PATH_CFG3 (0x0510)
247#define CDC_RX_RX2_RX_VOL_CTL (0x0514)
248#define CDC_RX_RX2_RX_PATH_MIX_CTL (0x0518)
249#define CDC_RX_RX2_RX_PATH_MIX_CFG (0x051C)
250#define CDC_RX_RX2_RX_VOL_MIX_CTL (0x0520)
251#define CDC_RX_RX2_RX_PATH_SEC0 (0x0524)
252#define CDC_RX_RX2_RX_PATH_SEC1 (0x0528)
253#define CDC_RX_RX2_RX_PATH_SEC2 (0x052C)
254#define CDC_RX_RX2_RX_PATH_SEC3 (0x0530)
255#define CDC_RX_RX2_RX_PATH_SEC4 (0x0534)
256#define CDC_RX_RX2_RX_PATH_SEC5 (0x0538)
257#define CDC_RX_RX2_RX_PATH_SEC6 (0x053C)
258#define CDC_RX_RX2_RX_PATH_SEC7 (0x0540)
259#define CDC_RX_RX2_RX_PATH_MIX_SEC0 (0x0544)
260#define CDC_RX_RX2_RX_PATH_MIX_SEC1 (0x0548)
261#define CDC_RX_RX2_RX_PATH_DSM_CTL (0x054C)
262#define CDC_RX_IDLE_DETECT_PATH_CTL (0x0780)
263#define CDC_RX_IDLE_DETECT_CFG0 (0x0784)
264#define CDC_RX_IDLE_DETECT_CFG1 (0x0788)
265#define CDC_RX_IDLE_DETECT_CFG2 (0x078C)
266#define CDC_RX_IDLE_DETECT_CFG3 (0x0790)
267#define CDC_RX_COMPANDERn_CTL0(n) (0x0800 + 0x40 * n)
268#define CDC_RX_COMPANDERn_CLK_EN_MASK BIT(0)
269#define CDC_RX_COMPANDERn_SOFT_RST_MASK BIT(1)
270#define CDC_RX_COMPANDERn_HALT_MASK BIT(2)
271#define CDC_RX_COMPANDER0_CTL0 (0x0800)
272#define CDC_RX_COMPANDER0_CTL1 (0x0804)
273#define CDC_RX_COMPANDER0_CTL2 (0x0808)
274#define CDC_RX_COMPANDER0_CTL3 (0x080C)
275#define CDC_RX_COMPANDER0_CTL4 (0x0810)
276#define CDC_RX_COMPANDER0_CTL5 (0x0814)
277#define CDC_RX_COMPANDER0_CTL6 (0x0818)
278#define CDC_RX_COMPANDER0_CTL7 (0x081C)
279#define CDC_RX_COMPANDER1_CTL0 (0x0840)
280#define CDC_RX_COMPANDER1_CTL1 (0x0844)
281#define CDC_RX_COMPANDER1_CTL2 (0x0848)
282#define CDC_RX_COMPANDER1_CTL3 (0x084C)
283#define CDC_RX_COMPANDER1_CTL4 (0x0850)
284#define CDC_RX_COMPANDER1_CTL5 (0x0854)
285#define CDC_RX_COMPANDER1_CTL6 (0x0858)
286#define CDC_RX_COMPANDER1_CTL7 (0x085C)
287#define CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK BIT(5)
288#define CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL (0x0A00)
289#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL (0x0A04)
290#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL (0x0A08)
291#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL (0x0A0C)
292#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL (0x0A10)
293#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL (0x0A14)
294#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL (0x0A18)
295#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL (0x0A1C)
296#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL (0x0A20)
297#define CDC_RX_SIDETONE_IIR0_IIR_CTL (0x0A24)
298#define CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL (0x0A28)
299#define CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL (0x0A2C)
300#define CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL (0x0A30)
301#define CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL (0x0A80)
302#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL (0x0A84)
303#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL (0x0A88)
304#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL (0x0A8C)
305#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL (0x0A90)
306#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL (0x0A94)
307#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL (0x0A98)
308#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL (0x0A9C)
309#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL (0x0AA0)
310#define CDC_RX_SIDETONE_IIR1_IIR_CTL (0x0AA4)
311#define CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL (0x0AA8)
312#define CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL (0x0AAC)
313#define CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL (0x0AB0)
314#define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0 (0x0B00)
315#define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1 (0x0B04)
316#define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2 (0x0B08)
317#define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3 (0x0B0C)
318#define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0 (0x0B10)
319#define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1 (0x0B14)
320#define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2 (0x0B18)
321#define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3 (0x0B1C)
322#define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL (0x0B40)
323#define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 (0x0B44)
324#define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL (0x0B50)
325#define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 (0x0B54)
326#define CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL (0x0C00)
327#define CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 (0x0C04)
328#define CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL (0x0C40)
329#define CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0 (0x0C44)
330#define CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL (0x0C80)
331#define CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0 (0x0C84)
332#define CDC_RX_EC_ASRC0_CLK_RST_CTL (0x0D00)
333#define CDC_RX_EC_ASRC0_CTL0 (0x0D04)
334#define CDC_RX_EC_ASRC0_CTL1 (0x0D08)
335#define CDC_RX_EC_ASRC0_FIFO_CTL (0x0D0C)
336#define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB (0x0D10)
337#define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB (0x0D14)
338#define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB (0x0D18)
339#define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB (0x0D1C)
340#define CDC_RX_EC_ASRC0_STATUS_FIFO (0x0D20)
341#define CDC_RX_EC_ASRC1_CLK_RST_CTL (0x0D40)
342#define CDC_RX_EC_ASRC1_CTL0 (0x0D44)
343#define CDC_RX_EC_ASRC1_CTL1 (0x0D48)
344#define CDC_RX_EC_ASRC1_FIFO_CTL (0x0D4C)
345#define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB (0x0D50)
346#define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB (0x0D54)
347#define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB (0x0D58)
348#define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB (0x0D5C)
349#define CDC_RX_EC_ASRC1_STATUS_FIFO (0x0D60)
350#define CDC_RX_EC_ASRC2_CLK_RST_CTL (0x0D80)
351#define CDC_RX_EC_ASRC2_CTL0 (0x0D84)
352#define CDC_RX_EC_ASRC2_CTL1 (0x0D88)
353#define CDC_RX_EC_ASRC2_FIFO_CTL (0x0D8C)
354#define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB (0x0D90)
355#define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB (0x0D94)
356#define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB (0x0D98)
357#define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB (0x0D9C)
358#define CDC_RX_EC_ASRC2_STATUS_FIFO (0x0DA0)
359#define CDC_RX_DSD0_PATH_CTL (0x0F00)
360#define CDC_RX_DSD0_CFG0 (0x0F04)
361#define CDC_RX_DSD0_CFG1 (0x0F08)
362#define CDC_RX_DSD0_CFG2 (0x0F0C)
363#define CDC_RX_DSD1_PATH_CTL (0x0F80)
364#define CDC_RX_DSD1_CFG0 (0x0F84)
365#define CDC_RX_DSD1_CFG1 (0x0F88)
366#define CDC_RX_DSD1_CFG2 (0x0F8C)
367#define RX_MAX_OFFSET (0x0F8C)
368
369#define MCLK_FREQ 19200000
370
371#define RX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
372 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
373 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
374 SNDRV_PCM_RATE_384000)
375/* Fractional Rates */
376#define RX_MACRO_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
377 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
378
379#define RX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
380 SNDRV_PCM_FMTBIT_S24_LE |\
381 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
382
383#define RX_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
384 SNDRV_PCM_RATE_48000)
385#define RX_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
386 SNDRV_PCM_FMTBIT_S24_LE |\
387 SNDRV_PCM_FMTBIT_S24_3LE)
388
389#define RX_MACRO_MAX_DMA_CH_PER_PORT 2
390
391#define RX_MACRO_EC_MIX_TX0_MASK 0xf0
392#define RX_MACRO_EC_MIX_TX1_MASK 0x0f
393#define RX_MACRO_EC_MIX_TX2_MASK 0x0f
394
395#define COMP_MAX_COEFF 25
396#define RX_NUM_CLKS_MAX 5
397
398struct comp_coeff_val {
399 u8 lsb;
400 u8 msb;
401};
402
403enum {
404 HPH_ULP,
405 HPH_LOHIFI,
406 HPH_MODE_MAX,
407};
408
409static const struct comp_coeff_val comp_coeff_table[HPH_MODE_MAX][COMP_MAX_COEFF] = {
410 {
411 {0x40, 0x00},
412 {0x4C, 0x00},
413 {0x5A, 0x00},
414 {0x6B, 0x00},
415 {0x7F, 0x00},
416 {0x97, 0x00},
417 {0xB3, 0x00},
418 {0xD5, 0x00},
419 {0xFD, 0x00},
420 {0x2D, 0x01},
421 {0x66, 0x01},
422 {0xA7, 0x01},
423 {0xF8, 0x01},
424 {0x57, 0x02},
425 {0xC7, 0x02},
426 {0x4B, 0x03},
427 {0xE9, 0x03},
428 {0xA3, 0x04},
429 {0x7D, 0x05},
430 {0x90, 0x06},
431 {0xD1, 0x07},
432 {0x49, 0x09},
433 {0x00, 0x0B},
434 {0x01, 0x0D},
435 {0x59, 0x0F},
436 },
437 {
438 {0x40, 0x00},
439 {0x4C, 0x00},
440 {0x5A, 0x00},
441 {0x6B, 0x00},
442 {0x80, 0x00},
443 {0x98, 0x00},
444 {0xB4, 0x00},
445 {0xD5, 0x00},
446 {0xFE, 0x00},
447 {0x2E, 0x01},
448 {0x66, 0x01},
449 {0xA9, 0x01},
450 {0xF8, 0x01},
451 {0x56, 0x02},
452 {0xC4, 0x02},
453 {0x4F, 0x03},
454 {0xF0, 0x03},
455 {0xAE, 0x04},
456 {0x8B, 0x05},
457 {0x8E, 0x06},
458 {0xBC, 0x07},
459 {0x56, 0x09},
460 {0x0F, 0x0B},
461 {0x13, 0x0D},
462 {0x6F, 0x0F},
463 },
464};
465
466struct rx_macro_reg_mask_val {
467 u16 reg;
468 u8 mask;
469 u8 val;
470};
471
472enum {
473 INTERP_HPHL,
474 INTERP_HPHR,
475 INTERP_AUX,
476 INTERP_MAX
477};
478
479enum {
480 RX_MACRO_RX0,
481 RX_MACRO_RX1,
482 RX_MACRO_RX2,
483 RX_MACRO_RX3,
484 RX_MACRO_RX4,
485 RX_MACRO_RX5,
486 RX_MACRO_PORTS_MAX
487};
488
489enum {
490 RX_MACRO_COMP1, /* HPH_L */
491 RX_MACRO_COMP2, /* HPH_R */
492 RX_MACRO_COMP_MAX
493};
494
495enum {
496 RX_MACRO_EC0_MUX = 0,
497 RX_MACRO_EC1_MUX,
498 RX_MACRO_EC2_MUX,
499 RX_MACRO_EC_MUX_MAX,
500};
501
502enum {
503 INTn_1_INP_SEL_ZERO = 0,
504 INTn_1_INP_SEL_DEC0,
505 INTn_1_INP_SEL_DEC1,
506 INTn_1_INP_SEL_IIR0,
507 INTn_1_INP_SEL_IIR1,
508 INTn_1_INP_SEL_RX0,
509 INTn_1_INP_SEL_RX1,
510 INTn_1_INP_SEL_RX2,
511 INTn_1_INP_SEL_RX3,
512 INTn_1_INP_SEL_RX4,
513 INTn_1_INP_SEL_RX5,
514};
515
516enum {
517 INTn_2_INP_SEL_ZERO = 0,
518 INTn_2_INP_SEL_RX0,
519 INTn_2_INP_SEL_RX1,
520 INTn_2_INP_SEL_RX2,
521 INTn_2_INP_SEL_RX3,
522 INTn_2_INP_SEL_RX4,
523 INTn_2_INP_SEL_RX5,
524};
525
526enum {
527 INTERP_MAIN_PATH,
528 INTERP_MIX_PATH,
529};
530
531/* Codec supports 2 IIR filters */
532enum {
533 IIR0 = 0,
534 IIR1,
535 IIR_MAX,
536};
537
538/* Each IIR has 5 Filter Stages */
539enum {
540 BAND1 = 0,
541 BAND2,
542 BAND3,
543 BAND4,
544 BAND5,
545 BAND_MAX,
546};
547
548#define RX_MACRO_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX)
549
550#define RX_MACRO_IIR_FILTER_CTL(xname, iidx, bidx) \
551{ \
552 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
553 .info = rx_macro_iir_filter_info, \
554 .get = rx_macro_get_iir_band_audio_mixer, \
555 .put = rx_macro_put_iir_band_audio_mixer, \
556 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
557 .iir_idx = iidx, \
558 .band_idx = bidx, \
559 .bytes_ext = {.max = RX_MACRO_IIR_FILTER_SIZE, }, \
560 } \
561}
562
563struct interp_sample_rate {
564 int sample_rate;
565 int rate_val;
566};
567
568static struct interp_sample_rate sr_val_tbl[] = {
569 {8000, 0x0}, {16000, 0x1}, {32000, 0x3}, {48000, 0x4}, {96000, 0x5},
570 {192000, 0x6}, {384000, 0x7}, {44100, 0x9}, {88200, 0xA},
571 {176400, 0xB}, {352800, 0xC},
572};
573
574enum {
575 RX_MACRO_AIF_INVALID = 0,
576 RX_MACRO_AIF1_PB,
577 RX_MACRO_AIF2_PB,
578 RX_MACRO_AIF3_PB,
579 RX_MACRO_AIF4_PB,
580 RX_MACRO_AIF_ECHO,
581 RX_MACRO_MAX_DAIS,
582};
583
584enum {
585 RX_MACRO_AIF1_CAP = 0,
586 RX_MACRO_AIF2_CAP,
587 RX_MACRO_AIF3_CAP,
588 RX_MACRO_MAX_AIF_CAP_DAIS
589};
590
591struct rx_macro {
592 struct device *dev;
593 int comp_enabled[RX_MACRO_COMP_MAX];
594 /* Main path clock users count */
595 int main_clk_users[INTERP_MAX];
596 int rx_port_value[RX_MACRO_PORTS_MAX];
597 u16 prim_int_users[INTERP_MAX];
598 int rx_mclk_users;
599 int clsh_users;
600 int rx_mclk_cnt;
601 bool is_ear_mode_on;
602 bool hph_pwr_mode;
603 bool hph_hd2_mode;
604 struct snd_soc_component *component;
605 unsigned long active_ch_mask[RX_MACRO_MAX_DAIS];
606 unsigned long active_ch_cnt[RX_MACRO_MAX_DAIS];
607 u16 bit_width[RX_MACRO_MAX_DAIS];
608 int is_softclip_on;
609 int is_aux_hpf_on;
610 int softclip_clk_users;
611 struct lpass_macro *pds;
612 struct regmap *regmap;
613 struct clk *mclk;
614 struct clk *npl;
615 struct clk *macro;
616 struct clk *dcodec;
617 struct clk *fsgen;
618 struct clk_hw hw;
619};
620#define to_rx_macro(_hw) container_of(_hw, struct rx_macro, hw)
621
622struct wcd_iir_filter_ctl {
623 unsigned int iir_idx;
624 unsigned int band_idx;
625 struct soc_bytes_ext bytes_ext;
626};
627
628static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
629
630static const char * const rx_int_mix_mux_text[] = {
631 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5"
632};
633
634static const char * const rx_prim_mix_text[] = {
635 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
636 "RX3", "RX4", "RX5"
637};
638
639static const char * const rx_sidetone_mix_text[] = {
640 "ZERO", "SRC0", "SRC1", "SRC_SUM"
641};
642
643static const char * const iir_inp_mux_text[] = {
644 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3",
645 "RX0", "RX1", "RX2", "RX3", "RX4", "RX5"
646};
647
648static const char * const rx_int_dem_inp_mux_text[] = {
649 "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
650};
651
652static const char * const rx_int0_1_interp_mux_text[] = {
653 "ZERO", "RX INT0_1 MIX1",
654};
655
656static const char * const rx_int1_1_interp_mux_text[] = {
657 "ZERO", "RX INT1_1 MIX1",
658};
659
660static const char * const rx_int2_1_interp_mux_text[] = {
661 "ZERO", "RX INT2_1 MIX1",
662};
663
664static const char * const rx_int0_2_interp_mux_text[] = {
665 "ZERO", "RX INT0_2 MUX",
666};
667
668static const char * const rx_int1_2_interp_mux_text[] = {
669 "ZERO", "RX INT1_2 MUX",
670};
671
672static const char * const rx_int2_2_interp_mux_text[] = {
673 "ZERO", "RX INT2_2 MUX",
674};
675
676static const char *const rx_macro_mux_text[] = {
677 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB"
678};
679
680static const char *const rx_macro_hph_pwr_mode_text[] = {
681 "ULP", "LOHIFI"
682};
683
684static const char * const rx_echo_mux_text[] = {
685 "ZERO", "RX_MIX0", "RX_MIX1", "RX_MIX2"
686};
687
688static const struct soc_enum rx_macro_hph_pwr_mode_enum =
689 SOC_ENUM_SINGLE_EXT(2, rx_macro_hph_pwr_mode_text);
690static const struct soc_enum rx_mix_tx2_mux_enum =
691 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG5, 0, 4, rx_echo_mux_text);
692static const struct soc_enum rx_mix_tx1_mux_enum =
693 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 0, 4, rx_echo_mux_text);
694static const struct soc_enum rx_mix_tx0_mux_enum =
695 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 4, 4, rx_echo_mux_text);
696
697static SOC_ENUM_SINGLE_DECL(rx_int0_2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 0,
698 rx_int_mix_mux_text);
699static SOC_ENUM_SINGLE_DECL(rx_int1_2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 0,
700 rx_int_mix_mux_text);
701static SOC_ENUM_SINGLE_DECL(rx_int2_2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 0,
702 rx_int_mix_mux_text);
703
704static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 0,
705 rx_prim_mix_text);
706static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 4,
707 rx_prim_mix_text);
708static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 4,
709 rx_prim_mix_text);
710static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 0,
711 rx_prim_mix_text);
712static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 4,
713 rx_prim_mix_text);
714static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 4,
715 rx_prim_mix_text);
716static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 0,
717 rx_prim_mix_text);
718static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 4,
719 rx_prim_mix_text);
720static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 4,
721 rx_prim_mix_text);
722
723static SOC_ENUM_SINGLE_DECL(rx_int0_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2,
724 rx_sidetone_mix_text);
725static SOC_ENUM_SINGLE_DECL(rx_int1_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4,
726 rx_sidetone_mix_text);
727static SOC_ENUM_SINGLE_DECL(rx_int2_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6,
728 rx_sidetone_mix_text);
729static SOC_ENUM_SINGLE_DECL(iir0_inp0_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0,
730 iir_inp_mux_text);
731static SOC_ENUM_SINGLE_DECL(iir0_inp1_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0,
732 iir_inp_mux_text);
733static SOC_ENUM_SINGLE_DECL(iir0_inp2_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0,
734 iir_inp_mux_text);
735static SOC_ENUM_SINGLE_DECL(iir0_inp3_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0,
736 iir_inp_mux_text);
737static SOC_ENUM_SINGLE_DECL(iir1_inp0_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0,
738 iir_inp_mux_text);
739static SOC_ENUM_SINGLE_DECL(iir1_inp1_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0,
740 iir_inp_mux_text);
741static SOC_ENUM_SINGLE_DECL(iir1_inp2_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0,
742 iir_inp_mux_text);
743static SOC_ENUM_SINGLE_DECL(iir1_inp3_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0,
744 iir_inp_mux_text);
745
746static SOC_ENUM_SINGLE_DECL(rx_int0_1_interp_enum, SND_SOC_NOPM, 0,
747 rx_int0_1_interp_mux_text);
748static SOC_ENUM_SINGLE_DECL(rx_int1_1_interp_enum, SND_SOC_NOPM, 0,
749 rx_int1_1_interp_mux_text);
750static SOC_ENUM_SINGLE_DECL(rx_int2_1_interp_enum, SND_SOC_NOPM, 0,
751 rx_int2_1_interp_mux_text);
752static SOC_ENUM_SINGLE_DECL(rx_int0_2_interp_enum, SND_SOC_NOPM, 0,
753 rx_int0_2_interp_mux_text);
754static SOC_ENUM_SINGLE_DECL(rx_int1_2_interp_enum, SND_SOC_NOPM, 0,
755 rx_int1_2_interp_mux_text);
756static SOC_ENUM_SINGLE_DECL(rx_int2_2_interp_enum, SND_SOC_NOPM, 0,
757 rx_int2_2_interp_mux_text);
758static SOC_ENUM_SINGLE_DECL(rx_int0_dem_inp_enum, CDC_RX_RX0_RX_PATH_CFG1, 0,
759 rx_int_dem_inp_mux_text);
760static SOC_ENUM_SINGLE_DECL(rx_int1_dem_inp_enum, CDC_RX_RX1_RX_PATH_CFG1, 0,
761 rx_int_dem_inp_mux_text);
762
763static SOC_ENUM_SINGLE_DECL(rx_macro_rx0_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
764static SOC_ENUM_SINGLE_DECL(rx_macro_rx1_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
765static SOC_ENUM_SINGLE_DECL(rx_macro_rx2_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
766static SOC_ENUM_SINGLE_DECL(rx_macro_rx3_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
767static SOC_ENUM_SINGLE_DECL(rx_macro_rx4_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
768static SOC_ENUM_SINGLE_DECL(rx_macro_rx5_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
769
770static const struct snd_kcontrol_new rx_mix_tx1_mux =
771 SOC_DAPM_ENUM("RX MIX TX1_MUX Mux", rx_mix_tx1_mux_enum);
772static const struct snd_kcontrol_new rx_mix_tx2_mux =
773 SOC_DAPM_ENUM("RX MIX TX2_MUX Mux", rx_mix_tx2_mux_enum);
774static const struct snd_kcontrol_new rx_int0_2_mux =
775 SOC_DAPM_ENUM("rx_int0_2", rx_int0_2_enum);
776static const struct snd_kcontrol_new rx_int1_2_mux =
777 SOC_DAPM_ENUM("rx_int1_2", rx_int1_2_enum);
778static const struct snd_kcontrol_new rx_int2_2_mux =
779 SOC_DAPM_ENUM("rx_int2_2", rx_int2_2_enum);
780static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
781 SOC_DAPM_ENUM("rx_int0_1_mix_inp0", rx_int0_1_mix_inp0_enum);
782static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
783 SOC_DAPM_ENUM("rx_int0_1_mix_inp1", rx_int0_1_mix_inp1_enum);
784static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
785 SOC_DAPM_ENUM("rx_int0_1_mix_inp2", rx_int0_1_mix_inp2_enum);
786static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
787 SOC_DAPM_ENUM("rx_int1_1_mix_inp0", rx_int1_1_mix_inp0_enum);
788static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
789 SOC_DAPM_ENUM("rx_int1_1_mix_inp1", rx_int1_1_mix_inp1_enum);
790static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
791 SOC_DAPM_ENUM("rx_int1_1_mix_inp2", rx_int1_1_mix_inp2_enum);
792static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
793 SOC_DAPM_ENUM("rx_int2_1_mix_inp0", rx_int2_1_mix_inp0_enum);
794static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
795 SOC_DAPM_ENUM("rx_int2_1_mix_inp1", rx_int2_1_mix_inp1_enum);
796static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
797 SOC_DAPM_ENUM("rx_int2_1_mix_inp2", rx_int2_1_mix_inp2_enum);
798static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
799 SOC_DAPM_ENUM("rx_int0_mix2_inp", rx_int0_mix2_inp_enum);
800static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
801 SOC_DAPM_ENUM("rx_int1_mix2_inp", rx_int1_mix2_inp_enum);
802static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
803 SOC_DAPM_ENUM("rx_int2_mix2_inp", rx_int2_mix2_inp_enum);
804static const struct snd_kcontrol_new iir0_inp0_mux =
805 SOC_DAPM_ENUM("iir0_inp0", iir0_inp0_enum);
806static const struct snd_kcontrol_new iir0_inp1_mux =
807 SOC_DAPM_ENUM("iir0_inp1", iir0_inp1_enum);
808static const struct snd_kcontrol_new iir0_inp2_mux =
809 SOC_DAPM_ENUM("iir0_inp2", iir0_inp2_enum);
810static const struct snd_kcontrol_new iir0_inp3_mux =
811 SOC_DAPM_ENUM("iir0_inp3", iir0_inp3_enum);
812static const struct snd_kcontrol_new iir1_inp0_mux =
813 SOC_DAPM_ENUM("iir1_inp0", iir1_inp0_enum);
814static const struct snd_kcontrol_new iir1_inp1_mux =
815 SOC_DAPM_ENUM("iir1_inp1", iir1_inp1_enum);
816static const struct snd_kcontrol_new iir1_inp2_mux =
817 SOC_DAPM_ENUM("iir1_inp2", iir1_inp2_enum);
818static const struct snd_kcontrol_new iir1_inp3_mux =
819 SOC_DAPM_ENUM("iir1_inp3", iir1_inp3_enum);
820static const struct snd_kcontrol_new rx_int0_1_interp_mux =
821 SOC_DAPM_ENUM("rx_int0_1_interp", rx_int0_1_interp_enum);
822static const struct snd_kcontrol_new rx_int1_1_interp_mux =
823 SOC_DAPM_ENUM("rx_int1_1_interp", rx_int1_1_interp_enum);
824static const struct snd_kcontrol_new rx_int2_1_interp_mux =
825 SOC_DAPM_ENUM("rx_int2_1_interp", rx_int2_1_interp_enum);
826static const struct snd_kcontrol_new rx_int0_2_interp_mux =
827 SOC_DAPM_ENUM("rx_int0_2_interp", rx_int0_2_interp_enum);
828static const struct snd_kcontrol_new rx_int1_2_interp_mux =
829 SOC_DAPM_ENUM("rx_int1_2_interp", rx_int1_2_interp_enum);
830static const struct snd_kcontrol_new rx_int2_2_interp_mux =
831 SOC_DAPM_ENUM("rx_int2_2_interp", rx_int2_2_interp_enum);
832static const struct snd_kcontrol_new rx_mix_tx0_mux =
833 SOC_DAPM_ENUM("RX MIX TX0_MUX Mux", rx_mix_tx0_mux_enum);
834
835static const struct reg_default rx_defaults[] = {
836 /* RX Macro */
837 { CDC_RX_TOP_TOP_CFG0, 0x00 },
838 { CDC_RX_TOP_SWR_CTRL, 0x00 },
839 { CDC_RX_TOP_DEBUG, 0x00 },
840 { CDC_RX_TOP_DEBUG_BUS, 0x00 },
841 { CDC_RX_TOP_DEBUG_EN0, 0x00 },
842 { CDC_RX_TOP_DEBUG_EN1, 0x00 },
843 { CDC_RX_TOP_DEBUG_EN2, 0x00 },
844 { CDC_RX_TOP_HPHL_COMP_WR_LSB, 0x00 },
845 { CDC_RX_TOP_HPHL_COMP_WR_MSB, 0x00 },
846 { CDC_RX_TOP_HPHL_COMP_LUT, 0x00 },
847 { CDC_RX_TOP_HPHL_COMP_RD_LSB, 0x00 },
848 { CDC_RX_TOP_HPHL_COMP_RD_MSB, 0x00 },
849 { CDC_RX_TOP_HPHR_COMP_WR_LSB, 0x00 },
850 { CDC_RX_TOP_HPHR_COMP_WR_MSB, 0x00 },
851 { CDC_RX_TOP_HPHR_COMP_LUT, 0x00 },
852 { CDC_RX_TOP_HPHR_COMP_RD_LSB, 0x00 },
853 { CDC_RX_TOP_HPHR_COMP_RD_MSB, 0x00 },
854 { CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11 },
855 { CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20 },
856 { CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00 },
857 { CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00 },
858 { CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11 },
859 { CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20 },
860 { CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00 },
861 { CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00 },
862 { CDC_RX_TOP_RX_I2S_CTL, 0x0C },
863 { CDC_RX_TOP_TX_I2S2_CTL, 0x0C },
864 { CDC_RX_TOP_I2S_CLK, 0x0C },
865 { CDC_RX_TOP_I2S_RESET, 0x00 },
866 { CDC_RX_TOP_I2S_MUX, 0x00 },
867 { CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
868 { CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
869 { CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 0x00 },
870 { CDC_RX_CLK_RST_CTRL_DSD_CONTROL, 0x00 },
871 { CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL, 0x08 },
872 { CDC_RX_SOFTCLIP_CRC, 0x00 },
873 { CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 0x38 },
874 { CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00 },
875 { CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00 },
876 { CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00 },
877 { CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00 },
878 { CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00 },
879 { CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00 },
880 { CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00 },
881 { CDC_RX_INP_MUX_RX_MIX_CFG5, 0x00 },
882 { CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00 },
883 { CDC_RX_CLSH_CRC, 0x00 },
884 { CDC_RX_CLSH_DLY_CTRL, 0x03 },
885 { CDC_RX_CLSH_DECAY_CTRL, 0x02 },
886 { CDC_RX_CLSH_HPH_V_PA, 0x1C },
887 { CDC_RX_CLSH_EAR_V_PA, 0x39 },
888 { CDC_RX_CLSH_HPH_V_HD, 0x0C },
889 { CDC_RX_CLSH_EAR_V_HD, 0x0C },
890 { CDC_RX_CLSH_K1_MSB, 0x01 },
891 { CDC_RX_CLSH_K1_LSB, 0x00 },
892 { CDC_RX_CLSH_K2_MSB, 0x00 },
893 { CDC_RX_CLSH_K2_LSB, 0x80 },
894 { CDC_RX_CLSH_IDLE_CTRL, 0x00 },
895 { CDC_RX_CLSH_IDLE_HPH, 0x00 },
896 { CDC_RX_CLSH_IDLE_EAR, 0x00 },
897 { CDC_RX_CLSH_TEST0, 0x07 },
898 { CDC_RX_CLSH_TEST1, 0x00 },
899 { CDC_RX_CLSH_OVR_VREF, 0x00 },
900 { CDC_RX_CLSH_CLSG_CTL, 0x02 },
901 { CDC_RX_CLSH_CLSG_CFG1, 0x9A },
902 { CDC_RX_CLSH_CLSG_CFG2, 0x10 },
903 { CDC_RX_BCL_VBAT_PATH_CTL, 0x00 },
904 { CDC_RX_BCL_VBAT_CFG, 0x10 },
905 { CDC_RX_BCL_VBAT_ADC_CAL1, 0x00 },
906 { CDC_RX_BCL_VBAT_ADC_CAL2, 0x00 },
907 { CDC_RX_BCL_VBAT_ADC_CAL3, 0x04 },
908 { CDC_RX_BCL_VBAT_PK_EST1, 0xE0 },
909 { CDC_RX_BCL_VBAT_PK_EST2, 0x01 },
910 { CDC_RX_BCL_VBAT_PK_EST3, 0x40 },
911 { CDC_RX_BCL_VBAT_RF_PROC1, 0x2A },
912 { CDC_RX_BCL_VBAT_RF_PROC1, 0x00 },
913 { CDC_RX_BCL_VBAT_TAC1, 0x00 },
914 { CDC_RX_BCL_VBAT_TAC2, 0x18 },
915 { CDC_RX_BCL_VBAT_TAC3, 0x18 },
916 { CDC_RX_BCL_VBAT_TAC4, 0x03 },
917 { CDC_RX_BCL_VBAT_GAIN_UPD1, 0x01 },
918 { CDC_RX_BCL_VBAT_GAIN_UPD2, 0x00 },
919 { CDC_RX_BCL_VBAT_GAIN_UPD3, 0x00 },
920 { CDC_RX_BCL_VBAT_GAIN_UPD4, 0x64 },
921 { CDC_RX_BCL_VBAT_GAIN_UPD5, 0x01 },
922 { CDC_RX_BCL_VBAT_DEBUG1, 0x00 },
923 { CDC_RX_BCL_VBAT_GAIN_UPD_MON, 0x00 },
924 { CDC_RX_BCL_VBAT_GAIN_MON_VAL, 0x00 },
925 { CDC_RX_BCL_VBAT_BAN, 0x0C },
926 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD1, 0x00 },
927 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD2, 0x77 },
928 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD3, 0x01 },
929 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD4, 0x00 },
930 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD5, 0x4B },
931 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD6, 0x00 },
932 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD7, 0x01 },
933 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD8, 0x00 },
934 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, 0x00 },
935 { CDC_RX_BCL_VBAT_ATTN1, 0x04 },
936 { CDC_RX_BCL_VBAT_ATTN2, 0x08 },
937 { CDC_RX_BCL_VBAT_ATTN3, 0x0C },
938 { CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0 },
939 { CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00 },
940 { CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00 },
941 { CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00 },
942 { CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00 },
943 { CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00 },
944 { CDC_RX_BCL_VBAT_DECODE_ST, 0x00 },
945 { CDC_RX_INTR_CTRL_CFG, 0x00 },
946 { CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00 },
947 { CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF },
948 { CDC_RX_INTR_CTRL_PIN1_STATUS0, 0x00 },
949 { CDC_RX_INTR_CTRL_PIN1_CLEAR0, 0x00 },
950 { CDC_RX_INTR_CTRL_PIN2_MASK0, 0xFF },
951 { CDC_RX_INTR_CTRL_PIN2_STATUS0, 0x00 },
952 { CDC_RX_INTR_CTRL_PIN2_CLEAR0, 0x00 },
953 { CDC_RX_INTR_CTRL_LEVEL0, 0x00 },
954 { CDC_RX_INTR_CTRL_BYPASS0, 0x00 },
955 { CDC_RX_INTR_CTRL_SET0, 0x00 },
956 { CDC_RX_RX0_RX_PATH_CTL, 0x04 },
957 { CDC_RX_RX0_RX_PATH_CFG0, 0x00 },
958 { CDC_RX_RX0_RX_PATH_CFG1, 0x64 },
959 { CDC_RX_RX0_RX_PATH_CFG2, 0x8F },
960 { CDC_RX_RX0_RX_PATH_CFG3, 0x00 },
961 { CDC_RX_RX0_RX_VOL_CTL, 0x00 },
962 { CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04 },
963 { CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E },
964 { CDC_RX_RX0_RX_VOL_MIX_CTL, 0x00 },
965 { CDC_RX_RX0_RX_PATH_SEC1, 0x08 },
966 { CDC_RX_RX0_RX_PATH_SEC2, 0x00 },
967 { CDC_RX_RX0_RX_PATH_SEC3, 0x00 },
968 { CDC_RX_RX0_RX_PATH_SEC4, 0x00 },
969 { CDC_RX_RX0_RX_PATH_SEC7, 0x00 },
970 { CDC_RX_RX0_RX_PATH_MIX_SEC0, 0x08 },
971 { CDC_RX_RX0_RX_PATH_MIX_SEC1, 0x00 },
972 { CDC_RX_RX0_RX_PATH_DSM_CTL, 0x08 },
973 { CDC_RX_RX0_RX_PATH_DSM_DATA1, 0x00 },
974 { CDC_RX_RX0_RX_PATH_DSM_DATA2, 0x00 },
975 { CDC_RX_RX0_RX_PATH_DSM_DATA3, 0x00 },
976 { CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55 },
977 { CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55 },
978 { CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55 },
979 { CDC_RX_RX1_RX_PATH_CTL, 0x04 },
980 { CDC_RX_RX1_RX_PATH_CFG0, 0x00 },
981 { CDC_RX_RX1_RX_PATH_CFG1, 0x64 },
982 { CDC_RX_RX1_RX_PATH_CFG2, 0x8F },
983 { CDC_RX_RX1_RX_PATH_CFG3, 0x00 },
984 { CDC_RX_RX1_RX_VOL_CTL, 0x00 },
985 { CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04 },
986 { CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E },
987 { CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00 },
988 { CDC_RX_RX1_RX_PATH_SEC1, 0x08 },
989 { CDC_RX_RX1_RX_PATH_SEC2, 0x00 },
990 { CDC_RX_RX1_RX_PATH_SEC3, 0x00 },
991 { CDC_RX_RX1_RX_PATH_SEC4, 0x00 },
992 { CDC_RX_RX1_RX_PATH_SEC7, 0x00 },
993 { CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08 },
994 { CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00 },
995 { CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08 },
996 { CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00 },
997 { CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00 },
998 { CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00 },
999 { CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55 },
1000 { CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55 },
1001 { CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55 },
1002 { CDC_RX_RX2_RX_PATH_CTL, 0x04 },
1003 { CDC_RX_RX2_RX_PATH_CFG0, 0x00 },
1004 { CDC_RX_RX2_RX_PATH_CFG1, 0x64 },
1005 { CDC_RX_RX2_RX_PATH_CFG2, 0x8F },
1006 { CDC_RX_RX2_RX_PATH_CFG3, 0x00 },
1007 { CDC_RX_RX2_RX_VOL_CTL, 0x00 },
1008 { CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04 },
1009 { CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E },
1010 { CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00 },
1011 { CDC_RX_RX2_RX_PATH_SEC0, 0x04 },
1012 { CDC_RX_RX2_RX_PATH_SEC1, 0x08 },
1013 { CDC_RX_RX2_RX_PATH_SEC2, 0x00 },
1014 { CDC_RX_RX2_RX_PATH_SEC3, 0x00 },
1015 { CDC_RX_RX2_RX_PATH_SEC4, 0x00 },
1016 { CDC_RX_RX2_RX_PATH_SEC5, 0x00 },
1017 { CDC_RX_RX2_RX_PATH_SEC6, 0x00 },
1018 { CDC_RX_RX2_RX_PATH_SEC7, 0x00 },
1019 { CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08 },
1020 { CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00 },
1021 { CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00 },
1022 { CDC_RX_IDLE_DETECT_PATH_CTL, 0x00 },
1023 { CDC_RX_IDLE_DETECT_CFG0, 0x07 },
1024 { CDC_RX_IDLE_DETECT_CFG1, 0x3C },
1025 { CDC_RX_IDLE_DETECT_CFG2, 0x00 },
1026 { CDC_RX_IDLE_DETECT_CFG3, 0x00 },
1027 { CDC_RX_COMPANDER0_CTL0, 0x60 },
1028 { CDC_RX_COMPANDER0_CTL1, 0xDB },
1029 { CDC_RX_COMPANDER0_CTL2, 0xFF },
1030 { CDC_RX_COMPANDER0_CTL3, 0x35 },
1031 { CDC_RX_COMPANDER0_CTL4, 0xFF },
1032 { CDC_RX_COMPANDER0_CTL5, 0x00 },
1033 { CDC_RX_COMPANDER0_CTL6, 0x01 },
1034 { CDC_RX_COMPANDER0_CTL7, 0x28 },
1035 { CDC_RX_COMPANDER1_CTL0, 0x60 },
1036 { CDC_RX_COMPANDER1_CTL1, 0xDB },
1037 { CDC_RX_COMPANDER1_CTL2, 0xFF },
1038 { CDC_RX_COMPANDER1_CTL3, 0x35 },
1039 { CDC_RX_COMPANDER1_CTL4, 0xFF },
1040 { CDC_RX_COMPANDER1_CTL5, 0x00 },
1041 { CDC_RX_COMPANDER1_CTL6, 0x01 },
1042 { CDC_RX_COMPANDER1_CTL7, 0x28 },
1043 { CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00 },
1044 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00 },
1045 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00 },
1046 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00 },
1047 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00 },
1048 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00 },
1049 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00 },
1050 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00 },
1051 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00 },
1052 { CDC_RX_SIDETONE_IIR0_IIR_CTL, 0x40 },
1053 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00 },
1054 { CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00 },
1055 { CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00 },
1056 { CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 0x00 },
1057 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00 },
1058 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00 },
1059 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00 },
1060 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00 },
1061 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00 },
1062 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00 },
1063 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00 },
1064 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00 },
1065 { CDC_RX_SIDETONE_IIR1_IIR_CTL, 0x40 },
1066 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00 },
1067 { CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00 },
1068 { CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00 },
1069 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00 },
1070 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00 },
1071 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00 },
1072 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00 },
1073 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00 },
1074 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00 },
1075 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00 },
1076 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00 },
1077 { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04 },
1078 { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00 },
1079 { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04 },
1080 { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00 },
1081 { CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL, 0x00 },
1082 { CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0, 0x01 },
1083 { CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL, 0x00 },
1084 { CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0, 0x01 },
1085 { CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL, 0x00 },
1086 { CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0, 0x01 },
1087 { CDC_RX_EC_ASRC0_CLK_RST_CTL, 0x00 },
1088 { CDC_RX_EC_ASRC0_CTL0, 0x00 },
1089 { CDC_RX_EC_ASRC0_CTL1, 0x00 },
1090 { CDC_RX_EC_ASRC0_FIFO_CTL, 0xA8 },
1091 { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00 },
1092 { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00 },
1093 { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00 },
1094 { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00 },
1095 { CDC_RX_EC_ASRC0_STATUS_FIFO, 0x00 },
1096 { CDC_RX_EC_ASRC1_CLK_RST_CTL, 0x00 },
1097 { CDC_RX_EC_ASRC1_CTL0, 0x00 },
1098 { CDC_RX_EC_ASRC1_CTL1, 0x00 },
1099 { CDC_RX_EC_ASRC1_FIFO_CTL, 0xA8 },
1100 { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00 },
1101 { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00 },
1102 { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00 },
1103 { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00 },
1104 { CDC_RX_EC_ASRC1_STATUS_FIFO, 0x00 },
1105 { CDC_RX_EC_ASRC2_CLK_RST_CTL, 0x00 },
1106 { CDC_RX_EC_ASRC2_CTL0, 0x00 },
1107 { CDC_RX_EC_ASRC2_CTL1, 0x00 },
1108 { CDC_RX_EC_ASRC2_FIFO_CTL, 0xA8 },
1109 { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB, 0x00 },
1110 { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB, 0x00 },
1111 { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB, 0x00 },
1112 { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB, 0x00 },
1113 { CDC_RX_EC_ASRC2_STATUS_FIFO, 0x00 },
1114 { CDC_RX_DSD0_PATH_CTL, 0x00 },
1115 { CDC_RX_DSD0_CFG0, 0x00 },
1116 { CDC_RX_DSD0_CFG1, 0x62 },
1117 { CDC_RX_DSD0_CFG2, 0x96 },
1118 { CDC_RX_DSD1_PATH_CTL, 0x00 },
1119 { CDC_RX_DSD1_CFG0, 0x00 },
1120 { CDC_RX_DSD1_CFG1, 0x62 },
1121 { CDC_RX_DSD1_CFG2, 0x96 },
1122};
1123
1124static bool rx_is_wronly_register(struct device *dev,
1125 unsigned int reg)
1126{
1127 switch (reg) {
1128 case CDC_RX_BCL_VBAT_GAIN_UPD_MON:
1129 case CDC_RX_INTR_CTRL_CLR_COMMIT:
1130 case CDC_RX_INTR_CTRL_PIN1_CLEAR0:
1131 case CDC_RX_INTR_CTRL_PIN2_CLEAR0:
1132 return true;
1133 }
1134
1135 return false;
1136}
1137
1138static bool rx_is_volatile_register(struct device *dev, unsigned int reg)
1139{
1140 /* Update volatile list for rx/tx macros */
1141 switch (reg) {
1142 case CDC_RX_TOP_HPHL_COMP_RD_LSB:
1143 case CDC_RX_TOP_HPHL_COMP_WR_LSB:
1144 case CDC_RX_TOP_HPHL_COMP_RD_MSB:
1145 case CDC_RX_TOP_HPHL_COMP_WR_MSB:
1146 case CDC_RX_TOP_HPHR_COMP_RD_LSB:
1147 case CDC_RX_TOP_HPHR_COMP_WR_LSB:
1148 case CDC_RX_TOP_HPHR_COMP_RD_MSB:
1149 case CDC_RX_TOP_HPHR_COMP_WR_MSB:
1150 case CDC_RX_TOP_DSD0_DEBUG_CFG2:
1151 case CDC_RX_TOP_DSD1_DEBUG_CFG2:
1152 case CDC_RX_BCL_VBAT_GAIN_MON_VAL:
1153 case CDC_RX_BCL_VBAT_DECODE_ST:
1154 case CDC_RX_INTR_CTRL_PIN1_STATUS0:
1155 case CDC_RX_INTR_CTRL_PIN2_STATUS0:
1156 case CDC_RX_COMPANDER0_CTL6:
1157 case CDC_RX_COMPANDER1_CTL6:
1158 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:
1159 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:
1160 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:
1161 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:
1162 case CDC_RX_EC_ASRC0_STATUS_FIFO:
1163 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:
1164 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:
1165 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:
1166 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:
1167 case CDC_RX_EC_ASRC1_STATUS_FIFO:
1168 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:
1169 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:
1170 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:
1171 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:
1172 case CDC_RX_EC_ASRC2_STATUS_FIFO:
1173 return true;
1174 }
1175 return false;
1176}
1177
1178static bool rx_is_rw_register(struct device *dev, unsigned int reg)
1179{
1180 switch (reg) {
1181 case CDC_RX_TOP_TOP_CFG0:
1182 case CDC_RX_TOP_SWR_CTRL:
1183 case CDC_RX_TOP_DEBUG:
1184 case CDC_RX_TOP_DEBUG_BUS:
1185 case CDC_RX_TOP_DEBUG_EN0:
1186 case CDC_RX_TOP_DEBUG_EN1:
1187 case CDC_RX_TOP_DEBUG_EN2:
1188 case CDC_RX_TOP_HPHL_COMP_WR_LSB:
1189 case CDC_RX_TOP_HPHL_COMP_WR_MSB:
1190 case CDC_RX_TOP_HPHL_COMP_LUT:
1191 case CDC_RX_TOP_HPHR_COMP_WR_LSB:
1192 case CDC_RX_TOP_HPHR_COMP_WR_MSB:
1193 case CDC_RX_TOP_HPHR_COMP_LUT:
1194 case CDC_RX_TOP_DSD0_DEBUG_CFG0:
1195 case CDC_RX_TOP_DSD0_DEBUG_CFG1:
1196 case CDC_RX_TOP_DSD0_DEBUG_CFG3:
1197 case CDC_RX_TOP_DSD1_DEBUG_CFG0:
1198 case CDC_RX_TOP_DSD1_DEBUG_CFG1:
1199 case CDC_RX_TOP_DSD1_DEBUG_CFG3:
1200 case CDC_RX_TOP_RX_I2S_CTL:
1201 case CDC_RX_TOP_TX_I2S2_CTL:
1202 case CDC_RX_TOP_I2S_CLK:
1203 case CDC_RX_TOP_I2S_RESET:
1204 case CDC_RX_TOP_I2S_MUX:
1205 case CDC_RX_CLK_RST_CTRL_MCLK_CONTROL:
1206 case CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL:
1207 case CDC_RX_CLK_RST_CTRL_SWR_CONTROL:
1208 case CDC_RX_CLK_RST_CTRL_DSD_CONTROL:
1209 case CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL:
1210 case CDC_RX_SOFTCLIP_CRC:
1211 case CDC_RX_SOFTCLIP_SOFTCLIP_CTRL:
1212 case CDC_RX_INP_MUX_RX_INT0_CFG0:
1213 case CDC_RX_INP_MUX_RX_INT0_CFG1:
1214 case CDC_RX_INP_MUX_RX_INT1_CFG0:
1215 case CDC_RX_INP_MUX_RX_INT1_CFG1:
1216 case CDC_RX_INP_MUX_RX_INT2_CFG0:
1217 case CDC_RX_INP_MUX_RX_INT2_CFG1:
1218 case CDC_RX_INP_MUX_RX_MIX_CFG4:
1219 case CDC_RX_INP_MUX_RX_MIX_CFG5:
1220 case CDC_RX_INP_MUX_SIDETONE_SRC_CFG0:
1221 case CDC_RX_CLSH_CRC:
1222 case CDC_RX_CLSH_DLY_CTRL:
1223 case CDC_RX_CLSH_DECAY_CTRL:
1224 case CDC_RX_CLSH_HPH_V_PA:
1225 case CDC_RX_CLSH_EAR_V_PA:
1226 case CDC_RX_CLSH_HPH_V_HD:
1227 case CDC_RX_CLSH_EAR_V_HD:
1228 case CDC_RX_CLSH_K1_MSB:
1229 case CDC_RX_CLSH_K1_LSB:
1230 case CDC_RX_CLSH_K2_MSB:
1231 case CDC_RX_CLSH_K2_LSB:
1232 case CDC_RX_CLSH_IDLE_CTRL:
1233 case CDC_RX_CLSH_IDLE_HPH:
1234 case CDC_RX_CLSH_IDLE_EAR:
1235 case CDC_RX_CLSH_TEST0:
1236 case CDC_RX_CLSH_TEST1:
1237 case CDC_RX_CLSH_OVR_VREF:
1238 case CDC_RX_CLSH_CLSG_CTL:
1239 case CDC_RX_CLSH_CLSG_CFG1:
1240 case CDC_RX_CLSH_CLSG_CFG2:
1241 case CDC_RX_BCL_VBAT_PATH_CTL:
1242 case CDC_RX_BCL_VBAT_CFG:
1243 case CDC_RX_BCL_VBAT_ADC_CAL1:
1244 case CDC_RX_BCL_VBAT_ADC_CAL2:
1245 case CDC_RX_BCL_VBAT_ADC_CAL3:
1246 case CDC_RX_BCL_VBAT_PK_EST1:
1247 case CDC_RX_BCL_VBAT_PK_EST2:
1248 case CDC_RX_BCL_VBAT_PK_EST3:
1249 case CDC_RX_BCL_VBAT_RF_PROC1:
1250 case CDC_RX_BCL_VBAT_RF_PROC2:
1251 case CDC_RX_BCL_VBAT_TAC1:
1252 case CDC_RX_BCL_VBAT_TAC2:
1253 case CDC_RX_BCL_VBAT_TAC3:
1254 case CDC_RX_BCL_VBAT_TAC4:
1255 case CDC_RX_BCL_VBAT_GAIN_UPD1:
1256 case CDC_RX_BCL_VBAT_GAIN_UPD2:
1257 case CDC_RX_BCL_VBAT_GAIN_UPD3:
1258 case CDC_RX_BCL_VBAT_GAIN_UPD4:
1259 case CDC_RX_BCL_VBAT_GAIN_UPD5:
1260 case CDC_RX_BCL_VBAT_DEBUG1:
1261 case CDC_RX_BCL_VBAT_BAN:
1262 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD1:
1263 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD2:
1264 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD3:
1265 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD4:
1266 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD5:
1267 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD6:
1268 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD7:
1269 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD8:
1270 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD9:
1271 case CDC_RX_BCL_VBAT_ATTN1:
1272 case CDC_RX_BCL_VBAT_ATTN2:
1273 case CDC_RX_BCL_VBAT_ATTN3:
1274 case CDC_RX_BCL_VBAT_DECODE_CTL1:
1275 case CDC_RX_BCL_VBAT_DECODE_CTL2:
1276 case CDC_RX_BCL_VBAT_DECODE_CFG1:
1277 case CDC_RX_BCL_VBAT_DECODE_CFG2:
1278 case CDC_RX_BCL_VBAT_DECODE_CFG3:
1279 case CDC_RX_BCL_VBAT_DECODE_CFG4:
1280 case CDC_RX_INTR_CTRL_CFG:
1281 case CDC_RX_INTR_CTRL_PIN1_MASK0:
1282 case CDC_RX_INTR_CTRL_PIN2_MASK0:
1283 case CDC_RX_INTR_CTRL_LEVEL0:
1284 case CDC_RX_INTR_CTRL_BYPASS0:
1285 case CDC_RX_INTR_CTRL_SET0:
1286 case CDC_RX_RX0_RX_PATH_CTL:
1287 case CDC_RX_RX0_RX_PATH_CFG0:
1288 case CDC_RX_RX0_RX_PATH_CFG1:
1289 case CDC_RX_RX0_RX_PATH_CFG2:
1290 case CDC_RX_RX0_RX_PATH_CFG3:
1291 case CDC_RX_RX0_RX_VOL_CTL:
1292 case CDC_RX_RX0_RX_PATH_MIX_CTL:
1293 case CDC_RX_RX0_RX_PATH_MIX_CFG:
1294 case CDC_RX_RX0_RX_VOL_MIX_CTL:
1295 case CDC_RX_RX0_RX_PATH_SEC1:
1296 case CDC_RX_RX0_RX_PATH_SEC2:
1297 case CDC_RX_RX0_RX_PATH_SEC3:
1298 case CDC_RX_RX0_RX_PATH_SEC4:
1299 case CDC_RX_RX0_RX_PATH_SEC7:
1300 case CDC_RX_RX0_RX_PATH_MIX_SEC0:
1301 case CDC_RX_RX0_RX_PATH_MIX_SEC1:
1302 case CDC_RX_RX0_RX_PATH_DSM_CTL:
1303 case CDC_RX_RX0_RX_PATH_DSM_DATA1:
1304 case CDC_RX_RX0_RX_PATH_DSM_DATA2:
1305 case CDC_RX_RX0_RX_PATH_DSM_DATA3:
1306 case CDC_RX_RX0_RX_PATH_DSM_DATA4:
1307 case CDC_RX_RX0_RX_PATH_DSM_DATA5:
1308 case CDC_RX_RX0_RX_PATH_DSM_DATA6:
1309 case CDC_RX_RX1_RX_PATH_CTL:
1310 case CDC_RX_RX1_RX_PATH_CFG0:
1311 case CDC_RX_RX1_RX_PATH_CFG1:
1312 case CDC_RX_RX1_RX_PATH_CFG2:
1313 case CDC_RX_RX1_RX_PATH_CFG3:
1314 case CDC_RX_RX1_RX_VOL_CTL:
1315 case CDC_RX_RX1_RX_PATH_MIX_CTL:
1316 case CDC_RX_RX1_RX_PATH_MIX_CFG:
1317 case CDC_RX_RX1_RX_VOL_MIX_CTL:
1318 case CDC_RX_RX1_RX_PATH_SEC1:
1319 case CDC_RX_RX1_RX_PATH_SEC2:
1320 case CDC_RX_RX1_RX_PATH_SEC3:
1321 case CDC_RX_RX1_RX_PATH_SEC4:
1322 case CDC_RX_RX1_RX_PATH_SEC7:
1323 case CDC_RX_RX1_RX_PATH_MIX_SEC0:
1324 case CDC_RX_RX1_RX_PATH_MIX_SEC1:
1325 case CDC_RX_RX1_RX_PATH_DSM_CTL:
1326 case CDC_RX_RX1_RX_PATH_DSM_DATA1:
1327 case CDC_RX_RX1_RX_PATH_DSM_DATA2:
1328 case CDC_RX_RX1_RX_PATH_DSM_DATA3:
1329 case CDC_RX_RX1_RX_PATH_DSM_DATA4:
1330 case CDC_RX_RX1_RX_PATH_DSM_DATA5:
1331 case CDC_RX_RX1_RX_PATH_DSM_DATA6:
1332 case CDC_RX_RX2_RX_PATH_CTL:
1333 case CDC_RX_RX2_RX_PATH_CFG0:
1334 case CDC_RX_RX2_RX_PATH_CFG1:
1335 case CDC_RX_RX2_RX_PATH_CFG2:
1336 case CDC_RX_RX2_RX_PATH_CFG3:
1337 case CDC_RX_RX2_RX_VOL_CTL:
1338 case CDC_RX_RX2_RX_PATH_MIX_CTL:
1339 case CDC_RX_RX2_RX_PATH_MIX_CFG:
1340 case CDC_RX_RX2_RX_VOL_MIX_CTL:
1341 case CDC_RX_RX2_RX_PATH_SEC0:
1342 case CDC_RX_RX2_RX_PATH_SEC1:
1343 case CDC_RX_RX2_RX_PATH_SEC2:
1344 case CDC_RX_RX2_RX_PATH_SEC3:
1345 case CDC_RX_RX2_RX_PATH_SEC4:
1346 case CDC_RX_RX2_RX_PATH_SEC5:
1347 case CDC_RX_RX2_RX_PATH_SEC6:
1348 case CDC_RX_RX2_RX_PATH_SEC7:
1349 case CDC_RX_RX2_RX_PATH_MIX_SEC0:
1350 case CDC_RX_RX2_RX_PATH_MIX_SEC1:
1351 case CDC_RX_RX2_RX_PATH_DSM_CTL:
1352 case CDC_RX_IDLE_DETECT_PATH_CTL:
1353 case CDC_RX_IDLE_DETECT_CFG0:
1354 case CDC_RX_IDLE_DETECT_CFG1:
1355 case CDC_RX_IDLE_DETECT_CFG2:
1356 case CDC_RX_IDLE_DETECT_CFG3:
1357 case CDC_RX_COMPANDER0_CTL0:
1358 case CDC_RX_COMPANDER0_CTL1:
1359 case CDC_RX_COMPANDER0_CTL2:
1360 case CDC_RX_COMPANDER0_CTL3:
1361 case CDC_RX_COMPANDER0_CTL4:
1362 case CDC_RX_COMPANDER0_CTL5:
1363 case CDC_RX_COMPANDER0_CTL7:
1364 case CDC_RX_COMPANDER1_CTL0:
1365 case CDC_RX_COMPANDER1_CTL1:
1366 case CDC_RX_COMPANDER1_CTL2:
1367 case CDC_RX_COMPANDER1_CTL3:
1368 case CDC_RX_COMPANDER1_CTL4:
1369 case CDC_RX_COMPANDER1_CTL5:
1370 case CDC_RX_COMPANDER1_CTL7:
1371 case CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL:
1372 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL:
1373 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL:
1374 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL:
1375 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL:
1376 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL:
1377 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL:
1378 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL:
1379 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL:
1380 case CDC_RX_SIDETONE_IIR0_IIR_CTL:
1381 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL:
1382 case CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL:
1383 case CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL:
1384 case CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL:
1385 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL:
1386 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL:
1387 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL:
1388 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL:
1389 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL:
1390 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL:
1391 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL:
1392 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL:
1393 case CDC_RX_SIDETONE_IIR1_IIR_CTL:
1394 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL:
1395 case CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL:
1396 case CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL:
1397 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0:
1398 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1:
1399 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2:
1400 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3:
1401 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0:
1402 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1:
1403 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2:
1404 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3:
1405 case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL:
1406 case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1:
1407 case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL:
1408 case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1:
1409 case CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL:
1410 case CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0:
1411 case CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL:
1412 case CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0:
1413 case CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL:
1414 case CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0:
1415 case CDC_RX_EC_ASRC0_CLK_RST_CTL:
1416 case CDC_RX_EC_ASRC0_CTL0:
1417 case CDC_RX_EC_ASRC0_CTL1:
1418 case CDC_RX_EC_ASRC0_FIFO_CTL:
1419 case CDC_RX_EC_ASRC1_CLK_RST_CTL:
1420 case CDC_RX_EC_ASRC1_CTL0:
1421 case CDC_RX_EC_ASRC1_CTL1:
1422 case CDC_RX_EC_ASRC1_FIFO_CTL:
1423 case CDC_RX_EC_ASRC2_CLK_RST_CTL:
1424 case CDC_RX_EC_ASRC2_CTL0:
1425 case CDC_RX_EC_ASRC2_CTL1:
1426 case CDC_RX_EC_ASRC2_FIFO_CTL:
1427 case CDC_RX_DSD0_PATH_CTL:
1428 case CDC_RX_DSD0_CFG0:
1429 case CDC_RX_DSD0_CFG1:
1430 case CDC_RX_DSD0_CFG2:
1431 case CDC_RX_DSD1_PATH_CTL:
1432 case CDC_RX_DSD1_CFG0:
1433 case CDC_RX_DSD1_CFG1:
1434 case CDC_RX_DSD1_CFG2:
1435 return true;
1436 }
1437
1438 return false;
1439}
1440
1441static bool rx_is_writeable_register(struct device *dev, unsigned int reg)
1442{
1443 bool ret;
1444
1445 ret = rx_is_rw_register(dev, reg);
1446 if (!ret)
1447 return rx_is_wronly_register(dev, reg);
1448
1449 return ret;
1450}
1451
1452static bool rx_is_readable_register(struct device *dev, unsigned int reg)
1453{
1454 switch (reg) {
1455 case CDC_RX_TOP_HPHL_COMP_RD_LSB:
1456 case CDC_RX_TOP_HPHL_COMP_RD_MSB:
1457 case CDC_RX_TOP_HPHR_COMP_RD_LSB:
1458 case CDC_RX_TOP_HPHR_COMP_RD_MSB:
1459 case CDC_RX_TOP_DSD0_DEBUG_CFG2:
1460 case CDC_RX_TOP_DSD1_DEBUG_CFG2:
1461 case CDC_RX_BCL_VBAT_GAIN_MON_VAL:
1462 case CDC_RX_BCL_VBAT_DECODE_ST:
1463 case CDC_RX_INTR_CTRL_PIN1_STATUS0:
1464 case CDC_RX_INTR_CTRL_PIN2_STATUS0:
1465 case CDC_RX_COMPANDER0_CTL6:
1466 case CDC_RX_COMPANDER1_CTL6:
1467 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:
1468 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:
1469 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:
1470 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:
1471 case CDC_RX_EC_ASRC0_STATUS_FIFO:
1472 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:
1473 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:
1474 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:
1475 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:
1476 case CDC_RX_EC_ASRC1_STATUS_FIFO:
1477 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:
1478 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:
1479 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:
1480 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:
1481 case CDC_RX_EC_ASRC2_STATUS_FIFO:
1482 return true;
1483 }
1484
1485 return rx_is_rw_register(dev, reg);
1486}
1487
1488static const struct regmap_config rx_regmap_config = {
1489 .name = "rx_macro",
1490 .reg_bits = 16,
1491 .val_bits = 32, /* 8 but with 32 bit read/write */
1492 .reg_stride = 4,
1493 .cache_type = REGCACHE_FLAT,
1494 .reg_defaults = rx_defaults,
1495 .num_reg_defaults = ARRAY_SIZE(rx_defaults),
1496 .max_register = RX_MAX_OFFSET,
1497 .writeable_reg = rx_is_writeable_register,
1498 .volatile_reg = rx_is_volatile_register,
1499 .readable_reg = rx_is_readable_register,
1500};
1501
1502static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol,
1503 struct snd_ctl_elem_value *ucontrol)
1504{
1505 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
1506 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: widget->dapm);
1507 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1508 unsigned short look_ahead_dly_reg;
1509 unsigned int val;
1510
1511 val = ucontrol->value.enumerated.item[0];
1512
1513 if (e->reg == CDC_RX_RX0_RX_PATH_CFG1)
1514 look_ahead_dly_reg = CDC_RX_RX0_RX_PATH_CFG0;
1515 else if (e->reg == CDC_RX_RX1_RX_PATH_CFG1)
1516 look_ahead_dly_reg = CDC_RX_RX1_RX_PATH_CFG0;
1517
1518 /* Set Look Ahead Delay */
1519 if (val)
1520 snd_soc_component_update_bits(component, reg: look_ahead_dly_reg,
1521 CDC_RX_DLY_ZN_EN_MASK,
1522 CDC_RX_DLY_ZN_ENABLE);
1523 else
1524 snd_soc_component_update_bits(component, reg: look_ahead_dly_reg,
1525 CDC_RX_DLY_ZN_EN_MASK, val: 0);
1526 /* Set DEM INP Select */
1527 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1528}
1529
1530static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
1531 SOC_DAPM_ENUM_EXT("rx_int0_dem_inp", rx_int0_dem_inp_enum,
1532 snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
1533static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
1534 SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_int1_dem_inp_enum,
1535 snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
1536
1537static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1538 int rate_reg_val, u32 sample_rate)
1539{
1540
1541 u8 int_1_mix1_inp;
1542 u32 j, port;
1543 u16 int_mux_cfg0, int_mux_cfg1;
1544 u16 int_fs_reg;
1545 u8 inp0_sel, inp1_sel, inp2_sel;
1546 struct snd_soc_component *component = dai->component;
1547 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
1548
1549 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) {
1550 int_1_mix1_inp = port;
1551 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0;
1552 /*
1553 * Loop through all interpolator MUX inputs and find out
1554 * to which interpolator input, the rx port
1555 * is connected
1556 */
1557 for (j = 0; j < INTERP_MAX; j++) {
1558 int_mux_cfg1 = int_mux_cfg0 + 4;
1559
1560 inp0_sel = snd_soc_component_read_field(component, reg: int_mux_cfg0,
1561 CDC_RX_INTX_1_MIX_INP0_SEL_MASK);
1562 inp1_sel = snd_soc_component_read_field(component, reg: int_mux_cfg0,
1563 CDC_RX_INTX_1_MIX_INP1_SEL_MASK);
1564 inp2_sel = snd_soc_component_read_field(component, reg: int_mux_cfg1,
1565 CDC_RX_INTX_1_MIX_INP2_SEL_MASK);
1566
1567 if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
1568 (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
1569 (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
1570 int_fs_reg = CDC_RX_RXn_RX_PATH_CTL(j);
1571 /* sample_rate is in Hz */
1572 snd_soc_component_update_bits(component, reg: int_fs_reg,
1573 CDC_RX_PATH_PCM_RATE_MASK,
1574 val: rate_reg_val);
1575 }
1576 int_mux_cfg0 += 8;
1577 }
1578 }
1579
1580 return 0;
1581}
1582
1583static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1584 int rate_reg_val, u32 sample_rate)
1585{
1586
1587 u8 int_2_inp;
1588 u32 j, port;
1589 u16 int_mux_cfg1, int_fs_reg;
1590 u8 int_mux_cfg1_val;
1591 struct snd_soc_component *component = dai->component;
1592 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
1593
1594 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) {
1595 int_2_inp = port;
1596
1597 int_mux_cfg1 = CDC_RX_INP_MUX_RX_INT0_CFG1;
1598 for (j = 0; j < INTERP_MAX; j++) {
1599 int_mux_cfg1_val = snd_soc_component_read_field(component, reg: int_mux_cfg1,
1600 CDC_RX_INTX_2_SEL_MASK);
1601
1602 if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {
1603 int_fs_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);
1604 snd_soc_component_update_bits(component, reg: int_fs_reg,
1605 CDC_RX_RXn_MIX_PCM_RATE_MASK,
1606 val: rate_reg_val);
1607 }
1608 int_mux_cfg1 += 8;
1609 }
1610 }
1611 return 0;
1612}
1613
1614static int rx_macro_set_interpolator_rate(struct snd_soc_dai *dai,
1615 u32 sample_rate)
1616{
1617 int rate_val = 0;
1618 int i, ret;
1619
1620 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++)
1621 if (sample_rate == sr_val_tbl[i].sample_rate)
1622 rate_val = sr_val_tbl[i].rate_val;
1623
1624 ret = rx_macro_set_prim_interpolator_rate(dai, rate_reg_val: rate_val, sample_rate);
1625 if (ret)
1626 return ret;
1627
1628 ret = rx_macro_set_mix_interpolator_rate(dai, rate_reg_val: rate_val, sample_rate);
1629
1630 return ret;
1631}
1632
1633static int rx_macro_hw_params(struct snd_pcm_substream *substream,
1634 struct snd_pcm_hw_params *params,
1635 struct snd_soc_dai *dai)
1636{
1637 struct snd_soc_component *component = dai->component;
1638 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
1639 int ret;
1640
1641 switch (substream->stream) {
1642 case SNDRV_PCM_STREAM_PLAYBACK:
1643 ret = rx_macro_set_interpolator_rate(dai, sample_rate: params_rate(p: params));
1644 if (ret) {
1645 dev_err(component->dev, "%s: cannot set sample rate: %u\n",
1646 __func__, params_rate(params));
1647 return ret;
1648 }
1649 rx->bit_width[dai->id] = params_width(p: params);
1650 break;
1651 default:
1652 break;
1653 }
1654 return 0;
1655}
1656
1657static int rx_macro_get_channel_map(struct snd_soc_dai *dai,
1658 unsigned int *tx_num, unsigned int *tx_slot,
1659 unsigned int *rx_num, unsigned int *rx_slot)
1660{
1661 struct snd_soc_component *component = dai->component;
1662 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
1663 u16 val, mask = 0, cnt = 0, temp;
1664
1665 switch (dai->id) {
1666 case RX_MACRO_AIF1_PB:
1667 case RX_MACRO_AIF2_PB:
1668 case RX_MACRO_AIF3_PB:
1669 case RX_MACRO_AIF4_PB:
1670 for_each_set_bit(temp, &rx->active_ch_mask[dai->id],
1671 RX_MACRO_PORTS_MAX) {
1672 mask |= (1 << temp);
1673 if (++cnt == RX_MACRO_MAX_DMA_CH_PER_PORT)
1674 break;
1675 }
1676 /*
1677 * CDC_DMA_RX_0 port drives RX0/RX1 -- ch_mask 0x1/0x2/0x3
1678 * CDC_DMA_RX_1 port drives RX2/RX3 -- ch_mask 0x1/0x2/0x3
1679 * CDC_DMA_RX_2 port drives RX4 -- ch_mask 0x1
1680 * CDC_DMA_RX_3 port drives RX5 -- ch_mask 0x1
1681 * AIFn can pair to any CDC_DMA_RX_n port.
1682 * In general, below convention is used::
1683 * CDC_DMA_RX_0(AIF1)/CDC_DMA_RX_1(AIF2)/
1684 * CDC_DMA_RX_2(AIF3)/CDC_DMA_RX_3(AIF4)
1685 */
1686 if (mask & 0x0C)
1687 mask = mask >> 2;
1688 if ((mask & 0x10) || (mask & 0x20))
1689 mask = 0x1;
1690 *rx_slot = mask;
1691 *rx_num = rx->active_ch_cnt[dai->id];
1692 break;
1693 case RX_MACRO_AIF_ECHO:
1694 val = snd_soc_component_read(component, CDC_RX_INP_MUX_RX_MIX_CFG4);
1695 if (val & RX_MACRO_EC_MIX_TX0_MASK) {
1696 mask |= 0x1;
1697 cnt++;
1698 }
1699 if (val & RX_MACRO_EC_MIX_TX1_MASK) {
1700 mask |= 0x2;
1701 cnt++;
1702 }
1703 val = snd_soc_component_read(component,
1704 CDC_RX_INP_MUX_RX_MIX_CFG5);
1705 if (val & RX_MACRO_EC_MIX_TX2_MASK) {
1706 mask |= 0x4;
1707 cnt++;
1708 }
1709 *tx_slot = mask;
1710 *tx_num = cnt;
1711 break;
1712 default:
1713 dev_err(component->dev, "%s: Invalid AIF\n", __func__);
1714 break;
1715 }
1716 return 0;
1717}
1718
1719static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1720{
1721 struct snd_soc_component *component = dai->component;
1722 uint16_t j, reg, mix_reg, dsm_reg;
1723 u16 int_mux_cfg0, int_mux_cfg1;
1724 u8 int_mux_cfg0_val, int_mux_cfg1_val;
1725
1726 switch (dai->id) {
1727 case RX_MACRO_AIF1_PB:
1728 case RX_MACRO_AIF2_PB:
1729 case RX_MACRO_AIF3_PB:
1730 case RX_MACRO_AIF4_PB:
1731 for (j = 0; j < INTERP_MAX; j++) {
1732 reg = CDC_RX_RXn_RX_PATH_CTL(j);
1733 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);
1734 dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(j);
1735
1736 if (mute) {
1737 snd_soc_component_update_bits(component, reg,
1738 CDC_RX_PATH_PGA_MUTE_MASK,
1739 CDC_RX_PATH_PGA_MUTE_ENABLE);
1740 snd_soc_component_update_bits(component, reg: mix_reg,
1741 CDC_RX_PATH_PGA_MUTE_MASK,
1742 CDC_RX_PATH_PGA_MUTE_ENABLE);
1743 } else {
1744 snd_soc_component_update_bits(component, reg,
1745 CDC_RX_PATH_PGA_MUTE_MASK, val: 0x0);
1746 snd_soc_component_update_bits(component, reg: mix_reg,
1747 CDC_RX_PATH_PGA_MUTE_MASK, val: 0x0);
1748 }
1749
1750 if (j == INTERP_AUX)
1751 dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
1752
1753 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8;
1754 int_mux_cfg1 = int_mux_cfg0 + 4;
1755 int_mux_cfg0_val = snd_soc_component_read(component, reg: int_mux_cfg0);
1756 int_mux_cfg1_val = snd_soc_component_read(component, reg: int_mux_cfg1);
1757
1758 if (snd_soc_component_read(component, reg: dsm_reg) & 0x01) {
1759 if (int_mux_cfg0_val || (int_mux_cfg1_val & 0xF0))
1760 snd_soc_component_update_bits(component, reg, mask: 0x20, val: 0x20);
1761 if (int_mux_cfg1_val & 0x0F) {
1762 snd_soc_component_update_bits(component, reg, mask: 0x20, val: 0x20);
1763 snd_soc_component_update_bits(component, reg: mix_reg, mask: 0x20,
1764 val: 0x20);
1765 }
1766 }
1767 }
1768 break;
1769 default:
1770 break;
1771 }
1772 return 0;
1773}
1774
1775static const struct snd_soc_dai_ops rx_macro_dai_ops = {
1776 .hw_params = rx_macro_hw_params,
1777 .get_channel_map = rx_macro_get_channel_map,
1778 .mute_stream = rx_macro_digital_mute,
1779};
1780
1781static struct snd_soc_dai_driver rx_macro_dai[] = {
1782 {
1783 .name = "rx_macro_rx1",
1784 .id = RX_MACRO_AIF1_PB,
1785 .playback = {
1786 .stream_name = "RX_MACRO_AIF1 Playback",
1787 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1788 .formats = RX_MACRO_FORMATS,
1789 .rate_max = 384000,
1790 .rate_min = 8000,
1791 .channels_min = 1,
1792 .channels_max = 2,
1793 },
1794 .ops = &rx_macro_dai_ops,
1795 },
1796 {
1797 .name = "rx_macro_rx2",
1798 .id = RX_MACRO_AIF2_PB,
1799 .playback = {
1800 .stream_name = "RX_MACRO_AIF2 Playback",
1801 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1802 .formats = RX_MACRO_FORMATS,
1803 .rate_max = 384000,
1804 .rate_min = 8000,
1805 .channels_min = 1,
1806 .channels_max = 2,
1807 },
1808 .ops = &rx_macro_dai_ops,
1809 },
1810 {
1811 .name = "rx_macro_rx3",
1812 .id = RX_MACRO_AIF3_PB,
1813 .playback = {
1814 .stream_name = "RX_MACRO_AIF3 Playback",
1815 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1816 .formats = RX_MACRO_FORMATS,
1817 .rate_max = 384000,
1818 .rate_min = 8000,
1819 .channels_min = 1,
1820 .channels_max = 2,
1821 },
1822 .ops = &rx_macro_dai_ops,
1823 },
1824 {
1825 .name = "rx_macro_rx4",
1826 .id = RX_MACRO_AIF4_PB,
1827 .playback = {
1828 .stream_name = "RX_MACRO_AIF4 Playback",
1829 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1830 .formats = RX_MACRO_FORMATS,
1831 .rate_max = 384000,
1832 .rate_min = 8000,
1833 .channels_min = 1,
1834 .channels_max = 2,
1835 },
1836 .ops = &rx_macro_dai_ops,
1837 },
1838 {
1839 .name = "rx_macro_echo",
1840 .id = RX_MACRO_AIF_ECHO,
1841 .capture = {
1842 .stream_name = "RX_AIF_ECHO Capture",
1843 .rates = RX_MACRO_ECHO_RATES,
1844 .formats = RX_MACRO_ECHO_FORMATS,
1845 .rate_max = 48000,
1846 .rate_min = 8000,
1847 .channels_min = 1,
1848 .channels_max = 3,
1849 },
1850 .ops = &rx_macro_dai_ops,
1851 },
1852};
1853
1854static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable)
1855{
1856 struct regmap *regmap = rx->regmap;
1857
1858 if (mclk_enable) {
1859 if (rx->rx_mclk_users == 0) {
1860 regmap_update_bits(map: regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL,
1861 CDC_RX_CLK_MCLK_EN_MASK |
1862 CDC_RX_CLK_MCLK2_EN_MASK,
1863 CDC_RX_CLK_MCLK_ENABLE |
1864 CDC_RX_CLK_MCLK2_ENABLE);
1865 regmap_update_bits(map: regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1866 CDC_RX_FS_MCLK_CNT_CLR_MASK, val: 0x00);
1867 regmap_update_bits(map: regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1868 CDC_RX_FS_MCLK_CNT_EN_MASK,
1869 CDC_RX_FS_MCLK_CNT_ENABLE);
1870 regcache_mark_dirty(map: regmap);
1871 regcache_sync(map: regmap);
1872 }
1873 rx->rx_mclk_users++;
1874 } else {
1875 if (rx->rx_mclk_users <= 0) {
1876 dev_err(rx->dev, "%s: clock already disabled\n", __func__);
1877 rx->rx_mclk_users = 0;
1878 return;
1879 }
1880 rx->rx_mclk_users--;
1881 if (rx->rx_mclk_users == 0) {
1882 regmap_update_bits(map: regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1883 CDC_RX_FS_MCLK_CNT_EN_MASK, val: 0x0);
1884 regmap_update_bits(map: regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1885 CDC_RX_FS_MCLK_CNT_CLR_MASK,
1886 CDC_RX_FS_MCLK_CNT_CLR);
1887 regmap_update_bits(map: regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL,
1888 CDC_RX_CLK_MCLK_EN_MASK |
1889 CDC_RX_CLK_MCLK2_EN_MASK, val: 0x0);
1890 }
1891 }
1892}
1893
1894static int rx_macro_mclk_event(struct snd_soc_dapm_widget *w,
1895 struct snd_kcontrol *kcontrol, int event)
1896{
1897 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1898 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
1899 int ret = 0;
1900
1901 switch (event) {
1902 case SND_SOC_DAPM_PRE_PMU:
1903 rx_macro_mclk_enable(rx, mclk_enable: true);
1904 break;
1905 case SND_SOC_DAPM_POST_PMD:
1906 rx_macro_mclk_enable(rx, mclk_enable: false);
1907 break;
1908 default:
1909 dev_err(component->dev, "%s: invalid DAPM event %d\n", __func__, event);
1910 ret = -EINVAL;
1911 }
1912 return ret;
1913}
1914
1915static bool rx_macro_adie_lb(struct snd_soc_component *component,
1916 int interp_idx)
1917{
1918 u16 int_mux_cfg0, int_mux_cfg1;
1919 u8 int_n_inp0, int_n_inp1, int_n_inp2;
1920
1921 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
1922 int_mux_cfg1 = int_mux_cfg0 + 4;
1923
1924 int_n_inp0 = snd_soc_component_read_field(component, reg: int_mux_cfg0,
1925 CDC_RX_INTX_1_MIX_INP0_SEL_MASK);
1926 int_n_inp1 = snd_soc_component_read_field(component, reg: int_mux_cfg0,
1927 CDC_RX_INTX_1_MIX_INP1_SEL_MASK);
1928 int_n_inp2 = snd_soc_component_read_field(component, reg: int_mux_cfg1,
1929 CDC_RX_INTX_1_MIX_INP2_SEL_MASK);
1930
1931 if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
1932 int_n_inp0 == INTn_1_INP_SEL_DEC1 ||
1933 int_n_inp0 == INTn_1_INP_SEL_IIR0 ||
1934 int_n_inp0 == INTn_1_INP_SEL_IIR1)
1935 return true;
1936
1937 if (int_n_inp1 == INTn_1_INP_SEL_DEC0 ||
1938 int_n_inp1 == INTn_1_INP_SEL_DEC1 ||
1939 int_n_inp1 == INTn_1_INP_SEL_IIR0 ||
1940 int_n_inp1 == INTn_1_INP_SEL_IIR1)
1941 return true;
1942
1943 if (int_n_inp2 == INTn_1_INP_SEL_DEC0 ||
1944 int_n_inp2 == INTn_1_INP_SEL_DEC1 ||
1945 int_n_inp2 == INTn_1_INP_SEL_IIR0 ||
1946 int_n_inp2 == INTn_1_INP_SEL_IIR1)
1947 return true;
1948
1949 return false;
1950}
1951
1952static int rx_macro_enable_interp_clk(struct snd_soc_component *component,
1953 int event, int interp_idx);
1954static int rx_macro_enable_main_path(struct snd_soc_dapm_widget *w,
1955 struct snd_kcontrol *kcontrol,
1956 int event)
1957{
1958 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
1959 u16 gain_reg, reg;
1960
1961 reg = CDC_RX_RXn_RX_PATH_CTL(w->shift);
1962 gain_reg = CDC_RX_RXn_RX_VOL_CTL(w->shift);
1963
1964 switch (event) {
1965 case SND_SOC_DAPM_PRE_PMU:
1966 rx_macro_enable_interp_clk(component, event, interp_idx: w->shift);
1967 if (rx_macro_adie_lb(component, interp_idx: w->shift))
1968 snd_soc_component_update_bits(component, reg,
1969 CDC_RX_PATH_CLK_EN_MASK,
1970 CDC_RX_PATH_CLK_ENABLE);
1971 break;
1972 case SND_SOC_DAPM_POST_PMU:
1973 snd_soc_component_write(component, reg: gain_reg,
1974 val: snd_soc_component_read(component, reg: gain_reg));
1975 break;
1976 case SND_SOC_DAPM_POST_PMD:
1977 rx_macro_enable_interp_clk(component, event, interp_idx: w->shift);
1978 break;
1979 }
1980
1981 return 0;
1982}
1983
1984static int rx_macro_config_compander(struct snd_soc_component *component,
1985 struct rx_macro *rx,
1986 int comp, int event)
1987{
1988 u8 pcm_rate, val;
1989
1990 /* AUX does not have compander */
1991 if (comp == INTERP_AUX)
1992 return 0;
1993
1994 pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(comp)) & 0x0F;
1995 if (pcm_rate < 0x06)
1996 val = 0x03;
1997 else if (pcm_rate < 0x08)
1998 val = 0x01;
1999 else if (pcm_rate < 0x0B)
2000 val = 0x02;
2001 else
2002 val = 0x00;
2003
2004 if (SND_SOC_DAPM_EVENT_ON(event))
2005 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp),
2006 CDC_RX_DC_COEFF_SEL_MASK, val);
2007
2008 if (SND_SOC_DAPM_EVENT_OFF(event))
2009 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp),
2010 CDC_RX_DC_COEFF_SEL_MASK, val: 0x3);
2011 if (!rx->comp_enabled[comp])
2012 return 0;
2013
2014 if (SND_SOC_DAPM_EVENT_ON(event)) {
2015 /* Enable Compander Clock */
2016 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2017 CDC_RX_COMPANDERn_CLK_EN_MASK, val: 0x1);
2018 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2019 CDC_RX_COMPANDERn_SOFT_RST_MASK, val: 0x1);
2020 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2021 CDC_RX_COMPANDERn_SOFT_RST_MASK, val: 0x0);
2022 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp),
2023 CDC_RX_RXn_COMP_EN_MASK, val: 0x1);
2024 }
2025
2026 if (SND_SOC_DAPM_EVENT_OFF(event)) {
2027 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2028 CDC_RX_COMPANDERn_HALT_MASK, val: 0x1);
2029 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp),
2030 CDC_RX_RXn_COMP_EN_MASK, val: 0x0);
2031 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2032 CDC_RX_COMPANDERn_CLK_EN_MASK, val: 0x0);
2033 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2034 CDC_RX_COMPANDERn_HALT_MASK, val: 0x0);
2035 }
2036
2037 return 0;
2038}
2039
2040static int rx_macro_load_compander_coeff(struct snd_soc_component *component,
2041 struct rx_macro *rx,
2042 int comp, int event)
2043{
2044 u16 comp_coeff_lsb_reg, comp_coeff_msb_reg;
2045 int i;
2046 int hph_pwr_mode;
2047
2048 /* AUX does not have compander */
2049 if (comp == INTERP_AUX)
2050 return 0;
2051
2052 if (!rx->comp_enabled[comp])
2053 return 0;
2054
2055 if (comp == INTERP_HPHL) {
2056 comp_coeff_lsb_reg = CDC_RX_TOP_HPHL_COMP_WR_LSB;
2057 comp_coeff_msb_reg = CDC_RX_TOP_HPHL_COMP_WR_MSB;
2058 } else if (comp == INTERP_HPHR) {
2059 comp_coeff_lsb_reg = CDC_RX_TOP_HPHR_COMP_WR_LSB;
2060 comp_coeff_msb_reg = CDC_RX_TOP_HPHR_COMP_WR_MSB;
2061 } else {
2062 /* compander coefficients are loaded only for hph path */
2063 return 0;
2064 }
2065
2066 hph_pwr_mode = rx->hph_pwr_mode;
2067
2068 if (SND_SOC_DAPM_EVENT_ON(event)) {
2069 /* Load Compander Coeff */
2070 for (i = 0; i < COMP_MAX_COEFF; i++) {
2071 snd_soc_component_write(component, reg: comp_coeff_lsb_reg,
2072 val: comp_coeff_table[hph_pwr_mode][i].lsb);
2073 snd_soc_component_write(component, reg: comp_coeff_msb_reg,
2074 val: comp_coeff_table[hph_pwr_mode][i].msb);
2075 }
2076 }
2077
2078 return 0;
2079}
2080
2081static void rx_macro_enable_softclip_clk(struct snd_soc_component *component,
2082 struct rx_macro *rx, bool enable)
2083{
2084 if (enable) {
2085 if (rx->softclip_clk_users == 0)
2086 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC,
2087 CDC_RX_SOFTCLIP_CLK_EN_MASK, val: 1);
2088 rx->softclip_clk_users++;
2089 } else {
2090 rx->softclip_clk_users--;
2091 if (rx->softclip_clk_users == 0)
2092 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC,
2093 CDC_RX_SOFTCLIP_CLK_EN_MASK, val: 0);
2094 }
2095}
2096
2097static int rx_macro_config_softclip(struct snd_soc_component *component,
2098 struct rx_macro *rx, int event)
2099{
2100
2101 if (!rx->is_softclip_on)
2102 return 0;
2103
2104 if (SND_SOC_DAPM_EVENT_ON(event)) {
2105 /* Enable Softclip clock */
2106 rx_macro_enable_softclip_clk(component, rx, enable: true);
2107 /* Enable Softclip control */
2108 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL,
2109 CDC_RX_SOFTCLIP_EN_MASK, val: 0x01);
2110 }
2111
2112 if (SND_SOC_DAPM_EVENT_OFF(event)) {
2113 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL,
2114 CDC_RX_SOFTCLIP_EN_MASK, val: 0x0);
2115 rx_macro_enable_softclip_clk(component, rx, enable: false);
2116 }
2117
2118 return 0;
2119}
2120
2121static int rx_macro_config_aux_hpf(struct snd_soc_component *component,
2122 struct rx_macro *rx, int event)
2123{
2124 if (SND_SOC_DAPM_EVENT_ON(event)) {
2125 /* Update Aux HPF control */
2126 if (!rx->is_aux_hpf_on)
2127 snd_soc_component_update_bits(component,
2128 CDC_RX_RX2_RX_PATH_CFG1, mask: 0x04, val: 0x00);
2129 }
2130
2131 if (SND_SOC_DAPM_EVENT_OFF(event)) {
2132 /* Reset to default (HPF=ON) */
2133 snd_soc_component_update_bits(component,
2134 CDC_RX_RX2_RX_PATH_CFG1, mask: 0x04, val: 0x04);
2135 }
2136
2137 return 0;
2138}
2139
2140static inline void rx_macro_enable_clsh_block(struct rx_macro *rx, bool enable)
2141{
2142 if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0))
2143 snd_soc_component_update_bits(component: rx->component, CDC_RX_CLSH_CRC,
2144 CDC_RX_CLSH_CLK_EN_MASK, val: enable);
2145 if (rx->clsh_users < 0)
2146 rx->clsh_users = 0;
2147}
2148
2149static int rx_macro_config_classh(struct snd_soc_component *component,
2150 struct rx_macro *rx,
2151 int interp_n, int event)
2152{
2153 if (SND_SOC_DAPM_EVENT_OFF(event)) {
2154 rx_macro_enable_clsh_block(rx, enable: false);
2155 return 0;
2156 }
2157
2158 if (!SND_SOC_DAPM_EVENT_ON(event))
2159 return 0;
2160
2161 rx_macro_enable_clsh_block(rx, enable: true);
2162 if (interp_n == INTERP_HPHL ||
2163 interp_n == INTERP_HPHR) {
2164 /*
2165 * These K1 values depend on the Headphone Impedance
2166 * For now it is assumed to be 16 ohm
2167 */
2168 snd_soc_component_write(component, CDC_RX_CLSH_K1_LSB, val: 0xc0);
2169 snd_soc_component_write_field(component, CDC_RX_CLSH_K1_MSB,
2170 CDC_RX_CLSH_K1_MSB_COEFF_MASK, val: 0);
2171 }
2172 switch (interp_n) {
2173 case INTERP_HPHL:
2174 if (rx->is_ear_mode_on)
2175 snd_soc_component_update_bits(component,
2176 CDC_RX_CLSH_HPH_V_PA,
2177 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, val: 0x39);
2178 else
2179 snd_soc_component_update_bits(component,
2180 CDC_RX_CLSH_HPH_V_PA,
2181 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, val: 0x1c);
2182 snd_soc_component_update_bits(component,
2183 CDC_RX_CLSH_DECAY_CTRL,
2184 CDC_RX_CLSH_DECAY_RATE_MASK, val: 0x0);
2185 snd_soc_component_write_field(component,
2186 CDC_RX_RX0_RX_PATH_CFG0,
2187 CDC_RX_RXn_CLSH_EN_MASK, val: 0x1);
2188 break;
2189 case INTERP_HPHR:
2190 if (rx->is_ear_mode_on)
2191 snd_soc_component_update_bits(component,
2192 CDC_RX_CLSH_HPH_V_PA,
2193 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, val: 0x39);
2194 else
2195 snd_soc_component_update_bits(component,
2196 CDC_RX_CLSH_HPH_V_PA,
2197 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, val: 0x1c);
2198 snd_soc_component_update_bits(component,
2199 CDC_RX_CLSH_DECAY_CTRL,
2200 CDC_RX_CLSH_DECAY_RATE_MASK, val: 0x0);
2201 snd_soc_component_write_field(component,
2202 CDC_RX_RX1_RX_PATH_CFG0,
2203 CDC_RX_RXn_CLSH_EN_MASK, val: 0x1);
2204 break;
2205 case INTERP_AUX:
2206 snd_soc_component_update_bits(component,
2207 CDC_RX_RX2_RX_PATH_CFG0,
2208 CDC_RX_RX2_DLY_Z_EN_MASK, val: 1);
2209 snd_soc_component_write_field(component,
2210 CDC_RX_RX2_RX_PATH_CFG0,
2211 CDC_RX_RX2_CLSH_EN_MASK, val: 1);
2212 break;
2213 }
2214
2215 return 0;
2216}
2217
2218static void rx_macro_hd2_control(struct snd_soc_component *component,
2219 u16 interp_idx, int event)
2220{
2221 u16 hd2_scale_reg, hd2_enable_reg;
2222
2223 switch (interp_idx) {
2224 case INTERP_HPHL:
2225 hd2_scale_reg = CDC_RX_RX0_RX_PATH_SEC3;
2226 hd2_enable_reg = CDC_RX_RX0_RX_PATH_CFG0;
2227 break;
2228 case INTERP_HPHR:
2229 hd2_scale_reg = CDC_RX_RX1_RX_PATH_SEC3;
2230 hd2_enable_reg = CDC_RX_RX1_RX_PATH_CFG0;
2231 break;
2232 }
2233
2234 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
2235 snd_soc_component_update_bits(component, reg: hd2_scale_reg,
2236 CDC_RX_RXn_HD2_ALPHA_MASK, val: 0x14);
2237 snd_soc_component_write_field(component, reg: hd2_enable_reg,
2238 CDC_RX_RXn_HD2_EN_MASK, val: 1);
2239 }
2240
2241 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
2242 snd_soc_component_write_field(component, reg: hd2_enable_reg,
2243 CDC_RX_RXn_HD2_EN_MASK, val: 0);
2244 snd_soc_component_update_bits(component, reg: hd2_scale_reg,
2245 CDC_RX_RXn_HD2_ALPHA_MASK, val: 0x0);
2246 }
2247}
2248
2249static int rx_macro_get_compander(struct snd_kcontrol *kcontrol,
2250 struct snd_ctl_elem_value *ucontrol)
2251{
2252 struct snd_soc_component *component =
2253 snd_soc_kcontrol_component(kcontrol);
2254 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2255 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
2256
2257 ucontrol->value.integer.value[0] = rx->comp_enabled[comp];
2258 return 0;
2259}
2260
2261static int rx_macro_set_compander(struct snd_kcontrol *kcontrol,
2262 struct snd_ctl_elem_value *ucontrol)
2263{
2264 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2265 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2266 int value = ucontrol->value.integer.value[0];
2267 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
2268
2269 rx->comp_enabled[comp] = value;
2270
2271 return 0;
2272}
2273
2274static int rx_macro_mux_get(struct snd_kcontrol *kcontrol,
2275 struct snd_ctl_elem_value *ucontrol)
2276{
2277 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
2278 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: widget->dapm);
2279 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
2280
2281 ucontrol->value.enumerated.item[0] =
2282 rx->rx_port_value[widget->shift];
2283 return 0;
2284}
2285
2286static int rx_macro_mux_put(struct snd_kcontrol *kcontrol,
2287 struct snd_ctl_elem_value *ucontrol)
2288{
2289 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
2290 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: widget->dapm);
2291 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2292 struct snd_soc_dapm_update *update = NULL;
2293 u32 rx_port_value = ucontrol->value.enumerated.item[0];
2294 u32 aif_rst;
2295 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
2296
2297 aif_rst = rx->rx_port_value[widget->shift];
2298 if (!rx_port_value) {
2299 if (aif_rst == 0)
2300 return 0;
2301 if (aif_rst > RX_MACRO_AIF4_PB) {
2302 dev_err(component->dev, "%s: Invalid AIF reset\n", __func__);
2303 return 0;
2304 }
2305 }
2306 rx->rx_port_value[widget->shift] = rx_port_value;
2307
2308 switch (rx_port_value) {
2309 case 0:
2310 if (rx->active_ch_cnt[aif_rst]) {
2311 clear_bit(nr: widget->shift,
2312 addr: &rx->active_ch_mask[aif_rst]);
2313 rx->active_ch_cnt[aif_rst]--;
2314 }
2315 break;
2316 case 1:
2317 case 2:
2318 case 3:
2319 case 4:
2320 set_bit(nr: widget->shift,
2321 addr: &rx->active_ch_mask[rx_port_value]);
2322 rx->active_ch_cnt[rx_port_value]++;
2323 break;
2324 default:
2325 dev_err(component->dev,
2326 "%s:Invalid AIF_ID for RX_MACRO MUX %d\n",
2327 __func__, rx_port_value);
2328 goto err;
2329 }
2330
2331 snd_soc_dapm_mux_update_power(dapm: widget->dapm, kcontrol,
2332 mux: rx_port_value, e, update);
2333 return 0;
2334err:
2335 return -EINVAL;
2336}
2337
2338static const struct snd_kcontrol_new rx_macro_rx0_mux =
2339 SOC_DAPM_ENUM_EXT("rx_macro_rx0", rx_macro_rx0_enum,
2340 rx_macro_mux_get, rx_macro_mux_put);
2341static const struct snd_kcontrol_new rx_macro_rx1_mux =
2342 SOC_DAPM_ENUM_EXT("rx_macro_rx1", rx_macro_rx1_enum,
2343 rx_macro_mux_get, rx_macro_mux_put);
2344static const struct snd_kcontrol_new rx_macro_rx2_mux =
2345 SOC_DAPM_ENUM_EXT("rx_macro_rx2", rx_macro_rx2_enum,
2346 rx_macro_mux_get, rx_macro_mux_put);
2347static const struct snd_kcontrol_new rx_macro_rx3_mux =
2348 SOC_DAPM_ENUM_EXT("rx_macro_rx3", rx_macro_rx3_enum,
2349 rx_macro_mux_get, rx_macro_mux_put);
2350static const struct snd_kcontrol_new rx_macro_rx4_mux =
2351 SOC_DAPM_ENUM_EXT("rx_macro_rx4", rx_macro_rx4_enum,
2352 rx_macro_mux_get, rx_macro_mux_put);
2353static const struct snd_kcontrol_new rx_macro_rx5_mux =
2354 SOC_DAPM_ENUM_EXT("rx_macro_rx5", rx_macro_rx5_enum,
2355 rx_macro_mux_get, rx_macro_mux_put);
2356
2357static int rx_macro_get_ear_mode(struct snd_kcontrol *kcontrol,
2358 struct snd_ctl_elem_value *ucontrol)
2359{
2360 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2361 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
2362
2363 ucontrol->value.integer.value[0] = rx->is_ear_mode_on;
2364 return 0;
2365}
2366
2367static int rx_macro_put_ear_mode(struct snd_kcontrol *kcontrol,
2368 struct snd_ctl_elem_value *ucontrol)
2369{
2370 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2371 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
2372
2373 rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true);
2374 return 0;
2375}
2376
2377static int rx_macro_get_hph_hd2_mode(struct snd_kcontrol *kcontrol,
2378 struct snd_ctl_elem_value *ucontrol)
2379{
2380 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2381 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
2382
2383 ucontrol->value.integer.value[0] = rx->hph_hd2_mode;
2384 return 0;
2385}
2386
2387static int rx_macro_put_hph_hd2_mode(struct snd_kcontrol *kcontrol,
2388 struct snd_ctl_elem_value *ucontrol)
2389{
2390 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2391 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
2392
2393 rx->hph_hd2_mode = ucontrol->value.integer.value[0];
2394 return 0;
2395}
2396
2397static int rx_macro_get_hph_pwr_mode(struct snd_kcontrol *kcontrol,
2398 struct snd_ctl_elem_value *ucontrol)
2399{
2400 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2401 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
2402
2403 ucontrol->value.enumerated.item[0] = rx->hph_pwr_mode;
2404 return 0;
2405}
2406
2407static int rx_macro_put_hph_pwr_mode(struct snd_kcontrol *kcontrol,
2408 struct snd_ctl_elem_value *ucontrol)
2409{
2410 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2411 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
2412
2413 rx->hph_pwr_mode = ucontrol->value.enumerated.item[0];
2414 return 0;
2415}
2416
2417static int rx_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol,
2418 struct snd_ctl_elem_value *ucontrol)
2419{
2420 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2421 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
2422
2423 ucontrol->value.integer.value[0] = rx->is_softclip_on;
2424
2425 return 0;
2426}
2427
2428static int rx_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol,
2429 struct snd_ctl_elem_value *ucontrol)
2430{
2431 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2432 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
2433
2434 rx->is_softclip_on = ucontrol->value.integer.value[0];
2435
2436 return 0;
2437}
2438
2439static int rx_macro_aux_hpf_mode_get(struct snd_kcontrol *kcontrol,
2440 struct snd_ctl_elem_value *ucontrol)
2441{
2442 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2443 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
2444
2445 ucontrol->value.integer.value[0] = rx->is_aux_hpf_on;
2446
2447 return 0;
2448}
2449
2450static int rx_macro_aux_hpf_mode_put(struct snd_kcontrol *kcontrol,
2451 struct snd_ctl_elem_value *ucontrol)
2452{
2453 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2454 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
2455
2456 rx->is_aux_hpf_on = ucontrol->value.integer.value[0];
2457
2458 return 0;
2459}
2460
2461static int rx_macro_hphdelay_lutbypass(struct snd_soc_component *component,
2462 struct rx_macro *rx,
2463 u16 interp_idx, int event)
2464{
2465 u16 hph_lut_bypass_reg;
2466 u16 hph_comp_ctrl7;
2467
2468 switch (interp_idx) {
2469 case INTERP_HPHL:
2470 hph_lut_bypass_reg = CDC_RX_TOP_HPHL_COMP_LUT;
2471 hph_comp_ctrl7 = CDC_RX_COMPANDER0_CTL7;
2472 break;
2473 case INTERP_HPHR:
2474 hph_lut_bypass_reg = CDC_RX_TOP_HPHR_COMP_LUT;
2475 hph_comp_ctrl7 = CDC_RX_COMPANDER1_CTL7;
2476 break;
2477 default:
2478 return -EINVAL;
2479 }
2480
2481 if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_ON(event)) {
2482 if (interp_idx == INTERP_HPHL) {
2483 if (rx->is_ear_mode_on)
2484 snd_soc_component_write_field(component,
2485 CDC_RX_RX0_RX_PATH_CFG1,
2486 CDC_RX_RX0_HPH_L_EAR_SEL_MASK, val: 0x1);
2487 else
2488 snd_soc_component_write_field(component,
2489 reg: hph_lut_bypass_reg,
2490 CDC_RX_TOP_HPH_LUT_BYPASS_MASK, val: 1);
2491 } else {
2492 snd_soc_component_write_field(component, reg: hph_lut_bypass_reg,
2493 CDC_RX_TOP_HPH_LUT_BYPASS_MASK, val: 1);
2494 }
2495 if (rx->hph_pwr_mode)
2496 snd_soc_component_write_field(component, reg: hph_comp_ctrl7,
2497 CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, val: 0x0);
2498 }
2499
2500 if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
2501 snd_soc_component_write_field(component,
2502 CDC_RX_RX0_RX_PATH_CFG1,
2503 CDC_RX_RX0_HPH_L_EAR_SEL_MASK, val: 0x0);
2504 snd_soc_component_update_bits(component, reg: hph_lut_bypass_reg,
2505 CDC_RX_TOP_HPH_LUT_BYPASS_MASK, val: 0);
2506 snd_soc_component_write_field(component, reg: hph_comp_ctrl7,
2507 CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, val: 0x1);
2508 }
2509
2510 return 0;
2511}
2512
2513static int rx_macro_enable_interp_clk(struct snd_soc_component *component,
2514 int event, int interp_idx)
2515{
2516 u16 main_reg, dsm_reg, rx_cfg2_reg;
2517 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
2518
2519 main_reg = CDC_RX_RXn_RX_PATH_CTL(interp_idx);
2520 dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(interp_idx);
2521 if (interp_idx == INTERP_AUX)
2522 dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
2523 rx_cfg2_reg = CDC_RX_RXn_RX_PATH_CFG2(interp_idx);
2524
2525 if (SND_SOC_DAPM_EVENT_ON(event)) {
2526 if (rx->main_clk_users[interp_idx] == 0) {
2527 /* Main path PGA mute enable */
2528 snd_soc_component_write_field(component, reg: main_reg,
2529 CDC_RX_PATH_PGA_MUTE_MASK, val: 0x1);
2530 snd_soc_component_write_field(component, reg: dsm_reg,
2531 CDC_RX_RXn_DSM_CLK_EN_MASK, val: 0x1);
2532 snd_soc_component_update_bits(component, reg: rx_cfg2_reg,
2533 CDC_RX_RXn_HPF_CUT_FREQ_MASK, val: 0x03);
2534 rx_macro_load_compander_coeff(component, rx, comp: interp_idx, event);
2535 if (rx->hph_hd2_mode)
2536 rx_macro_hd2_control(component, interp_idx, event);
2537 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event);
2538 rx_macro_config_compander(component, rx, comp: interp_idx, event);
2539 if (interp_idx == INTERP_AUX) {
2540 rx_macro_config_softclip(component, rx, event);
2541 rx_macro_config_aux_hpf(component, rx, event);
2542 }
2543 rx_macro_config_classh(component, rx, interp_n: interp_idx, event);
2544 }
2545 rx->main_clk_users[interp_idx]++;
2546 }
2547
2548 if (SND_SOC_DAPM_EVENT_OFF(event)) {
2549 rx->main_clk_users[interp_idx]--;
2550 if (rx->main_clk_users[interp_idx] <= 0) {
2551 rx->main_clk_users[interp_idx] = 0;
2552 /* Main path PGA mute enable */
2553 snd_soc_component_write_field(component, reg: main_reg,
2554 CDC_RX_PATH_PGA_MUTE_MASK, val: 0x1);
2555 /* Clk Disable */
2556 snd_soc_component_write_field(component, reg: dsm_reg,
2557 CDC_RX_RXn_DSM_CLK_EN_MASK, val: 0);
2558 snd_soc_component_write_field(component, reg: main_reg,
2559 CDC_RX_PATH_CLK_EN_MASK, val: 0);
2560 /* Reset enable and disable */
2561 snd_soc_component_write_field(component, reg: main_reg,
2562 CDC_RX_PATH_RESET_EN_MASK, val: 1);
2563 snd_soc_component_write_field(component, reg: main_reg,
2564 CDC_RX_PATH_RESET_EN_MASK, val: 0);
2565 /* Reset rate to 48K*/
2566 snd_soc_component_update_bits(component, reg: main_reg,
2567 CDC_RX_PATH_PCM_RATE_MASK,
2568 val: 0x04);
2569 snd_soc_component_update_bits(component, reg: rx_cfg2_reg,
2570 CDC_RX_RXn_HPF_CUT_FREQ_MASK, val: 0x00);
2571 rx_macro_config_classh(component, rx, interp_n: interp_idx, event);
2572 rx_macro_config_compander(component, rx, comp: interp_idx, event);
2573 if (interp_idx == INTERP_AUX) {
2574 rx_macro_config_softclip(component, rx, event);
2575 rx_macro_config_aux_hpf(component, rx, event);
2576 }
2577 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event);
2578 if (rx->hph_hd2_mode)
2579 rx_macro_hd2_control(component, interp_idx, event);
2580 }
2581 }
2582
2583 return rx->main_clk_users[interp_idx];
2584}
2585
2586static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
2587 struct snd_kcontrol *kcontrol, int event)
2588{
2589 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
2590 u16 gain_reg, mix_reg;
2591
2592 gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(w->shift);
2593 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(w->shift);
2594
2595 switch (event) {
2596 case SND_SOC_DAPM_PRE_PMU:
2597 rx_macro_enable_interp_clk(component, event, interp_idx: w->shift);
2598 break;
2599 case SND_SOC_DAPM_POST_PMU:
2600 snd_soc_component_write(component, reg: gain_reg,
2601 val: snd_soc_component_read(component, reg: gain_reg));
2602 break;
2603 case SND_SOC_DAPM_POST_PMD:
2604 /* Clk Disable */
2605 snd_soc_component_update_bits(component, reg: mix_reg,
2606 CDC_RX_RXn_MIX_CLK_EN_MASK, val: 0x00);
2607 rx_macro_enable_interp_clk(component, event, interp_idx: w->shift);
2608 /* Reset enable and disable */
2609 snd_soc_component_update_bits(component, reg: mix_reg,
2610 CDC_RX_RXn_MIX_RESET_MASK,
2611 CDC_RX_RXn_MIX_RESET);
2612 snd_soc_component_update_bits(component, reg: mix_reg,
2613 CDC_RX_RXn_MIX_RESET_MASK, val: 0x00);
2614 break;
2615 }
2616
2617 return 0;
2618}
2619
2620static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w,
2621 struct snd_kcontrol *kcontrol, int event)
2622{
2623 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
2624
2625 switch (event) {
2626 case SND_SOC_DAPM_PRE_PMU:
2627 rx_macro_enable_interp_clk(component, event, interp_idx: w->shift);
2628 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift),
2629 CDC_RX_RXn_SIDETONE_EN_MASK, val: 1);
2630 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(w->shift),
2631 CDC_RX_PATH_CLK_EN_MASK, val: 1);
2632 break;
2633 case SND_SOC_DAPM_POST_PMD:
2634 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift),
2635 CDC_RX_RXn_SIDETONE_EN_MASK, val: 0);
2636 rx_macro_enable_interp_clk(component, event, interp_idx: w->shift);
2637 break;
2638 default:
2639 break;
2640 }
2641 return 0;
2642}
2643
2644static int rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w,
2645 struct snd_kcontrol *kcontrol, int event)
2646{
2647 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
2648
2649 switch (event) {
2650 case SND_SOC_DAPM_POST_PMU: /* fall through */
2651 case SND_SOC_DAPM_PRE_PMD:
2652 if (strnstr(w->name, "IIR0", sizeof("IIR0"))) {
2653 snd_soc_component_write(component,
2654 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
2655 val: snd_soc_component_read(component,
2656 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL));
2657 snd_soc_component_write(component,
2658 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL,
2659 val: snd_soc_component_read(component,
2660 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL));
2661 snd_soc_component_write(component,
2662 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL,
2663 val: snd_soc_component_read(component,
2664 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL));
2665 snd_soc_component_write(component,
2666 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL,
2667 val: snd_soc_component_read(component,
2668 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL));
2669 } else {
2670 snd_soc_component_write(component,
2671 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
2672 val: snd_soc_component_read(component,
2673 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL));
2674 snd_soc_component_write(component,
2675 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL,
2676 val: snd_soc_component_read(component,
2677 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL));
2678 snd_soc_component_write(component,
2679 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL,
2680 val: snd_soc_component_read(component,
2681 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL));
2682 snd_soc_component_write(component,
2683 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL,
2684 val: snd_soc_component_read(component,
2685 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL));
2686 }
2687 break;
2688 }
2689 return 0;
2690}
2691
2692static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
2693 int iir_idx, int band_idx, int coeff_idx)
2694{
2695 u32 value;
2696 int reg, b2_reg;
2697
2698 /* Address does not automatically update if reading */
2699 reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx;
2700 b2_reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx;
2701
2702 snd_soc_component_write(component, reg,
2703 val: ((band_idx * BAND_MAX + coeff_idx) *
2704 sizeof(uint32_t)) & 0x7F);
2705
2706 value = snd_soc_component_read(component, reg: b2_reg);
2707 snd_soc_component_write(component, reg,
2708 val: ((band_idx * BAND_MAX + coeff_idx)
2709 * sizeof(uint32_t) + 1) & 0x7F);
2710
2711 value |= (snd_soc_component_read(component, reg: b2_reg) << 8);
2712 snd_soc_component_write(component, reg,
2713 val: ((band_idx * BAND_MAX + coeff_idx)
2714 * sizeof(uint32_t) + 2) & 0x7F);
2715
2716 value |= (snd_soc_component_read(component, reg: b2_reg) << 16);
2717 snd_soc_component_write(component, reg,
2718 val: ((band_idx * BAND_MAX + coeff_idx)
2719 * sizeof(uint32_t) + 3) & 0x7F);
2720
2721 /* Mask bits top 2 bits since they are reserved */
2722 value |= (snd_soc_component_read(component, reg: b2_reg) << 24);
2723 return value;
2724}
2725
2726static void set_iir_band_coeff(struct snd_soc_component *component,
2727 int iir_idx, int band_idx, uint32_t value)
2728{
2729 int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx;
2730
2731 snd_soc_component_write(component, reg, val: (value & 0xFF));
2732 snd_soc_component_write(component, reg, val: (value >> 8) & 0xFF);
2733 snd_soc_component_write(component, reg, val: (value >> 16) & 0xFF);
2734 /* Mask top 2 bits, 7-8 are reserved */
2735 snd_soc_component_write(component, reg, val: (value >> 24) & 0x3F);
2736}
2737
2738static int rx_macro_put_iir_band_audio_mixer(
2739 struct snd_kcontrol *kcontrol,
2740 struct snd_ctl_elem_value *ucontrol)
2741{
2742 struct snd_soc_component *component =
2743 snd_soc_kcontrol_component(kcontrol);
2744 struct wcd_iir_filter_ctl *ctl =
2745 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2746 struct soc_bytes_ext *params = &ctl->bytes_ext;
2747 int iir_idx = ctl->iir_idx;
2748 int band_idx = ctl->band_idx;
2749 u32 coeff[BAND_MAX];
2750 int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx;
2751
2752 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
2753
2754 /* Mask top bit it is reserved */
2755 /* Updates addr automatically for each B2 write */
2756 snd_soc_component_write(component, reg, val: (band_idx * BAND_MAX *
2757 sizeof(uint32_t)) & 0x7F);
2758
2759 set_iir_band_coeff(component, iir_idx, band_idx, value: coeff[0]);
2760 set_iir_band_coeff(component, iir_idx, band_idx, value: coeff[1]);
2761 set_iir_band_coeff(component, iir_idx, band_idx, value: coeff[2]);
2762 set_iir_band_coeff(component, iir_idx, band_idx, value: coeff[3]);
2763 set_iir_band_coeff(component, iir_idx, band_idx, value: coeff[4]);
2764
2765 return 0;
2766}
2767
2768static int rx_macro_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
2769 struct snd_ctl_elem_value *ucontrol)
2770{
2771 struct snd_soc_component *component =
2772 snd_soc_kcontrol_component(kcontrol);
2773 struct wcd_iir_filter_ctl *ctl =
2774 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2775 struct soc_bytes_ext *params = &ctl->bytes_ext;
2776 int iir_idx = ctl->iir_idx;
2777 int band_idx = ctl->band_idx;
2778 u32 coeff[BAND_MAX];
2779
2780 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, coeff_idx: 0);
2781 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, coeff_idx: 1);
2782 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, coeff_idx: 2);
2783 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, coeff_idx: 3);
2784 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, coeff_idx: 4);
2785
2786 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
2787
2788 return 0;
2789}
2790
2791static int rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol,
2792 struct snd_ctl_elem_info *ucontrol)
2793{
2794 struct wcd_iir_filter_ctl *ctl =
2795 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2796 struct soc_bytes_ext *params = &ctl->bytes_ext;
2797
2798 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
2799 ucontrol->count = params->max;
2800
2801 return 0;
2802}
2803
2804static const struct snd_kcontrol_new rx_macro_snd_controls[] = {
2805 SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL,
2806 -84, 40, digital_gain),
2807 SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_RX_RX1_RX_VOL_CTL,
2808 -84, 40, digital_gain),
2809 SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_RX_RX2_RX_VOL_CTL,
2810 -84, 40, digital_gain),
2811 SOC_SINGLE_S8_TLV("RX_RX0 Mix Digital Volume", CDC_RX_RX0_RX_VOL_MIX_CTL,
2812 -84, 40, digital_gain),
2813 SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_RX_RX1_RX_VOL_MIX_CTL,
2814 -84, 40, digital_gain),
2815 SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_RX_RX2_RX_VOL_MIX_CTL,
2816 -84, 40, digital_gain),
2817
2818 SOC_SINGLE_EXT("RX_COMP1 Switch", SND_SOC_NOPM, RX_MACRO_COMP1, 1, 0,
2819 rx_macro_get_compander, rx_macro_set_compander),
2820 SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, RX_MACRO_COMP2, 1, 0,
2821 rx_macro_get_compander, rx_macro_set_compander),
2822
2823 SOC_SINGLE_EXT("RX_EAR Mode Switch", SND_SOC_NOPM, 0, 1, 0,
2824 rx_macro_get_ear_mode, rx_macro_put_ear_mode),
2825
2826 SOC_SINGLE_EXT("RX_HPH HD2 Mode Switch", SND_SOC_NOPM, 0, 1, 0,
2827 rx_macro_get_hph_hd2_mode, rx_macro_put_hph_hd2_mode),
2828
2829 SOC_ENUM_EXT("RX_HPH PWR Mode", rx_macro_hph_pwr_mode_enum,
2830 rx_macro_get_hph_pwr_mode, rx_macro_put_hph_pwr_mode),
2831
2832 SOC_SINGLE_EXT("RX_Softclip Switch", SND_SOC_NOPM, 0, 1, 0,
2833 rx_macro_soft_clip_enable_get,
2834 rx_macro_soft_clip_enable_put),
2835 SOC_SINGLE_EXT("AUX_HPF Switch", SND_SOC_NOPM, 0, 1, 0,
2836 rx_macro_aux_hpf_mode_get,
2837 rx_macro_aux_hpf_mode_put),
2838
2839 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
2840 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
2841 digital_gain),
2842 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
2843 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
2844 digital_gain),
2845 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
2846 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
2847 digital_gain),
2848 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
2849 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
2850 digital_gain),
2851 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
2852 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
2853 digital_gain),
2854 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
2855 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
2856 digital_gain),
2857 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
2858 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
2859 digital_gain),
2860 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
2861 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
2862 digital_gain),
2863
2864 SOC_SINGLE("IIR1 Band1 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2865 0, 1, 0),
2866 SOC_SINGLE("IIR1 Band2 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2867 1, 1, 0),
2868 SOC_SINGLE("IIR1 Band3 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2869 2, 1, 0),
2870 SOC_SINGLE("IIR1 Band4 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2871 3, 1, 0),
2872 SOC_SINGLE("IIR1 Band5 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2873 4, 1, 0),
2874 SOC_SINGLE("IIR2 Band1 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2875 0, 1, 0),
2876 SOC_SINGLE("IIR2 Band2 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2877 1, 1, 0),
2878 SOC_SINGLE("IIR2 Band3 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2879 2, 1, 0),
2880 SOC_SINGLE("IIR2 Band4 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2881 3, 1, 0),
2882 SOC_SINGLE("IIR2 Band5 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2883 4, 1, 0),
2884
2885 RX_MACRO_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
2886 RX_MACRO_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
2887 RX_MACRO_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
2888 RX_MACRO_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
2889 RX_MACRO_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
2890
2891 RX_MACRO_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
2892 RX_MACRO_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
2893 RX_MACRO_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
2894 RX_MACRO_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
2895 RX_MACRO_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
2896
2897};
2898
2899static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w,
2900 struct snd_kcontrol *kcontrol,
2901 int event)
2902{
2903 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
2904 u16 val, ec_hq_reg;
2905 int ec_tx = -1;
2906
2907 val = snd_soc_component_read(component,
2908 CDC_RX_INP_MUX_RX_MIX_CFG4);
2909 if (!(snd_soc_dapm_widget_name_cmp(widget: w, s: "RX MIX TX0 MUX")))
2910 ec_tx = ((val & 0xf0) >> 0x4) - 1;
2911 else if (!(snd_soc_dapm_widget_name_cmp(widget: w, s: "RX MIX TX1 MUX")))
2912 ec_tx = (val & 0x0f) - 1;
2913
2914 val = snd_soc_component_read(component,
2915 CDC_RX_INP_MUX_RX_MIX_CFG5);
2916 if (!(snd_soc_dapm_widget_name_cmp(widget: w, s: "RX MIX TX2 MUX")))
2917 ec_tx = (val & 0x0f) - 1;
2918
2919 if (ec_tx < 0 || (ec_tx >= RX_MACRO_EC_MUX_MAX)) {
2920 dev_err(component->dev, "%s: EC mix control not set correctly\n",
2921 __func__);
2922 return -EINVAL;
2923 }
2924 ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL +
2925 0x40 * ec_tx;
2926 snd_soc_component_update_bits(component, reg: ec_hq_reg, mask: 0x01, val: 0x01);
2927 ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 +
2928 0x40 * ec_tx;
2929 /* default set to 48k */
2930 snd_soc_component_update_bits(component, reg: ec_hq_reg, mask: 0x1E, val: 0x08);
2931
2932 return 0;
2933}
2934
2935static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = {
2936 SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0,
2937 SND_SOC_NOPM, 0, 0),
2938
2939 SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0,
2940 SND_SOC_NOPM, 0, 0),
2941
2942 SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0,
2943 SND_SOC_NOPM, 0, 0),
2944
2945 SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0,
2946 SND_SOC_NOPM, 0, 0),
2947
2948 SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0,
2949 SND_SOC_NOPM, 0, 0),
2950
2951 SND_SOC_DAPM_MUX("RX_MACRO RX0 MUX", SND_SOC_NOPM, RX_MACRO_RX0, 0,
2952 &rx_macro_rx0_mux),
2953 SND_SOC_DAPM_MUX("RX_MACRO RX1 MUX", SND_SOC_NOPM, RX_MACRO_RX1, 0,
2954 &rx_macro_rx1_mux),
2955 SND_SOC_DAPM_MUX("RX_MACRO RX2 MUX", SND_SOC_NOPM, RX_MACRO_RX2, 0,
2956 &rx_macro_rx2_mux),
2957 SND_SOC_DAPM_MUX("RX_MACRO RX3 MUX", SND_SOC_NOPM, RX_MACRO_RX3, 0,
2958 &rx_macro_rx3_mux),
2959 SND_SOC_DAPM_MUX("RX_MACRO RX4 MUX", SND_SOC_NOPM, RX_MACRO_RX4, 0,
2960 &rx_macro_rx4_mux),
2961 SND_SOC_DAPM_MUX("RX_MACRO RX5 MUX", SND_SOC_NOPM, RX_MACRO_RX5, 0,
2962 &rx_macro_rx5_mux),
2963
2964 SND_SOC_DAPM_MIXER("RX_RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
2965 SND_SOC_DAPM_MIXER("RX_RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
2966 SND_SOC_DAPM_MIXER("RX_RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
2967 SND_SOC_DAPM_MIXER("RX_RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
2968 SND_SOC_DAPM_MIXER("RX_RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
2969 SND_SOC_DAPM_MIXER("RX_RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
2970
2971 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
2972 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
2973 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
2974 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
2975 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
2976 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
2977 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
2978 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
2979
2980 SND_SOC_DAPM_MUX_E("RX MIX TX0 MUX", SND_SOC_NOPM,
2981 RX_MACRO_EC0_MUX, 0,
2982 &rx_mix_tx0_mux, rx_macro_enable_echo,
2983 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2984 SND_SOC_DAPM_MUX_E("RX MIX TX1 MUX", SND_SOC_NOPM,
2985 RX_MACRO_EC1_MUX, 0,
2986 &rx_mix_tx1_mux, rx_macro_enable_echo,
2987 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2988 SND_SOC_DAPM_MUX_E("RX MIX TX2 MUX", SND_SOC_NOPM,
2989 RX_MACRO_EC2_MUX, 0,
2990 &rx_mix_tx2_mux, rx_macro_enable_echo,
2991 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2992
2993 SND_SOC_DAPM_MIXER_E("IIR0", CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL,
2994 4, 0, NULL, 0, rx_macro_set_iir_gain,
2995 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2996 SND_SOC_DAPM_MIXER_E("IIR1", CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL,
2997 4, 0, NULL, 0, rx_macro_set_iir_gain,
2998 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2999 SND_SOC_DAPM_MIXER("SRC0", CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL,
3000 4, 0, NULL, 0),
3001 SND_SOC_DAPM_MIXER("SRC1", CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL,
3002 4, 0, NULL, 0),
3003
3004 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
3005 &rx_int0_dem_inp_mux),
3006 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
3007 &rx_int1_dem_inp_mux),
3008
3009 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
3010 &rx_int0_2_mux, rx_macro_enable_mix_path,
3011 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3012 SND_SOC_DAPM_POST_PMD),
3013 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
3014 &rx_int1_2_mux, rx_macro_enable_mix_path,
3015 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3016 SND_SOC_DAPM_POST_PMD),
3017 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0,
3018 &rx_int2_2_mux, rx_macro_enable_mix_path,
3019 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3020 SND_SOC_DAPM_POST_PMD),
3021
3022 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp0_mux),
3023 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp1_mux),
3024 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp2_mux),
3025 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp0_mux),
3026 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp1_mux),
3027 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp2_mux),
3028 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp0_mux),
3029 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp1_mux),
3030 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp2_mux),
3031
3032 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
3033 &rx_int0_1_interp_mux, rx_macro_enable_main_path,
3034 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3035 SND_SOC_DAPM_POST_PMD),
3036 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
3037 &rx_int1_1_interp_mux, rx_macro_enable_main_path,
3038 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3039 SND_SOC_DAPM_POST_PMD),
3040 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0,
3041 &rx_int2_1_interp_mux, rx_macro_enable_main_path,
3042 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3043 SND_SOC_DAPM_POST_PMD),
3044
3045 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
3046 &rx_int0_2_interp_mux),
3047 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
3048 &rx_int1_2_interp_mux),
3049 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
3050 &rx_int2_2_interp_mux),
3051
3052 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3053 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3054 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3055 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3056 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3057 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3058
3059 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", SND_SOC_NOPM, INTERP_HPHL,
3060 0, &rx_int0_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3061 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3062 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", SND_SOC_NOPM, INTERP_HPHR,
3063 0, &rx_int1_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3064 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3065 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", SND_SOC_NOPM, INTERP_AUX,
3066 0, &rx_int2_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3067 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3068
3069 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3070 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3071 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3072
3073 SND_SOC_DAPM_OUTPUT("HPHL_OUT"),
3074 SND_SOC_DAPM_OUTPUT("HPHR_OUT"),
3075 SND_SOC_DAPM_OUTPUT("AUX_OUT"),
3076
3077 SND_SOC_DAPM_INPUT("RX_TX DEC0_INP"),
3078 SND_SOC_DAPM_INPUT("RX_TX DEC1_INP"),
3079 SND_SOC_DAPM_INPUT("RX_TX DEC2_INP"),
3080 SND_SOC_DAPM_INPUT("RX_TX DEC3_INP"),
3081
3082 SND_SOC_DAPM_SUPPLY_S("RX_MCLK", 0, SND_SOC_NOPM, 0, 0,
3083 rx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3084};
3085
3086static const struct snd_soc_dapm_route rx_audio_map[] = {
3087 {"RX AIF1 PB", NULL, "RX_MCLK"},
3088 {"RX AIF2 PB", NULL, "RX_MCLK"},
3089 {"RX AIF3 PB", NULL, "RX_MCLK"},
3090 {"RX AIF4 PB", NULL, "RX_MCLK"},
3091
3092 {"RX_MACRO RX0 MUX", "AIF1_PB", "RX AIF1 PB"},
3093 {"RX_MACRO RX1 MUX", "AIF1_PB", "RX AIF1 PB"},
3094 {"RX_MACRO RX2 MUX", "AIF1_PB", "RX AIF1 PB"},
3095 {"RX_MACRO RX3 MUX", "AIF1_PB", "RX AIF1 PB"},
3096 {"RX_MACRO RX4 MUX", "AIF1_PB", "RX AIF1 PB"},
3097 {"RX_MACRO RX5 MUX", "AIF1_PB", "RX AIF1 PB"},
3098
3099 {"RX_MACRO RX0 MUX", "AIF2_PB", "RX AIF2 PB"},
3100 {"RX_MACRO RX1 MUX", "AIF2_PB", "RX AIF2 PB"},
3101 {"RX_MACRO RX2 MUX", "AIF2_PB", "RX AIF2 PB"},
3102 {"RX_MACRO RX3 MUX", "AIF2_PB", "RX AIF2 PB"},
3103 {"RX_MACRO RX4 MUX", "AIF2_PB", "RX AIF2 PB"},
3104 {"RX_MACRO RX5 MUX", "AIF2_PB", "RX AIF2 PB"},
3105
3106 {"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"},
3107 {"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"},
3108 {"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"},
3109 {"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"},
3110 {"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"},
3111 {"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"},
3112
3113 {"RX_MACRO RX0 MUX", "AIF4_PB", "RX AIF4 PB"},
3114 {"RX_MACRO RX1 MUX", "AIF4_PB", "RX AIF4 PB"},
3115 {"RX_MACRO RX2 MUX", "AIF4_PB", "RX AIF4 PB"},
3116 {"RX_MACRO RX3 MUX", "AIF4_PB", "RX AIF4 PB"},
3117 {"RX_MACRO RX4 MUX", "AIF4_PB", "RX AIF4 PB"},
3118 {"RX_MACRO RX5 MUX", "AIF4_PB", "RX AIF4 PB"},
3119
3120 {"RX_RX0", NULL, "RX_MACRO RX0 MUX"},
3121 {"RX_RX1", NULL, "RX_MACRO RX1 MUX"},
3122 {"RX_RX2", NULL, "RX_MACRO RX2 MUX"},
3123 {"RX_RX3", NULL, "RX_MACRO RX3 MUX"},
3124 {"RX_RX4", NULL, "RX_MACRO RX4 MUX"},
3125 {"RX_RX5", NULL, "RX_MACRO RX5 MUX"},
3126
3127 {"RX INT0_1 MIX1 INP0", "RX0", "RX_RX0"},
3128 {"RX INT0_1 MIX1 INP0", "RX1", "RX_RX1"},
3129 {"RX INT0_1 MIX1 INP0", "RX2", "RX_RX2"},
3130 {"RX INT0_1 MIX1 INP0", "RX3", "RX_RX3"},
3131 {"RX INT0_1 MIX1 INP0", "RX4", "RX_RX4"},
3132 {"RX INT0_1 MIX1 INP0", "RX5", "RX_RX5"},
3133 {"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"},
3134 {"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"},
3135 {"RX INT0_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3136 {"RX INT0_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3137 {"RX INT0_1 MIX1 INP1", "RX0", "RX_RX0"},
3138 {"RX INT0_1 MIX1 INP1", "RX1", "RX_RX1"},
3139 {"RX INT0_1 MIX1 INP1", "RX2", "RX_RX2"},
3140 {"RX INT0_1 MIX1 INP1", "RX3", "RX_RX3"},
3141 {"RX INT0_1 MIX1 INP1", "RX4", "RX_RX4"},
3142 {"RX INT0_1 MIX1 INP1", "RX5", "RX_RX5"},
3143 {"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"},
3144 {"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"},
3145 {"RX INT0_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3146 {"RX INT0_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3147 {"RX INT0_1 MIX1 INP2", "RX0", "RX_RX0"},
3148 {"RX INT0_1 MIX1 INP2", "RX1", "RX_RX1"},
3149 {"RX INT0_1 MIX1 INP2", "RX2", "RX_RX2"},
3150 {"RX INT0_1 MIX1 INP2", "RX3", "RX_RX3"},
3151 {"RX INT0_1 MIX1 INP2", "RX4", "RX_RX4"},
3152 {"RX INT0_1 MIX1 INP2", "RX5", "RX_RX5"},
3153 {"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"},
3154 {"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"},
3155 {"RX INT0_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3156 {"RX INT0_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3157
3158 {"RX INT1_1 MIX1 INP0", "RX0", "RX_RX0"},
3159 {"RX INT1_1 MIX1 INP0", "RX1", "RX_RX1"},
3160 {"RX INT1_1 MIX1 INP0", "RX2", "RX_RX2"},
3161 {"RX INT1_1 MIX1 INP0", "RX3", "RX_RX3"},
3162 {"RX INT1_1 MIX1 INP0", "RX4", "RX_RX4"},
3163 {"RX INT1_1 MIX1 INP0", "RX5", "RX_RX5"},
3164 {"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"},
3165 {"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"},
3166 {"RX INT1_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3167 {"RX INT1_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3168 {"RX INT1_1 MIX1 INP1", "RX0", "RX_RX0"},
3169 {"RX INT1_1 MIX1 INP1", "RX1", "RX_RX1"},
3170 {"RX INT1_1 MIX1 INP1", "RX2", "RX_RX2"},
3171 {"RX INT1_1 MIX1 INP1", "RX3", "RX_RX3"},
3172 {"RX INT1_1 MIX1 INP1", "RX4", "RX_RX4"},
3173 {"RX INT1_1 MIX1 INP1", "RX5", "RX_RX5"},
3174 {"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"},
3175 {"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"},
3176 {"RX INT1_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3177 {"RX INT1_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3178 {"RX INT1_1 MIX1 INP2", "RX0", "RX_RX0"},
3179 {"RX INT1_1 MIX1 INP2", "RX1", "RX_RX1"},
3180 {"RX INT1_1 MIX1 INP2", "RX2", "RX_RX2"},
3181 {"RX INT1_1 MIX1 INP2", "RX3", "RX_RX3"},
3182 {"RX INT1_1 MIX1 INP2", "RX4", "RX_RX4"},
3183 {"RX INT1_1 MIX1 INP2", "RX5", "RX_RX5"},
3184 {"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"},
3185 {"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"},
3186 {"RX INT1_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3187 {"RX INT1_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3188
3189 {"RX INT2_1 MIX1 INP0", "RX0", "RX_RX0"},
3190 {"RX INT2_1 MIX1 INP0", "RX1", "RX_RX1"},
3191 {"RX INT2_1 MIX1 INP0", "RX2", "RX_RX2"},
3192 {"RX INT2_1 MIX1 INP0", "RX3", "RX_RX3"},
3193 {"RX INT2_1 MIX1 INP0", "RX4", "RX_RX4"},
3194 {"RX INT2_1 MIX1 INP0", "RX5", "RX_RX5"},
3195 {"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"},
3196 {"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"},
3197 {"RX INT2_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3198 {"RX INT2_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3199 {"RX INT2_1 MIX1 INP1", "RX0", "RX_RX0"},
3200 {"RX INT2_1 MIX1 INP1", "RX1", "RX_RX1"},
3201 {"RX INT2_1 MIX1 INP1", "RX2", "RX_RX2"},
3202 {"RX INT2_1 MIX1 INP1", "RX3", "RX_RX3"},
3203 {"RX INT2_1 MIX1 INP1", "RX4", "RX_RX4"},
3204 {"RX INT2_1 MIX1 INP1", "RX5", "RX_RX5"},
3205 {"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"},
3206 {"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"},
3207 {"RX INT2_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3208 {"RX INT2_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3209 {"RX INT2_1 MIX1 INP2", "RX0", "RX_RX0"},
3210 {"RX INT2_1 MIX1 INP2", "RX1", "RX_RX1"},
3211 {"RX INT2_1 MIX1 INP2", "RX2", "RX_RX2"},
3212 {"RX INT2_1 MIX1 INP2", "RX3", "RX_RX3"},
3213 {"RX INT2_1 MIX1 INP2", "RX4", "RX_RX4"},
3214 {"RX INT2_1 MIX1 INP2", "RX5", "RX_RX5"},
3215 {"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"},
3216 {"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"},
3217 {"RX INT2_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3218 {"RX INT2_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3219
3220 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"},
3221 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"},
3222 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"},
3223 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"},
3224 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"},
3225 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"},
3226 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"},
3227 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"},
3228 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"},
3229
3230 {"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3231 {"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3232 {"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3233 {"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3234 {"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3235 {"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3236 {"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3237 {"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3238 {"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3239 {"RX AIF_ECHO", NULL, "RX MIX TX0 MUX"},
3240 {"RX AIF_ECHO", NULL, "RX MIX TX1 MUX"},
3241 {"RX AIF_ECHO", NULL, "RX MIX TX2 MUX"},
3242 {"RX AIF_ECHO", NULL, "RX_MCLK"},
3243
3244 /* Mixing path INT0 */
3245 {"RX INT0_2 MUX", "RX0", "RX_RX0"},
3246 {"RX INT0_2 MUX", "RX1", "RX_RX1"},
3247 {"RX INT0_2 MUX", "RX2", "RX_RX2"},
3248 {"RX INT0_2 MUX", "RX3", "RX_RX3"},
3249 {"RX INT0_2 MUX", "RX4", "RX_RX4"},
3250 {"RX INT0_2 MUX", "RX5", "RX_RX5"},
3251 {"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"},
3252 {"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"},
3253
3254 /* Mixing path INT1 */
3255 {"RX INT1_2 MUX", "RX0", "RX_RX0"},
3256 {"RX INT1_2 MUX", "RX1", "RX_RX1"},
3257 {"RX INT1_2 MUX", "RX2", "RX_RX2"},
3258 {"RX INT1_2 MUX", "RX3", "RX_RX3"},
3259 {"RX INT1_2 MUX", "RX4", "RX_RX4"},
3260 {"RX INT1_2 MUX", "RX5", "RX_RX5"},
3261 {"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"},
3262 {"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"},
3263
3264 /* Mixing path INT2 */
3265 {"RX INT2_2 MUX", "RX0", "RX_RX0"},
3266 {"RX INT2_2 MUX", "RX1", "RX_RX1"},
3267 {"RX INT2_2 MUX", "RX2", "RX_RX2"},
3268 {"RX INT2_2 MUX", "RX3", "RX_RX3"},
3269 {"RX INT2_2 MUX", "RX4", "RX_RX4"},
3270 {"RX INT2_2 MUX", "RX5", "RX_RX5"},
3271 {"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"},
3272 {"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"},
3273
3274 {"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"},
3275 {"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"},
3276 {"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"},
3277 {"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"},
3278 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
3279 {"HPHL_OUT", NULL, "RX INT0 DEM MUX"},
3280 {"HPHL_OUT", NULL, "RX_MCLK"},
3281
3282 {"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"},
3283 {"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"},
3284 {"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"},
3285 {"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"},
3286 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX2"},
3287 {"HPHR_OUT", NULL, "RX INT1 DEM MUX"},
3288 {"HPHR_OUT", NULL, "RX_MCLK"},
3289
3290 {"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"},
3291
3292 {"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"},
3293 {"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"},
3294 {"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"},
3295 {"AUX_OUT", NULL, "RX INT2 MIX2"},
3296 {"AUX_OUT", NULL, "RX_MCLK"},
3297
3298 {"IIR0", NULL, "RX_MCLK"},
3299 {"IIR0", NULL, "IIR0 INP0 MUX"},
3300 {"IIR0 INP0 MUX", "DEC0", "RX_TX DEC0_INP"},
3301 {"IIR0 INP0 MUX", "DEC1", "RX_TX DEC1_INP"},
3302 {"IIR0 INP0 MUX", "DEC2", "RX_TX DEC2_INP"},
3303 {"IIR0 INP0 MUX", "DEC3", "RX_TX DEC3_INP"},
3304 {"IIR0 INP0 MUX", "RX0", "RX_RX0"},
3305 {"IIR0 INP0 MUX", "RX1", "RX_RX1"},
3306 {"IIR0 INP0 MUX", "RX2", "RX_RX2"},
3307 {"IIR0 INP0 MUX", "RX3", "RX_RX3"},
3308 {"IIR0 INP0 MUX", "RX4", "RX_RX4"},
3309 {"IIR0 INP0 MUX", "RX5", "RX_RX5"},
3310 {"IIR0", NULL, "IIR0 INP1 MUX"},
3311 {"IIR0 INP1 MUX", "DEC0", "RX_TX DEC0_INP"},
3312 {"IIR0 INP1 MUX", "DEC1", "RX_TX DEC1_INP"},
3313 {"IIR0 INP1 MUX", "DEC2", "RX_TX DEC2_INP"},
3314 {"IIR0 INP1 MUX", "DEC3", "RX_TX DEC3_INP"},
3315 {"IIR0 INP1 MUX", "RX0", "RX_RX0"},
3316 {"IIR0 INP1 MUX", "RX1", "RX_RX1"},
3317 {"IIR0 INP1 MUX", "RX2", "RX_RX2"},
3318 {"IIR0 INP1 MUX", "RX3", "RX_RX3"},
3319 {"IIR0 INP1 MUX", "RX4", "RX_RX4"},
3320 {"IIR0 INP1 MUX", "RX5", "RX_RX5"},
3321 {"IIR0", NULL, "IIR0 INP2 MUX"},
3322 {"IIR0 INP2 MUX", "DEC0", "RX_TX DEC0_INP"},
3323 {"IIR0 INP2 MUX", "DEC1", "RX_TX DEC1_INP"},
3324 {"IIR0 INP2 MUX", "DEC2", "RX_TX DEC2_INP"},
3325 {"IIR0 INP2 MUX", "DEC3", "RX_TX DEC3_INP"},
3326 {"IIR0 INP2 MUX", "RX0", "RX_RX0"},
3327 {"IIR0 INP2 MUX", "RX1", "RX_RX1"},
3328 {"IIR0 INP2 MUX", "RX2", "RX_RX2"},
3329 {"IIR0 INP2 MUX", "RX3", "RX_RX3"},
3330 {"IIR0 INP2 MUX", "RX4", "RX_RX4"},
3331 {"IIR0 INP2 MUX", "RX5", "RX_RX5"},
3332 {"IIR0", NULL, "IIR0 INP3 MUX"},
3333 {"IIR0 INP3 MUX", "DEC0", "RX_TX DEC0_INP"},
3334 {"IIR0 INP3 MUX", "DEC1", "RX_TX DEC1_INP"},
3335 {"IIR0 INP3 MUX", "DEC2", "RX_TX DEC2_INP"},
3336 {"IIR0 INP3 MUX", "DEC3", "RX_TX DEC3_INP"},
3337 {"IIR0 INP3 MUX", "RX0", "RX_RX0"},
3338 {"IIR0 INP3 MUX", "RX1", "RX_RX1"},
3339 {"IIR0 INP3 MUX", "RX2", "RX_RX2"},
3340 {"IIR0 INP3 MUX", "RX3", "RX_RX3"},
3341 {"IIR0 INP3 MUX", "RX4", "RX_RX4"},
3342 {"IIR0 INP3 MUX", "RX5", "RX_RX5"},
3343
3344 {"IIR1", NULL, "RX_MCLK"},
3345 {"IIR1", NULL, "IIR1 INP0 MUX"},
3346 {"IIR1 INP0 MUX", "DEC0", "RX_TX DEC0_INP"},
3347 {"IIR1 INP0 MUX", "DEC1", "RX_TX DEC1_INP"},
3348 {"IIR1 INP0 MUX", "DEC2", "RX_TX DEC2_INP"},
3349 {"IIR1 INP0 MUX", "DEC3", "RX_TX DEC3_INP"},
3350 {"IIR1 INP0 MUX", "RX0", "RX_RX0"},
3351 {"IIR1 INP0 MUX", "RX1", "RX_RX1"},
3352 {"IIR1 INP0 MUX", "RX2", "RX_RX2"},
3353 {"IIR1 INP0 MUX", "RX3", "RX_RX3"},
3354 {"IIR1 INP0 MUX", "RX4", "RX_RX4"},
3355 {"IIR1 INP0 MUX", "RX5", "RX_RX5"},
3356 {"IIR1", NULL, "IIR1 INP1 MUX"},
3357 {"IIR1 INP1 MUX", "DEC0", "RX_TX DEC0_INP"},
3358 {"IIR1 INP1 MUX", "DEC1", "RX_TX DEC1_INP"},
3359 {"IIR1 INP1 MUX", "DEC2", "RX_TX DEC2_INP"},
3360 {"IIR1 INP1 MUX", "DEC3", "RX_TX DEC3_INP"},
3361 {"IIR1 INP1 MUX", "RX0", "RX_RX0"},
3362 {"IIR1 INP1 MUX", "RX1", "RX_RX1"},
3363 {"IIR1 INP1 MUX", "RX2", "RX_RX2"},
3364 {"IIR1 INP1 MUX", "RX3", "RX_RX3"},
3365 {"IIR1 INP1 MUX", "RX4", "RX_RX4"},
3366 {"IIR1 INP1 MUX", "RX5", "RX_RX5"},
3367 {"IIR1", NULL, "IIR1 INP2 MUX"},
3368 {"IIR1 INP2 MUX", "DEC0", "RX_TX DEC0_INP"},
3369 {"IIR1 INP2 MUX", "DEC1", "RX_TX DEC1_INP"},
3370 {"IIR1 INP2 MUX", "DEC2", "RX_TX DEC2_INP"},
3371 {"IIR1 INP2 MUX", "DEC3", "RX_TX DEC3_INP"},
3372 {"IIR1 INP2 MUX", "RX0", "RX_RX0"},
3373 {"IIR1 INP2 MUX", "RX1", "RX_RX1"},
3374 {"IIR1 INP2 MUX", "RX2", "RX_RX2"},
3375 {"IIR1 INP2 MUX", "RX3", "RX_RX3"},
3376 {"IIR1 INP2 MUX", "RX4", "RX_RX4"},
3377 {"IIR1 INP2 MUX", "RX5", "RX_RX5"},
3378 {"IIR1", NULL, "IIR1 INP3 MUX"},
3379 {"IIR1 INP3 MUX", "DEC0", "RX_TX DEC0_INP"},
3380 {"IIR1 INP3 MUX", "DEC1", "RX_TX DEC1_INP"},
3381 {"IIR1 INP3 MUX", "DEC2", "RX_TX DEC2_INP"},
3382 {"IIR1 INP3 MUX", "DEC3", "RX_TX DEC3_INP"},
3383 {"IIR1 INP3 MUX", "RX0", "RX_RX0"},
3384 {"IIR1 INP3 MUX", "RX1", "RX_RX1"},
3385 {"IIR1 INP3 MUX", "RX2", "RX_RX2"},
3386 {"IIR1 INP3 MUX", "RX3", "RX_RX3"},
3387 {"IIR1 INP3 MUX", "RX4", "RX_RX4"},
3388 {"IIR1 INP3 MUX", "RX5", "RX_RX5"},
3389
3390 {"SRC0", NULL, "IIR0"},
3391 {"SRC1", NULL, "IIR1"},
3392 {"RX INT0 MIX2 INP", "SRC0", "SRC0"},
3393 {"RX INT0 MIX2 INP", "SRC1", "SRC1"},
3394 {"RX INT1 MIX2 INP", "SRC0", "SRC0"},
3395 {"RX INT1 MIX2 INP", "SRC1", "SRC1"},
3396 {"RX INT2 MIX2 INP", "SRC0", "SRC0"},
3397 {"RX INT2 MIX2 INP", "SRC1", "SRC1"},
3398};
3399
3400static int rx_macro_component_probe(struct snd_soc_component *component)
3401{
3402 struct rx_macro *rx = snd_soc_component_get_drvdata(c: component);
3403
3404 snd_soc_component_init_regmap(component, regmap: rx->regmap);
3405
3406 snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_SEC7,
3407 CDC_RX_DSM_OUT_DELAY_SEL_MASK,
3408 CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
3409 snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_SEC7,
3410 CDC_RX_DSM_OUT_DELAY_SEL_MASK,
3411 CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
3412 snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_SEC7,
3413 CDC_RX_DSM_OUT_DELAY_SEL_MASK,
3414 CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
3415 snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_CFG3,
3416 CDC_RX_DC_COEFF_SEL_MASK,
3417 CDC_RX_DC_COEFF_SEL_TWO);
3418 snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_CFG3,
3419 CDC_RX_DC_COEFF_SEL_MASK,
3420 CDC_RX_DC_COEFF_SEL_TWO);
3421 snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_CFG3,
3422 CDC_RX_DC_COEFF_SEL_MASK,
3423 CDC_RX_DC_COEFF_SEL_TWO);
3424
3425 rx->component = component;
3426
3427 return 0;
3428}
3429
3430static int swclk_gate_enable(struct clk_hw *hw)
3431{
3432 struct rx_macro *rx = to_rx_macro(hw);
3433 int ret;
3434
3435 ret = clk_prepare_enable(clk: rx->mclk);
3436 if (ret) {
3437 dev_err(rx->dev, "unable to prepare mclk\n");
3438 return ret;
3439 }
3440
3441 rx_macro_mclk_enable(rx, mclk_enable: true);
3442
3443 regmap_update_bits(map: rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3444 CDC_RX_SWR_CLK_EN_MASK, val: 1);
3445
3446 return 0;
3447}
3448
3449static void swclk_gate_disable(struct clk_hw *hw)
3450{
3451 struct rx_macro *rx = to_rx_macro(hw);
3452
3453 regmap_update_bits(map: rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3454 CDC_RX_SWR_CLK_EN_MASK, val: 0);
3455
3456 rx_macro_mclk_enable(rx, mclk_enable: false);
3457 clk_disable_unprepare(clk: rx->mclk);
3458}
3459
3460static int swclk_gate_is_enabled(struct clk_hw *hw)
3461{
3462 struct rx_macro *rx = to_rx_macro(hw);
3463 int ret, val;
3464
3465 regmap_read(map: rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, val: &val);
3466 ret = val & BIT(0);
3467
3468 return ret;
3469}
3470
3471static unsigned long swclk_recalc_rate(struct clk_hw *hw,
3472 unsigned long parent_rate)
3473{
3474 return parent_rate / 2;
3475}
3476
3477static const struct clk_ops swclk_gate_ops = {
3478 .prepare = swclk_gate_enable,
3479 .unprepare = swclk_gate_disable,
3480 .is_enabled = swclk_gate_is_enabled,
3481 .recalc_rate = swclk_recalc_rate,
3482
3483};
3484
3485static int rx_macro_register_mclk_output(struct rx_macro *rx)
3486{
3487 struct device *dev = rx->dev;
3488 const char *parent_clk_name = NULL;
3489 const char *clk_name = "lpass-rx-mclk";
3490 struct clk_hw *hw;
3491 struct clk_init_data init;
3492 int ret;
3493
3494 if (rx->npl)
3495 parent_clk_name = __clk_get_name(clk: rx->npl);
3496 else
3497 parent_clk_name = __clk_get_name(clk: rx->mclk);
3498
3499 init.name = clk_name;
3500 init.ops = &swclk_gate_ops;
3501 init.flags = 0;
3502 init.parent_names = &parent_clk_name;
3503 init.num_parents = 1;
3504 rx->hw.init = &init;
3505 hw = &rx->hw;
3506 ret = devm_clk_hw_register(dev: rx->dev, hw);
3507 if (ret)
3508 return ret;
3509
3510 return devm_of_clk_add_hw_provider(dev, get: of_clk_hw_simple_get, data: hw);
3511}
3512
3513static const struct snd_soc_component_driver rx_macro_component_drv = {
3514 .name = "RX-MACRO",
3515 .probe = rx_macro_component_probe,
3516 .controls = rx_macro_snd_controls,
3517 .num_controls = ARRAY_SIZE(rx_macro_snd_controls),
3518 .dapm_widgets = rx_macro_dapm_widgets,
3519 .num_dapm_widgets = ARRAY_SIZE(rx_macro_dapm_widgets),
3520 .dapm_routes = rx_audio_map,
3521 .num_dapm_routes = ARRAY_SIZE(rx_audio_map),
3522};
3523
3524static int rx_macro_probe(struct platform_device *pdev)
3525{
3526 struct device *dev = &pdev->dev;
3527 kernel_ulong_t flags;
3528 struct rx_macro *rx;
3529 void __iomem *base;
3530 int ret;
3531
3532 flags = (kernel_ulong_t)device_get_match_data(dev);
3533
3534 rx = devm_kzalloc(dev, size: sizeof(*rx), GFP_KERNEL);
3535 if (!rx)
3536 return -ENOMEM;
3537
3538 rx->macro = devm_clk_get_optional(dev, id: "macro");
3539 if (IS_ERR(ptr: rx->macro))
3540 return dev_err_probe(dev, err: PTR_ERR(ptr: rx->macro), fmt: "unable to get macro clock\n");
3541
3542 rx->dcodec = devm_clk_get_optional(dev, id: "dcodec");
3543 if (IS_ERR(ptr: rx->dcodec))
3544 return dev_err_probe(dev, err: PTR_ERR(ptr: rx->dcodec), fmt: "unable to get dcodec clock\n");
3545
3546 rx->mclk = devm_clk_get(dev, id: "mclk");
3547 if (IS_ERR(ptr: rx->mclk))
3548 return dev_err_probe(dev, err: PTR_ERR(ptr: rx->mclk), fmt: "unable to get mclk clock\n");
3549
3550 if (flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) {
3551 rx->npl = devm_clk_get(dev, id: "npl");
3552 if (IS_ERR(ptr: rx->npl))
3553 return dev_err_probe(dev, err: PTR_ERR(ptr: rx->npl), fmt: "unable to get npl clock\n");
3554 }
3555
3556 rx->fsgen = devm_clk_get(dev, id: "fsgen");
3557 if (IS_ERR(ptr: rx->fsgen))
3558 return dev_err_probe(dev, err: PTR_ERR(ptr: rx->fsgen), fmt: "unable to get fsgen clock\n");
3559
3560 rx->pds = lpass_macro_pds_init(dev);
3561 if (IS_ERR(ptr: rx->pds))
3562 return PTR_ERR(ptr: rx->pds);
3563
3564 base = devm_platform_ioremap_resource(pdev, index: 0);
3565 if (IS_ERR(ptr: base)) {
3566 ret = PTR_ERR(ptr: base);
3567 goto err;
3568 }
3569
3570 rx->regmap = devm_regmap_init_mmio(dev, base, &rx_regmap_config);
3571 if (IS_ERR(ptr: rx->regmap)) {
3572 ret = PTR_ERR(ptr: rx->regmap);
3573 goto err;
3574 }
3575
3576 dev_set_drvdata(dev, data: rx);
3577
3578 rx->dev = dev;
3579
3580 /* set MCLK and NPL rates */
3581 clk_set_rate(clk: rx->mclk, MCLK_FREQ);
3582 clk_set_rate(clk: rx->npl, MCLK_FREQ);
3583
3584 ret = clk_prepare_enable(clk: rx->macro);
3585 if (ret)
3586 goto err;
3587
3588 ret = clk_prepare_enable(clk: rx->dcodec);
3589 if (ret)
3590 goto err_dcodec;
3591
3592 ret = clk_prepare_enable(clk: rx->mclk);
3593 if (ret)
3594 goto err_mclk;
3595
3596 ret = clk_prepare_enable(clk: rx->npl);
3597 if (ret)
3598 goto err_npl;
3599
3600 ret = clk_prepare_enable(clk: rx->fsgen);
3601 if (ret)
3602 goto err_fsgen;
3603
3604 /* reset swr block */
3605 regmap_update_bits(map: rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3606 CDC_RX_SWR_RESET_MASK,
3607 CDC_RX_SWR_RESET);
3608
3609 regmap_update_bits(map: rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3610 CDC_RX_SWR_CLK_EN_MASK, val: 1);
3611
3612 regmap_update_bits(map: rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3613 CDC_RX_SWR_RESET_MASK, val: 0);
3614
3615 ret = devm_snd_soc_register_component(dev, component_driver: &rx_macro_component_drv,
3616 dai_drv: rx_macro_dai,
3617 ARRAY_SIZE(rx_macro_dai));
3618 if (ret)
3619 goto err_clkout;
3620
3621
3622 pm_runtime_set_autosuspend_delay(dev, delay: 3000);
3623 pm_runtime_use_autosuspend(dev);
3624 pm_runtime_mark_last_busy(dev);
3625 pm_runtime_set_active(dev);
3626 pm_runtime_enable(dev);
3627
3628 ret = rx_macro_register_mclk_output(rx);
3629 if (ret)
3630 goto err_clkout;
3631
3632 return 0;
3633
3634err_clkout:
3635 clk_disable_unprepare(clk: rx->fsgen);
3636err_fsgen:
3637 clk_disable_unprepare(clk: rx->npl);
3638err_npl:
3639 clk_disable_unprepare(clk: rx->mclk);
3640err_mclk:
3641 clk_disable_unprepare(clk: rx->dcodec);
3642err_dcodec:
3643 clk_disable_unprepare(clk: rx->macro);
3644err:
3645 lpass_macro_pds_exit(pds: rx->pds);
3646
3647 return ret;
3648}
3649
3650static void rx_macro_remove(struct platform_device *pdev)
3651{
3652 struct rx_macro *rx = dev_get_drvdata(dev: &pdev->dev);
3653
3654 clk_disable_unprepare(clk: rx->mclk);
3655 clk_disable_unprepare(clk: rx->npl);
3656 clk_disable_unprepare(clk: rx->fsgen);
3657 clk_disable_unprepare(clk: rx->macro);
3658 clk_disable_unprepare(clk: rx->dcodec);
3659
3660 lpass_macro_pds_exit(pds: rx->pds);
3661}
3662
3663static const struct of_device_id rx_macro_dt_match[] = {
3664 {
3665 .compatible = "qcom,sc7280-lpass-rx-macro",
3666 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
3667
3668 }, {
3669 .compatible = "qcom,sm8250-lpass-rx-macro",
3670 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
3671 }, {
3672 .compatible = "qcom,sm8450-lpass-rx-macro",
3673 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
3674 }, {
3675 .compatible = "qcom,sm8550-lpass-rx-macro",
3676 }, {
3677 .compatible = "qcom,sc8280xp-lpass-rx-macro",
3678 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
3679 },
3680 { }
3681};
3682MODULE_DEVICE_TABLE(of, rx_macro_dt_match);
3683
3684static int __maybe_unused rx_macro_runtime_suspend(struct device *dev)
3685{
3686 struct rx_macro *rx = dev_get_drvdata(dev);
3687
3688 regcache_cache_only(map: rx->regmap, enable: true);
3689 regcache_mark_dirty(map: rx->regmap);
3690
3691 clk_disable_unprepare(clk: rx->fsgen);
3692 clk_disable_unprepare(clk: rx->npl);
3693 clk_disable_unprepare(clk: rx->mclk);
3694
3695 return 0;
3696}
3697
3698static int __maybe_unused rx_macro_runtime_resume(struct device *dev)
3699{
3700 struct rx_macro *rx = dev_get_drvdata(dev);
3701 int ret;
3702
3703 ret = clk_prepare_enable(clk: rx->mclk);
3704 if (ret) {
3705 dev_err(dev, "unable to prepare mclk\n");
3706 return ret;
3707 }
3708
3709 ret = clk_prepare_enable(clk: rx->npl);
3710 if (ret) {
3711 dev_err(dev, "unable to prepare mclkx2\n");
3712 goto err_npl;
3713 }
3714
3715 ret = clk_prepare_enable(clk: rx->fsgen);
3716 if (ret) {
3717 dev_err(dev, "unable to prepare fsgen\n");
3718 goto err_fsgen;
3719 }
3720 regcache_cache_only(map: rx->regmap, enable: false);
3721 regcache_sync(map: rx->regmap);
3722
3723 return 0;
3724err_fsgen:
3725 clk_disable_unprepare(clk: rx->npl);
3726err_npl:
3727 clk_disable_unprepare(clk: rx->mclk);
3728
3729 return ret;
3730}
3731
3732static const struct dev_pm_ops rx_macro_pm_ops = {
3733 SET_RUNTIME_PM_OPS(rx_macro_runtime_suspend, rx_macro_runtime_resume, NULL)
3734};
3735
3736static struct platform_driver rx_macro_driver = {
3737 .driver = {
3738 .name = "rx_macro",
3739 .of_match_table = rx_macro_dt_match,
3740 .suppress_bind_attrs = true,
3741 .pm = &rx_macro_pm_ops,
3742 },
3743 .probe = rx_macro_probe,
3744 .remove_new = rx_macro_remove,
3745};
3746
3747module_platform_driver(rx_macro_driver);
3748
3749MODULE_DESCRIPTION("RX macro driver");
3750MODULE_LICENSE("GPL");
3751

source code of linux/sound/soc/codecs/lpass-rx-macro.c