1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * NAU88L24 ALSA SoC audio driver
4 *
5 * Copyright 2016 Nuvoton Technology Corp.
6 * Author: John Hsu <KCHSU0@nuvoton.com>
7 */
8
9#include <linux/module.h>
10#include <linux/delay.h>
11#include <linux/dmi.h>
12#include <linux/init.h>
13#include <linux/i2c.h>
14#include <linux/regmap.h>
15#include <linux/slab.h>
16#include <linux/clk.h>
17#include <linux/acpi.h>
18#include <linux/math64.h>
19#include <linux/semaphore.h>
20
21#include <sound/initval.h>
22#include <sound/tlv.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/jack.h>
28
29#include "nau8824.h"
30
31#define NAU8824_JD_ACTIVE_HIGH BIT(0)
32#define NAU8824_MONO_SPEAKER BIT(1)
33
34static int nau8824_quirk;
35static int quirk_override = -1;
36module_param_named(quirk, quirk_override, uint, 0444);
37MODULE_PARM_DESC(quirk, "Board-specific quirk override");
38
39static int nau8824_config_sysclk(struct nau8824 *nau8824,
40 int clk_id, unsigned int freq);
41static bool nau8824_is_jack_inserted(struct nau8824 *nau8824);
42
43/* the ADC threshold of headset */
44#define DMIC_CLK 3072000
45
46/* the ADC threshold of headset */
47#define HEADSET_SARADC_THD 0x80
48
49/* the parameter threshold of FLL */
50#define NAU_FREF_MAX 13500000
51#define NAU_FVCO_MAX 100000000
52#define NAU_FVCO_MIN 90000000
53
54/* scaling for mclk from sysclk_src output */
55static const struct nau8824_fll_attr mclk_src_scaling[] = {
56 { .param: 1, .val: 0x0 },
57 { 2, 0x2 },
58 { 4, 0x3 },
59 { 8, 0x4 },
60 { 16, 0x5 },
61 { 32, 0x6 },
62 { 3, 0x7 },
63 { 6, 0xa },
64 { 12, 0xb },
65 { 24, 0xc },
66};
67
68/* ratio for input clk freq */
69static const struct nau8824_fll_attr fll_ratio[] = {
70 { 512000, 0x01 },
71 { 256000, 0x02 },
72 { 128000, 0x04 },
73 { 64000, 0x08 },
74 { 32000, 0x10 },
75 { 8000, 0x20 },
76 { 4000, 0x40 },
77};
78
79static const struct nau8824_fll_attr fll_pre_scalar[] = {
80 { 1, 0x0 },
81 { 2, 0x1 },
82 { 4, 0x2 },
83 { 8, 0x3 },
84};
85
86/* the maximum frequency of CLK_ADC and CLK_DAC */
87#define CLK_DA_AD_MAX 6144000
88
89/* over sampling rate */
90static const struct nau8824_osr_attr osr_dac_sel[] = {
91 { 64, 2 }, /* OSR 64, SRC 1/4 */
92 { 256, 0 }, /* OSR 256, SRC 1 */
93 { 128, 1 }, /* OSR 128, SRC 1/2 */
94 { 0, 0 },
95 { 32, 3 }, /* OSR 32, SRC 1/8 */
96};
97
98static const struct nau8824_osr_attr osr_adc_sel[] = {
99 { 32, 3 }, /* OSR 32, SRC 1/8 */
100 { 64, 2 }, /* OSR 64, SRC 1/4 */
101 { 128, 1 }, /* OSR 128, SRC 1/2 */
102 { 256, 0 }, /* OSR 256, SRC 1 */
103};
104
105static const struct reg_default nau8824_reg_defaults[] = {
106 { NAU8824_REG_ENA_CTRL, 0x0000 },
107 { NAU8824_REG_CLK_GATING_ENA, 0x0000 },
108 { NAU8824_REG_CLK_DIVIDER, 0x0000 },
109 { NAU8824_REG_FLL1, 0x0000 },
110 { NAU8824_REG_FLL2, 0x3126 },
111 { NAU8824_REG_FLL3, 0x0008 },
112 { NAU8824_REG_FLL4, 0x0010 },
113 { NAU8824_REG_FLL5, 0xC000 },
114 { NAU8824_REG_FLL6, 0x6000 },
115 { NAU8824_REG_FLL_VCO_RSV, 0xF13C },
116 { NAU8824_REG_JACK_DET_CTRL, 0x0000 },
117 { NAU8824_REG_INTERRUPT_SETTING_1, 0x0000 },
118 { NAU8824_REG_IRQ, 0x0000 },
119 { NAU8824_REG_CLEAR_INT_REG, 0x0000 },
120 { NAU8824_REG_INTERRUPT_SETTING, 0x1000 },
121 { NAU8824_REG_SAR_ADC, 0x0015 },
122 { NAU8824_REG_VDET_COEFFICIENT, 0x0110 },
123 { NAU8824_REG_VDET_THRESHOLD_1, 0x0000 },
124 { NAU8824_REG_VDET_THRESHOLD_2, 0x0000 },
125 { NAU8824_REG_VDET_THRESHOLD_3, 0x0000 },
126 { NAU8824_REG_VDET_THRESHOLD_4, 0x0000 },
127 { NAU8824_REG_GPIO_SEL, 0x0000 },
128 { NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 0x000B },
129 { NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 0x0010 },
130 { NAU8824_REG_PORT0_LEFT_TIME_SLOT, 0x0000 },
131 { NAU8824_REG_PORT0_RIGHT_TIME_SLOT, 0x0000 },
132 { NAU8824_REG_TDM_CTRL, 0x0000 },
133 { NAU8824_REG_ADC_HPF_FILTER, 0x0000 },
134 { NAU8824_REG_ADC_FILTER_CTRL, 0x0002 },
135 { NAU8824_REG_DAC_FILTER_CTRL_1, 0x0000 },
136 { NAU8824_REG_DAC_FILTER_CTRL_2, 0x0000 },
137 { NAU8824_REG_NOTCH_FILTER_1, 0x0000 },
138 { NAU8824_REG_NOTCH_FILTER_2, 0x0000 },
139 { NAU8824_REG_EQ1_LOW, 0x112C },
140 { NAU8824_REG_EQ2_EQ3, 0x2C2C },
141 { NAU8824_REG_EQ4_EQ5, 0x2C2C },
142 { NAU8824_REG_ADC_CH0_DGAIN_CTRL, 0x0100 },
143 { NAU8824_REG_ADC_CH1_DGAIN_CTRL, 0x0100 },
144 { NAU8824_REG_ADC_CH2_DGAIN_CTRL, 0x0100 },
145 { NAU8824_REG_ADC_CH3_DGAIN_CTRL, 0x0100 },
146 { NAU8824_REG_DAC_MUTE_CTRL, 0x0000 },
147 { NAU8824_REG_DAC_CH0_DGAIN_CTRL, 0x0100 },
148 { NAU8824_REG_DAC_CH1_DGAIN_CTRL, 0x0100 },
149 { NAU8824_REG_ADC_TO_DAC_ST, 0x0000 },
150 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH01, 0x1486 },
151 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH01, 0x0F12 },
152 { NAU8824_REG_DRC_SLOPE_ADC_CH01, 0x25FF },
153 { NAU8824_REG_DRC_ATKDCY_ADC_CH01, 0x3457 },
154 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH23, 0x1486 },
155 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH23, 0x0F12 },
156 { NAU8824_REG_DRC_SLOPE_ADC_CH23, 0x25FF },
157 { NAU8824_REG_DRC_ATKDCY_ADC_CH23, 0x3457 },
158 { NAU8824_REG_DRC_GAINL_ADC0, 0x0200 },
159 { NAU8824_REG_DRC_GAINL_ADC1, 0x0200 },
160 { NAU8824_REG_DRC_GAINL_ADC2, 0x0200 },
161 { NAU8824_REG_DRC_GAINL_ADC3, 0x0200 },
162 { NAU8824_REG_DRC_KNEE_IP12_DAC, 0x1486 },
163 { NAU8824_REG_DRC_KNEE_IP34_DAC, 0x0F12 },
164 { NAU8824_REG_DRC_SLOPE_DAC, 0x25F9 },
165 { NAU8824_REG_DRC_ATKDCY_DAC, 0x3457 },
166 { NAU8824_REG_DRC_GAIN_DAC_CH0, 0x0200 },
167 { NAU8824_REG_DRC_GAIN_DAC_CH1, 0x0200 },
168 { NAU8824_REG_MODE, 0x0000 },
169 { NAU8824_REG_MODE1, 0x0000 },
170 { NAU8824_REG_MODE2, 0x0000 },
171 { NAU8824_REG_CLASSG, 0x0000 },
172 { NAU8824_REG_OTP_EFUSE, 0x0000 },
173 { NAU8824_REG_OTPDOUT_1, 0x0000 },
174 { NAU8824_REG_OTPDOUT_2, 0x0000 },
175 { NAU8824_REG_MISC_CTRL, 0x0000 },
176 { NAU8824_REG_I2C_TIMEOUT, 0xEFFF },
177 { NAU8824_REG_TEST_MODE, 0x0000 },
178 { NAU8824_REG_I2C_DEVICE_ID, 0x1AF1 },
179 { NAU8824_REG_SAR_ADC_DATA_OUT, 0x00FF },
180 { NAU8824_REG_BIAS_ADJ, 0x0000 },
181 { NAU8824_REG_PGA_GAIN, 0x0000 },
182 { NAU8824_REG_TRIM_SETTINGS, 0x0000 },
183 { NAU8824_REG_ANALOG_CONTROL_1, 0x0000 },
184 { NAU8824_REG_ANALOG_CONTROL_2, 0x0000 },
185 { NAU8824_REG_ENABLE_LO, 0x0000 },
186 { NAU8824_REG_GAIN_LO, 0x0000 },
187 { NAU8824_REG_CLASSD_GAIN_1, 0x0000 },
188 { NAU8824_REG_CLASSD_GAIN_2, 0x0000 },
189 { NAU8824_REG_ANALOG_ADC_1, 0x0011 },
190 { NAU8824_REG_ANALOG_ADC_2, 0x0020 },
191 { NAU8824_REG_RDAC, 0x0008 },
192 { NAU8824_REG_MIC_BIAS, 0x0006 },
193 { NAU8824_REG_HS_VOLUME_CONTROL, 0x0000 },
194 { NAU8824_REG_BOOST, 0x0000 },
195 { NAU8824_REG_FEPGA, 0x0000 },
196 { NAU8824_REG_FEPGA_II, 0x0000 },
197 { NAU8824_REG_FEPGA_SE, 0x0000 },
198 { NAU8824_REG_FEPGA_ATTENUATION, 0x0000 },
199 { NAU8824_REG_ATT_PORT0, 0x0000 },
200 { NAU8824_REG_ATT_PORT1, 0x0000 },
201 { NAU8824_REG_POWER_UP_CONTROL, 0x0000 },
202 { NAU8824_REG_CHARGE_PUMP_CONTROL, 0x0300 },
203 { NAU8824_REG_CHARGE_PUMP_INPUT, 0x0013 },
204};
205
206static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout)
207{
208 int ret;
209
210 if (timeout) {
211 ret = down_timeout(sem: &nau8824->jd_sem, jiffies: timeout);
212 if (ret < 0)
213 dev_warn(nau8824->dev, "Acquire semaphore timeout\n");
214 } else {
215 ret = down_interruptible(sem: &nau8824->jd_sem);
216 if (ret < 0)
217 dev_warn(nau8824->dev, "Acquire semaphore fail\n");
218 }
219
220 return ret;
221}
222
223static inline void nau8824_sema_release(struct nau8824 *nau8824)
224{
225 up(sem: &nau8824->jd_sem);
226}
227
228static bool nau8824_readable_reg(struct device *dev, unsigned int reg)
229{
230 switch (reg) {
231 case NAU8824_REG_ENA_CTRL ... NAU8824_REG_FLL_VCO_RSV:
232 case NAU8824_REG_JACK_DET_CTRL:
233 case NAU8824_REG_INTERRUPT_SETTING_1:
234 case NAU8824_REG_IRQ:
235 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
236 case NAU8824_REG_GPIO_SEL:
237 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
238 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
239 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
240 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 ... NAU8824_REG_DRC_GAINL_ADC3:
241 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_GAIN_DAC_CH1:
242 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
243 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
244 case NAU8824_REG_I2C_TIMEOUT:
245 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
246 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
247 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
248 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_INPUT:
249 return true;
250 default:
251 return false;
252 }
253
254}
255
256static bool nau8824_writeable_reg(struct device *dev, unsigned int reg)
257{
258 switch (reg) {
259 case NAU8824_REG_RESET ... NAU8824_REG_FLL_VCO_RSV:
260 case NAU8824_REG_JACK_DET_CTRL:
261 case NAU8824_REG_INTERRUPT_SETTING_1:
262 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
263 case NAU8824_REG_GPIO_SEL:
264 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
265 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
266 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
267 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01:
268 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH01:
269 case NAU8824_REG_DRC_SLOPE_ADC_CH01:
270 case NAU8824_REG_DRC_ATKDCY_ADC_CH01:
271 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH23:
272 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH23:
273 case NAU8824_REG_DRC_SLOPE_ADC_CH23:
274 case NAU8824_REG_DRC_ATKDCY_ADC_CH23:
275 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_ATKDCY_DAC:
276 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
277 case NAU8824_REG_I2C_TIMEOUT:
278 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
279 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
280 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_CONTROL:
281 return true;
282 default:
283 return false;
284 }
285}
286
287static bool nau8824_volatile_reg(struct device *dev, unsigned int reg)
288{
289 switch (reg) {
290 case NAU8824_REG_RESET:
291 case NAU8824_REG_IRQ ... NAU8824_REG_CLEAR_INT_REG:
292 case NAU8824_REG_DRC_GAINL_ADC0 ... NAU8824_REG_DRC_GAINL_ADC3:
293 case NAU8824_REG_DRC_GAIN_DAC_CH0 ... NAU8824_REG_DRC_GAIN_DAC_CH1:
294 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
295 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
296 case NAU8824_REG_CHARGE_PUMP_INPUT:
297 return true;
298 default:
299 return false;
300 }
301}
302
303static const char * const nau8824_companding[] = {
304 "Off", "NC", "u-law", "A-law" };
305
306static const struct soc_enum nau8824_companding_adc_enum =
307 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 12,
308 ARRAY_SIZE(nau8824_companding), nau8824_companding);
309
310static const struct soc_enum nau8824_companding_dac_enum =
311 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 14,
312 ARRAY_SIZE(nau8824_companding), nau8824_companding);
313
314static const char * const nau8824_adc_decimation[] = {
315 "32", "64", "128", "256" };
316
317static const struct soc_enum nau8824_adc_decimation_enum =
318 SOC_ENUM_SINGLE(NAU8824_REG_ADC_FILTER_CTRL, 0,
319 ARRAY_SIZE(nau8824_adc_decimation), nau8824_adc_decimation);
320
321static const char * const nau8824_dac_oversampl[] = {
322 "64", "256", "128", "", "32" };
323
324static const struct soc_enum nau8824_dac_oversampl_enum =
325 SOC_ENUM_SINGLE(NAU8824_REG_DAC_FILTER_CTRL_1, 0,
326 ARRAY_SIZE(nau8824_dac_oversampl), nau8824_dac_oversampl);
327
328static const char * const nau8824_input_channel[] = {
329 "Input CH0", "Input CH1", "Input CH2", "Input CH3" };
330
331static const struct soc_enum nau8824_adc_ch0_enum =
332 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH0_DGAIN_CTRL, 9,
333 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
334
335static const struct soc_enum nau8824_adc_ch1_enum =
336 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH1_DGAIN_CTRL, 9,
337 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
338
339static const struct soc_enum nau8824_adc_ch2_enum =
340 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH2_DGAIN_CTRL, 9,
341 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
342
343static const struct soc_enum nau8824_adc_ch3_enum =
344 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH3_DGAIN_CTRL, 9,
345 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
346
347static const char * const nau8824_tdm_slot[] = {
348 "Slot 0", "Slot 1", "Slot 2", "Slot 3" };
349
350static const struct soc_enum nau8824_dac_left_sel_enum =
351 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 6,
352 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
353
354static const struct soc_enum nau8824_dac_right_sel_enum =
355 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 4,
356 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
357
358static const DECLARE_TLV_DB_MINMAX_MUTE(spk_vol_tlv, 0, 2400);
359static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0);
360static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 200, 0);
361static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0);
362
363static const struct snd_kcontrol_new nau8824_snd_controls[] = {
364 SOC_ENUM("ADC Companding", nau8824_companding_adc_enum),
365 SOC_ENUM("DAC Companding", nau8824_companding_dac_enum),
366
367 SOC_ENUM("ADC Decimation Rate", nau8824_adc_decimation_enum),
368 SOC_ENUM("DAC Oversampling Rate", nau8824_dac_oversampl_enum),
369
370 SOC_SINGLE_TLV("Speaker Right DACR Volume",
371 NAU8824_REG_CLASSD_GAIN_1, 8, 0x1f, 0, spk_vol_tlv),
372 SOC_SINGLE_TLV("Speaker Left DACL Volume",
373 NAU8824_REG_CLASSD_GAIN_2, 0, 0x1f, 0, spk_vol_tlv),
374 SOC_SINGLE_TLV("Speaker Left DACR Volume",
375 NAU8824_REG_CLASSD_GAIN_1, 0, 0x1f, 0, spk_vol_tlv),
376 SOC_SINGLE_TLV("Speaker Right DACL Volume",
377 NAU8824_REG_CLASSD_GAIN_2, 8, 0x1f, 0, spk_vol_tlv),
378
379 SOC_SINGLE_TLV("Headphone Right DACR Volume",
380 NAU8824_REG_ATT_PORT0, 8, 0x1f, 0, hp_vol_tlv),
381 SOC_SINGLE_TLV("Headphone Left DACL Volume",
382 NAU8824_REG_ATT_PORT0, 0, 0x1f, 0, hp_vol_tlv),
383 SOC_SINGLE_TLV("Headphone Right DACL Volume",
384 NAU8824_REG_ATT_PORT1, 8, 0x1f, 0, hp_vol_tlv),
385 SOC_SINGLE_TLV("Headphone Left DACR Volume",
386 NAU8824_REG_ATT_PORT1, 0, 0x1f, 0, hp_vol_tlv),
387
388 SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II,
389 NAU8824_FEPGA_GAINL_SFT, 0x12, 0, mic_vol_tlv),
390 SOC_SINGLE_TLV("MIC2 Volume", NAU8824_REG_FEPGA_II,
391 NAU8824_FEPGA_GAINR_SFT, 0x12, 0, mic_vol_tlv),
392
393 SOC_SINGLE_TLV("DMIC1 Volume", NAU8824_REG_ADC_CH0_DGAIN_CTRL,
394 0, 0x164, 0, dmic_vol_tlv),
395 SOC_SINGLE_TLV("DMIC2 Volume", NAU8824_REG_ADC_CH1_DGAIN_CTRL,
396 0, 0x164, 0, dmic_vol_tlv),
397 SOC_SINGLE_TLV("DMIC3 Volume", NAU8824_REG_ADC_CH2_DGAIN_CTRL,
398 0, 0x164, 0, dmic_vol_tlv),
399 SOC_SINGLE_TLV("DMIC4 Volume", NAU8824_REG_ADC_CH3_DGAIN_CTRL,
400 0, 0x164, 0, dmic_vol_tlv),
401
402 SOC_ENUM("ADC CH0 Select", nau8824_adc_ch0_enum),
403 SOC_ENUM("ADC CH1 Select", nau8824_adc_ch1_enum),
404 SOC_ENUM("ADC CH2 Select", nau8824_adc_ch2_enum),
405 SOC_ENUM("ADC CH3 Select", nau8824_adc_ch3_enum),
406
407 SOC_SINGLE("ADC CH0 TX Switch", NAU8824_REG_TDM_CTRL, 0, 1, 0),
408 SOC_SINGLE("ADC CH1 TX Switch", NAU8824_REG_TDM_CTRL, 1, 1, 0),
409 SOC_SINGLE("ADC CH2 TX Switch", NAU8824_REG_TDM_CTRL, 2, 1, 0),
410 SOC_SINGLE("ADC CH3 TX Switch", NAU8824_REG_TDM_CTRL, 3, 1, 0),
411
412 SOC_ENUM("DACL Channel Source", nau8824_dac_left_sel_enum),
413 SOC_ENUM("DACR Channel Source", nau8824_dac_right_sel_enum),
414
415 SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0),
416 SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0),
417
418 SOC_SINGLE("THD for key media",
419 NAU8824_REG_VDET_THRESHOLD_1, 8, 0xff, 0),
420 SOC_SINGLE("THD for key voice command",
421 NAU8824_REG_VDET_THRESHOLD_1, 0, 0xff, 0),
422 SOC_SINGLE("THD for key volume up",
423 NAU8824_REG_VDET_THRESHOLD_2, 8, 0xff, 0),
424 SOC_SINGLE("THD for key volume down",
425 NAU8824_REG_VDET_THRESHOLD_2, 0, 0xff, 0),
426};
427
428static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w,
429 struct snd_kcontrol *kcontrol, int event)
430{
431 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
432 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
433
434 switch (event) {
435 case SND_SOC_DAPM_PRE_PMU:
436 /* Disables the TESTDAC to let DAC signal pass through. */
437 regmap_update_bits(map: nau8824->regmap, NAU8824_REG_ENABLE_LO,
438 NAU8824_TEST_DAC_EN, val: 0);
439 break;
440 case SND_SOC_DAPM_POST_PMD:
441 regmap_update_bits(map: nau8824->regmap, NAU8824_REG_ENABLE_LO,
442 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);
443 break;
444 default:
445 return -EINVAL;
446 }
447
448 return 0;
449}
450
451static int nau8824_spk_event(struct snd_soc_dapm_widget *w,
452 struct snd_kcontrol *kcontrol, int event)
453{
454 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
455 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
456
457 switch (event) {
458 case SND_SOC_DAPM_PRE_PMU:
459 regmap_update_bits(map: nau8824->regmap,
460 NAU8824_REG_ANALOG_CONTROL_2,
461 NAU8824_CLASSD_CLAMP_DIS, NAU8824_CLASSD_CLAMP_DIS);
462 break;
463 case SND_SOC_DAPM_POST_PMD:
464 regmap_update_bits(map: nau8824->regmap,
465 NAU8824_REG_ANALOG_CONTROL_2,
466 NAU8824_CLASSD_CLAMP_DIS, val: 0);
467 break;
468 default:
469 return -EINVAL;
470 }
471
472 return 0;
473}
474
475static int nau8824_pump_event(struct snd_soc_dapm_widget *w,
476 struct snd_kcontrol *kcontrol, int event)
477{
478 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
479 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
480
481 switch (event) {
482 case SND_SOC_DAPM_POST_PMU:
483 /* Prevent startup click by letting charge pump to ramp up */
484 msleep(msecs: 10);
485 regmap_update_bits(map: nau8824->regmap,
486 NAU8824_REG_CHARGE_PUMP_CONTROL,
487 NAU8824_JAMNODCLOW, NAU8824_JAMNODCLOW);
488 break;
489 case SND_SOC_DAPM_PRE_PMD:
490 regmap_update_bits(map: nau8824->regmap,
491 NAU8824_REG_CHARGE_PUMP_CONTROL,
492 NAU8824_JAMNODCLOW, val: 0);
493 break;
494 default:
495 return -EINVAL;
496 }
497
498 return 0;
499}
500
501static int system_clock_control(struct snd_soc_dapm_widget *w,
502 struct snd_kcontrol *k, int event)
503{
504 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
505 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
506 struct regmap *regmap = nau8824->regmap;
507 unsigned int value;
508 bool clk_fll, error;
509
510 if (SND_SOC_DAPM_EVENT_OFF(event)) {
511 dev_dbg(nau8824->dev, "system clock control : POWER OFF\n");
512 /* Set clock source to disable or internal clock before the
513 * playback or capture end. Codec needs clock for Jack
514 * detection and button press if jack inserted; otherwise,
515 * the clock should be closed.
516 */
517 if (nau8824_is_jack_inserted(nau8824)) {
518 nau8824_config_sysclk(nau8824,
519 clk_id: NAU8824_CLK_INTERNAL, freq: 0);
520 } else {
521 nau8824_config_sysclk(nau8824, clk_id: NAU8824_CLK_DIS, freq: 0);
522 }
523 } else {
524 dev_dbg(nau8824->dev, "system clock control : POWER ON\n");
525 /* Check the clock source setting is proper or not
526 * no matter the source is from FLL or MCLK.
527 */
528 regmap_read(map: regmap, NAU8824_REG_FLL1, val: &value);
529 clk_fll = value & NAU8824_FLL_RATIO_MASK;
530 /* It's error to use internal clock when playback */
531 regmap_read(map: regmap, NAU8824_REG_FLL6, val: &value);
532 error = value & NAU8824_DCO_EN;
533 if (!error) {
534 /* Check error depending on source is FLL or MCLK. */
535 regmap_read(map: regmap, NAU8824_REG_CLK_DIVIDER, val: &value);
536 if (clk_fll)
537 error = !(value & NAU8824_CLK_SRC_VCO);
538 else
539 error = value & NAU8824_CLK_SRC_VCO;
540 }
541 /* Recover the clock source setting if error. */
542 if (error) {
543 if (clk_fll) {
544 regmap_update_bits(map: regmap,
545 NAU8824_REG_FLL6, NAU8824_DCO_EN, val: 0);
546 regmap_update_bits(map: regmap,
547 NAU8824_REG_CLK_DIVIDER,
548 NAU8824_CLK_SRC_MASK,
549 NAU8824_CLK_SRC_VCO);
550 } else {
551 nau8824_config_sysclk(nau8824,
552 clk_id: NAU8824_CLK_MCLK, freq: 0);
553 }
554 }
555 }
556
557 return 0;
558}
559
560static int dmic_clock_control(struct snd_soc_dapm_widget *w,
561 struct snd_kcontrol *k, int event)
562{
563 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm);
564 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
565 int src;
566
567 /* The DMIC clock is gotten from system clock (256fs) divided by
568 * DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or
569 * less than 3.072 MHz.
570 */
571 for (src = 0; src < 5; src++) {
572 if ((0x1 << (8 - src)) * nau8824->fs <= DMIC_CLK)
573 break;
574 }
575 dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, nau8824->fs * 256);
576 regmap_update_bits(map: nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
577 NAU8824_CLK_DMIC_SRC_MASK, val: (src << NAU8824_CLK_DMIC_SRC_SFT));
578
579 return 0;
580}
581
582static const struct snd_kcontrol_new nau8824_adc_ch0_dmic =
583 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
584 NAU8824_ADC_CH0_DMIC_SFT, 1, 0);
585
586static const struct snd_kcontrol_new nau8824_adc_ch1_dmic =
587 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
588 NAU8824_ADC_CH1_DMIC_SFT, 1, 0);
589
590static const struct snd_kcontrol_new nau8824_adc_ch2_dmic =
591 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
592 NAU8824_ADC_CH2_DMIC_SFT, 1, 0);
593
594static const struct snd_kcontrol_new nau8824_adc_ch3_dmic =
595 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
596 NAU8824_ADC_CH3_DMIC_SFT, 1, 0);
597
598static const struct snd_kcontrol_new nau8824_adc_left_mixer[] = {
599 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
600 NAU8824_FEPGA_MODEL_MIC1_SFT, 1, 0),
601 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
602 NAU8824_FEPGA_MODEL_HSMIC_SFT, 1, 0),
603};
604
605static const struct snd_kcontrol_new nau8824_adc_right_mixer[] = {
606 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
607 NAU8824_FEPGA_MODER_MIC2_SFT, 1, 0),
608 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
609 NAU8824_FEPGA_MODER_HSMIC_SFT, 1, 0),
610};
611
612static const struct snd_kcontrol_new nau8824_hp_left_mixer[] = {
613 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
614 NAU8824_DACR_HPL_EN_SFT, 1, 0),
615 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
616 NAU8824_DACL_HPL_EN_SFT, 1, 0),
617};
618
619static const struct snd_kcontrol_new nau8824_hp_right_mixer[] = {
620 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
621 NAU8824_DACL_HPR_EN_SFT, 1, 0),
622 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
623 NAU8824_DACR_HPR_EN_SFT, 1, 0),
624};
625
626static const char * const nau8824_dac_src[] = { "DACL", "DACR" };
627
628static SOC_ENUM_SINGLE_DECL(
629 nau8824_dacl_enum, NAU8824_REG_DAC_CH0_DGAIN_CTRL,
630 NAU8824_DAC_CH0_SEL_SFT, nau8824_dac_src);
631
632static SOC_ENUM_SINGLE_DECL(
633 nau8824_dacr_enum, NAU8824_REG_DAC_CH1_DGAIN_CTRL,
634 NAU8824_DAC_CH1_SEL_SFT, nau8824_dac_src);
635
636static const struct snd_kcontrol_new nau8824_dacl_mux =
637 SOC_DAPM_ENUM("DACL Source", nau8824_dacl_enum);
638
639static const struct snd_kcontrol_new nau8824_dacr_mux =
640 SOC_DAPM_ENUM("DACR Source", nau8824_dacr_enum);
641
642
643static const struct snd_soc_dapm_widget nau8824_dapm_widgets[] = {
644 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
645 system_clock_control, SND_SOC_DAPM_POST_PMD |
646 SND_SOC_DAPM_POST_PMU),
647
648 SND_SOC_DAPM_INPUT("HSMIC1"),
649 SND_SOC_DAPM_INPUT("HSMIC2"),
650 SND_SOC_DAPM_INPUT("MIC1"),
651 SND_SOC_DAPM_INPUT("MIC2"),
652 SND_SOC_DAPM_INPUT("DMIC1"),
653 SND_SOC_DAPM_INPUT("DMIC2"),
654 SND_SOC_DAPM_INPUT("DMIC3"),
655 SND_SOC_DAPM_INPUT("DMIC4"),
656
657 SND_SOC_DAPM_SUPPLY("SAR", NAU8824_REG_SAR_ADC,
658 NAU8824_SAR_ADC_EN_SFT, 0, NULL, 0),
659 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8824_REG_MIC_BIAS,
660 NAU8824_MICBIAS_POWERUP_SFT, 0, NULL, 0),
661 SND_SOC_DAPM_SUPPLY("DMIC12 Power", NAU8824_REG_BIAS_ADJ,
662 NAU8824_DMIC1_EN_SFT, 0, NULL, 0),
663 SND_SOC_DAPM_SUPPLY("DMIC34 Power", NAU8824_REG_BIAS_ADJ,
664 NAU8824_DMIC2_EN_SFT, 0, NULL, 0),
665 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
666 dmic_clock_control, SND_SOC_DAPM_POST_PMU),
667
668 SND_SOC_DAPM_SWITCH("DMIC1 Enable", SND_SOC_NOPM,
669 0, 0, &nau8824_adc_ch0_dmic),
670 SND_SOC_DAPM_SWITCH("DMIC2 Enable", SND_SOC_NOPM,
671 0, 0, &nau8824_adc_ch1_dmic),
672 SND_SOC_DAPM_SWITCH("DMIC3 Enable", SND_SOC_NOPM,
673 0, 0, &nau8824_adc_ch2_dmic),
674 SND_SOC_DAPM_SWITCH("DMIC4 Enable", SND_SOC_NOPM,
675 0, 0, &nau8824_adc_ch3_dmic),
676
677 SND_SOC_DAPM_MIXER("Left ADC", NAU8824_REG_POWER_UP_CONTROL,
678 12, 0, nau8824_adc_left_mixer,
679 ARRAY_SIZE(nau8824_adc_left_mixer)),
680 SND_SOC_DAPM_MIXER("Right ADC", NAU8824_REG_POWER_UP_CONTROL,
681 13, 0, nau8824_adc_right_mixer,
682 ARRAY_SIZE(nau8824_adc_right_mixer)),
683
684 SND_SOC_DAPM_ADC("ADCL", NULL, NAU8824_REG_ANALOG_ADC_2,
685 NAU8824_ADCL_EN_SFT, 0),
686 SND_SOC_DAPM_ADC("ADCR", NULL, NAU8824_REG_ANALOG_ADC_2,
687 NAU8824_ADCR_EN_SFT, 0),
688
689 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0),
690 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
691
692 SND_SOC_DAPM_DAC("DACL", NULL, NAU8824_REG_RDAC,
693 NAU8824_DACL_EN_SFT, 0),
694 SND_SOC_DAPM_SUPPLY("DACL Clock", NAU8824_REG_RDAC,
695 NAU8824_DACL_CLK_SFT, 0, NULL, 0),
696 SND_SOC_DAPM_DAC("DACR", NULL, NAU8824_REG_RDAC,
697 NAU8824_DACR_EN_SFT, 0),
698 SND_SOC_DAPM_SUPPLY("DACR Clock", NAU8824_REG_RDAC,
699 NAU8824_DACR_CLK_SFT, 0, NULL, 0),
700
701 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacl_mux),
702 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacr_mux),
703
704 SND_SOC_DAPM_PGA_S("Output DACL", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
705 8, 1, nau8824_output_dac_event,
706 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
707 SND_SOC_DAPM_PGA_S("Output DACR", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
708 9, 1, nau8824_output_dac_event,
709 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
710
711 SND_SOC_DAPM_PGA_S("ClassD", 0, NAU8824_REG_CLASSD_GAIN_1,
712 NAU8824_CLASSD_EN_SFT, 0, nau8824_spk_event,
713 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
714
715 SND_SOC_DAPM_MIXER("Left Headphone", NAU8824_REG_CLASSG,
716 NAU8824_CLASSG_LDAC_EN_SFT, 0, nau8824_hp_left_mixer,
717 ARRAY_SIZE(nau8824_hp_left_mixer)),
718 SND_SOC_DAPM_MIXER("Right Headphone", NAU8824_REG_CLASSG,
719 NAU8824_CLASSG_RDAC_EN_SFT, 0, nau8824_hp_right_mixer,
720 ARRAY_SIZE(nau8824_hp_right_mixer)),
721 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8824_REG_CHARGE_PUMP_CONTROL,
722 NAU8824_CHARGE_PUMP_EN_SFT, 0, nau8824_pump_event,
723 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
724 SND_SOC_DAPM_PGA("Output Driver L",
725 NAU8824_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
726 SND_SOC_DAPM_PGA("Output Driver R",
727 NAU8824_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
728 SND_SOC_DAPM_PGA("Main Driver L",
729 NAU8824_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
730 SND_SOC_DAPM_PGA("Main Driver R",
731 NAU8824_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
732 SND_SOC_DAPM_PGA("HP Boost Driver", NAU8824_REG_BOOST,
733 NAU8824_HP_BOOST_DIS_SFT, 1, NULL, 0),
734 SND_SOC_DAPM_PGA("Class G", NAU8824_REG_CLASSG,
735 NAU8824_CLASSG_EN_SFT, 0, NULL, 0),
736
737 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
738 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
739 SND_SOC_DAPM_OUTPUT("HPOL"),
740 SND_SOC_DAPM_OUTPUT("HPOR"),
741};
742
743static const struct snd_soc_dapm_route nau8824_dapm_routes[] = {
744 {"DMIC1 Enable", "Switch", "DMIC1"},
745 {"DMIC2 Enable", "Switch", "DMIC2"},
746 {"DMIC3 Enable", "Switch", "DMIC3"},
747 {"DMIC4 Enable", "Switch", "DMIC4"},
748
749 {"DMIC1", NULL, "DMIC12 Power"},
750 {"DMIC2", NULL, "DMIC12 Power"},
751 {"DMIC3", NULL, "DMIC34 Power"},
752 {"DMIC4", NULL, "DMIC34 Power"},
753 {"DMIC12 Power", NULL, "DMIC Clock"},
754 {"DMIC34 Power", NULL, "DMIC Clock"},
755
756 {"Left ADC", "MIC Switch", "MIC1"},
757 {"Left ADC", "HSMIC Switch", "HSMIC1"},
758 {"Right ADC", "MIC Switch", "MIC2"},
759 {"Right ADC", "HSMIC Switch", "HSMIC2"},
760
761 {"ADCL", NULL, "Left ADC"},
762 {"ADCR", NULL, "Right ADC"},
763
764 {"AIFTX", NULL, "MICBIAS"},
765 {"AIFTX", NULL, "ADCL"},
766 {"AIFTX", NULL, "ADCR"},
767 {"AIFTX", NULL, "DMIC1 Enable"},
768 {"AIFTX", NULL, "DMIC2 Enable"},
769 {"AIFTX", NULL, "DMIC3 Enable"},
770 {"AIFTX", NULL, "DMIC4 Enable"},
771
772 {"AIFTX", NULL, "System Clock"},
773 {"AIFRX", NULL, "System Clock"},
774
775 {"DACL", NULL, "AIFRX"},
776 {"DACL", NULL, "DACL Clock"},
777 {"DACR", NULL, "AIFRX"},
778 {"DACR", NULL, "DACR Clock"},
779
780 {"DACL Mux", "DACL", "DACL"},
781 {"DACL Mux", "DACR", "DACR"},
782 {"DACR Mux", "DACL", "DACL"},
783 {"DACR Mux", "DACR", "DACR"},
784
785 {"Output DACL", NULL, "DACL Mux"},
786 {"Output DACR", NULL, "DACR Mux"},
787
788 {"ClassD", NULL, "Output DACL"},
789 {"ClassD", NULL, "Output DACR"},
790
791 {"Left Headphone", "DAC Left Switch", "Output DACL"},
792 {"Left Headphone", "DAC Right Switch", "Output DACR"},
793 {"Right Headphone", "DAC Left Switch", "Output DACL"},
794 {"Right Headphone", "DAC Right Switch", "Output DACR"},
795
796 {"Charge Pump", NULL, "Left Headphone"},
797 {"Charge Pump", NULL, "Right Headphone"},
798 {"Output Driver L", NULL, "Charge Pump"},
799 {"Output Driver R", NULL, "Charge Pump"},
800 {"Main Driver L", NULL, "Output Driver L"},
801 {"Main Driver R", NULL, "Output Driver R"},
802 {"Class G", NULL, "Main Driver L"},
803 {"Class G", NULL, "Main Driver R"},
804 {"HP Boost Driver", NULL, "Class G"},
805
806 {"SPKOUTL", NULL, "ClassD"},
807 {"SPKOUTR", NULL, "ClassD"},
808 {"HPOL", NULL, "HP Boost Driver"},
809 {"HPOR", NULL, "HP Boost Driver"},
810};
811
812static bool nau8824_is_jack_inserted(struct nau8824 *nau8824)
813{
814 struct snd_soc_jack *jack = nau8824->jack;
815 bool insert = false;
816
817 if (nau8824->irq && jack)
818 insert = jack->status & SND_JACK_HEADPHONE;
819
820 return insert;
821}
822
823static void nau8824_int_status_clear_all(struct regmap *regmap)
824{
825 int active_irq, clear_irq, i;
826
827 /* Reset the intrruption status from rightmost bit if the corres-
828 * ponding irq event occurs.
829 */
830 regmap_read(map: regmap, NAU8824_REG_IRQ, val: &active_irq);
831 for (i = 0; i < NAU8824_REG_DATA_LEN; i++) {
832 clear_irq = (0x1 << i);
833 if (active_irq & clear_irq)
834 regmap_write(map: regmap,
835 NAU8824_REG_CLEAR_INT_REG, val: clear_irq);
836 }
837}
838
839static void nau8824_eject_jack(struct nau8824 *nau8824)
840{
841 struct snd_soc_dapm_context *dapm = nau8824->dapm;
842 struct regmap *regmap = nau8824->regmap;
843
844 /* Clear all interruption status */
845 nau8824_int_status_clear_all(regmap);
846
847 snd_soc_dapm_disable_pin(dapm, pin: "SAR");
848 snd_soc_dapm_disable_pin(dapm, pin: "MICBIAS");
849 snd_soc_dapm_sync(dapm);
850
851 /* Enable the insertion interruption, disable the ejection
852 * interruption, and then bypass de-bounce circuit.
853 */
854 regmap_update_bits(map: regmap, NAU8824_REG_INTERRUPT_SETTING,
855 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
856 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS,
857 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
858 NAU8824_IRQ_EJECT_DIS);
859 regmap_update_bits(map: regmap, NAU8824_REG_INTERRUPT_SETTING_1,
860 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
861 NAU8824_IRQ_INSERT_EN);
862 regmap_update_bits(map: regmap, NAU8824_REG_ENA_CTRL,
863 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
864
865 /* Close clock for jack type detection at manual mode */
866 if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
867 nau8824_config_sysclk(nau8824, clk_id: NAU8824_CLK_DIS, freq: 0);
868}
869
870static void nau8824_jdet_work(struct work_struct *work)
871{
872 struct nau8824 *nau8824 = container_of(
873 work, struct nau8824, jdet_work);
874 struct snd_soc_dapm_context *dapm = nau8824->dapm;
875 struct regmap *regmap = nau8824->regmap;
876 int adc_value, event = 0, event_mask = 0;
877
878 snd_soc_dapm_force_enable_pin(dapm, pin: "MICBIAS");
879 snd_soc_dapm_force_enable_pin(dapm, pin: "SAR");
880 snd_soc_dapm_sync(dapm);
881
882 msleep(msecs: 100);
883
884 regmap_read(map: regmap, NAU8824_REG_SAR_ADC_DATA_OUT, val: &adc_value);
885 adc_value = adc_value & NAU8824_SAR_ADC_DATA_MASK;
886 dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value);
887 if (adc_value < HEADSET_SARADC_THD) {
888 event |= SND_JACK_HEADPHONE;
889
890 snd_soc_dapm_disable_pin(dapm, pin: "SAR");
891 snd_soc_dapm_disable_pin(dapm, pin: "MICBIAS");
892 snd_soc_dapm_sync(dapm);
893 } else {
894 event |= SND_JACK_HEADSET;
895 }
896 event_mask |= SND_JACK_HEADSET;
897 snd_soc_jack_report(jack: nau8824->jack, status: event, mask: event_mask);
898
899 /* Enable short key press and release interruption. */
900 regmap_update_bits(map: regmap, NAU8824_REG_INTERRUPT_SETTING,
901 NAU8824_IRQ_KEY_RELEASE_DIS |
902 NAU8824_IRQ_KEY_SHORT_PRESS_DIS, val: 0);
903
904 if (nau8824->resume_lock) {
905 nau8824_sema_release(nau8824);
906 nau8824->resume_lock = false;
907 }
908}
909
910static void nau8824_setup_auto_irq(struct nau8824 *nau8824)
911{
912 struct regmap *regmap = nau8824->regmap;
913
914 /* Enable jack ejection interruption. */
915 regmap_update_bits(map: regmap, NAU8824_REG_INTERRUPT_SETTING_1,
916 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
917 NAU8824_IRQ_EJECT_EN);
918 regmap_update_bits(map: regmap, NAU8824_REG_INTERRUPT_SETTING,
919 NAU8824_IRQ_EJECT_DIS, val: 0);
920 /* Enable internal VCO needed for interruptions */
921 if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE)
922 nau8824_config_sysclk(nau8824, clk_id: NAU8824_CLK_INTERNAL, freq: 0);
923 regmap_update_bits(map: regmap, NAU8824_REG_ENA_CTRL,
924 NAU8824_JD_SLEEP_MODE, val: 0);
925}
926
927static int nau8824_button_decode(int value)
928{
929 int buttons = 0;
930
931 /* The chip supports up to 8 buttons, but ALSA defines
932 * only 6 buttons.
933 */
934 if (value & BIT(0))
935 buttons |= SND_JACK_BTN_0;
936 if (value & BIT(1))
937 buttons |= SND_JACK_BTN_1;
938 if (value & BIT(2))
939 buttons |= SND_JACK_BTN_2;
940 if (value & BIT(3))
941 buttons |= SND_JACK_BTN_3;
942 if (value & BIT(4))
943 buttons |= SND_JACK_BTN_4;
944 if (value & BIT(5))
945 buttons |= SND_JACK_BTN_5;
946
947 return buttons;
948}
949
950#define NAU8824_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
951 SND_JACK_BTN_2 | SND_JACK_BTN_3)
952
953static irqreturn_t nau8824_interrupt(int irq, void *data)
954{
955 struct nau8824 *nau8824 = (struct nau8824 *)data;
956 struct regmap *regmap = nau8824->regmap;
957 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
958
959 if (regmap_read(map: regmap, NAU8824_REG_IRQ, val: &active_irq)) {
960 dev_err(nau8824->dev, "failed to read irq status\n");
961 return IRQ_NONE;
962 }
963 dev_dbg(nau8824->dev, "IRQ %x\n", active_irq);
964
965 if (active_irq & NAU8824_JACK_EJECTION_DETECTED) {
966 nau8824_eject_jack(nau8824);
967 event_mask |= SND_JACK_HEADSET;
968 clear_irq = NAU8824_JACK_EJECTION_DETECTED;
969 /* release semaphore held after resume,
970 * and cancel jack detection
971 */
972 if (nau8824->resume_lock) {
973 nau8824_sema_release(nau8824);
974 nau8824->resume_lock = false;
975 }
976 cancel_work_sync(work: &nau8824->jdet_work);
977 } else if (active_irq & NAU8824_KEY_SHORT_PRESS_IRQ) {
978 int key_status, button_pressed;
979
980 regmap_read(map: regmap, NAU8824_REG_CLEAR_INT_REG,
981 val: &key_status);
982
983 /* lower 8 bits of the register are for pressed keys */
984 button_pressed = nau8824_button_decode(value: key_status);
985
986 event |= button_pressed;
987 dev_dbg(nau8824->dev, "button %x pressed\n", event);
988 event_mask |= NAU8824_BUTTONS;
989 clear_irq = NAU8824_KEY_SHORT_PRESS_IRQ;
990 } else if (active_irq & NAU8824_KEY_RELEASE_IRQ) {
991 event_mask = NAU8824_BUTTONS;
992 clear_irq = NAU8824_KEY_RELEASE_IRQ;
993 } else if (active_irq & NAU8824_JACK_INSERTION_DETECTED) {
994 /* Turn off insertion interruption at manual mode */
995 regmap_update_bits(map: regmap,
996 NAU8824_REG_INTERRUPT_SETTING,
997 NAU8824_IRQ_INSERT_DIS,
998 NAU8824_IRQ_INSERT_DIS);
999 regmap_update_bits(map: regmap,
1000 NAU8824_REG_INTERRUPT_SETTING_1,
1001 NAU8824_IRQ_INSERT_EN, val: 0);
1002 /* detect microphone and jack type */
1003 cancel_work_sync(work: &nau8824->jdet_work);
1004 schedule_work(work: &nau8824->jdet_work);
1005
1006 /* Enable interruption for jack type detection at audo
1007 * mode which can detect microphone and jack type.
1008 */
1009 nau8824_setup_auto_irq(nau8824);
1010 }
1011
1012 if (!clear_irq)
1013 clear_irq = active_irq;
1014 /* clears the rightmost interruption */
1015 regmap_write(map: regmap, NAU8824_REG_CLEAR_INT_REG, val: clear_irq);
1016
1017 if (event_mask)
1018 snd_soc_jack_report(jack: nau8824->jack, status: event, mask: event_mask);
1019
1020 return IRQ_HANDLED;
1021}
1022
1023static const struct nau8824_osr_attr *
1024nau8824_get_osr(struct nau8824 *nau8824, int stream)
1025{
1026 unsigned int osr;
1027
1028 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1029 regmap_read(map: nau8824->regmap,
1030 NAU8824_REG_DAC_FILTER_CTRL_1, val: &osr);
1031 osr &= NAU8824_DAC_OVERSAMPLE_MASK;
1032 if (osr >= ARRAY_SIZE(osr_dac_sel))
1033 return NULL;
1034 return &osr_dac_sel[osr];
1035 } else {
1036 regmap_read(map: nau8824->regmap,
1037 NAU8824_REG_ADC_FILTER_CTRL, val: &osr);
1038 osr &= NAU8824_ADC_SYNC_DOWN_MASK;
1039 if (osr >= ARRAY_SIZE(osr_adc_sel))
1040 return NULL;
1041 return &osr_adc_sel[osr];
1042 }
1043}
1044
1045static int nau8824_dai_startup(struct snd_pcm_substream *substream,
1046 struct snd_soc_dai *dai)
1047{
1048 struct snd_soc_component *component = dai->component;
1049 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
1050 const struct nau8824_osr_attr *osr;
1051
1052 osr = nau8824_get_osr(nau8824, stream: substream->stream);
1053 if (!osr || !osr->osr)
1054 return -EINVAL;
1055
1056 return snd_pcm_hw_constraint_minmax(runtime: substream->runtime,
1057 SNDRV_PCM_HW_PARAM_RATE,
1058 min: 0, CLK_DA_AD_MAX / osr->osr);
1059}
1060
1061static int nau8824_hw_params(struct snd_pcm_substream *substream,
1062 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1063{
1064 struct snd_soc_component *component = dai->component;
1065 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
1066 unsigned int val_len = 0, ctrl_val, bclk_fs, bclk_div;
1067 const struct nau8824_osr_attr *osr;
1068 int err = -EINVAL;
1069
1070 nau8824_sema_acquire(nau8824, HZ);
1071
1072 /* CLK_DAC or CLK_ADC = OSR * FS
1073 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
1074 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
1075 * values must be selected such that the maximum frequency is less
1076 * than 6.144 MHz.
1077 */
1078 nau8824->fs = params_rate(p: params);
1079 osr = nau8824_get_osr(nau8824, stream: substream->stream);
1080 if (!osr || !osr->osr)
1081 goto error;
1082 if (nau8824->fs * osr->osr > CLK_DA_AD_MAX)
1083 goto error;
1084 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1085 regmap_update_bits(map: nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1086 NAU8824_CLK_DAC_SRC_MASK,
1087 val: osr->clk_src << NAU8824_CLK_DAC_SRC_SFT);
1088 else
1089 regmap_update_bits(map: nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1090 NAU8824_CLK_ADC_SRC_MASK,
1091 val: osr->clk_src << NAU8824_CLK_ADC_SRC_SFT);
1092
1093 /* make BCLK and LRC divde configuration if the codec as master. */
1094 regmap_read(map: nau8824->regmap,
1095 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, val: &ctrl_val);
1096 if (ctrl_val & NAU8824_I2S_MS_MASTER) {
1097 /* get the bclk and fs ratio */
1098 bclk_fs = snd_soc_params_to_bclk(parms: params) / nau8824->fs;
1099 if (bclk_fs <= 32)
1100 bclk_div = 0x3;
1101 else if (bclk_fs <= 64)
1102 bclk_div = 0x2;
1103 else if (bclk_fs <= 128)
1104 bclk_div = 0x1;
1105 else if (bclk_fs <= 256)
1106 bclk_div = 0;
1107 else
1108 goto error;
1109 regmap_update_bits(map: nau8824->regmap,
1110 NAU8824_REG_PORT0_I2S_PCM_CTRL_2,
1111 NAU8824_I2S_LRC_DIV_MASK | NAU8824_I2S_BLK_DIV_MASK,
1112 val: (bclk_div << NAU8824_I2S_LRC_DIV_SFT) | bclk_div);
1113 }
1114
1115 switch (params_width(p: params)) {
1116 case 16:
1117 val_len |= NAU8824_I2S_DL_16;
1118 break;
1119 case 20:
1120 val_len |= NAU8824_I2S_DL_20;
1121 break;
1122 case 24:
1123 val_len |= NAU8824_I2S_DL_24;
1124 break;
1125 case 32:
1126 val_len |= NAU8824_I2S_DL_32;
1127 break;
1128 default:
1129 goto error;
1130 }
1131
1132 regmap_update_bits(map: nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
1133 NAU8824_I2S_DL_MASK, val: val_len);
1134 err = 0;
1135
1136 error:
1137 nau8824_sema_release(nau8824);
1138
1139 return err;
1140}
1141
1142static int nau8824_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1143{
1144 struct snd_soc_component *component = dai->component;
1145 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
1146 unsigned int ctrl1_val = 0, ctrl2_val = 0;
1147
1148 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1149 case SND_SOC_DAIFMT_CBM_CFM:
1150 ctrl2_val |= NAU8824_I2S_MS_MASTER;
1151 break;
1152 case SND_SOC_DAIFMT_CBS_CFS:
1153 break;
1154 default:
1155 return -EINVAL;
1156 }
1157
1158 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1159 case SND_SOC_DAIFMT_NB_NF:
1160 break;
1161 case SND_SOC_DAIFMT_IB_NF:
1162 ctrl1_val |= NAU8824_I2S_BP_INV;
1163 break;
1164 default:
1165 return -EINVAL;
1166 }
1167
1168 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1169 case SND_SOC_DAIFMT_I2S:
1170 ctrl1_val |= NAU8824_I2S_DF_I2S;
1171 break;
1172 case SND_SOC_DAIFMT_LEFT_J:
1173 ctrl1_val |= NAU8824_I2S_DF_LEFT;
1174 break;
1175 case SND_SOC_DAIFMT_RIGHT_J:
1176 ctrl1_val |= NAU8824_I2S_DF_RIGTH;
1177 break;
1178 case SND_SOC_DAIFMT_DSP_A:
1179 ctrl1_val |= NAU8824_I2S_DF_PCM_AB;
1180 break;
1181 case SND_SOC_DAIFMT_DSP_B:
1182 ctrl1_val |= NAU8824_I2S_DF_PCM_AB;
1183 ctrl1_val |= NAU8824_I2S_PCMB_EN;
1184 break;
1185 default:
1186 return -EINVAL;
1187 }
1188
1189 nau8824_sema_acquire(nau8824, HZ);
1190
1191 regmap_update_bits(map: nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
1192 NAU8824_I2S_DF_MASK | NAU8824_I2S_BP_MASK |
1193 NAU8824_I2S_PCMB_EN, val: ctrl1_val);
1194 regmap_update_bits(map: nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_2,
1195 NAU8824_I2S_MS_MASK, val: ctrl2_val);
1196
1197 nau8824_sema_release(nau8824);
1198
1199 return 0;
1200}
1201
1202/**
1203 * nau8824_set_tdm_slot - configure DAI TDM.
1204 * @dai: DAI
1205 * @tx_mask: Bitmask representing active TX slots. Ex.
1206 * 0xf for normal 4 channel TDM.
1207 * 0xf0 for shifted 4 channel TDM
1208 * @rx_mask: Bitmask [0:1] representing active DACR RX slots.
1209 * Bitmask [2:3] representing active DACL RX slots.
1210 * 00=CH0,01=CH1,10=CH2,11=CH3. Ex.
1211 * 0xf for DACL/R selecting TDM CH3.
1212 * 0xf0 for DACL/R selecting shifted TDM CH3.
1213 * @slots: Number of slots in use.
1214 * @slot_width: Width in bits for each slot.
1215 *
1216 * Configures a DAI for TDM operation. Only support 4 slots TDM.
1217 */
1218static int nau8824_set_tdm_slot(struct snd_soc_dai *dai,
1219 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1220{
1221 struct snd_soc_component *component = dai->component;
1222 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
1223 unsigned int tslot_l = 0, ctrl_val = 0;
1224
1225 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)) ||
1226 ((rx_mask & 0xf0) && (rx_mask & 0xf)) ||
1227 ((rx_mask & 0xf0) && (tx_mask & 0xf)) ||
1228 ((rx_mask & 0xf) && (tx_mask & 0xf0)))
1229 return -EINVAL;
1230
1231 ctrl_val |= (NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN);
1232 if (tx_mask & 0xf0) {
1233 tslot_l = 4 * slot_width;
1234 ctrl_val |= (tx_mask >> 4);
1235 } else {
1236 ctrl_val |= tx_mask;
1237 }
1238 if (rx_mask & 0xf0)
1239 ctrl_val |= ((rx_mask >> 4) << NAU8824_TDM_DACR_RX_SFT);
1240 else
1241 ctrl_val |= (rx_mask << NAU8824_TDM_DACR_RX_SFT);
1242
1243 regmap_update_bits(map: nau8824->regmap, NAU8824_REG_TDM_CTRL,
1244 NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN |
1245 NAU8824_TDM_DACL_RX_MASK | NAU8824_TDM_DACR_RX_MASK |
1246 NAU8824_TDM_TX_MASK, val: ctrl_val);
1247 regmap_update_bits(map: nau8824->regmap, NAU8824_REG_PORT0_LEFT_TIME_SLOT,
1248 NAU8824_TSLOT_L_MASK, val: tslot_l);
1249
1250 return 0;
1251}
1252
1253/**
1254 * nau8824_calc_fll_param - Calculate FLL parameters.
1255 * @fll_in: external clock provided to codec.
1256 * @fs: sampling rate.
1257 * @fll_param: Pointer to structure of FLL parameters.
1258 *
1259 * Calculate FLL parameters to configure codec.
1260 *
1261 * Returns 0 for success or negative error code.
1262 */
1263static int nau8824_calc_fll_param(unsigned int fll_in,
1264 unsigned int fs, struct nau8824_fll *fll_param)
1265{
1266 u64 fvco, fvco_max;
1267 unsigned int fref, i, fvco_sel;
1268
1269 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
1270 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1271 * FREF = freq_in / NAU8824_FLL_REF_DIV_MASK
1272 */
1273 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1274 fref = fll_in / fll_pre_scalar[i].param;
1275 if (fref <= NAU_FREF_MAX)
1276 break;
1277 }
1278 if (i == ARRAY_SIZE(fll_pre_scalar))
1279 return -EINVAL;
1280 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1281
1282 /* Choose the FLL ratio based on FREF */
1283 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1284 if (fref >= fll_ratio[i].param)
1285 break;
1286 }
1287 if (i == ARRAY_SIZE(fll_ratio))
1288 return -EINVAL;
1289 fll_param->ratio = fll_ratio[i].val;
1290
1291 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1292 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
1293 * guaranteed across the full range of operation.
1294 * FDCO = freq_out * 2 * mclk_src_scaling
1295 */
1296 fvco_max = 0;
1297 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1298 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1299 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
1300 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1301 fvco_max < fvco) {
1302 fvco_max = fvco;
1303 fvco_sel = i;
1304 }
1305 }
1306 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1307 return -EINVAL;
1308 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1309
1310 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
1311 * input based on FDCO, FREF and FLL ratio.
1312 */
1313 fvco = div_u64(dividend: fvco_max << 16, divisor: fref * fll_param->ratio);
1314 fll_param->fll_int = (fvco >> 16) & 0x3FF;
1315 fll_param->fll_frac = fvco & 0xFFFF;
1316 return 0;
1317}
1318
1319static void nau8824_fll_apply(struct regmap *regmap,
1320 struct nau8824_fll *fll_param)
1321{
1322 regmap_update_bits(map: regmap, NAU8824_REG_CLK_DIVIDER,
1323 NAU8824_CLK_SRC_MASK | NAU8824_CLK_MCLK_SRC_MASK,
1324 NAU8824_CLK_SRC_MCLK | fll_param->mclk_src);
1325 regmap_update_bits(map: regmap, NAU8824_REG_FLL1,
1326 NAU8824_FLL_RATIO_MASK, val: fll_param->ratio);
1327 /* FLL 16-bit fractional input */
1328 regmap_write(map: regmap, NAU8824_REG_FLL2, val: fll_param->fll_frac);
1329 /* FLL 10-bit integer input */
1330 regmap_update_bits(map: regmap, NAU8824_REG_FLL3,
1331 NAU8824_FLL_INTEGER_MASK, val: fll_param->fll_int);
1332 /* FLL pre-scaler */
1333 regmap_update_bits(map: regmap, NAU8824_REG_FLL4,
1334 NAU8824_FLL_REF_DIV_MASK,
1335 val: fll_param->clk_ref_div << NAU8824_FLL_REF_DIV_SFT);
1336 /* select divided VCO input */
1337 regmap_update_bits(map: regmap, NAU8824_REG_FLL5,
1338 NAU8824_FLL_CLK_SW_MASK, NAU8824_FLL_CLK_SW_REF);
1339 /* Disable free-running mode */
1340 regmap_update_bits(map: regmap,
1341 NAU8824_REG_FLL6, NAU8824_DCO_EN, val: 0);
1342 if (fll_param->fll_frac) {
1343 regmap_update_bits(map: regmap, NAU8824_REG_FLL5,
1344 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
1345 NAU8824_FLL_FTR_SW_MASK,
1346 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
1347 NAU8824_FLL_FTR_SW_FILTER);
1348 regmap_update_bits(map: regmap, NAU8824_REG_FLL6,
1349 NAU8824_SDM_EN, NAU8824_SDM_EN);
1350 } else {
1351 regmap_update_bits(map: regmap, NAU8824_REG_FLL5,
1352 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
1353 NAU8824_FLL_FTR_SW_MASK, NAU8824_FLL_FTR_SW_ACCU);
1354 regmap_update_bits(map: regmap,
1355 NAU8824_REG_FLL6, NAU8824_SDM_EN, val: 0);
1356 }
1357}
1358
1359/* freq_out must be 256*Fs in order to achieve the best performance */
1360static int nau8824_set_pll(struct snd_soc_component *component, int pll_id, int source,
1361 unsigned int freq_in, unsigned int freq_out)
1362{
1363 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
1364 struct nau8824_fll fll_param;
1365 int ret, fs;
1366
1367 fs = freq_out / 256;
1368 ret = nau8824_calc_fll_param(fll_in: freq_in, fs, fll_param: &fll_param);
1369 if (ret < 0) {
1370 dev_err(nau8824->dev, "Unsupported input clock %d\n", freq_in);
1371 return ret;
1372 }
1373 dev_dbg(nau8824->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1374 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
1375 fll_param.fll_int, fll_param.clk_ref_div);
1376
1377 nau8824_fll_apply(regmap: nau8824->regmap, fll_param: &fll_param);
1378 mdelay(2);
1379 regmap_update_bits(map: nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1380 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);
1381
1382 return 0;
1383}
1384
1385static int nau8824_config_sysclk(struct nau8824 *nau8824,
1386 int clk_id, unsigned int freq)
1387{
1388 struct regmap *regmap = nau8824->regmap;
1389
1390 switch (clk_id) {
1391 case NAU8824_CLK_DIS:
1392 regmap_update_bits(map: regmap, NAU8824_REG_CLK_DIVIDER,
1393 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);
1394 regmap_update_bits(map: regmap, NAU8824_REG_FLL6,
1395 NAU8824_DCO_EN, val: 0);
1396 break;
1397
1398 case NAU8824_CLK_MCLK:
1399 nau8824_sema_acquire(nau8824, HZ);
1400 regmap_update_bits(map: regmap, NAU8824_REG_CLK_DIVIDER,
1401 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);
1402 regmap_update_bits(map: regmap, NAU8824_REG_FLL6,
1403 NAU8824_DCO_EN, val: 0);
1404 nau8824_sema_release(nau8824);
1405 break;
1406
1407 case NAU8824_CLK_INTERNAL:
1408 regmap_update_bits(map: regmap, NAU8824_REG_FLL6,
1409 NAU8824_DCO_EN, NAU8824_DCO_EN);
1410 regmap_update_bits(map: regmap, NAU8824_REG_CLK_DIVIDER,
1411 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);
1412 break;
1413
1414 case NAU8824_CLK_FLL_MCLK:
1415 nau8824_sema_acquire(nau8824, HZ);
1416 regmap_update_bits(map: regmap, NAU8824_REG_FLL3,
1417 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_MCLK);
1418 nau8824_sema_release(nau8824);
1419 break;
1420
1421 case NAU8824_CLK_FLL_BLK:
1422 nau8824_sema_acquire(nau8824, HZ);
1423 regmap_update_bits(map: regmap, NAU8824_REG_FLL3,
1424 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_BLK);
1425 nau8824_sema_release(nau8824);
1426 break;
1427
1428 case NAU8824_CLK_FLL_FS:
1429 nau8824_sema_acquire(nau8824, HZ);
1430 regmap_update_bits(map: regmap, NAU8824_REG_FLL3,
1431 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_FS);
1432 nau8824_sema_release(nau8824);
1433 break;
1434
1435 default:
1436 dev_err(nau8824->dev, "Invalid clock id (%d)\n", clk_id);
1437 return -EINVAL;
1438 }
1439
1440 dev_dbg(nau8824->dev, "Sysclk is %dHz and clock id is %d\n", freq,
1441 clk_id);
1442
1443 return 0;
1444}
1445
1446static int nau8824_set_sysclk(struct snd_soc_component *component,
1447 int clk_id, int source, unsigned int freq, int dir)
1448{
1449 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
1450
1451 return nau8824_config_sysclk(nau8824, clk_id, freq);
1452}
1453
1454static void nau8824_resume_setup(struct nau8824 *nau8824)
1455{
1456 nau8824_config_sysclk(nau8824, clk_id: NAU8824_CLK_DIS, freq: 0);
1457 if (nau8824->irq) {
1458 /* Clear all interruption status */
1459 nau8824_int_status_clear_all(regmap: nau8824->regmap);
1460 /* Enable jack detection at sleep mode, insertion detection,
1461 * and ejection detection.
1462 */
1463 regmap_update_bits(map: nau8824->regmap, NAU8824_REG_ENA_CTRL,
1464 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
1465 regmap_update_bits(map: nau8824->regmap,
1466 NAU8824_REG_INTERRUPT_SETTING_1,
1467 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN,
1468 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN);
1469 regmap_update_bits(map: nau8824->regmap,
1470 NAU8824_REG_INTERRUPT_SETTING,
1471 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, val: 0);
1472 }
1473}
1474
1475static int nau8824_set_bias_level(struct snd_soc_component *component,
1476 enum snd_soc_bias_level level)
1477{
1478 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
1479
1480 switch (level) {
1481 case SND_SOC_BIAS_ON:
1482 break;
1483
1484 case SND_SOC_BIAS_PREPARE:
1485 break;
1486
1487 case SND_SOC_BIAS_STANDBY:
1488 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1489 /* Setup codec configuration after resume */
1490 nau8824_resume_setup(nau8824);
1491 }
1492 break;
1493
1494 case SND_SOC_BIAS_OFF:
1495 regmap_update_bits(map: nau8824->regmap,
1496 NAU8824_REG_INTERRUPT_SETTING, mask: 0x3ff, val: 0x3ff);
1497 regmap_update_bits(map: nau8824->regmap,
1498 NAU8824_REG_INTERRUPT_SETTING_1,
1499 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, val: 0);
1500 break;
1501 }
1502
1503 return 0;
1504}
1505
1506static int nau8824_component_probe(struct snd_soc_component *component)
1507{
1508 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
1509 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1510
1511 nau8824->dapm = dapm;
1512
1513 return 0;
1514}
1515
1516static int __maybe_unused nau8824_suspend(struct snd_soc_component *component)
1517{
1518 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
1519
1520 if (nau8824->irq) {
1521 disable_irq(irq: nau8824->irq);
1522 snd_soc_component_force_bias_level(component, level: SND_SOC_BIAS_OFF);
1523 }
1524 regcache_cache_only(map: nau8824->regmap, enable: true);
1525 regcache_mark_dirty(map: nau8824->regmap);
1526
1527 return 0;
1528}
1529
1530static int __maybe_unused nau8824_resume(struct snd_soc_component *component)
1531{
1532 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
1533 int ret;
1534
1535 regcache_cache_only(map: nau8824->regmap, enable: false);
1536 regcache_sync(map: nau8824->regmap);
1537 if (nau8824->irq) {
1538 /* Hold semaphore to postpone playback happening
1539 * until jack detection done.
1540 */
1541 nau8824->resume_lock = true;
1542 ret = nau8824_sema_acquire(nau8824, timeout: 0);
1543 if (ret)
1544 nau8824->resume_lock = false;
1545 enable_irq(irq: nau8824->irq);
1546 }
1547
1548 return 0;
1549}
1550
1551static const struct snd_soc_component_driver nau8824_component_driver = {
1552 .probe = nau8824_component_probe,
1553 .set_sysclk = nau8824_set_sysclk,
1554 .set_pll = nau8824_set_pll,
1555 .set_bias_level = nau8824_set_bias_level,
1556 .suspend = nau8824_suspend,
1557 .resume = nau8824_resume,
1558 .controls = nau8824_snd_controls,
1559 .num_controls = ARRAY_SIZE(nau8824_snd_controls),
1560 .dapm_widgets = nau8824_dapm_widgets,
1561 .num_dapm_widgets = ARRAY_SIZE(nau8824_dapm_widgets),
1562 .dapm_routes = nau8824_dapm_routes,
1563 .num_dapm_routes = ARRAY_SIZE(nau8824_dapm_routes),
1564 .suspend_bias_off = 1,
1565 .idle_bias_on = 1,
1566 .use_pmdown_time = 1,
1567 .endianness = 1,
1568};
1569
1570static const struct snd_soc_dai_ops nau8824_dai_ops = {
1571 .startup = nau8824_dai_startup,
1572 .hw_params = nau8824_hw_params,
1573 .set_fmt = nau8824_set_fmt,
1574 .set_tdm_slot = nau8824_set_tdm_slot,
1575};
1576
1577#define NAU8824_RATES SNDRV_PCM_RATE_8000_192000
1578#define NAU8824_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1579 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1580
1581static struct snd_soc_dai_driver nau8824_dai = {
1582 .name = NAU8824_CODEC_DAI,
1583 .playback = {
1584 .stream_name = "Playback",
1585 .channels_min = 1,
1586 .channels_max = 2,
1587 .rates = NAU8824_RATES,
1588 .formats = NAU8824_FORMATS,
1589 },
1590 .capture = {
1591 .stream_name = "Capture",
1592 .channels_min = 1,
1593 .channels_max = 2,
1594 .rates = NAU8824_RATES,
1595 .formats = NAU8824_FORMATS,
1596 },
1597 .ops = &nau8824_dai_ops,
1598};
1599
1600static const struct regmap_config nau8824_regmap_config = {
1601 .val_bits = NAU8824_REG_ADDR_LEN,
1602 .reg_bits = NAU8824_REG_DATA_LEN,
1603
1604 .max_register = NAU8824_REG_MAX,
1605 .readable_reg = nau8824_readable_reg,
1606 .writeable_reg = nau8824_writeable_reg,
1607 .volatile_reg = nau8824_volatile_reg,
1608
1609 .cache_type = REGCACHE_RBTREE,
1610 .reg_defaults = nau8824_reg_defaults,
1611 .num_reg_defaults = ARRAY_SIZE(nau8824_reg_defaults),
1612};
1613
1614/**
1615 * nau8824_enable_jack_detect - Specify a jack for event reporting
1616 *
1617 * @component: component to register the jack with
1618 * @jack: jack to use to report headset and button events on
1619 *
1620 * After this function has been called the headset insert/remove and button
1621 * events will be routed to the given jack. Jack can be null to stop
1622 * reporting.
1623 */
1624int nau8824_enable_jack_detect(struct snd_soc_component *component,
1625 struct snd_soc_jack *jack)
1626{
1627 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(c: component);
1628 int ret;
1629
1630 nau8824->jack = jack;
1631 /* Initiate jack detection work queue */
1632 INIT_WORK(&nau8824->jdet_work, nau8824_jdet_work);
1633 ret = devm_request_threaded_irq(dev: nau8824->dev, irq: nau8824->irq, NULL,
1634 thread_fn: nau8824_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1635 devname: "nau8824", dev_id: nau8824);
1636 if (ret) {
1637 dev_err(nau8824->dev, "Cannot request irq %d (%d)\n",
1638 nau8824->irq, ret);
1639 }
1640
1641 return ret;
1642}
1643EXPORT_SYMBOL_GPL(nau8824_enable_jack_detect);
1644
1645static void nau8824_reset_chip(struct regmap *regmap)
1646{
1647 regmap_write(map: regmap, NAU8824_REG_RESET, val: 0x00);
1648 regmap_write(map: regmap, NAU8824_REG_RESET, val: 0x00);
1649}
1650
1651static void nau8824_setup_buttons(struct nau8824 *nau8824)
1652{
1653 struct regmap *regmap = nau8824->regmap;
1654
1655 regmap_update_bits(map: regmap, NAU8824_REG_SAR_ADC,
1656 NAU8824_SAR_TRACKING_GAIN_MASK,
1657 val: nau8824->sar_voltage << NAU8824_SAR_TRACKING_GAIN_SFT);
1658 regmap_update_bits(map: regmap, NAU8824_REG_SAR_ADC,
1659 NAU8824_SAR_COMPARE_TIME_MASK,
1660 val: nau8824->sar_compare_time << NAU8824_SAR_COMPARE_TIME_SFT);
1661 regmap_update_bits(map: regmap, NAU8824_REG_SAR_ADC,
1662 NAU8824_SAR_SAMPLING_TIME_MASK,
1663 val: nau8824->sar_sampling_time << NAU8824_SAR_SAMPLING_TIME_SFT);
1664
1665 regmap_update_bits(map: regmap, NAU8824_REG_VDET_COEFFICIENT,
1666 NAU8824_LEVELS_NR_MASK,
1667 val: (nau8824->sar_threshold_num - 1) << NAU8824_LEVELS_NR_SFT);
1668 regmap_update_bits(map: regmap, NAU8824_REG_VDET_COEFFICIENT,
1669 NAU8824_HYSTERESIS_MASK,
1670 val: nau8824->sar_hysteresis << NAU8824_HYSTERESIS_SFT);
1671 regmap_update_bits(map: regmap, NAU8824_REG_VDET_COEFFICIENT,
1672 NAU8824_SHORTKEY_DEBOUNCE_MASK,
1673 val: nau8824->key_debounce << NAU8824_SHORTKEY_DEBOUNCE_SFT);
1674
1675 regmap_write(map: regmap, NAU8824_REG_VDET_THRESHOLD_1,
1676 val: (nau8824->sar_threshold[0] << 8) | nau8824->sar_threshold[1]);
1677 regmap_write(map: regmap, NAU8824_REG_VDET_THRESHOLD_2,
1678 val: (nau8824->sar_threshold[2] << 8) | nau8824->sar_threshold[3]);
1679 regmap_write(map: regmap, NAU8824_REG_VDET_THRESHOLD_3,
1680 val: (nau8824->sar_threshold[4] << 8) | nau8824->sar_threshold[5]);
1681 regmap_write(map: regmap, NAU8824_REG_VDET_THRESHOLD_4,
1682 val: (nau8824->sar_threshold[6] << 8) | nau8824->sar_threshold[7]);
1683}
1684
1685static void nau8824_init_regs(struct nau8824 *nau8824)
1686{
1687 struct regmap *regmap = nau8824->regmap;
1688
1689 /* Enable Bias/VMID/VMID Tieoff */
1690 regmap_update_bits(map: regmap, NAU8824_REG_BIAS_ADJ,
1691 NAU8824_VMID | NAU8824_VMID_SEL_MASK, NAU8824_VMID |
1692 (nau8824->vref_impedance << NAU8824_VMID_SEL_SFT));
1693 regmap_update_bits(map: regmap, NAU8824_REG_BOOST,
1694 NAU8824_GLOBAL_BIAS_EN, NAU8824_GLOBAL_BIAS_EN);
1695 mdelay(2);
1696 regmap_update_bits(map: regmap, NAU8824_REG_MIC_BIAS,
1697 NAU8824_MICBIAS_VOLTAGE_MASK, val: nau8824->micbias_voltage);
1698 /* Disable Boost Driver, Automatic Short circuit protection enable */
1699 regmap_update_bits(map: regmap, NAU8824_REG_BOOST,
1700 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |
1701 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN,
1702 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |
1703 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN);
1704 /* Scaling for ADC and DAC clock */
1705 regmap_update_bits(map: regmap, NAU8824_REG_CLK_DIVIDER,
1706 NAU8824_CLK_ADC_SRC_MASK | NAU8824_CLK_DAC_SRC_MASK,
1707 val: (0x1 << NAU8824_CLK_ADC_SRC_SFT) |
1708 (0x1 << NAU8824_CLK_DAC_SRC_SFT));
1709 regmap_update_bits(map: regmap, NAU8824_REG_DAC_MUTE_CTRL,
1710 NAU8824_DAC_ZC_EN, NAU8824_DAC_ZC_EN);
1711 regmap_update_bits(map: regmap, NAU8824_REG_ENA_CTRL,
1712 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |
1713 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |
1714 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN,
1715 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |
1716 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |
1717 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN);
1718 regmap_update_bits(map: regmap, NAU8824_REG_CLK_GATING_ENA,
1719 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |
1720 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |
1721 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |
1722 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN,
1723 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |
1724 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |
1725 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |
1726 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN);
1727 /* Class G timer 64ms */
1728 regmap_update_bits(map: regmap, NAU8824_REG_CLASSG,
1729 NAU8824_CLASSG_TIMER_MASK,
1730 val: 0x20 << NAU8824_CLASSG_TIMER_SFT);
1731 regmap_update_bits(map: regmap, NAU8824_REG_TRIM_SETTINGS,
1732 NAU8824_DRV_CURR_INC, NAU8824_DRV_CURR_INC);
1733 /* Disable DACR/L power */
1734 regmap_update_bits(map: regmap, NAU8824_REG_CHARGE_PUMP_CONTROL,
1735 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |
1736 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL,
1737 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |
1738 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL);
1739 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
1740 * signal to avoid any glitches due to power up transients in both
1741 * the analog and digital DAC circuit.
1742 */
1743 regmap_update_bits(map: regmap, NAU8824_REG_ENABLE_LO,
1744 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);
1745 /* Config L/R channel */
1746 regmap_update_bits(map: regmap, NAU8824_REG_DAC_CH0_DGAIN_CTRL,
1747 NAU8824_DAC_CH0_SEL_MASK, NAU8824_DAC_CH0_SEL_I2S0);
1748 regmap_update_bits(map: regmap, NAU8824_REG_DAC_CH1_DGAIN_CTRL,
1749 NAU8824_DAC_CH1_SEL_MASK, NAU8824_DAC_CH1_SEL_I2S1);
1750 regmap_update_bits(map: regmap, NAU8824_REG_ENABLE_LO,
1751 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN,
1752 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN);
1753 /* Default oversampling/decimations settings are unusable
1754 * (audible hiss). Set it to something better.
1755 */
1756 regmap_update_bits(map: regmap, NAU8824_REG_ADC_FILTER_CTRL,
1757 NAU8824_ADC_SYNC_DOWN_MASK, NAU8824_ADC_SYNC_DOWN_64);
1758 regmap_update_bits(map: regmap, NAU8824_REG_DAC_FILTER_CTRL_1,
1759 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_MASK,
1760 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_64);
1761 /* DAC clock delay 2ns, VREF */
1762 regmap_update_bits(map: regmap, NAU8824_REG_RDAC,
1763 NAU8824_RDAC_CLK_DELAY_MASK | NAU8824_RDAC_VREF_MASK,
1764 val: (0x2 << NAU8824_RDAC_CLK_DELAY_SFT) |
1765 (0x3 << NAU8824_RDAC_VREF_SFT));
1766 /* PGA input mode selection */
1767 regmap_update_bits(map: regmap, NAU8824_REG_FEPGA,
1768 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN,
1769 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN);
1770 /* Digital microphone control */
1771 regmap_update_bits(map: regmap, NAU8824_REG_ANALOG_CONTROL_1,
1772 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST,
1773 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST);
1774 regmap_update_bits(map: regmap, NAU8824_REG_JACK_DET_CTRL,
1775 NAU8824_JACK_LOGIC,
1776 /* jkdet_polarity - 1 is for active-low */
1777 val: nau8824->jkdet_polarity ? 0 : NAU8824_JACK_LOGIC);
1778 regmap_update_bits(map: regmap,
1779 NAU8824_REG_JACK_DET_CTRL, NAU8824_JACK_EJECT_DT_MASK,
1780 val: (nau8824->jack_eject_debounce << NAU8824_JACK_EJECT_DT_SFT));
1781 if (nau8824->sar_threshold_num)
1782 nau8824_setup_buttons(nau8824);
1783}
1784
1785static int nau8824_setup_irq(struct nau8824 *nau8824)
1786{
1787 /* Disable interruption before codec initiation done */
1788 regmap_update_bits(map: nau8824->regmap, NAU8824_REG_ENA_CTRL,
1789 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
1790 regmap_update_bits(map: nau8824->regmap,
1791 NAU8824_REG_INTERRUPT_SETTING, mask: 0x3ff, val: 0x3ff);
1792 regmap_update_bits(map: nau8824->regmap, NAU8824_REG_INTERRUPT_SETTING_1,
1793 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, val: 0);
1794
1795 return 0;
1796}
1797
1798static void nau8824_print_device_properties(struct nau8824 *nau8824)
1799{
1800 struct device *dev = nau8824->dev;
1801 int i;
1802
1803 dev_dbg(dev, "jkdet-polarity: %d\n", nau8824->jkdet_polarity);
1804 dev_dbg(dev, "micbias-voltage: %d\n", nau8824->micbias_voltage);
1805 dev_dbg(dev, "vref-impedance: %d\n", nau8824->vref_impedance);
1806
1807 dev_dbg(dev, "sar-threshold-num: %d\n", nau8824->sar_threshold_num);
1808 for (i = 0; i < nau8824->sar_threshold_num; i++)
1809 dev_dbg(dev, "sar-threshold[%d]=%x\n", i,
1810 nau8824->sar_threshold[i]);
1811
1812 dev_dbg(dev, "sar-hysteresis: %d\n", nau8824->sar_hysteresis);
1813 dev_dbg(dev, "sar-voltage: %d\n", nau8824->sar_voltage);
1814 dev_dbg(dev, "sar-compare-time: %d\n", nau8824->sar_compare_time);
1815 dev_dbg(dev, "sar-sampling-time: %d\n", nau8824->sar_sampling_time);
1816 dev_dbg(dev, "short-key-debounce: %d\n", nau8824->key_debounce);
1817 dev_dbg(dev, "jack-eject-debounce: %d\n",
1818 nau8824->jack_eject_debounce);
1819}
1820
1821static int nau8824_read_device_properties(struct device *dev,
1822 struct nau8824 *nau8824) {
1823 int ret;
1824
1825 ret = device_property_read_u32(dev, propname: "nuvoton,jkdet-polarity",
1826 val: &nau8824->jkdet_polarity);
1827 if (ret)
1828 nau8824->jkdet_polarity = 1;
1829 ret = device_property_read_u32(dev, propname: "nuvoton,micbias-voltage",
1830 val: &nau8824->micbias_voltage);
1831 if (ret)
1832 nau8824->micbias_voltage = 6;
1833 ret = device_property_read_u32(dev, propname: "nuvoton,vref-impedance",
1834 val: &nau8824->vref_impedance);
1835 if (ret)
1836 nau8824->vref_impedance = 2;
1837 ret = device_property_read_u32(dev, propname: "nuvoton,sar-threshold-num",
1838 val: &nau8824->sar_threshold_num);
1839 if (ret)
1840 nau8824->sar_threshold_num = 4;
1841 ret = device_property_read_u32_array(dev, propname: "nuvoton,sar-threshold",
1842 val: nau8824->sar_threshold, nval: nau8824->sar_threshold_num);
1843 if (ret) {
1844 nau8824->sar_threshold[0] = 0x0a;
1845 nau8824->sar_threshold[1] = 0x14;
1846 nau8824->sar_threshold[2] = 0x26;
1847 nau8824->sar_threshold[3] = 0x73;
1848 }
1849 ret = device_property_read_u32(dev, propname: "nuvoton,sar-hysteresis",
1850 val: &nau8824->sar_hysteresis);
1851 if (ret)
1852 nau8824->sar_hysteresis = 0;
1853 ret = device_property_read_u32(dev, propname: "nuvoton,sar-voltage",
1854 val: &nau8824->sar_voltage);
1855 if (ret)
1856 nau8824->sar_voltage = 6;
1857 ret = device_property_read_u32(dev, propname: "nuvoton,sar-compare-time",
1858 val: &nau8824->sar_compare_time);
1859 if (ret)
1860 nau8824->sar_compare_time = 1;
1861 ret = device_property_read_u32(dev, propname: "nuvoton,sar-sampling-time",
1862 val: &nau8824->sar_sampling_time);
1863 if (ret)
1864 nau8824->sar_sampling_time = 1;
1865 ret = device_property_read_u32(dev, propname: "nuvoton,short-key-debounce",
1866 val: &nau8824->key_debounce);
1867 if (ret)
1868 nau8824->key_debounce = 0;
1869 ret = device_property_read_u32(dev, propname: "nuvoton,jack-eject-debounce",
1870 val: &nau8824->jack_eject_debounce);
1871 if (ret)
1872 nau8824->jack_eject_debounce = 1;
1873
1874 return 0;
1875}
1876
1877/* Please keep this list alphabetically sorted */
1878static const struct dmi_system_id nau8824_quirk_table[] = {
1879 {
1880 /* Cyberbook T116 rugged tablet */
1881 .matches = {
1882 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Default string"),
1883 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
1884 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "20170531"),
1885 },
1886 .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH |
1887 NAU8824_MONO_SPEAKER),
1888 },
1889 {
1890 /* CUBE iwork8 Air */
1891 .matches = {
1892 DMI_MATCH(DMI_SYS_VENDOR, "cube"),
1893 DMI_MATCH(DMI_PRODUCT_NAME, "i1-TF"),
1894 DMI_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
1895 },
1896 .driver_data = (void *)(NAU8824_MONO_SPEAKER),
1897 },
1898 {
1899 /* Pipo W2S */
1900 .matches = {
1901 DMI_MATCH(DMI_SYS_VENDOR, "PIPO"),
1902 DMI_MATCH(DMI_PRODUCT_NAME, "W2S"),
1903 },
1904 .driver_data = (void *)(NAU8824_MONO_SPEAKER),
1905 },
1906 {
1907 /* Positivo CW14Q01P */
1908 .matches = {
1909 DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
1910 DMI_MATCH(DMI_BOARD_NAME, "CW14Q01P"),
1911 },
1912 .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH),
1913 },
1914 {
1915 /* Positivo K1424G */
1916 .matches = {
1917 DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
1918 DMI_MATCH(DMI_BOARD_NAME, "K1424G"),
1919 },
1920 .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH),
1921 },
1922 {
1923 /* Positivo N14ZP74G */
1924 .matches = {
1925 DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
1926 DMI_MATCH(DMI_BOARD_NAME, "N14ZP74G"),
1927 },
1928 .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH),
1929 },
1930 {}
1931};
1932
1933static void nau8824_check_quirks(void)
1934{
1935 const struct dmi_system_id *dmi_id;
1936
1937 if (quirk_override != -1) {
1938 nau8824_quirk = quirk_override;
1939 return;
1940 }
1941
1942 dmi_id = dmi_first_match(list: nau8824_quirk_table);
1943 if (dmi_id)
1944 nau8824_quirk = (unsigned long)dmi_id->driver_data;
1945}
1946
1947const char *nau8824_components(void)
1948{
1949 nau8824_check_quirks();
1950
1951 if (nau8824_quirk & NAU8824_MONO_SPEAKER)
1952 return "cfg-spk:1";
1953 else
1954 return "cfg-spk:2";
1955}
1956EXPORT_SYMBOL_GPL(nau8824_components);
1957
1958static int nau8824_i2c_probe(struct i2c_client *i2c)
1959{
1960 struct device *dev = &i2c->dev;
1961 struct nau8824 *nau8824 = dev_get_platdata(dev);
1962 int ret, value;
1963
1964 if (!nau8824) {
1965 nau8824 = devm_kzalloc(dev, size: sizeof(*nau8824), GFP_KERNEL);
1966 if (!nau8824)
1967 return -ENOMEM;
1968 ret = nau8824_read_device_properties(dev, nau8824);
1969 if (ret)
1970 return ret;
1971 }
1972 i2c_set_clientdata(client: i2c, data: nau8824);
1973
1974 nau8824->regmap = devm_regmap_init_i2c(i2c, &nau8824_regmap_config);
1975 if (IS_ERR(ptr: nau8824->regmap))
1976 return PTR_ERR(ptr: nau8824->regmap);
1977 nau8824->resume_lock = false;
1978 nau8824->dev = dev;
1979 nau8824->irq = i2c->irq;
1980 sema_init(sem: &nau8824->jd_sem, val: 1);
1981
1982 nau8824_check_quirks();
1983
1984 if (nau8824_quirk & NAU8824_JD_ACTIVE_HIGH)
1985 nau8824->jkdet_polarity = 0;
1986
1987 nau8824_print_device_properties(nau8824);
1988
1989 ret = regmap_read(map: nau8824->regmap, NAU8824_REG_I2C_DEVICE_ID, val: &value);
1990 if (ret < 0) {
1991 dev_err(dev, "Failed to read device id from the NAU8824: %d\n",
1992 ret);
1993 return ret;
1994 }
1995 nau8824_reset_chip(regmap: nau8824->regmap);
1996 nau8824_init_regs(nau8824);
1997
1998 if (i2c->irq)
1999 nau8824_setup_irq(nau8824);
2000
2001 return devm_snd_soc_register_component(dev,
2002 component_driver: &nau8824_component_driver, dai_drv: &nau8824_dai, num_dai: 1);
2003}
2004
2005static const struct i2c_device_id nau8824_i2c_ids[] = {
2006 { "nau8824", 0 },
2007 { }
2008};
2009MODULE_DEVICE_TABLE(i2c, nau8824_i2c_ids);
2010
2011#ifdef CONFIG_OF
2012static const struct of_device_id nau8824_of_ids[] = {
2013 { .compatible = "nuvoton,nau8824", },
2014 {}
2015};
2016MODULE_DEVICE_TABLE(of, nau8824_of_ids);
2017#endif
2018
2019#ifdef CONFIG_ACPI
2020static const struct acpi_device_id nau8824_acpi_match[] = {
2021 { "10508824", 0 },
2022 {},
2023};
2024MODULE_DEVICE_TABLE(acpi, nau8824_acpi_match);
2025#endif
2026
2027static struct i2c_driver nau8824_i2c_driver = {
2028 .driver = {
2029 .name = "nau8824",
2030 .of_match_table = of_match_ptr(nau8824_of_ids),
2031 .acpi_match_table = ACPI_PTR(nau8824_acpi_match),
2032 },
2033 .probe = nau8824_i2c_probe,
2034 .id_table = nau8824_i2c_ids,
2035};
2036module_i2c_driver(nau8824_i2c_driver);
2037
2038
2039MODULE_DESCRIPTION("ASoC NAU88L24 driver");
2040MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>");
2041MODULE_LICENSE("GPL v2");
2042

source code of linux/sound/soc/codecs/nau8824.c