1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * wm8900.c -- WM8900 ALSA Soc Audio driver |
4 | * |
5 | * Copyright 2007, 2008 Wolfson Microelectronics PLC. |
6 | * |
7 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> |
8 | * |
9 | * TODO: |
10 | * - Tristating. |
11 | * - TDM. |
12 | * - Jack detect. |
13 | * - FLL source configuration, currently only MCLK is supported. |
14 | */ |
15 | |
16 | #include <linux/module.h> |
17 | #include <linux/moduleparam.h> |
18 | #include <linux/kernel.h> |
19 | #include <linux/init.h> |
20 | #include <linux/delay.h> |
21 | #include <linux/pm.h> |
22 | #include <linux/i2c.h> |
23 | #include <linux/regmap.h> |
24 | #include <linux/spi/spi.h> |
25 | #include <linux/slab.h> |
26 | #include <sound/core.h> |
27 | #include <sound/pcm.h> |
28 | #include <sound/pcm_params.h> |
29 | #include <sound/soc.h> |
30 | #include <sound/initval.h> |
31 | #include <sound/tlv.h> |
32 | |
33 | #include "wm8900.h" |
34 | |
35 | /* WM8900 register space */ |
36 | #define WM8900_REG_RESET 0x0 |
37 | #define WM8900_REG_ID 0x0 |
38 | #define WM8900_REG_POWER1 0x1 |
39 | #define WM8900_REG_POWER2 0x2 |
40 | #define WM8900_REG_POWER3 0x3 |
41 | #define WM8900_REG_AUDIO1 0x4 |
42 | #define WM8900_REG_AUDIO2 0x5 |
43 | #define WM8900_REG_CLOCKING1 0x6 |
44 | #define WM8900_REG_CLOCKING2 0x7 |
45 | #define WM8900_REG_AUDIO3 0x8 |
46 | #define WM8900_REG_AUDIO4 0x9 |
47 | #define WM8900_REG_DACCTRL 0xa |
48 | #define WM8900_REG_LDAC_DV 0xb |
49 | #define WM8900_REG_RDAC_DV 0xc |
50 | #define WM8900_REG_SIDETONE 0xd |
51 | #define WM8900_REG_ADCCTRL 0xe |
52 | #define WM8900_REG_LADC_DV 0xf |
53 | #define WM8900_REG_RADC_DV 0x10 |
54 | #define WM8900_REG_GPIO 0x12 |
55 | #define WM8900_REG_INCTL 0x15 |
56 | #define WM8900_REG_LINVOL 0x16 |
57 | #define WM8900_REG_RINVOL 0x17 |
58 | #define WM8900_REG_INBOOSTMIX1 0x18 |
59 | #define WM8900_REG_INBOOSTMIX2 0x19 |
60 | #define WM8900_REG_ADCPATH 0x1a |
61 | #define WM8900_REG_AUXBOOST 0x1b |
62 | #define WM8900_REG_ADDCTL 0x1e |
63 | #define WM8900_REG_FLLCTL1 0x24 |
64 | #define WM8900_REG_FLLCTL2 0x25 |
65 | #define WM8900_REG_FLLCTL3 0x26 |
66 | #define WM8900_REG_FLLCTL4 0x27 |
67 | #define WM8900_REG_FLLCTL5 0x28 |
68 | #define WM8900_REG_FLLCTL6 0x29 |
69 | #define WM8900_REG_LOUTMIXCTL1 0x2c |
70 | #define WM8900_REG_ROUTMIXCTL1 0x2d |
71 | #define WM8900_REG_BYPASS1 0x2e |
72 | #define WM8900_REG_BYPASS2 0x2f |
73 | #define WM8900_REG_AUXOUT_CTL 0x30 |
74 | #define WM8900_REG_LOUT1CTL 0x33 |
75 | #define WM8900_REG_ROUT1CTL 0x34 |
76 | #define WM8900_REG_LOUT2CTL 0x35 |
77 | #define WM8900_REG_ROUT2CTL 0x36 |
78 | #define WM8900_REG_HPCTL1 0x3a |
79 | #define WM8900_REG_OUTBIASCTL 0x73 |
80 | |
81 | #define WM8900_MAXREG 0x80 |
82 | |
83 | #define WM8900_REG_ADDCTL_OUT1_DIS 0x80 |
84 | #define WM8900_REG_ADDCTL_OUT2_DIS 0x40 |
85 | #define WM8900_REG_ADDCTL_VMID_DIS 0x20 |
86 | #define WM8900_REG_ADDCTL_BIAS_SRC 0x10 |
87 | #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04 |
88 | #define WM8900_REG_ADDCTL_TEMP_SD 0x02 |
89 | |
90 | #define WM8900_REG_GPIO_TEMP_ENA 0x2 |
91 | |
92 | #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100 |
93 | #define WM8900_REG_POWER1_BIAS_ENA 0x0008 |
94 | #define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004 |
95 | #define WM8900_REG_POWER1_FLL_ENA 0x0040 |
96 | |
97 | #define WM8900_REG_POWER2_SYSCLK_ENA 0x8000 |
98 | #define WM8900_REG_POWER2_ADCL_ENA 0x0002 |
99 | #define WM8900_REG_POWER2_ADCR_ENA 0x0001 |
100 | |
101 | #define WM8900_REG_POWER3_DACL_ENA 0x0002 |
102 | #define WM8900_REG_POWER3_DACR_ENA 0x0001 |
103 | |
104 | #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018 |
105 | #define WM8900_REG_AUDIO1_LRCLK_INV 0x0080 |
106 | #define WM8900_REG_AUDIO1_BCLK_INV 0x0100 |
107 | |
108 | #define WM8900_REG_CLOCKING1_BCLK_DIR 0x1 |
109 | #define WM8900_REG_CLOCKING1_MCLK_SRC 0x100 |
110 | #define WM8900_REG_CLOCKING1_BCLK_MASK 0x01e |
111 | #define WM8900_REG_CLOCKING1_OPCLK_MASK 0x7000 |
112 | |
113 | #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0 |
114 | #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c |
115 | |
116 | #define WM8900_REG_DACCTRL_MUTE 0x004 |
117 | #define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100 |
118 | #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400 |
119 | |
120 | #define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800 |
121 | |
122 | #define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800 |
123 | |
124 | #define WM8900_REG_FLLCTL1_OSC_ENA 0x100 |
125 | |
126 | #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100 |
127 | |
128 | #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80 |
129 | #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40 |
130 | #define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20 |
131 | #define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10 |
132 | #define WM8900_REG_HPCTL1_HP_SHORT 0x08 |
133 | #define WM8900_REG_HPCTL1_HP_SHORT2 0x04 |
134 | |
135 | #define WM8900_LRC_MASK 0x03ff |
136 | |
137 | struct wm8900_priv { |
138 | struct regmap *regmap; |
139 | |
140 | u32 fll_in; /* FLL input frequency */ |
141 | u32 fll_out; /* FLL output frequency */ |
142 | }; |
143 | |
144 | /* |
145 | * wm8900 register cache. We can't read the entire register space and we |
146 | * have slow control buses so we cache the registers. |
147 | */ |
148 | static const struct reg_default wm8900_reg_defaults[] = { |
149 | { 1, 0x0000 }, |
150 | { 2, 0xc000 }, |
151 | { 3, 0x0000 }, |
152 | { 4, 0x4050 }, |
153 | { 5, 0x4000 }, |
154 | { 6, 0x0008 }, |
155 | { 7, 0x0000 }, |
156 | { 8, 0x0040 }, |
157 | { 9, 0x0040 }, |
158 | { 10, 0x1004 }, |
159 | { 11, 0x00c0 }, |
160 | { 12, 0x00c0 }, |
161 | { 13, 0x0000 }, |
162 | { 14, 0x0100 }, |
163 | { 15, 0x00c0 }, |
164 | { 16, 0x00c0 }, |
165 | { 17, 0x0000 }, |
166 | { 18, 0xb001 }, |
167 | { 19, 0x0000 }, |
168 | { 20, 0x0000 }, |
169 | { 21, 0x0044 }, |
170 | { 22, 0x004c }, |
171 | { 23, 0x004c }, |
172 | { 24, 0x0044 }, |
173 | { 25, 0x0044 }, |
174 | { 26, 0x0000 }, |
175 | { 27, 0x0044 }, |
176 | { 28, 0x0000 }, |
177 | { 29, 0x0000 }, |
178 | { 30, 0x0002 }, |
179 | { 31, 0x0000 }, |
180 | { 32, 0x0000 }, |
181 | { 33, 0x0000 }, |
182 | { 34, 0x0000 }, |
183 | { 35, 0x0000 }, |
184 | { 36, 0x0008 }, |
185 | { 37, 0x0000 }, |
186 | { 38, 0x0000 }, |
187 | { 39, 0x0008 }, |
188 | { 40, 0x0097 }, |
189 | { 41, 0x0100 }, |
190 | { 42, 0x0000 }, |
191 | { 43, 0x0000 }, |
192 | { 44, 0x0050 }, |
193 | { 45, 0x0050 }, |
194 | { 46, 0x0055 }, |
195 | { 47, 0x0055 }, |
196 | { 48, 0x0055 }, |
197 | { 49, 0x0000 }, |
198 | { 50, 0x0000 }, |
199 | { 51, 0x0079 }, |
200 | { 52, 0x0079 }, |
201 | { 53, 0x0079 }, |
202 | { 54, 0x0079 }, |
203 | { 55, 0x0000 }, |
204 | }; |
205 | |
206 | static bool wm8900_volatile_register(struct device *dev, unsigned int reg) |
207 | { |
208 | switch (reg) { |
209 | case WM8900_REG_ID: |
210 | return true; |
211 | default: |
212 | return false; |
213 | } |
214 | } |
215 | |
216 | static void wm8900_reset(struct snd_soc_component *component) |
217 | { |
218 | snd_soc_component_write(component, WM8900_REG_RESET, val: 0); |
219 | } |
220 | |
221 | static int wm8900_hp_event(struct snd_soc_dapm_widget *w, |
222 | struct snd_kcontrol *kcontrol, int event) |
223 | { |
224 | struct snd_soc_component *component = snd_soc_dapm_to_component(dapm: w->dapm); |
225 | u16 hpctl1 = snd_soc_component_read(component, WM8900_REG_HPCTL1); |
226 | |
227 | switch (event) { |
228 | case SND_SOC_DAPM_PRE_PMU: |
229 | /* Clamp headphone outputs */ |
230 | hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP | |
231 | WM8900_REG_HPCTL1_HP_CLAMP_OP; |
232 | snd_soc_component_write(component, WM8900_REG_HPCTL1, val: hpctl1); |
233 | break; |
234 | |
235 | case SND_SOC_DAPM_POST_PMU: |
236 | /* Enable the input stage */ |
237 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP; |
238 | hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT | |
239 | WM8900_REG_HPCTL1_HP_SHORT2 | |
240 | WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; |
241 | snd_soc_component_write(component, WM8900_REG_HPCTL1, val: hpctl1); |
242 | |
243 | msleep(msecs: 400); |
244 | |
245 | /* Enable the output stage */ |
246 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP; |
247 | hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; |
248 | snd_soc_component_write(component, WM8900_REG_HPCTL1, val: hpctl1); |
249 | |
250 | /* Remove the shorts */ |
251 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2; |
252 | snd_soc_component_write(component, WM8900_REG_HPCTL1, val: hpctl1); |
253 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT; |
254 | snd_soc_component_write(component, WM8900_REG_HPCTL1, val: hpctl1); |
255 | break; |
256 | |
257 | case SND_SOC_DAPM_PRE_PMD: |
258 | /* Short the output */ |
259 | hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT; |
260 | snd_soc_component_write(component, WM8900_REG_HPCTL1, val: hpctl1); |
261 | |
262 | /* Disable the output stage */ |
263 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; |
264 | snd_soc_component_write(component, WM8900_REG_HPCTL1, val: hpctl1); |
265 | |
266 | /* Clamp the outputs and power down input */ |
267 | hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP | |
268 | WM8900_REG_HPCTL1_HP_CLAMP_OP; |
269 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; |
270 | snd_soc_component_write(component, WM8900_REG_HPCTL1, val: hpctl1); |
271 | break; |
272 | |
273 | case SND_SOC_DAPM_POST_PMD: |
274 | /* Disable everything */ |
275 | snd_soc_component_write(component, WM8900_REG_HPCTL1, val: 0); |
276 | break; |
277 | |
278 | default: |
279 | WARN(1, "Invalid event %d\n" , event); |
280 | break; |
281 | } |
282 | |
283 | return 0; |
284 | } |
285 | |
286 | static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0); |
287 | |
288 | static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0); |
289 | |
290 | static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0); |
291 | |
292 | static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0); |
293 | |
294 | static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); |
295 | |
296 | static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1); |
297 | |
298 | static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0); |
299 | |
300 | static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1); |
301 | |
302 | static const char *mic_bias_level_txt[] = { "0.9*AVDD" , "0.65*AVDD" }; |
303 | |
304 | static SOC_ENUM_SINGLE_DECL(mic_bias_level, |
305 | WM8900_REG_INCTL, 8, mic_bias_level_txt); |
306 | |
307 | static const char *dac_mute_rate_txt[] = { "Fast" , "Slow" }; |
308 | |
309 | static SOC_ENUM_SINGLE_DECL(dac_mute_rate, |
310 | WM8900_REG_DACCTRL, 7, dac_mute_rate_txt); |
311 | |
312 | static const char *dac_deemphasis_txt[] = { |
313 | "Disabled" , "32kHz" , "44.1kHz" , "48kHz" |
314 | }; |
315 | |
316 | static SOC_ENUM_SINGLE_DECL(dac_deemphasis, |
317 | WM8900_REG_DACCTRL, 4, dac_deemphasis_txt); |
318 | |
319 | static const char *adc_hpf_cut_txt[] = { |
320 | "Hi-fi mode" , "Voice mode 1" , "Voice mode 2" , "Voice mode 3" |
321 | }; |
322 | |
323 | static SOC_ENUM_SINGLE_DECL(adc_hpf_cut, |
324 | WM8900_REG_ADCCTRL, 5, adc_hpf_cut_txt); |
325 | |
326 | static const char *lr_txt[] = { |
327 | "Left" , "Right" |
328 | }; |
329 | |
330 | static SOC_ENUM_SINGLE_DECL(aifl_src, |
331 | WM8900_REG_AUDIO1, 15, lr_txt); |
332 | |
333 | static SOC_ENUM_SINGLE_DECL(aifr_src, |
334 | WM8900_REG_AUDIO1, 14, lr_txt); |
335 | |
336 | static SOC_ENUM_SINGLE_DECL(dacl_src, |
337 | WM8900_REG_AUDIO2, 15, lr_txt); |
338 | |
339 | static SOC_ENUM_SINGLE_DECL(dacr_src, |
340 | WM8900_REG_AUDIO2, 14, lr_txt); |
341 | |
342 | static const char *sidetone_txt[] = { |
343 | "Disabled" , "Left ADC" , "Right ADC" |
344 | }; |
345 | |
346 | static SOC_ENUM_SINGLE_DECL(dacl_sidetone, |
347 | WM8900_REG_SIDETONE, 2, sidetone_txt); |
348 | |
349 | static SOC_ENUM_SINGLE_DECL(dacr_sidetone, |
350 | WM8900_REG_SIDETONE, 0, sidetone_txt); |
351 | |
352 | static const struct snd_kcontrol_new wm8900_snd_controls[] = { |
353 | SOC_ENUM("Mic Bias Level" , mic_bias_level), |
354 | |
355 | SOC_SINGLE_TLV("Left Input PGA Volume" , WM8900_REG_LINVOL, 0, 31, 0, |
356 | in_pga_tlv), |
357 | SOC_SINGLE("Left Input PGA Switch" , WM8900_REG_LINVOL, 6, 1, 1), |
358 | SOC_SINGLE("Left Input PGA ZC Switch" , WM8900_REG_LINVOL, 7, 1, 0), |
359 | |
360 | SOC_SINGLE_TLV("Right Input PGA Volume" , WM8900_REG_RINVOL, 0, 31, 0, |
361 | in_pga_tlv), |
362 | SOC_SINGLE("Right Input PGA Switch" , WM8900_REG_RINVOL, 6, 1, 1), |
363 | SOC_SINGLE("Right Input PGA ZC Switch" , WM8900_REG_RINVOL, 7, 1, 0), |
364 | |
365 | SOC_SINGLE("DAC Soft Mute Switch" , WM8900_REG_DACCTRL, 6, 1, 1), |
366 | SOC_ENUM("DAC Mute Rate" , dac_mute_rate), |
367 | SOC_SINGLE("DAC Mono Switch" , WM8900_REG_DACCTRL, 9, 1, 0), |
368 | SOC_ENUM("DAC Deemphasis" , dac_deemphasis), |
369 | SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch" , WM8900_REG_DACCTRL, |
370 | 12, 1, 0), |
371 | |
372 | SOC_SINGLE("ADC HPF Switch" , WM8900_REG_ADCCTRL, 8, 1, 0), |
373 | SOC_ENUM("ADC HPF Cut-Off" , adc_hpf_cut), |
374 | SOC_DOUBLE("ADC Invert Switch" , WM8900_REG_ADCCTRL, 1, 0, 1, 0), |
375 | SOC_SINGLE_TLV("Left ADC Sidetone Volume" , WM8900_REG_SIDETONE, 9, 12, 0, |
376 | adc_svol_tlv), |
377 | SOC_SINGLE_TLV("Right ADC Sidetone Volume" , WM8900_REG_SIDETONE, 5, 12, 0, |
378 | adc_svol_tlv), |
379 | SOC_ENUM("Left Digital Audio Source" , aifl_src), |
380 | SOC_ENUM("Right Digital Audio Source" , aifr_src), |
381 | |
382 | SOC_SINGLE_TLV("DAC Input Boost Volume" , WM8900_REG_AUDIO2, 10, 4, 0, |
383 | dac_boost_tlv), |
384 | SOC_ENUM("Left DAC Source" , dacl_src), |
385 | SOC_ENUM("Right DAC Source" , dacr_src), |
386 | SOC_ENUM("Left DAC Sidetone" , dacl_sidetone), |
387 | SOC_ENUM("Right DAC Sidetone" , dacr_sidetone), |
388 | SOC_DOUBLE("DAC Invert Switch" , WM8900_REG_DACCTRL, 1, 0, 1, 0), |
389 | |
390 | SOC_DOUBLE_R_TLV("Digital Playback Volume" , |
391 | WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV, |
392 | 1, 96, 0, dac_tlv), |
393 | SOC_DOUBLE_R_TLV("Digital Capture Volume" , |
394 | WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv), |
395 | |
396 | SOC_SINGLE_TLV("LINPUT3 Bypass Volume" , WM8900_REG_LOUTMIXCTL1, 4, 7, 0, |
397 | out_mix_tlv), |
398 | SOC_SINGLE_TLV("RINPUT3 Bypass Volume" , WM8900_REG_ROUTMIXCTL1, 4, 7, 0, |
399 | out_mix_tlv), |
400 | SOC_SINGLE_TLV("Left AUX Bypass Volume" , WM8900_REG_AUXOUT_CTL, 4, 7, 0, |
401 | out_mix_tlv), |
402 | SOC_SINGLE_TLV("Right AUX Bypass Volume" , WM8900_REG_AUXOUT_CTL, 0, 7, 0, |
403 | out_mix_tlv), |
404 | |
405 | SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume" , WM8900_REG_BYPASS1, 0, 7, 0, |
406 | out_mix_tlv), |
407 | SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume" , WM8900_REG_BYPASS1, 4, 7, 0, |
408 | out_mix_tlv), |
409 | SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume" , WM8900_REG_BYPASS2, 0, 7, 0, |
410 | out_mix_tlv), |
411 | SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume" , WM8900_REG_BYPASS2, 4, 7, 0, |
412 | out_mix_tlv), |
413 | |
414 | SOC_SINGLE_TLV("IN2L Boost Volume" , WM8900_REG_INBOOSTMIX1, 0, 3, 0, |
415 | in_boost_tlv), |
416 | SOC_SINGLE_TLV("IN3L Boost Volume" , WM8900_REG_INBOOSTMIX1, 4, 3, 0, |
417 | in_boost_tlv), |
418 | SOC_SINGLE_TLV("IN2R Boost Volume" , WM8900_REG_INBOOSTMIX2, 0, 3, 0, |
419 | in_boost_tlv), |
420 | SOC_SINGLE_TLV("IN3R Boost Volume" , WM8900_REG_INBOOSTMIX2, 4, 3, 0, |
421 | in_boost_tlv), |
422 | SOC_SINGLE_TLV("Left AUX Boost Volume" , WM8900_REG_AUXBOOST, 4, 3, 0, |
423 | in_boost_tlv), |
424 | SOC_SINGLE_TLV("Right AUX Boost Volume" , WM8900_REG_AUXBOOST, 0, 3, 0, |
425 | in_boost_tlv), |
426 | |
427 | SOC_DOUBLE_R_TLV("LINEOUT1 Volume" , WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL, |
428 | 0, 63, 0, out_pga_tlv), |
429 | SOC_DOUBLE_R("LINEOUT1 Switch" , WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL, |
430 | 6, 1, 1), |
431 | SOC_DOUBLE_R("LINEOUT1 ZC Switch" , WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL, |
432 | 7, 1, 0), |
433 | |
434 | SOC_DOUBLE_R_TLV("LINEOUT2 Volume" , |
435 | WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, |
436 | 0, 63, 0, out_pga_tlv), |
437 | SOC_DOUBLE_R("LINEOUT2 Switch" , |
438 | WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1), |
439 | SOC_DOUBLE_R("LINEOUT2 ZC Switch" , |
440 | WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0), |
441 | SOC_SINGLE("LINEOUT2 LP -12dB" , WM8900_REG_LOUTMIXCTL1, |
442 | 0, 1, 1), |
443 | |
444 | }; |
445 | |
446 | static const struct snd_kcontrol_new wm8900_loutmix_controls[] = { |
447 | SOC_DAPM_SINGLE("LINPUT3 Bypass Switch" , WM8900_REG_LOUTMIXCTL1, 7, 1, 0), |
448 | SOC_DAPM_SINGLE("AUX Bypass Switch" , WM8900_REG_AUXOUT_CTL, 7, 1, 0), |
449 | SOC_DAPM_SINGLE("Left Input Mixer Switch" , WM8900_REG_BYPASS1, 7, 1, 0), |
450 | SOC_DAPM_SINGLE("Right Input Mixer Switch" , WM8900_REG_BYPASS2, 3, 1, 0), |
451 | SOC_DAPM_SINGLE("DACL Switch" , WM8900_REG_LOUTMIXCTL1, 8, 1, 0), |
452 | }; |
453 | |
454 | static const struct snd_kcontrol_new wm8900_routmix_controls[] = { |
455 | SOC_DAPM_SINGLE("RINPUT3 Bypass Switch" , WM8900_REG_ROUTMIXCTL1, 7, 1, 0), |
456 | SOC_DAPM_SINGLE("AUX Bypass Switch" , WM8900_REG_AUXOUT_CTL, 3, 1, 0), |
457 | SOC_DAPM_SINGLE("Left Input Mixer Switch" , WM8900_REG_BYPASS1, 3, 1, 0), |
458 | SOC_DAPM_SINGLE("Right Input Mixer Switch" , WM8900_REG_BYPASS2, 7, 1, 0), |
459 | SOC_DAPM_SINGLE("DACR Switch" , WM8900_REG_ROUTMIXCTL1, 8, 1, 0), |
460 | }; |
461 | |
462 | static const struct snd_kcontrol_new wm8900_linmix_controls[] = { |
463 | SOC_DAPM_SINGLE("LINPUT2 Switch" , WM8900_REG_INBOOSTMIX1, 2, 1, 1), |
464 | SOC_DAPM_SINGLE("LINPUT3 Switch" , WM8900_REG_INBOOSTMIX1, 6, 1, 1), |
465 | SOC_DAPM_SINGLE("AUX Switch" , WM8900_REG_AUXBOOST, 6, 1, 1), |
466 | SOC_DAPM_SINGLE("Input PGA Switch" , WM8900_REG_ADCPATH, 6, 1, 0), |
467 | }; |
468 | |
469 | static const struct snd_kcontrol_new wm8900_rinmix_controls[] = { |
470 | SOC_DAPM_SINGLE("RINPUT2 Switch" , WM8900_REG_INBOOSTMIX2, 2, 1, 1), |
471 | SOC_DAPM_SINGLE("RINPUT3 Switch" , WM8900_REG_INBOOSTMIX2, 6, 1, 1), |
472 | SOC_DAPM_SINGLE("AUX Switch" , WM8900_REG_AUXBOOST, 2, 1, 1), |
473 | SOC_DAPM_SINGLE("Input PGA Switch" , WM8900_REG_ADCPATH, 2, 1, 0), |
474 | }; |
475 | |
476 | static const struct snd_kcontrol_new wm8900_linpga_controls[] = { |
477 | SOC_DAPM_SINGLE("LINPUT1 Switch" , WM8900_REG_INCTL, 6, 1, 0), |
478 | SOC_DAPM_SINGLE("LINPUT2 Switch" , WM8900_REG_INCTL, 5, 1, 0), |
479 | SOC_DAPM_SINGLE("LINPUT3 Switch" , WM8900_REG_INCTL, 4, 1, 0), |
480 | }; |
481 | |
482 | static const struct snd_kcontrol_new wm8900_rinpga_controls[] = { |
483 | SOC_DAPM_SINGLE("RINPUT1 Switch" , WM8900_REG_INCTL, 2, 1, 0), |
484 | SOC_DAPM_SINGLE("RINPUT2 Switch" , WM8900_REG_INCTL, 1, 1, 0), |
485 | SOC_DAPM_SINGLE("RINPUT3 Switch" , WM8900_REG_INCTL, 0, 1, 0), |
486 | }; |
487 | |
488 | static const char *wm8900_lp_mux[] = { "Disabled" , "Enabled" }; |
489 | |
490 | static SOC_ENUM_SINGLE_DECL(wm8900_lineout2_lp_mux, |
491 | WM8900_REG_LOUTMIXCTL1, 1, wm8900_lp_mux); |
492 | |
493 | static const struct snd_kcontrol_new wm8900_lineout2_lp = |
494 | SOC_DAPM_ENUM("Route" , wm8900_lineout2_lp_mux); |
495 | |
496 | static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = { |
497 | |
498 | /* Externally visible pins */ |
499 | SND_SOC_DAPM_OUTPUT("LINEOUT1L" ), |
500 | SND_SOC_DAPM_OUTPUT("LINEOUT1R" ), |
501 | SND_SOC_DAPM_OUTPUT("LINEOUT2L" ), |
502 | SND_SOC_DAPM_OUTPUT("LINEOUT2R" ), |
503 | SND_SOC_DAPM_OUTPUT("HP_L" ), |
504 | SND_SOC_DAPM_OUTPUT("HP_R" ), |
505 | |
506 | SND_SOC_DAPM_INPUT("RINPUT1" ), |
507 | SND_SOC_DAPM_INPUT("LINPUT1" ), |
508 | SND_SOC_DAPM_INPUT("RINPUT2" ), |
509 | SND_SOC_DAPM_INPUT("LINPUT2" ), |
510 | SND_SOC_DAPM_INPUT("RINPUT3" ), |
511 | SND_SOC_DAPM_INPUT("LINPUT3" ), |
512 | SND_SOC_DAPM_INPUT("AUX" ), |
513 | |
514 | SND_SOC_DAPM_VMID("VMID" ), |
515 | |
516 | /* Input */ |
517 | SND_SOC_DAPM_MIXER("Left Input PGA" , WM8900_REG_POWER2, 3, 0, |
518 | wm8900_linpga_controls, |
519 | ARRAY_SIZE(wm8900_linpga_controls)), |
520 | SND_SOC_DAPM_MIXER("Right Input PGA" , WM8900_REG_POWER2, 2, 0, |
521 | wm8900_rinpga_controls, |
522 | ARRAY_SIZE(wm8900_rinpga_controls)), |
523 | |
524 | SND_SOC_DAPM_MIXER("Left Input Mixer" , WM8900_REG_POWER2, 5, 0, |
525 | wm8900_linmix_controls, |
526 | ARRAY_SIZE(wm8900_linmix_controls)), |
527 | SND_SOC_DAPM_MIXER("Right Input Mixer" , WM8900_REG_POWER2, 4, 0, |
528 | wm8900_rinmix_controls, |
529 | ARRAY_SIZE(wm8900_rinmix_controls)), |
530 | |
531 | SND_SOC_DAPM_SUPPLY("Mic Bias" , WM8900_REG_POWER1, 4, 0, NULL, 0), |
532 | |
533 | SND_SOC_DAPM_ADC("ADCL" , "Left HiFi Capture" , WM8900_REG_POWER2, 1, 0), |
534 | SND_SOC_DAPM_ADC("ADCR" , "Right HiFi Capture" , WM8900_REG_POWER2, 0, 0), |
535 | |
536 | /* Output */ |
537 | SND_SOC_DAPM_DAC("DACL" , "Left HiFi Playback" , WM8900_REG_POWER3, 1, 0), |
538 | SND_SOC_DAPM_DAC("DACR" , "Right HiFi Playback" , WM8900_REG_POWER3, 0, 0), |
539 | |
540 | SND_SOC_DAPM_PGA_E("Headphone Amplifier" , WM8900_REG_POWER3, 7, 0, NULL, 0, |
541 | wm8900_hp_event, |
542 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
543 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
544 | |
545 | SND_SOC_DAPM_PGA("LINEOUT1L PGA" , WM8900_REG_POWER2, 8, 0, NULL, 0), |
546 | SND_SOC_DAPM_PGA("LINEOUT1R PGA" , WM8900_REG_POWER2, 7, 0, NULL, 0), |
547 | |
548 | SND_SOC_DAPM_MUX("LINEOUT2 LP" , SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp), |
549 | SND_SOC_DAPM_PGA("LINEOUT2L PGA" , WM8900_REG_POWER3, 6, 0, NULL, 0), |
550 | SND_SOC_DAPM_PGA("LINEOUT2R PGA" , WM8900_REG_POWER3, 5, 0, NULL, 0), |
551 | |
552 | SND_SOC_DAPM_MIXER("Left Output Mixer" , WM8900_REG_POWER3, 3, 0, |
553 | wm8900_loutmix_controls, |
554 | ARRAY_SIZE(wm8900_loutmix_controls)), |
555 | SND_SOC_DAPM_MIXER("Right Output Mixer" , WM8900_REG_POWER3, 2, 0, |
556 | wm8900_routmix_controls, |
557 | ARRAY_SIZE(wm8900_routmix_controls)), |
558 | }; |
559 | |
560 | /* Target, Path, Source */ |
561 | static const struct snd_soc_dapm_route wm8900_dapm_routes[] = { |
562 | /* Inputs */ |
563 | {"Left Input PGA" , "LINPUT1 Switch" , "LINPUT1" }, |
564 | {"Left Input PGA" , "LINPUT2 Switch" , "LINPUT2" }, |
565 | {"Left Input PGA" , "LINPUT3 Switch" , "LINPUT3" }, |
566 | |
567 | {"Right Input PGA" , "RINPUT1 Switch" , "RINPUT1" }, |
568 | {"Right Input PGA" , "RINPUT2 Switch" , "RINPUT2" }, |
569 | {"Right Input PGA" , "RINPUT3 Switch" , "RINPUT3" }, |
570 | |
571 | {"Left Input Mixer" , "LINPUT2 Switch" , "LINPUT2" }, |
572 | {"Left Input Mixer" , "LINPUT3 Switch" , "LINPUT3" }, |
573 | {"Left Input Mixer" , "AUX Switch" , "AUX" }, |
574 | {"Left Input Mixer" , "Input PGA Switch" , "Left Input PGA" }, |
575 | |
576 | {"Right Input Mixer" , "RINPUT2 Switch" , "RINPUT2" }, |
577 | {"Right Input Mixer" , "RINPUT3 Switch" , "RINPUT3" }, |
578 | {"Right Input Mixer" , "AUX Switch" , "AUX" }, |
579 | {"Right Input Mixer" , "Input PGA Switch" , "Right Input PGA" }, |
580 | |
581 | {"ADCL" , NULL, "Left Input Mixer" }, |
582 | {"ADCR" , NULL, "Right Input Mixer" }, |
583 | |
584 | /* Outputs */ |
585 | {"LINEOUT1L" , NULL, "LINEOUT1L PGA" }, |
586 | {"LINEOUT1L PGA" , NULL, "Left Output Mixer" }, |
587 | {"LINEOUT1R" , NULL, "LINEOUT1R PGA" }, |
588 | {"LINEOUT1R PGA" , NULL, "Right Output Mixer" }, |
589 | |
590 | {"LINEOUT2L PGA" , NULL, "Left Output Mixer" }, |
591 | {"LINEOUT2 LP" , "Disabled" , "LINEOUT2L PGA" }, |
592 | {"LINEOUT2 LP" , "Enabled" , "Left Output Mixer" }, |
593 | {"LINEOUT2L" , NULL, "LINEOUT2 LP" }, |
594 | |
595 | {"LINEOUT2R PGA" , NULL, "Right Output Mixer" }, |
596 | {"LINEOUT2 LP" , "Disabled" , "LINEOUT2R PGA" }, |
597 | {"LINEOUT2 LP" , "Enabled" , "Right Output Mixer" }, |
598 | {"LINEOUT2R" , NULL, "LINEOUT2 LP" }, |
599 | |
600 | {"Left Output Mixer" , "LINPUT3 Bypass Switch" , "LINPUT3" }, |
601 | {"Left Output Mixer" , "AUX Bypass Switch" , "AUX" }, |
602 | {"Left Output Mixer" , "Left Input Mixer Switch" , "Left Input Mixer" }, |
603 | {"Left Output Mixer" , "Right Input Mixer Switch" , "Right Input Mixer" }, |
604 | {"Left Output Mixer" , "DACL Switch" , "DACL" }, |
605 | |
606 | {"Right Output Mixer" , "RINPUT3 Bypass Switch" , "RINPUT3" }, |
607 | {"Right Output Mixer" , "AUX Bypass Switch" , "AUX" }, |
608 | {"Right Output Mixer" , "Left Input Mixer Switch" , "Left Input Mixer" }, |
609 | {"Right Output Mixer" , "Right Input Mixer Switch" , "Right Input Mixer" }, |
610 | {"Right Output Mixer" , "DACR Switch" , "DACR" }, |
611 | |
612 | /* Note that the headphone output stage needs to be connected |
613 | * externally to LINEOUT2 via DC blocking capacitors. Other |
614 | * configurations are not supported. |
615 | * |
616 | * Note also that left and right headphone paths are treated as a |
617 | * mono path. |
618 | */ |
619 | {"Headphone Amplifier" , NULL, "LINEOUT2 LP" }, |
620 | {"Headphone Amplifier" , NULL, "LINEOUT2 LP" }, |
621 | {"HP_L" , NULL, "Headphone Amplifier" }, |
622 | {"HP_R" , NULL, "Headphone Amplifier" }, |
623 | }; |
624 | |
625 | static int wm8900_hw_params(struct snd_pcm_substream *substream, |
626 | struct snd_pcm_hw_params *params, |
627 | struct snd_soc_dai *dai) |
628 | { |
629 | struct snd_soc_component *component = dai->component; |
630 | u16 reg; |
631 | |
632 | reg = snd_soc_component_read(component, WM8900_REG_AUDIO1) & ~0x60; |
633 | |
634 | switch (params_width(p: params)) { |
635 | case 16: |
636 | break; |
637 | case 20: |
638 | reg |= 0x20; |
639 | break; |
640 | case 24: |
641 | reg |= 0x40; |
642 | break; |
643 | case 32: |
644 | reg |= 0x60; |
645 | break; |
646 | default: |
647 | return -EINVAL; |
648 | } |
649 | |
650 | snd_soc_component_write(component, WM8900_REG_AUDIO1, val: reg); |
651 | |
652 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
653 | reg = snd_soc_component_read(component, WM8900_REG_DACCTRL); |
654 | |
655 | if (params_rate(p: params) <= 24000) |
656 | reg |= WM8900_REG_DACCTRL_DAC_SB_FILT; |
657 | else |
658 | reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT; |
659 | |
660 | snd_soc_component_write(component, WM8900_REG_DACCTRL, val: reg); |
661 | } |
662 | |
663 | return 0; |
664 | } |
665 | |
666 | /* FLL divisors */ |
667 | struct _fll_div { |
668 | u16 fll_ratio; |
669 | u16 fllclk_div; |
670 | u16 fll_slow_lock_ref; |
671 | u16 n; |
672 | u16 k; |
673 | }; |
674 | |
675 | /* The size in bits of the FLL divide multiplied by 10 |
676 | * to allow rounding later */ |
677 | #define FIXED_FLL_SIZE ((1 << 16) * 10) |
678 | |
679 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, |
680 | unsigned int Fout) |
681 | { |
682 | u64 Kpart; |
683 | unsigned int K, Ndiv, Nmod, target; |
684 | unsigned int div; |
685 | |
686 | if (WARN_ON(!Fout)) |
687 | return -EINVAL; |
688 | |
689 | /* The FLL must run at 90-100MHz which is then scaled down to |
690 | * the output value by FLLCLK_DIV. */ |
691 | target = Fout; |
692 | div = 1; |
693 | while (target < 90000000) { |
694 | div *= 2; |
695 | target *= 2; |
696 | } |
697 | |
698 | if (target > 100000000) |
699 | printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u" |
700 | " Fout=%u\n" , target, Fref, Fout); |
701 | if (div > 32) { |
702 | printk(KERN_ERR "wm8900: Invalid FLL division rate %u, " |
703 | "Fref=%u, Fout=%u, target=%u\n" , |
704 | div, Fref, Fout, target); |
705 | return -EINVAL; |
706 | } |
707 | |
708 | fll_div->fllclk_div = div >> 2; |
709 | |
710 | if (Fref < 48000) |
711 | fll_div->fll_slow_lock_ref = 1; |
712 | else |
713 | fll_div->fll_slow_lock_ref = 0; |
714 | |
715 | Ndiv = target / Fref; |
716 | |
717 | if (Fref < 1000000) |
718 | fll_div->fll_ratio = 8; |
719 | else |
720 | fll_div->fll_ratio = 1; |
721 | |
722 | fll_div->n = Ndiv / fll_div->fll_ratio; |
723 | Nmod = (target / fll_div->fll_ratio) % Fref; |
724 | |
725 | /* Calculate fractional part - scale up so we can round. */ |
726 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; |
727 | |
728 | do_div(Kpart, Fref); |
729 | |
730 | K = Kpart & 0xFFFFFFFF; |
731 | |
732 | if ((K % 10) >= 5) |
733 | K += 5; |
734 | |
735 | /* Move down to proper range now rounding is done */ |
736 | fll_div->k = K / 10; |
737 | |
738 | if (WARN_ON(target != Fout * (fll_div->fllclk_div << 2)) || |
739 | WARN_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n)) |
740 | return -EINVAL; |
741 | |
742 | return 0; |
743 | } |
744 | |
745 | static int wm8900_set_fll(struct snd_soc_component *component, |
746 | int fll_id, unsigned int freq_in, unsigned int freq_out) |
747 | { |
748 | struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(c: component); |
749 | struct _fll_div fll_div; |
750 | |
751 | if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out) |
752 | return 0; |
753 | |
754 | /* The digital side should be disabled during any change. */ |
755 | snd_soc_component_update_bits(component, WM8900_REG_POWER1, |
756 | WM8900_REG_POWER1_FLL_ENA, val: 0); |
757 | |
758 | /* Disable the FLL? */ |
759 | if (!freq_in || !freq_out) { |
760 | snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1, |
761 | WM8900_REG_CLOCKING1_MCLK_SRC, val: 0); |
762 | snd_soc_component_update_bits(component, WM8900_REG_FLLCTL1, |
763 | WM8900_REG_FLLCTL1_OSC_ENA, val: 0); |
764 | wm8900->fll_in = freq_in; |
765 | wm8900->fll_out = freq_out; |
766 | |
767 | return 0; |
768 | } |
769 | |
770 | if (fll_factors(fll_div: &fll_div, Fref: freq_in, Fout: freq_out) != 0) |
771 | goto reenable; |
772 | |
773 | wm8900->fll_in = freq_in; |
774 | wm8900->fll_out = freq_out; |
775 | |
776 | /* The osclilator *MUST* be enabled before we enable the |
777 | * digital circuit. */ |
778 | snd_soc_component_write(component, WM8900_REG_FLLCTL1, |
779 | val: fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA); |
780 | |
781 | snd_soc_component_write(component, WM8900_REG_FLLCTL4, val: fll_div.n >> 5); |
782 | snd_soc_component_write(component, WM8900_REG_FLLCTL5, |
783 | val: (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f)); |
784 | |
785 | if (fll_div.k) { |
786 | snd_soc_component_write(component, WM8900_REG_FLLCTL2, |
787 | val: (fll_div.k >> 8) | 0x100); |
788 | snd_soc_component_write(component, WM8900_REG_FLLCTL3, val: fll_div.k & 0xff); |
789 | } else |
790 | snd_soc_component_write(component, WM8900_REG_FLLCTL2, val: 0); |
791 | |
792 | if (fll_div.fll_slow_lock_ref) |
793 | snd_soc_component_write(component, WM8900_REG_FLLCTL6, |
794 | WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF); |
795 | else |
796 | snd_soc_component_write(component, WM8900_REG_FLLCTL6, val: 0); |
797 | |
798 | snd_soc_component_update_bits(component, WM8900_REG_POWER1, |
799 | WM8900_REG_POWER1_FLL_ENA, |
800 | WM8900_REG_POWER1_FLL_ENA); |
801 | |
802 | reenable: |
803 | snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1, |
804 | WM8900_REG_CLOCKING1_MCLK_SRC, |
805 | WM8900_REG_CLOCKING1_MCLK_SRC); |
806 | return 0; |
807 | } |
808 | |
809 | static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, |
810 | int source, unsigned int freq_in, unsigned int freq_out) |
811 | { |
812 | return wm8900_set_fll(component: codec_dai->component, fll_id: pll_id, freq_in, freq_out); |
813 | } |
814 | |
815 | static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai, |
816 | int div_id, int div) |
817 | { |
818 | struct snd_soc_component *component = codec_dai->component; |
819 | |
820 | switch (div_id) { |
821 | case WM8900_BCLK_DIV: |
822 | snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1, |
823 | WM8900_REG_CLOCKING1_BCLK_MASK, val: div); |
824 | break; |
825 | case WM8900_OPCLK_DIV: |
826 | snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1, |
827 | WM8900_REG_CLOCKING1_OPCLK_MASK, val: div); |
828 | break; |
829 | case WM8900_DAC_LRCLK: |
830 | snd_soc_component_update_bits(component, WM8900_REG_AUDIO4, |
831 | WM8900_LRC_MASK, val: div); |
832 | break; |
833 | case WM8900_ADC_LRCLK: |
834 | snd_soc_component_update_bits(component, WM8900_REG_AUDIO3, |
835 | WM8900_LRC_MASK, val: div); |
836 | break; |
837 | case WM8900_DAC_CLKDIV: |
838 | snd_soc_component_update_bits(component, WM8900_REG_CLOCKING2, |
839 | WM8900_REG_CLOCKING2_DAC_CLKDIV, val: div); |
840 | break; |
841 | case WM8900_ADC_CLKDIV: |
842 | snd_soc_component_update_bits(component, WM8900_REG_CLOCKING2, |
843 | WM8900_REG_CLOCKING2_ADC_CLKDIV, val: div); |
844 | break; |
845 | case WM8900_LRCLK_MODE: |
846 | snd_soc_component_update_bits(component, WM8900_REG_DACCTRL, |
847 | WM8900_REG_DACCTRL_AIF_LRCLKRATE, val: div); |
848 | break; |
849 | default: |
850 | return -EINVAL; |
851 | } |
852 | |
853 | return 0; |
854 | } |
855 | |
856 | |
857 | static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai, |
858 | unsigned int fmt) |
859 | { |
860 | struct snd_soc_component *component = codec_dai->component; |
861 | unsigned int clocking1, aif1, aif3, aif4; |
862 | |
863 | clocking1 = snd_soc_component_read(component, WM8900_REG_CLOCKING1); |
864 | aif1 = snd_soc_component_read(component, WM8900_REG_AUDIO1); |
865 | aif3 = snd_soc_component_read(component, WM8900_REG_AUDIO3); |
866 | aif4 = snd_soc_component_read(component, WM8900_REG_AUDIO4); |
867 | |
868 | /* set master/slave audio interface */ |
869 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
870 | case SND_SOC_DAIFMT_CBS_CFS: |
871 | clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR; |
872 | aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR; |
873 | aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR; |
874 | break; |
875 | case SND_SOC_DAIFMT_CBS_CFM: |
876 | clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR; |
877 | aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR; |
878 | aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR; |
879 | break; |
880 | case SND_SOC_DAIFMT_CBM_CFM: |
881 | clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR; |
882 | aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR; |
883 | aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR; |
884 | break; |
885 | case SND_SOC_DAIFMT_CBM_CFS: |
886 | clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR; |
887 | aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR; |
888 | aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR; |
889 | break; |
890 | default: |
891 | return -EINVAL; |
892 | } |
893 | |
894 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
895 | case SND_SOC_DAIFMT_DSP_A: |
896 | aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK; |
897 | aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV; |
898 | break; |
899 | case SND_SOC_DAIFMT_DSP_B: |
900 | aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK; |
901 | aif1 |= WM8900_REG_AUDIO1_LRCLK_INV; |
902 | break; |
903 | case SND_SOC_DAIFMT_I2S: |
904 | aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK; |
905 | aif1 |= 0x10; |
906 | break; |
907 | case SND_SOC_DAIFMT_RIGHT_J: |
908 | aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK; |
909 | break; |
910 | case SND_SOC_DAIFMT_LEFT_J: |
911 | aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK; |
912 | aif1 |= 0x8; |
913 | break; |
914 | default: |
915 | return -EINVAL; |
916 | } |
917 | |
918 | /* Clock inversion */ |
919 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
920 | case SND_SOC_DAIFMT_DSP_A: |
921 | case SND_SOC_DAIFMT_DSP_B: |
922 | /* frame inversion not valid for DSP modes */ |
923 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
924 | case SND_SOC_DAIFMT_NB_NF: |
925 | aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV; |
926 | break; |
927 | case SND_SOC_DAIFMT_IB_NF: |
928 | aif1 |= WM8900_REG_AUDIO1_BCLK_INV; |
929 | break; |
930 | default: |
931 | return -EINVAL; |
932 | } |
933 | break; |
934 | case SND_SOC_DAIFMT_I2S: |
935 | case SND_SOC_DAIFMT_RIGHT_J: |
936 | case SND_SOC_DAIFMT_LEFT_J: |
937 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
938 | case SND_SOC_DAIFMT_NB_NF: |
939 | aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV; |
940 | aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV; |
941 | break; |
942 | case SND_SOC_DAIFMT_IB_IF: |
943 | aif1 |= WM8900_REG_AUDIO1_BCLK_INV; |
944 | aif1 |= WM8900_REG_AUDIO1_LRCLK_INV; |
945 | break; |
946 | case SND_SOC_DAIFMT_IB_NF: |
947 | aif1 |= WM8900_REG_AUDIO1_BCLK_INV; |
948 | aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV; |
949 | break; |
950 | case SND_SOC_DAIFMT_NB_IF: |
951 | aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV; |
952 | aif1 |= WM8900_REG_AUDIO1_LRCLK_INV; |
953 | break; |
954 | default: |
955 | return -EINVAL; |
956 | } |
957 | break; |
958 | default: |
959 | return -EINVAL; |
960 | } |
961 | |
962 | snd_soc_component_write(component, WM8900_REG_CLOCKING1, val: clocking1); |
963 | snd_soc_component_write(component, WM8900_REG_AUDIO1, val: aif1); |
964 | snd_soc_component_write(component, WM8900_REG_AUDIO3, val: aif3); |
965 | snd_soc_component_write(component, WM8900_REG_AUDIO4, val: aif4); |
966 | |
967 | return 0; |
968 | } |
969 | |
970 | static int wm8900_mute(struct snd_soc_dai *codec_dai, int mute, int direction) |
971 | { |
972 | struct snd_soc_component *component = codec_dai->component; |
973 | u16 reg; |
974 | |
975 | reg = snd_soc_component_read(component, WM8900_REG_DACCTRL); |
976 | |
977 | if (mute) |
978 | reg |= WM8900_REG_DACCTRL_MUTE; |
979 | else |
980 | reg &= ~WM8900_REG_DACCTRL_MUTE; |
981 | |
982 | snd_soc_component_write(component, WM8900_REG_DACCTRL, val: reg); |
983 | |
984 | return 0; |
985 | } |
986 | |
987 | #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ |
988 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\ |
989 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) |
990 | |
991 | #define WM8900_PCM_FORMATS \ |
992 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ |
993 | SNDRV_PCM_FMTBIT_S24_LE) |
994 | |
995 | static const struct snd_soc_dai_ops wm8900_dai_ops = { |
996 | .hw_params = wm8900_hw_params, |
997 | .set_clkdiv = wm8900_set_dai_clkdiv, |
998 | .set_pll = wm8900_set_dai_pll, |
999 | .set_fmt = wm8900_set_dai_fmt, |
1000 | .mute_stream = wm8900_mute, |
1001 | .no_capture_mute = 1, |
1002 | }; |
1003 | |
1004 | static struct snd_soc_dai_driver wm8900_dai = { |
1005 | .name = "wm8900-hifi" , |
1006 | .playback = { |
1007 | .stream_name = "HiFi Playback" , |
1008 | .channels_min = 1, |
1009 | .channels_max = 2, |
1010 | .rates = WM8900_RATES, |
1011 | .formats = WM8900_PCM_FORMATS, |
1012 | }, |
1013 | .capture = { |
1014 | .stream_name = "HiFi Capture" , |
1015 | .channels_min = 1, |
1016 | .channels_max = 2, |
1017 | .rates = WM8900_RATES, |
1018 | .formats = WM8900_PCM_FORMATS, |
1019 | }, |
1020 | .ops = &wm8900_dai_ops, |
1021 | }; |
1022 | |
1023 | static int wm8900_set_bias_level(struct snd_soc_component *component, |
1024 | enum snd_soc_bias_level level) |
1025 | { |
1026 | u16 reg; |
1027 | |
1028 | switch (level) { |
1029 | case SND_SOC_BIAS_ON: |
1030 | /* Enable thermal shutdown */ |
1031 | snd_soc_component_update_bits(component, WM8900_REG_GPIO, |
1032 | WM8900_REG_GPIO_TEMP_ENA, |
1033 | WM8900_REG_GPIO_TEMP_ENA); |
1034 | snd_soc_component_update_bits(component, WM8900_REG_ADDCTL, |
1035 | WM8900_REG_ADDCTL_TEMP_SD, |
1036 | WM8900_REG_ADDCTL_TEMP_SD); |
1037 | break; |
1038 | |
1039 | case SND_SOC_BIAS_PREPARE: |
1040 | break; |
1041 | |
1042 | case SND_SOC_BIAS_STANDBY: |
1043 | /* Charge capacitors if initial power up */ |
1044 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { |
1045 | /* STARTUP_BIAS_ENA on */ |
1046 | snd_soc_component_write(component, WM8900_REG_POWER1, |
1047 | WM8900_REG_POWER1_STARTUP_BIAS_ENA); |
1048 | |
1049 | /* Startup bias mode */ |
1050 | snd_soc_component_write(component, WM8900_REG_ADDCTL, |
1051 | WM8900_REG_ADDCTL_BIAS_SRC | |
1052 | WM8900_REG_ADDCTL_VMID_SOFTST); |
1053 | |
1054 | /* VMID 2x50k */ |
1055 | snd_soc_component_write(component, WM8900_REG_POWER1, |
1056 | WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1); |
1057 | |
1058 | /* Allow capacitors to charge */ |
1059 | schedule_timeout_interruptible(timeout: msecs_to_jiffies(m: 400)); |
1060 | |
1061 | /* Enable bias */ |
1062 | snd_soc_component_write(component, WM8900_REG_POWER1, |
1063 | WM8900_REG_POWER1_STARTUP_BIAS_ENA | |
1064 | WM8900_REG_POWER1_BIAS_ENA | 0x1); |
1065 | |
1066 | snd_soc_component_write(component, WM8900_REG_ADDCTL, val: 0); |
1067 | |
1068 | snd_soc_component_write(component, WM8900_REG_POWER1, |
1069 | WM8900_REG_POWER1_BIAS_ENA | 0x1); |
1070 | } |
1071 | |
1072 | reg = snd_soc_component_read(component, WM8900_REG_POWER1); |
1073 | snd_soc_component_write(component, WM8900_REG_POWER1, |
1074 | val: (reg & WM8900_REG_POWER1_FLL_ENA) | |
1075 | WM8900_REG_POWER1_BIAS_ENA | 0x1); |
1076 | snd_soc_component_write(component, WM8900_REG_POWER2, |
1077 | WM8900_REG_POWER2_SYSCLK_ENA); |
1078 | snd_soc_component_write(component, WM8900_REG_POWER3, val: 0); |
1079 | break; |
1080 | |
1081 | case SND_SOC_BIAS_OFF: |
1082 | /* Startup bias enable */ |
1083 | reg = snd_soc_component_read(component, WM8900_REG_POWER1); |
1084 | snd_soc_component_write(component, WM8900_REG_POWER1, |
1085 | val: reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA); |
1086 | snd_soc_component_write(component, WM8900_REG_ADDCTL, |
1087 | WM8900_REG_ADDCTL_BIAS_SRC | |
1088 | WM8900_REG_ADDCTL_VMID_SOFTST); |
1089 | |
1090 | /* Discharge caps */ |
1091 | snd_soc_component_write(component, WM8900_REG_POWER1, |
1092 | WM8900_REG_POWER1_STARTUP_BIAS_ENA); |
1093 | schedule_timeout_interruptible(timeout: msecs_to_jiffies(m: 500)); |
1094 | |
1095 | /* Remove clamp */ |
1096 | snd_soc_component_write(component, WM8900_REG_HPCTL1, val: 0); |
1097 | |
1098 | /* Power down */ |
1099 | snd_soc_component_write(component, WM8900_REG_ADDCTL, val: 0); |
1100 | snd_soc_component_write(component, WM8900_REG_POWER1, val: 0); |
1101 | snd_soc_component_write(component, WM8900_REG_POWER2, val: 0); |
1102 | snd_soc_component_write(component, WM8900_REG_POWER3, val: 0); |
1103 | |
1104 | /* Need to let things settle before stopping the clock |
1105 | * to ensure that restart works, see "Stopping the |
1106 | * master clock" in the datasheet. */ |
1107 | schedule_timeout_interruptible(timeout: msecs_to_jiffies(m: 1)); |
1108 | snd_soc_component_write(component, WM8900_REG_POWER2, |
1109 | WM8900_REG_POWER2_SYSCLK_ENA); |
1110 | break; |
1111 | } |
1112 | return 0; |
1113 | } |
1114 | |
1115 | static int wm8900_suspend(struct snd_soc_component *component) |
1116 | { |
1117 | struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(c: component); |
1118 | int fll_out = wm8900->fll_out; |
1119 | int fll_in = wm8900->fll_in; |
1120 | int ret; |
1121 | |
1122 | /* Stop the FLL in an orderly fashion */ |
1123 | ret = wm8900_set_fll(component, fll_id: 0, freq_in: 0, freq_out: 0); |
1124 | if (ret != 0) { |
1125 | dev_err(component->dev, "Failed to stop FLL\n" ); |
1126 | return ret; |
1127 | } |
1128 | |
1129 | wm8900->fll_out = fll_out; |
1130 | wm8900->fll_in = fll_in; |
1131 | |
1132 | snd_soc_component_force_bias_level(component, level: SND_SOC_BIAS_OFF); |
1133 | |
1134 | return 0; |
1135 | } |
1136 | |
1137 | static int wm8900_resume(struct snd_soc_component *component) |
1138 | { |
1139 | struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(c: component); |
1140 | int ret; |
1141 | |
1142 | wm8900_reset(component); |
1143 | |
1144 | ret = regcache_sync(map: wm8900->regmap); |
1145 | if (ret != 0) { |
1146 | dev_err(component->dev, "Failed to restore cache: %d\n" , ret); |
1147 | return ret; |
1148 | } |
1149 | |
1150 | snd_soc_component_force_bias_level(component, level: SND_SOC_BIAS_STANDBY); |
1151 | |
1152 | /* Restart the FLL? */ |
1153 | if (wm8900->fll_out) { |
1154 | int fll_out = wm8900->fll_out; |
1155 | int fll_in = wm8900->fll_in; |
1156 | |
1157 | wm8900->fll_in = 0; |
1158 | wm8900->fll_out = 0; |
1159 | |
1160 | ret = wm8900_set_fll(component, fll_id: 0, freq_in: fll_in, freq_out: fll_out); |
1161 | if (ret != 0) { |
1162 | dev_err(component->dev, "Failed to restart FLL\n" ); |
1163 | return ret; |
1164 | } |
1165 | } |
1166 | |
1167 | return 0; |
1168 | } |
1169 | |
1170 | static int wm8900_probe(struct snd_soc_component *component) |
1171 | { |
1172 | int reg; |
1173 | |
1174 | reg = snd_soc_component_read(component, WM8900_REG_ID); |
1175 | if (reg != 0x8900) { |
1176 | dev_err(component->dev, "Device is not a WM8900 - ID %x\n" , reg); |
1177 | return -ENODEV; |
1178 | } |
1179 | |
1180 | wm8900_reset(component); |
1181 | |
1182 | /* Turn the chip on */ |
1183 | snd_soc_component_force_bias_level(component, level: SND_SOC_BIAS_STANDBY); |
1184 | |
1185 | /* Latch the volume update bits */ |
1186 | snd_soc_component_update_bits(component, WM8900_REG_LINVOL, mask: 0x100, val: 0x100); |
1187 | snd_soc_component_update_bits(component, WM8900_REG_RINVOL, mask: 0x100, val: 0x100); |
1188 | snd_soc_component_update_bits(component, WM8900_REG_LOUT1CTL, mask: 0x100, val: 0x100); |
1189 | snd_soc_component_update_bits(component, WM8900_REG_ROUT1CTL, mask: 0x100, val: 0x100); |
1190 | snd_soc_component_update_bits(component, WM8900_REG_LOUT2CTL, mask: 0x100, val: 0x100); |
1191 | snd_soc_component_update_bits(component, WM8900_REG_ROUT2CTL, mask: 0x100, val: 0x100); |
1192 | snd_soc_component_update_bits(component, WM8900_REG_LDAC_DV, mask: 0x100, val: 0x100); |
1193 | snd_soc_component_update_bits(component, WM8900_REG_RDAC_DV, mask: 0x100, val: 0x100); |
1194 | snd_soc_component_update_bits(component, WM8900_REG_LADC_DV, mask: 0x100, val: 0x100); |
1195 | snd_soc_component_update_bits(component, WM8900_REG_RADC_DV, mask: 0x100, val: 0x100); |
1196 | |
1197 | /* Set the DAC and mixer output bias */ |
1198 | snd_soc_component_write(component, WM8900_REG_OUTBIASCTL, val: 0x81); |
1199 | |
1200 | return 0; |
1201 | } |
1202 | |
1203 | static const struct snd_soc_component_driver soc_component_dev_wm8900 = { |
1204 | .probe = wm8900_probe, |
1205 | .suspend = wm8900_suspend, |
1206 | .resume = wm8900_resume, |
1207 | .set_bias_level = wm8900_set_bias_level, |
1208 | .controls = wm8900_snd_controls, |
1209 | .num_controls = ARRAY_SIZE(wm8900_snd_controls), |
1210 | .dapm_widgets = wm8900_dapm_widgets, |
1211 | .num_dapm_widgets = ARRAY_SIZE(wm8900_dapm_widgets), |
1212 | .dapm_routes = wm8900_dapm_routes, |
1213 | .num_dapm_routes = ARRAY_SIZE(wm8900_dapm_routes), |
1214 | .idle_bias_on = 1, |
1215 | .use_pmdown_time = 1, |
1216 | .endianness = 1, |
1217 | }; |
1218 | |
1219 | static const struct regmap_config wm8900_regmap = { |
1220 | .reg_bits = 8, |
1221 | .val_bits = 16, |
1222 | .max_register = WM8900_MAXREG, |
1223 | |
1224 | .reg_defaults = wm8900_reg_defaults, |
1225 | .num_reg_defaults = ARRAY_SIZE(wm8900_reg_defaults), |
1226 | .cache_type = REGCACHE_MAPLE, |
1227 | |
1228 | .volatile_reg = wm8900_volatile_register, |
1229 | }; |
1230 | |
1231 | #if defined(CONFIG_SPI_MASTER) |
1232 | static int wm8900_spi_probe(struct spi_device *spi) |
1233 | { |
1234 | struct wm8900_priv *wm8900; |
1235 | int ret; |
1236 | |
1237 | wm8900 = devm_kzalloc(dev: &spi->dev, size: sizeof(struct wm8900_priv), |
1238 | GFP_KERNEL); |
1239 | if (wm8900 == NULL) |
1240 | return -ENOMEM; |
1241 | |
1242 | wm8900->regmap = devm_regmap_init_spi(spi, &wm8900_regmap); |
1243 | if (IS_ERR(ptr: wm8900->regmap)) |
1244 | return PTR_ERR(ptr: wm8900->regmap); |
1245 | |
1246 | spi_set_drvdata(spi, data: wm8900); |
1247 | |
1248 | ret = devm_snd_soc_register_component(dev: &spi->dev, |
1249 | component_driver: &soc_component_dev_wm8900, dai_drv: &wm8900_dai, num_dai: 1); |
1250 | |
1251 | return ret; |
1252 | } |
1253 | |
1254 | static struct spi_driver wm8900_spi_driver = { |
1255 | .driver = { |
1256 | .name = "wm8900" , |
1257 | }, |
1258 | .probe = wm8900_spi_probe, |
1259 | }; |
1260 | #endif /* CONFIG_SPI_MASTER */ |
1261 | |
1262 | #if IS_ENABLED(CONFIG_I2C) |
1263 | static int wm8900_i2c_probe(struct i2c_client *i2c) |
1264 | { |
1265 | struct wm8900_priv *wm8900; |
1266 | int ret; |
1267 | |
1268 | wm8900 = devm_kzalloc(dev: &i2c->dev, size: sizeof(struct wm8900_priv), |
1269 | GFP_KERNEL); |
1270 | if (wm8900 == NULL) |
1271 | return -ENOMEM; |
1272 | |
1273 | wm8900->regmap = devm_regmap_init_i2c(i2c, &wm8900_regmap); |
1274 | if (IS_ERR(ptr: wm8900->regmap)) |
1275 | return PTR_ERR(ptr: wm8900->regmap); |
1276 | |
1277 | i2c_set_clientdata(client: i2c, data: wm8900); |
1278 | |
1279 | ret = devm_snd_soc_register_component(dev: &i2c->dev, |
1280 | component_driver: &soc_component_dev_wm8900, dai_drv: &wm8900_dai, num_dai: 1); |
1281 | |
1282 | return ret; |
1283 | } |
1284 | |
1285 | static void wm8900_i2c_remove(struct i2c_client *client) |
1286 | {} |
1287 | |
1288 | static const struct i2c_device_id wm8900_i2c_id[] = { |
1289 | { "wm8900" , 0 }, |
1290 | { } |
1291 | }; |
1292 | MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id); |
1293 | |
1294 | static struct i2c_driver wm8900_i2c_driver = { |
1295 | .driver = { |
1296 | .name = "wm8900" , |
1297 | }, |
1298 | .probe = wm8900_i2c_probe, |
1299 | .remove = wm8900_i2c_remove, |
1300 | .id_table = wm8900_i2c_id, |
1301 | }; |
1302 | #endif |
1303 | |
1304 | static int __init wm8900_modinit(void) |
1305 | { |
1306 | int ret = 0; |
1307 | #if IS_ENABLED(CONFIG_I2C) |
1308 | ret = i2c_add_driver(&wm8900_i2c_driver); |
1309 | if (ret != 0) { |
1310 | printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n" , |
1311 | ret); |
1312 | } |
1313 | #endif |
1314 | #if defined(CONFIG_SPI_MASTER) |
1315 | ret = spi_register_driver(&wm8900_spi_driver); |
1316 | if (ret != 0) { |
1317 | printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n" , |
1318 | ret); |
1319 | } |
1320 | #endif |
1321 | return ret; |
1322 | } |
1323 | module_init(wm8900_modinit); |
1324 | |
1325 | static void __exit wm8900_exit(void) |
1326 | { |
1327 | #if IS_ENABLED(CONFIG_I2C) |
1328 | i2c_del_driver(driver: &wm8900_i2c_driver); |
1329 | #endif |
1330 | #if defined(CONFIG_SPI_MASTER) |
1331 | spi_unregister_driver(sdrv: &wm8900_spi_driver); |
1332 | #endif |
1333 | } |
1334 | module_exit(wm8900_exit); |
1335 | |
1336 | MODULE_DESCRIPTION("ASoC WM8900 driver" ); |
1337 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>" ); |
1338 | MODULE_LICENSE("GPL" ); |
1339 | |