1 | //===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | /// \file |
10 | /// The AMDGPU TargetMachine interface definition for hw codegen targets. |
11 | // |
12 | //===----------------------------------------------------------------------===// |
13 | |
14 | #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H |
15 | #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H |
16 | |
17 | #include "GCNSubtarget.h" |
18 | #include "llvm/CodeGen/TargetPassConfig.h" |
19 | #include "llvm/Target/TargetMachine.h" |
20 | #include <optional> |
21 | #include <utility> |
22 | |
23 | namespace llvm { |
24 | |
25 | //===----------------------------------------------------------------------===// |
26 | // AMDGPU Target Machine (R600+) |
27 | //===----------------------------------------------------------------------===// |
28 | |
29 | class AMDGPUTargetMachine : public LLVMTargetMachine { |
30 | protected: |
31 | std::unique_ptr<TargetLoweringObjectFile> TLOF; |
32 | |
33 | StringRef getGPUName(const Function &F) const; |
34 | StringRef getFeatureString(const Function &F) const; |
35 | |
36 | public: |
37 | static bool EnableLateStructurizeCFG; |
38 | static bool EnableFunctionCalls; |
39 | static bool EnableLowerModuleLDS; |
40 | static bool DisableStructurizer; |
41 | |
42 | AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, |
43 | StringRef FS, const TargetOptions &Options, |
44 | std::optional<Reloc::Model> RM, |
45 | std::optional<CodeModel::Model> CM, CodeGenOptLevel OL); |
46 | ~AMDGPUTargetMachine() override; |
47 | |
48 | const TargetSubtargetInfo *getSubtargetImpl() const; |
49 | const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override = 0; |
50 | |
51 | TargetLoweringObjectFile *getObjFileLowering() const override { |
52 | return TLOF.get(); |
53 | } |
54 | |
55 | void registerPassBuilderCallbacks(PassBuilder &PB, |
56 | bool PopulateClassToPassNames) override; |
57 | void registerDefaultAliasAnalyses(AAManager &) override; |
58 | |
59 | /// Get the integer value of a null pointer in the given address space. |
60 | static int64_t getNullPointerValue(unsigned AddrSpace); |
61 | |
62 | bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; |
63 | |
64 | unsigned getAssumedAddrSpace(const Value *V) const override; |
65 | |
66 | std::pair<const Value *, unsigned> |
67 | getPredicatedAddrSpace(const Value *V) const override; |
68 | |
69 | unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override; |
70 | }; |
71 | |
72 | //===----------------------------------------------------------------------===// |
73 | // GCN Target Machine (SI+) |
74 | //===----------------------------------------------------------------------===// |
75 | |
76 | class GCNTargetMachine final : public AMDGPUTargetMachine { |
77 | private: |
78 | mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap; |
79 | |
80 | public: |
81 | GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, |
82 | StringRef FS, const TargetOptions &Options, |
83 | std::optional<Reloc::Model> RM, |
84 | std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, |
85 | bool JIT); |
86 | |
87 | TargetPassConfig *createPassConfig(PassManagerBase &PM) override; |
88 | |
89 | const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override; |
90 | |
91 | TargetTransformInfo getTargetTransformInfo(const Function &F) const override; |
92 | |
93 | bool useIPRA() const override { |
94 | return true; |
95 | } |
96 | |
97 | void registerMachineRegisterInfoCallback(MachineFunction &MF) const override; |
98 | |
99 | MachineFunctionInfo * |
100 | createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, |
101 | const TargetSubtargetInfo *STI) const override; |
102 | |
103 | yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override; |
104 | yaml::MachineFunctionInfo * |
105 | convertFuncInfoToYAML(const MachineFunction &MF) const override; |
106 | bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, |
107 | PerFunctionMIParsingState &PFS, |
108 | SMDiagnostic &Error, |
109 | SMRange &SourceRange) const override; |
110 | }; |
111 | |
112 | //===----------------------------------------------------------------------===// |
113 | // AMDGPU Pass Setup |
114 | //===----------------------------------------------------------------------===// |
115 | |
116 | class AMDGPUPassConfig : public TargetPassConfig { |
117 | public: |
118 | AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM); |
119 | |
120 | AMDGPUTargetMachine &getAMDGPUTargetMachine() const { |
121 | return getTM<AMDGPUTargetMachine>(); |
122 | } |
123 | |
124 | ScheduleDAGInstrs * |
125 | createMachineScheduler(MachineSchedContext *C) const override; |
126 | |
127 | void addEarlyCSEOrGVNPass(); |
128 | void addStraightLineScalarOptimizationPasses(); |
129 | void addIRPasses() override; |
130 | void addCodeGenPrepare() override; |
131 | bool addPreISel() override; |
132 | bool addInstSelector() override; |
133 | bool addGCPasses() override; |
134 | |
135 | std::unique_ptr<CSEConfigBase> getCSEConfig() const override; |
136 | |
137 | /// Check if a pass is enabled given \p Opt option. The option always |
138 | /// overrides defaults if explicitly used. Otherwise its default will |
139 | /// be used given that a pass shall work at an optimization \p Level |
140 | /// minimum. |
141 | bool isPassEnabled(const cl::opt<bool> &Opt, |
142 | CodeGenOptLevel Level = CodeGenOptLevel::Default) const { |
143 | if (Opt.getNumOccurrences()) |
144 | return Opt; |
145 | if (TM->getOptLevel() < Level) |
146 | return false; |
147 | return Opt; |
148 | } |
149 | }; |
150 | |
151 | } // end namespace llvm |
152 | |
153 | #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H |
154 | |