1 | //===- ARCInstrInfo.h - ARC Instruction Information -------------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file contains the ARC implementation of the TargetInstrInfo class. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #ifndef LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H |
14 | #define LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H |
15 | |
16 | #include "ARCRegisterInfo.h" |
17 | #include "llvm/CodeGen/TargetInstrInfo.h" |
18 | |
19 | #define |
20 | #include "ARCGenInstrInfo.inc" |
21 | |
22 | namespace llvm { |
23 | |
24 | class ARCSubtarget; |
25 | |
26 | class ARCInstrInfo : public ARCGenInstrInfo { |
27 | const ARCRegisterInfo RI; |
28 | virtual void anchor(); |
29 | |
30 | public: |
31 | ARCInstrInfo(const ARCSubtarget &); |
32 | |
33 | const ARCRegisterInfo &getRegisterInfo() const { return RI; } |
34 | |
35 | /// If the specified machine instruction is a direct |
36 | /// load from a stack slot, return the virtual or physical register number of |
37 | /// the destination along with the FrameIndex of the loaded stack slot. If |
38 | /// not, return 0. This predicate must return 0 if the instruction has |
39 | /// any side effects other than loading from the stack slot. |
40 | Register isLoadFromStackSlot(const MachineInstr &MI, |
41 | int &FrameIndex) const override; |
42 | |
43 | /// If the specified machine instruction is a direct |
44 | /// store to a stack slot, return the virtual or physical register number of |
45 | /// the source reg along with the FrameIndex of the loaded stack slot. If |
46 | /// not, return 0. This predicate must return 0 if the instruction has |
47 | /// any side effects other than storing to the stack slot. |
48 | Register isStoreToStackSlot(const MachineInstr &MI, |
49 | int &FrameIndex) const override; |
50 | |
51 | unsigned getInstSizeInBytes(const MachineInstr &MI) const override; |
52 | |
53 | bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, |
54 | MachineBasicBlock *&FBB, |
55 | SmallVectorImpl<MachineOperand> &Cond, |
56 | bool AllowModify) const override; |
57 | |
58 | unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
59 | MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, |
60 | const DebugLoc &, |
61 | int *BytesAdded = nullptr) const override; |
62 | |
63 | unsigned removeBranch(MachineBasicBlock &MBB, |
64 | int *BytesRemoved = nullptr) const override; |
65 | |
66 | void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
67 | const DebugLoc &, MCRegister DestReg, MCRegister SrcReg, |
68 | bool KillSrc) const override; |
69 | |
70 | void storeRegToStackSlot(MachineBasicBlock &MBB, |
71 | MachineBasicBlock::iterator MI, Register SrcReg, |
72 | bool IsKill, int FrameIndex, |
73 | const TargetRegisterClass *RC, |
74 | const TargetRegisterInfo *TRI, |
75 | Register VReg) const override; |
76 | |
77 | void loadRegFromStackSlot(MachineBasicBlock &MBB, |
78 | MachineBasicBlock::iterator MI, Register DestReg, |
79 | int FrameIndex, const TargetRegisterClass *RC, |
80 | const TargetRegisterInfo *TRI, |
81 | Register VReg) const override; |
82 | |
83 | bool |
84 | reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; |
85 | |
86 | |
87 | bool isPostIncrement(const MachineInstr &MI) const override; |
88 | |
89 | // ARC-specific |
90 | bool isPreIncrement(const MachineInstr &MI) const; |
91 | |
92 | virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, |
93 | unsigned &BasePos, |
94 | unsigned &OffsetPos) const override; |
95 | |
96 | // Emit code before MBBI to load immediate value into physical register Reg. |
97 | // Returns an iterator to the new instruction. |
98 | MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB, |
99 | MachineBasicBlock::iterator MI, |
100 | unsigned Reg, uint64_t Value) const; |
101 | }; |
102 | |
103 | } // end namespace llvm |
104 | |
105 | #endif // LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H |
106 | |