1 | //===-- CSKYInstrInfo.h - CSKY Instruction Information --------*- C++ -*---===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file contains the CSKY implementation of the TargetInstrInfo class. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #ifndef LLVM_LIB_TARGET_CSKY_CSKYINSTRINFO_H |
14 | #define LLVM_LIB_TARGET_CSKY_CSKYINSTRINFO_H |
15 | |
16 | #include "MCTargetDesc/CSKYMCTargetDesc.h" |
17 | #include "llvm/CodeGen/TargetInstrInfo.h" |
18 | |
19 | #define |
20 | #include "CSKYGenInstrInfo.inc" |
21 | |
22 | namespace llvm { |
23 | |
24 | class CSKYSubtarget; |
25 | |
26 | class CSKYInstrInfo : public CSKYGenInstrInfo { |
27 | bool v2sf; |
28 | bool v2df; |
29 | bool v3sf; |
30 | bool v3df; |
31 | |
32 | protected: |
33 | const CSKYSubtarget &STI; |
34 | |
35 | public: |
36 | explicit CSKYInstrInfo(CSKYSubtarget &STI); |
37 | |
38 | Register isLoadFromStackSlot(const MachineInstr &MI, |
39 | int &FrameIndex) const override; |
40 | Register isStoreToStackSlot(const MachineInstr &MI, |
41 | int &FrameIndex) const override; |
42 | |
43 | void storeRegToStackSlot(MachineBasicBlock &MBB, |
44 | MachineBasicBlock::iterator MI, Register SrcReg, |
45 | bool IsKill, int FrameIndex, |
46 | const TargetRegisterClass *RC, |
47 | const TargetRegisterInfo *TRI, |
48 | Register VReg) const override; |
49 | |
50 | void loadRegFromStackSlot(MachineBasicBlock &MBB, |
51 | MachineBasicBlock::iterator MI, Register DestReg, |
52 | int FrameIndex, const TargetRegisterClass *RC, |
53 | const TargetRegisterInfo *TRI, |
54 | Register VReg) const override; |
55 | |
56 | void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, |
57 | const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, |
58 | bool KillSrc) const override; |
59 | |
60 | unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
61 | MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, |
62 | const DebugLoc &DL, |
63 | int *BytesAdded = nullptr) const override; |
64 | |
65 | bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, |
66 | MachineBasicBlock *&FBB, |
67 | SmallVectorImpl<MachineOperand> &Cond, |
68 | bool AllowModify = false) const override; |
69 | |
70 | unsigned removeBranch(MachineBasicBlock &MBB, |
71 | int *BytesRemoved = nullptr) const override; |
72 | |
73 | bool |
74 | reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; |
75 | |
76 | MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; |
77 | |
78 | unsigned getInstSizeInBytes(const MachineInstr &MI) const override; |
79 | |
80 | Register getGlobalBaseReg(MachineFunction &MF) const; |
81 | |
82 | // Materializes the given integer Val into DstReg. |
83 | Register movImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, |
84 | const DebugLoc &DL, uint64_t Val, |
85 | MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; |
86 | }; |
87 | |
88 | } // namespace llvm |
89 | |
90 | #endif // LLVM_LIB_TARGET_CSKY_CSKYINSTRINFO_H |
91 | |