1 | //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file implements the MipsAsmBackend class. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | // |
13 | |
14 | #include "MCTargetDesc/MipsAsmBackend.h" |
15 | #include "MCTargetDesc/MipsABIInfo.h" |
16 | #include "MCTargetDesc/MipsFixupKinds.h" |
17 | #include "MCTargetDesc/MipsMCExpr.h" |
18 | #include "MCTargetDesc/MipsMCTargetDesc.h" |
19 | #include "llvm/ADT/STLExtras.h" |
20 | #include "llvm/MC/MCAsmBackend.h" |
21 | #include "llvm/MC/MCAssembler.h" |
22 | #include "llvm/MC/MCContext.h" |
23 | #include "llvm/MC/MCDirectives.h" |
24 | #include "llvm/MC/MCELFObjectWriter.h" |
25 | #include "llvm/MC/MCFixupKindInfo.h" |
26 | #include "llvm/MC/MCObjectWriter.h" |
27 | #include "llvm/MC/MCSubtargetInfo.h" |
28 | #include "llvm/MC/MCTargetOptions.h" |
29 | #include "llvm/MC/MCValue.h" |
30 | #include "llvm/Support/ErrorHandling.h" |
31 | #include "llvm/Support/Format.h" |
32 | #include "llvm/Support/MathExtras.h" |
33 | #include "llvm/Support/raw_ostream.h" |
34 | |
35 | using namespace llvm; |
36 | |
37 | // Prepare value for the target space for it |
38 | static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, |
39 | MCContext &Ctx) { |
40 | |
41 | unsigned Kind = Fixup.getKind(); |
42 | |
43 | // Add/subtract and shift |
44 | switch (Kind) { |
45 | default: |
46 | return 0; |
47 | case FK_Data_2: |
48 | case Mips::fixup_Mips_LO16: |
49 | case Mips::fixup_Mips_GPREL16: |
50 | case Mips::fixup_Mips_GPOFF_HI: |
51 | case Mips::fixup_Mips_GPOFF_LO: |
52 | case Mips::fixup_Mips_GOT_PAGE: |
53 | case Mips::fixup_Mips_GOT_OFST: |
54 | case Mips::fixup_Mips_GOT_DISP: |
55 | case Mips::fixup_Mips_GOT_LO16: |
56 | case Mips::fixup_Mips_CALL_LO16: |
57 | case Mips::fixup_MICROMIPS_GPOFF_HI: |
58 | case Mips::fixup_MICROMIPS_GPOFF_LO: |
59 | case Mips::fixup_MICROMIPS_LO16: |
60 | case Mips::fixup_MICROMIPS_GOT_PAGE: |
61 | case Mips::fixup_MICROMIPS_GOT_OFST: |
62 | case Mips::fixup_MICROMIPS_GOT_DISP: |
63 | case Mips::fixup_MIPS_PCLO16: |
64 | Value &= 0xffff; |
65 | break; |
66 | case FK_DTPRel_4: |
67 | case FK_DTPRel_8: |
68 | case FK_TPRel_4: |
69 | case FK_TPRel_8: |
70 | case FK_GPRel_4: |
71 | case FK_Data_4: |
72 | case FK_Data_8: |
73 | case Mips::fixup_Mips_SUB: |
74 | case Mips::fixup_MICROMIPS_SUB: |
75 | break; |
76 | case Mips::fixup_Mips_PC16: |
77 | // The displacement is then divided by 4 to give us an 18 bit |
78 | // address range. Forcing a signed division because Value can be negative. |
79 | Value = (int64_t)Value / 4; |
80 | // We now check if Value can be encoded as a 16-bit signed immediate. |
81 | if (!isInt<16>(x: Value)) { |
82 | Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC16 fixup" ); |
83 | return 0; |
84 | } |
85 | break; |
86 | case Mips::fixup_MIPS_PC19_S2: |
87 | case Mips::fixup_MICROMIPS_PC19_S2: |
88 | // Forcing a signed division because Value can be negative. |
89 | Value = (int64_t)Value / 4; |
90 | // We now check if Value can be encoded as a 19-bit signed immediate. |
91 | if (!isInt<19>(x: Value)) { |
92 | Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC19 fixup" ); |
93 | return 0; |
94 | } |
95 | break; |
96 | case Mips::fixup_Mips_26: |
97 | // So far we are only using this type for jumps. |
98 | // The displacement is then divided by 4 to give us an 28 bit |
99 | // address range. |
100 | Value >>= 2; |
101 | break; |
102 | case Mips::fixup_Mips_HI16: |
103 | case Mips::fixup_Mips_GOT: |
104 | case Mips::fixup_MICROMIPS_GOT16: |
105 | case Mips::fixup_Mips_GOT_HI16: |
106 | case Mips::fixup_Mips_CALL_HI16: |
107 | case Mips::fixup_MICROMIPS_HI16: |
108 | case Mips::fixup_MIPS_PCHI16: |
109 | // Get the 2nd 16-bits. Also add 1 if bit 15 is 1. |
110 | Value = ((Value + 0x8000) >> 16) & 0xffff; |
111 | break; |
112 | case Mips::fixup_Mips_HIGHER: |
113 | case Mips::fixup_MICROMIPS_HIGHER: |
114 | // Get the 3rd 16-bits. |
115 | Value = ((Value + 0x80008000LL) >> 32) & 0xffff; |
116 | break; |
117 | case Mips::fixup_Mips_HIGHEST: |
118 | case Mips::fixup_MICROMIPS_HIGHEST: |
119 | // Get the 4th 16-bits. |
120 | Value = ((Value + 0x800080008000LL) >> 48) & 0xffff; |
121 | break; |
122 | case Mips::fixup_MICROMIPS_26_S1: |
123 | Value >>= 1; |
124 | break; |
125 | case Mips::fixup_MICROMIPS_PC7_S1: |
126 | Value -= 4; |
127 | // Forcing a signed division because Value can be negative. |
128 | Value = (int64_t) Value / 2; |
129 | // We now check if Value can be encoded as a 7-bit signed immediate. |
130 | if (!isInt<7>(x: Value)) { |
131 | Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC7 fixup" ); |
132 | return 0; |
133 | } |
134 | break; |
135 | case Mips::fixup_MICROMIPS_PC10_S1: |
136 | Value -= 2; |
137 | // Forcing a signed division because Value can be negative. |
138 | Value = (int64_t) Value / 2; |
139 | // We now check if Value can be encoded as a 10-bit signed immediate. |
140 | if (!isInt<10>(x: Value)) { |
141 | Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC10 fixup" ); |
142 | return 0; |
143 | } |
144 | break; |
145 | case Mips::fixup_MICROMIPS_PC16_S1: |
146 | Value -= 4; |
147 | // Forcing a signed division because Value can be negative. |
148 | Value = (int64_t)Value / 2; |
149 | // We now check if Value can be encoded as a 16-bit signed immediate. |
150 | if (!isInt<16>(x: Value)) { |
151 | Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC16 fixup" ); |
152 | return 0; |
153 | } |
154 | break; |
155 | case Mips::fixup_MIPS_PC18_S3: |
156 | // Forcing a signed division because Value can be negative. |
157 | Value = (int64_t)Value / 8; |
158 | // We now check if Value can be encoded as a 18-bit signed immediate. |
159 | if (!isInt<18>(x: Value)) { |
160 | Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC18 fixup" ); |
161 | return 0; |
162 | } |
163 | break; |
164 | case Mips::fixup_MICROMIPS_PC18_S3: |
165 | // Check alignment. |
166 | if ((Value & 7)) { |
167 | Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC18 fixup" ); |
168 | } |
169 | // Forcing a signed division because Value can be negative. |
170 | Value = (int64_t)Value / 8; |
171 | // We now check if Value can be encoded as a 18-bit signed immediate. |
172 | if (!isInt<18>(x: Value)) { |
173 | Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC18 fixup" ); |
174 | return 0; |
175 | } |
176 | break; |
177 | case Mips::fixup_MIPS_PC21_S2: |
178 | // Forcing a signed division because Value can be negative. |
179 | Value = (int64_t) Value / 4; |
180 | // We now check if Value can be encoded as a 21-bit signed immediate. |
181 | if (!isInt<21>(x: Value)) { |
182 | Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC21 fixup" ); |
183 | return 0; |
184 | } |
185 | break; |
186 | case Mips::fixup_MIPS_PC26_S2: |
187 | // Forcing a signed division because Value can be negative. |
188 | Value = (int64_t) Value / 4; |
189 | // We now check if Value can be encoded as a 26-bit signed immediate. |
190 | if (!isInt<26>(x: Value)) { |
191 | Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC26 fixup" ); |
192 | return 0; |
193 | } |
194 | break; |
195 | case Mips::fixup_MICROMIPS_PC26_S1: |
196 | // Forcing a signed division because Value can be negative. |
197 | Value = (int64_t)Value / 2; |
198 | // We now check if Value can be encoded as a 26-bit signed immediate. |
199 | if (!isInt<26>(x: Value)) { |
200 | Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC26 fixup" ); |
201 | return 0; |
202 | } |
203 | break; |
204 | case Mips::fixup_MICROMIPS_PC21_S1: |
205 | // Forcing a signed division because Value can be negative. |
206 | Value = (int64_t)Value / 2; |
207 | // We now check if Value can be encoded as a 21-bit signed immediate. |
208 | if (!isInt<21>(x: Value)) { |
209 | Ctx.reportError(L: Fixup.getLoc(), Msg: "out of range PC21 fixup" ); |
210 | return 0; |
211 | } |
212 | break; |
213 | } |
214 | |
215 | return Value; |
216 | } |
217 | |
218 | std::unique_ptr<MCObjectTargetWriter> |
219 | MipsAsmBackend::createObjectTargetWriter() const { |
220 | return createMipsELFObjectWriter(TT: TheTriple, IsN32); |
221 | } |
222 | |
223 | // Little-endian fixup data byte ordering: |
224 | // mips32r2: a | b | x | x |
225 | // microMIPS: x | x | a | b |
226 | |
227 | static bool needsMMLEByteOrder(unsigned Kind) { |
228 | return Kind != Mips::fixup_MICROMIPS_PC10_S1 && |
229 | Kind >= Mips::fixup_MICROMIPS_26_S1 && |
230 | Kind < Mips::LastTargetFixupKind; |
231 | } |
232 | |
233 | // Calculate index for microMIPS specific little endian byte order |
234 | static unsigned calculateMMLEIndex(unsigned i) { |
235 | assert(i <= 3 && "Index out of range!" ); |
236 | |
237 | return (1 - i / 2) * 2 + i % 2; |
238 | } |
239 | |
240 | /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided |
241 | /// data fragment, at the offset specified by the fixup and following the |
242 | /// fixup kind as appropriate. |
243 | void MipsAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, |
244 | const MCValue &Target, |
245 | MutableArrayRef<char> Data, uint64_t Value, |
246 | bool IsResolved, |
247 | const MCSubtargetInfo *STI) const { |
248 | MCFixupKind Kind = Fixup.getKind(); |
249 | MCContext &Ctx = Asm.getContext(); |
250 | Value = adjustFixupValue(Fixup, Value, Ctx); |
251 | |
252 | if (!Value) |
253 | return; // Doesn't change encoding. |
254 | |
255 | // Where do we start in the object |
256 | unsigned Offset = Fixup.getOffset(); |
257 | // Number of bytes we need to fixup |
258 | unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; |
259 | // Used to point to big endian bytes |
260 | unsigned FullSize; |
261 | |
262 | switch ((unsigned)Kind) { |
263 | case FK_Data_2: |
264 | case Mips::fixup_Mips_16: |
265 | case Mips::fixup_MICROMIPS_PC10_S1: |
266 | FullSize = 2; |
267 | break; |
268 | case FK_Data_8: |
269 | case Mips::fixup_Mips_64: |
270 | FullSize = 8; |
271 | break; |
272 | case FK_Data_4: |
273 | default: |
274 | FullSize = 4; |
275 | break; |
276 | } |
277 | |
278 | // Grab current value, if any, from bits. |
279 | uint64_t CurVal = 0; |
280 | |
281 | bool microMipsLEByteOrder = needsMMLEByteOrder(Kind: (unsigned) Kind); |
282 | |
283 | for (unsigned i = 0; i != NumBytes; ++i) { |
284 | unsigned Idx = Endian == llvm::endianness::little |
285 | ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i) |
286 | : (FullSize - 1 - i); |
287 | CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); |
288 | } |
289 | |
290 | uint64_t Mask = ((uint64_t)(-1) >> |
291 | (64 - getFixupKindInfo(Kind).TargetSize)); |
292 | CurVal |= Value & Mask; |
293 | |
294 | // Write out the fixed up bytes back to the code/data bits. |
295 | for (unsigned i = 0; i != NumBytes; ++i) { |
296 | unsigned Idx = Endian == llvm::endianness::little |
297 | ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i) |
298 | : (FullSize - 1 - i); |
299 | Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); |
300 | } |
301 | } |
302 | |
303 | std::optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const { |
304 | unsigned Type = llvm::StringSwitch<unsigned>(Name) |
305 | .Case(S: "BFD_RELOC_NONE" , Value: ELF::R_MIPS_NONE) |
306 | .Case(S: "BFD_RELOC_16" , Value: ELF::R_MIPS_16) |
307 | .Case(S: "BFD_RELOC_32" , Value: ELF::R_MIPS_32) |
308 | .Case(S: "BFD_RELOC_64" , Value: ELF::R_MIPS_64) |
309 | .Default(Value: -1u); |
310 | if (Type != -1u) |
311 | return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type); |
312 | |
313 | return StringSwitch<std::optional<MCFixupKind>>(Name) |
314 | .Case(S: "R_MIPS_NONE" , Value: FK_NONE) |
315 | .Case(S: "R_MIPS_32" , Value: FK_Data_4) |
316 | .Case(S: "R_MIPS_CALL_HI16" , Value: (MCFixupKind)Mips::fixup_Mips_CALL_HI16) |
317 | .Case(S: "R_MIPS_CALL_LO16" , Value: (MCFixupKind)Mips::fixup_Mips_CALL_LO16) |
318 | .Case(S: "R_MIPS_CALL16" , Value: (MCFixupKind)Mips::fixup_Mips_CALL16) |
319 | .Case(S: "R_MIPS_GOT16" , Value: (MCFixupKind)Mips::fixup_Mips_GOT) |
320 | .Case(S: "R_MIPS_GOT_PAGE" , Value: (MCFixupKind)Mips::fixup_Mips_GOT_PAGE) |
321 | .Case(S: "R_MIPS_GOT_OFST" , Value: (MCFixupKind)Mips::fixup_Mips_GOT_OFST) |
322 | .Case(S: "R_MIPS_GOT_DISP" , Value: (MCFixupKind)Mips::fixup_Mips_GOT_DISP) |
323 | .Case(S: "R_MIPS_GOT_HI16" , Value: (MCFixupKind)Mips::fixup_Mips_GOT_HI16) |
324 | .Case(S: "R_MIPS_GOT_LO16" , Value: (MCFixupKind)Mips::fixup_Mips_GOT_LO16) |
325 | .Case(S: "R_MIPS_TLS_GOTTPREL" , Value: (MCFixupKind)Mips::fixup_Mips_GOTTPREL) |
326 | .Case(S: "R_MIPS_TLS_DTPREL_HI16" , Value: (MCFixupKind)Mips::fixup_Mips_DTPREL_HI) |
327 | .Case(S: "R_MIPS_TLS_DTPREL_LO16" , Value: (MCFixupKind)Mips::fixup_Mips_DTPREL_LO) |
328 | .Case(S: "R_MIPS_TLS_GD" , Value: (MCFixupKind)Mips::fixup_Mips_TLSGD) |
329 | .Case(S: "R_MIPS_TLS_LDM" , Value: (MCFixupKind)Mips::fixup_Mips_TLSLDM) |
330 | .Case(S: "R_MIPS_TLS_TPREL_HI16" , Value: (MCFixupKind)Mips::fixup_Mips_TPREL_HI) |
331 | .Case(S: "R_MIPS_TLS_TPREL_LO16" , Value: (MCFixupKind)Mips::fixup_Mips_TPREL_LO) |
332 | .Case(S: "R_MICROMIPS_CALL16" , Value: (MCFixupKind)Mips::fixup_MICROMIPS_CALL16) |
333 | .Case(S: "R_MICROMIPS_GOT_DISP" , Value: (MCFixupKind)Mips::fixup_MICROMIPS_GOT_DISP) |
334 | .Case(S: "R_MICROMIPS_GOT_PAGE" , Value: (MCFixupKind)Mips::fixup_MICROMIPS_GOT_PAGE) |
335 | .Case(S: "R_MICROMIPS_GOT_OFST" , Value: (MCFixupKind)Mips::fixup_MICROMIPS_GOT_OFST) |
336 | .Case(S: "R_MICROMIPS_GOT16" , Value: (MCFixupKind)Mips::fixup_MICROMIPS_GOT16) |
337 | .Case(S: "R_MICROMIPS_TLS_GOTTPREL" , |
338 | Value: (MCFixupKind)Mips::fixup_MICROMIPS_GOTTPREL) |
339 | .Case(S: "R_MICROMIPS_TLS_DTPREL_HI16" , |
340 | Value: (MCFixupKind)Mips::fixup_MICROMIPS_TLS_DTPREL_HI16) |
341 | .Case(S: "R_MICROMIPS_TLS_DTPREL_LO16" , |
342 | Value: (MCFixupKind)Mips::fixup_MICROMIPS_TLS_DTPREL_LO16) |
343 | .Case(S: "R_MICROMIPS_TLS_GD" , Value: (MCFixupKind)Mips::fixup_MICROMIPS_TLS_GD) |
344 | .Case(S: "R_MICROMIPS_TLS_LDM" , Value: (MCFixupKind)Mips::fixup_MICROMIPS_TLS_LDM) |
345 | .Case(S: "R_MICROMIPS_TLS_TPREL_HI16" , |
346 | Value: (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_HI16) |
347 | .Case(S: "R_MICROMIPS_TLS_TPREL_LO16" , |
348 | Value: (MCFixupKind)Mips::fixup_MICROMIPS_TLS_TPREL_LO16) |
349 | .Case(S: "R_MIPS_JALR" , Value: (MCFixupKind)Mips::fixup_Mips_JALR) |
350 | .Case(S: "R_MICROMIPS_JALR" , Value: (MCFixupKind)Mips::fixup_MICROMIPS_JALR) |
351 | .Default(Value: MCAsmBackend::getFixupKind(Name)); |
352 | } |
353 | |
354 | const MCFixupKindInfo &MipsAsmBackend:: |
355 | getFixupKindInfo(MCFixupKind Kind) const { |
356 | const static MCFixupKindInfo LittleEndianInfos[] = { |
357 | // This table *must* be in same the order of fixup_* kinds in |
358 | // MipsFixupKinds.h. |
359 | // |
360 | // name offset bits flags |
361 | { .Name: "fixup_Mips_16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
362 | { .Name: "fixup_Mips_32" , .TargetOffset: 0, .TargetSize: 32, .Flags: 0 }, |
363 | { .Name: "fixup_Mips_REL32" , .TargetOffset: 0, .TargetSize: 32, .Flags: 0 }, |
364 | { .Name: "fixup_Mips_26" , .TargetOffset: 0, .TargetSize: 26, .Flags: 0 }, |
365 | { .Name: "fixup_Mips_HI16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
366 | { .Name: "fixup_Mips_LO16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
367 | { .Name: "fixup_Mips_GPREL16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
368 | { .Name: "fixup_Mips_LITERAL" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
369 | { .Name: "fixup_Mips_GOT" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
370 | { .Name: "fixup_Mips_PC16" , .TargetOffset: 0, .TargetSize: 16, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
371 | { .Name: "fixup_Mips_CALL16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
372 | { .Name: "fixup_Mips_GPREL32" , .TargetOffset: 0, .TargetSize: 32, .Flags: 0 }, |
373 | { .Name: "fixup_Mips_SHIFT5" , .TargetOffset: 6, .TargetSize: 5, .Flags: 0 }, |
374 | { .Name: "fixup_Mips_SHIFT6" , .TargetOffset: 6, .TargetSize: 5, .Flags: 0 }, |
375 | { .Name: "fixup_Mips_64" , .TargetOffset: 0, .TargetSize: 64, .Flags: 0 }, |
376 | { .Name: "fixup_Mips_TLSGD" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
377 | { .Name: "fixup_Mips_GOTTPREL" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
378 | { .Name: "fixup_Mips_TPREL_HI" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
379 | { .Name: "fixup_Mips_TPREL_LO" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
380 | { .Name: "fixup_Mips_TLSLDM" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
381 | { .Name: "fixup_Mips_DTPREL_HI" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
382 | { .Name: "fixup_Mips_DTPREL_LO" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
383 | { .Name: "fixup_Mips_Branch_PCRel" , .TargetOffset: 0, .TargetSize: 16, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
384 | { .Name: "fixup_Mips_GPOFF_HI" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
385 | { .Name: "fixup_MICROMIPS_GPOFF_HI" ,.TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
386 | { .Name: "fixup_Mips_GPOFF_LO" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
387 | { .Name: "fixup_MICROMIPS_GPOFF_LO" ,.TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
388 | { .Name: "fixup_Mips_GOT_PAGE" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
389 | { .Name: "fixup_Mips_GOT_OFST" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
390 | { .Name: "fixup_Mips_GOT_DISP" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
391 | { .Name: "fixup_Mips_HIGHER" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
392 | { .Name: "fixup_MICROMIPS_HIGHER" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
393 | { .Name: "fixup_Mips_HIGHEST" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
394 | { .Name: "fixup_MICROMIPS_HIGHEST" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
395 | { .Name: "fixup_Mips_GOT_HI16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
396 | { .Name: "fixup_Mips_GOT_LO16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
397 | { .Name: "fixup_Mips_CALL_HI16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
398 | { .Name: "fixup_Mips_CALL_LO16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
399 | { .Name: "fixup_Mips_PC18_S3" , .TargetOffset: 0, .TargetSize: 18, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
400 | { .Name: "fixup_MIPS_PC19_S2" , .TargetOffset: 0, .TargetSize: 19, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
401 | { .Name: "fixup_MIPS_PC21_S2" , .TargetOffset: 0, .TargetSize: 21, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
402 | { .Name: "fixup_MIPS_PC26_S2" , .TargetOffset: 0, .TargetSize: 26, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
403 | { .Name: "fixup_MIPS_PCHI16" , .TargetOffset: 0, .TargetSize: 16, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
404 | { .Name: "fixup_MIPS_PCLO16" , .TargetOffset: 0, .TargetSize: 16, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
405 | { .Name: "fixup_MICROMIPS_26_S1" , .TargetOffset: 0, .TargetSize: 26, .Flags: 0 }, |
406 | { .Name: "fixup_MICROMIPS_HI16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
407 | { .Name: "fixup_MICROMIPS_LO16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
408 | { .Name: "fixup_MICROMIPS_GOT16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
409 | { .Name: "fixup_MICROMIPS_PC7_S1" , .TargetOffset: 0, .TargetSize: 7, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
410 | { .Name: "fixup_MICROMIPS_PC10_S1" , .TargetOffset: 0, .TargetSize: 10, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
411 | { .Name: "fixup_MICROMIPS_PC16_S1" , .TargetOffset: 0, .TargetSize: 16, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
412 | { .Name: "fixup_MICROMIPS_PC26_S1" , .TargetOffset: 0, .TargetSize: 26, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
413 | { .Name: "fixup_MICROMIPS_PC19_S2" , .TargetOffset: 0, .TargetSize: 19, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
414 | { .Name: "fixup_MICROMIPS_PC18_S3" , .TargetOffset: 0, .TargetSize: 18, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
415 | { .Name: "fixup_MICROMIPS_PC21_S1" , .TargetOffset: 0, .TargetSize: 21, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
416 | { .Name: "fixup_MICROMIPS_CALL16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
417 | { .Name: "fixup_MICROMIPS_GOT_DISP" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
418 | { .Name: "fixup_MICROMIPS_GOT_PAGE" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
419 | { .Name: "fixup_MICROMIPS_GOT_OFST" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
420 | { .Name: "fixup_MICROMIPS_TLS_GD" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
421 | { .Name: "fixup_MICROMIPS_TLS_LDM" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
422 | { .Name: "fixup_MICROMIPS_TLS_DTPREL_HI16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
423 | { .Name: "fixup_MICROMIPS_TLS_DTPREL_LO16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
424 | { .Name: "fixup_MICROMIPS_GOTTPREL" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
425 | { .Name: "fixup_MICROMIPS_TLS_TPREL_HI16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
426 | { .Name: "fixup_MICROMIPS_TLS_TPREL_LO16" , .TargetOffset: 0, .TargetSize: 16, .Flags: 0 }, |
427 | { .Name: "fixup_Mips_SUB" , .TargetOffset: 0, .TargetSize: 64, .Flags: 0 }, |
428 | { .Name: "fixup_MICROMIPS_SUB" , .TargetOffset: 0, .TargetSize: 64, .Flags: 0 }, |
429 | { .Name: "fixup_Mips_JALR" , .TargetOffset: 0, .TargetSize: 32, .Flags: 0 }, |
430 | { .Name: "fixup_MICROMIPS_JALR" , .TargetOffset: 0, .TargetSize: 32, .Flags: 0 } |
431 | }; |
432 | static_assert(std::size(LittleEndianInfos) == Mips::NumTargetFixupKinds, |
433 | "Not all MIPS little endian fixup kinds added!" ); |
434 | |
435 | const static MCFixupKindInfo BigEndianInfos[] = { |
436 | // This table *must* be in same the order of fixup_* kinds in |
437 | // MipsFixupKinds.h. |
438 | // |
439 | // name offset bits flags |
440 | { .Name: "fixup_Mips_16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
441 | { .Name: "fixup_Mips_32" , .TargetOffset: 0, .TargetSize: 32, .Flags: 0 }, |
442 | { .Name: "fixup_Mips_REL32" , .TargetOffset: 0, .TargetSize: 32, .Flags: 0 }, |
443 | { .Name: "fixup_Mips_26" , .TargetOffset: 6, .TargetSize: 26, .Flags: 0 }, |
444 | { .Name: "fixup_Mips_HI16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
445 | { .Name: "fixup_Mips_LO16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
446 | { .Name: "fixup_Mips_GPREL16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
447 | { .Name: "fixup_Mips_LITERAL" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
448 | { .Name: "fixup_Mips_GOT" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
449 | { .Name: "fixup_Mips_PC16" , .TargetOffset: 16, .TargetSize: 16, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
450 | { .Name: "fixup_Mips_CALL16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
451 | { .Name: "fixup_Mips_GPREL32" , .TargetOffset: 0, .TargetSize: 32, .Flags: 0 }, |
452 | { .Name: "fixup_Mips_SHIFT5" , .TargetOffset: 21, .TargetSize: 5, .Flags: 0 }, |
453 | { .Name: "fixup_Mips_SHIFT6" , .TargetOffset: 21, .TargetSize: 5, .Flags: 0 }, |
454 | { .Name: "fixup_Mips_64" , .TargetOffset: 0, .TargetSize: 64, .Flags: 0 }, |
455 | { .Name: "fixup_Mips_TLSGD" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
456 | { .Name: "fixup_Mips_GOTTPREL" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
457 | { .Name: "fixup_Mips_TPREL_HI" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
458 | { .Name: "fixup_Mips_TPREL_LO" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
459 | { .Name: "fixup_Mips_TLSLDM" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
460 | { .Name: "fixup_Mips_DTPREL_HI" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
461 | { .Name: "fixup_Mips_DTPREL_LO" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
462 | { .Name: "fixup_Mips_Branch_PCRel" ,.TargetOffset: 16, .TargetSize: 16, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
463 | { .Name: "fixup_Mips_GPOFF_HI" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
464 | { .Name: "fixup_MICROMIPS_GPOFF_HI" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
465 | { .Name: "fixup_Mips_GPOFF_LO" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
466 | { .Name: "fixup_MICROMIPS_GPOFF_LO" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
467 | { .Name: "fixup_Mips_GOT_PAGE" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
468 | { .Name: "fixup_Mips_GOT_OFST" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
469 | { .Name: "fixup_Mips_GOT_DISP" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
470 | { .Name: "fixup_Mips_HIGHER" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
471 | { .Name: "fixup_MICROMIPS_HIGHER" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
472 | { .Name: "fixup_Mips_HIGHEST" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
473 | { .Name: "fixup_MICROMIPS_HIGHEST" ,.TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
474 | { .Name: "fixup_Mips_GOT_HI16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
475 | { .Name: "fixup_Mips_GOT_LO16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
476 | { .Name: "fixup_Mips_CALL_HI16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
477 | { .Name: "fixup_Mips_CALL_LO16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
478 | { .Name: "fixup_Mips_PC18_S3" , .TargetOffset: 14, .TargetSize: 18, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
479 | { .Name: "fixup_MIPS_PC19_S2" , .TargetOffset: 13, .TargetSize: 19, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
480 | { .Name: "fixup_MIPS_PC21_S2" , .TargetOffset: 11, .TargetSize: 21, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
481 | { .Name: "fixup_MIPS_PC26_S2" , .TargetOffset: 6, .TargetSize: 26, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
482 | { .Name: "fixup_MIPS_PCHI16" , .TargetOffset: 16, .TargetSize: 16, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
483 | { .Name: "fixup_MIPS_PCLO16" , .TargetOffset: 16, .TargetSize: 16, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
484 | { .Name: "fixup_MICROMIPS_26_S1" , .TargetOffset: 6, .TargetSize: 26, .Flags: 0 }, |
485 | { .Name: "fixup_MICROMIPS_HI16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
486 | { .Name: "fixup_MICROMIPS_LO16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
487 | { .Name: "fixup_MICROMIPS_GOT16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
488 | { .Name: "fixup_MICROMIPS_PC7_S1" , .TargetOffset: 9, .TargetSize: 7, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
489 | { .Name: "fixup_MICROMIPS_PC10_S1" , .TargetOffset: 6, .TargetSize: 10, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
490 | { .Name: "fixup_MICROMIPS_PC16_S1" ,.TargetOffset: 16, .TargetSize: 16, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
491 | { .Name: "fixup_MICROMIPS_PC26_S1" , .TargetOffset: 6, .TargetSize: 26, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
492 | { .Name: "fixup_MICROMIPS_PC19_S2" ,.TargetOffset: 13, .TargetSize: 19, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
493 | { .Name: "fixup_MICROMIPS_PC18_S3" ,.TargetOffset: 14, .TargetSize: 18, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
494 | { .Name: "fixup_MICROMIPS_PC21_S1" ,.TargetOffset: 11, .TargetSize: 21, .Flags: MCFixupKindInfo::FKF_IsPCRel }, |
495 | { .Name: "fixup_MICROMIPS_CALL16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
496 | { .Name: "fixup_MICROMIPS_GOT_DISP" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
497 | { .Name: "fixup_MICROMIPS_GOT_PAGE" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
498 | { .Name: "fixup_MICROMIPS_GOT_OFST" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
499 | { .Name: "fixup_MICROMIPS_TLS_GD" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
500 | { .Name: "fixup_MICROMIPS_TLS_LDM" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
501 | { .Name: "fixup_MICROMIPS_TLS_DTPREL_HI16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
502 | { .Name: "fixup_MICROMIPS_TLS_DTPREL_LO16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
503 | { .Name: "fixup_MICROMIPS_GOTTPREL" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
504 | { .Name: "fixup_MICROMIPS_TLS_TPREL_HI16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
505 | { .Name: "fixup_MICROMIPS_TLS_TPREL_LO16" , .TargetOffset: 16, .TargetSize: 16, .Flags: 0 }, |
506 | { .Name: "fixup_Mips_SUB" , .TargetOffset: 0, .TargetSize: 64, .Flags: 0 }, |
507 | { .Name: "fixup_MICROMIPS_SUB" , .TargetOffset: 0, .TargetSize: 64, .Flags: 0 }, |
508 | { .Name: "fixup_Mips_JALR" , .TargetOffset: 0, .TargetSize: 32, .Flags: 0 }, |
509 | { .Name: "fixup_MICROMIPS_JALR" , .TargetOffset: 0, .TargetSize: 32, .Flags: 0 } |
510 | }; |
511 | static_assert(std::size(BigEndianInfos) == Mips::NumTargetFixupKinds, |
512 | "Not all MIPS big endian fixup kinds added!" ); |
513 | |
514 | if (Kind >= FirstLiteralRelocationKind) |
515 | return MCAsmBackend::getFixupKindInfo(Kind: FK_NONE); |
516 | if (Kind < FirstTargetFixupKind) |
517 | return MCAsmBackend::getFixupKindInfo(Kind); |
518 | |
519 | assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && |
520 | "Invalid kind!" ); |
521 | |
522 | if (Endian == llvm::endianness::little) |
523 | return LittleEndianInfos[Kind - FirstTargetFixupKind]; |
524 | return BigEndianInfos[Kind - FirstTargetFixupKind]; |
525 | } |
526 | |
527 | /// WriteNopData - Write an (optimal) nop sequence of Count bytes |
528 | /// to the given output. If the target cannot generate such a sequence, |
529 | /// it should return an error. |
530 | /// |
531 | /// \return - True on success. |
532 | bool MipsAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count, |
533 | const MCSubtargetInfo *STI) const { |
534 | // Check for a less than instruction size number of bytes |
535 | // FIXME: 16 bit instructions are not handled yet here. |
536 | // We shouldn't be using a hard coded number for instruction size. |
537 | |
538 | // If the count is not 4-byte aligned, we must be writing data into the text |
539 | // section (otherwise we have unaligned instructions, and thus have far |
540 | // bigger problems), so just write zeros instead. |
541 | OS.write_zeros(NumZeros: Count); |
542 | return true; |
543 | } |
544 | |
545 | bool MipsAsmBackend::shouldForceRelocation(const MCAssembler &Asm, |
546 | const MCFixup &Fixup, |
547 | const MCValue &Target, |
548 | const MCSubtargetInfo *STI) { |
549 | if (Fixup.getKind() >= FirstLiteralRelocationKind) |
550 | return true; |
551 | const unsigned FixupKind = Fixup.getKind(); |
552 | switch (FixupKind) { |
553 | default: |
554 | return false; |
555 | // All these relocations require special processing |
556 | // at linking time. Delegate this work to a linker. |
557 | case Mips::fixup_Mips_CALL_HI16: |
558 | case Mips::fixup_Mips_CALL_LO16: |
559 | case Mips::fixup_Mips_CALL16: |
560 | case Mips::fixup_Mips_GOT: |
561 | case Mips::fixup_Mips_GOT_PAGE: |
562 | case Mips::fixup_Mips_GOT_OFST: |
563 | case Mips::fixup_Mips_GOT_DISP: |
564 | case Mips::fixup_Mips_GOT_HI16: |
565 | case Mips::fixup_Mips_GOT_LO16: |
566 | case Mips::fixup_Mips_GOTTPREL: |
567 | case Mips::fixup_Mips_DTPREL_HI: |
568 | case Mips::fixup_Mips_DTPREL_LO: |
569 | case Mips::fixup_Mips_TLSGD: |
570 | case Mips::fixup_Mips_TLSLDM: |
571 | case Mips::fixup_Mips_TPREL_HI: |
572 | case Mips::fixup_Mips_TPREL_LO: |
573 | case Mips::fixup_Mips_JALR: |
574 | case Mips::fixup_MICROMIPS_CALL16: |
575 | case Mips::fixup_MICROMIPS_GOT_DISP: |
576 | case Mips::fixup_MICROMIPS_GOT_PAGE: |
577 | case Mips::fixup_MICROMIPS_GOT_OFST: |
578 | case Mips::fixup_MICROMIPS_GOT16: |
579 | case Mips::fixup_MICROMIPS_GOTTPREL: |
580 | case Mips::fixup_MICROMIPS_TLS_DTPREL_HI16: |
581 | case Mips::fixup_MICROMIPS_TLS_DTPREL_LO16: |
582 | case Mips::fixup_MICROMIPS_TLS_GD: |
583 | case Mips::fixup_MICROMIPS_TLS_LDM: |
584 | case Mips::fixup_MICROMIPS_TLS_TPREL_HI16: |
585 | case Mips::fixup_MICROMIPS_TLS_TPREL_LO16: |
586 | case Mips::fixup_MICROMIPS_JALR: |
587 | return true; |
588 | } |
589 | } |
590 | |
591 | bool MipsAsmBackend::isMicroMips(const MCSymbol *Sym) const { |
592 | if (const auto *ElfSym = dyn_cast<const MCSymbolELF>(Val: Sym)) { |
593 | if (ElfSym->getOther() & ELF::STO_MIPS_MICROMIPS) |
594 | return true; |
595 | } |
596 | return false; |
597 | } |
598 | |
599 | MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, |
600 | const MCSubtargetInfo &STI, |
601 | const MCRegisterInfo &MRI, |
602 | const MCTargetOptions &Options) { |
603 | MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT: STI.getTargetTriple(), |
604 | CPU: STI.getCPU(), Options); |
605 | return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), |
606 | ABI.IsN32()); |
607 | } |
608 | |