1 | //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // Top-level implementation for the NVPTX target. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #include "NVPTXTargetMachine.h" |
14 | #include "NVPTX.h" |
15 | #include "NVPTXAliasAnalysis.h" |
16 | #include "NVPTXAllocaHoisting.h" |
17 | #include "NVPTXAtomicLower.h" |
18 | #include "NVPTXCtorDtorLowering.h" |
19 | #include "NVPTXLowerAggrCopies.h" |
20 | #include "NVPTXMachineFunctionInfo.h" |
21 | #include "NVPTXTargetObjectFile.h" |
22 | #include "NVPTXTargetTransformInfo.h" |
23 | #include "TargetInfo/NVPTXTargetInfo.h" |
24 | #include "llvm/ADT/STLExtras.h" |
25 | #include "llvm/Analysis/TargetTransformInfo.h" |
26 | #include "llvm/CodeGen/Passes.h" |
27 | #include "llvm/CodeGen/TargetPassConfig.h" |
28 | #include "llvm/IR/IntrinsicsNVPTX.h" |
29 | #include "llvm/MC/TargetRegistry.h" |
30 | #include "llvm/Pass.h" |
31 | #include "llvm/Passes/PassBuilder.h" |
32 | #include "llvm/Support/CommandLine.h" |
33 | #include "llvm/Target/TargetMachine.h" |
34 | #include "llvm/Target/TargetOptions.h" |
35 | #include "llvm/TargetParser/Triple.h" |
36 | #include "llvm/Transforms/Scalar.h" |
37 | #include "llvm/Transforms/Scalar/GVN.h" |
38 | #include "llvm/Transforms/Vectorize/LoadStoreVectorizer.h" |
39 | #include <cassert> |
40 | #include <optional> |
41 | #include <string> |
42 | |
43 | using namespace llvm; |
44 | |
45 | // LSV is still relatively new; this switch lets us turn it off in case we |
46 | // encounter (or suspect) a bug. |
47 | static cl::opt<bool> |
48 | DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer" , |
49 | cl::desc("Disable load/store vectorizer" ), |
50 | cl::init(Val: false), cl::Hidden); |
51 | |
52 | // TODO: Remove this flag when we are confident with no regressions. |
53 | static cl::opt<bool> DisableRequireStructuredCFG( |
54 | "disable-nvptx-require-structured-cfg" , |
55 | cl::desc("Transitional flag to turn off NVPTX's requirement on preserving " |
56 | "structured CFG. The requirement should be disabled only when " |
57 | "unexpected regressions happen." ), |
58 | cl::init(Val: false), cl::Hidden); |
59 | |
60 | static cl::opt<bool> UseShortPointersOpt( |
61 | "nvptx-short-ptr" , |
62 | cl::desc( |
63 | "Use 32-bit pointers for accessing const/local/shared address spaces." ), |
64 | cl::init(Val: false), cl::Hidden); |
65 | |
66 | namespace llvm { |
67 | |
68 | void initializeGenericToNVVMLegacyPassPass(PassRegistry &); |
69 | void initializeNVPTXAllocaHoistingPass(PassRegistry &); |
70 | void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry &); |
71 | void initializeNVPTXAtomicLowerPass(PassRegistry &); |
72 | void initializeNVPTXCtorDtorLoweringLegacyPass(PassRegistry &); |
73 | void initializeNVPTXLowerAggrCopiesPass(PassRegistry &); |
74 | void initializeNVPTXLowerAllocaPass(PassRegistry &); |
75 | void initializeNVPTXLowerUnreachablePass(PassRegistry &); |
76 | void initializeNVPTXCtorDtorLoweringLegacyPass(PassRegistry &); |
77 | void initializeNVPTXLowerArgsPass(PassRegistry &); |
78 | void initializeNVPTXProxyRegErasurePass(PassRegistry &); |
79 | void initializeNVVMIntrRangePass(PassRegistry &); |
80 | void initializeNVVMReflectPass(PassRegistry &); |
81 | void initializeNVPTXAAWrapperPassPass(PassRegistry &); |
82 | void initializeNVPTXExternalAAWrapperPass(PassRegistry &); |
83 | |
84 | } // end namespace llvm |
85 | |
86 | extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() { |
87 | // Register the target. |
88 | RegisterTargetMachine<NVPTXTargetMachine32> X(getTheNVPTXTarget32()); |
89 | RegisterTargetMachine<NVPTXTargetMachine64> Y(getTheNVPTXTarget64()); |
90 | |
91 | PassRegistry &PR = *PassRegistry::getPassRegistry(); |
92 | // FIXME: This pass is really intended to be invoked during IR optimization, |
93 | // but it's very NVPTX-specific. |
94 | initializeNVVMReflectPass(PR); |
95 | initializeNVVMIntrRangePass(PR); |
96 | initializeGenericToNVVMLegacyPassPass(PR); |
97 | initializeNVPTXAllocaHoistingPass(PR); |
98 | initializeNVPTXAssignValidGlobalNamesPass(PR); |
99 | initializeNVPTXAtomicLowerPass(PR); |
100 | initializeNVPTXLowerArgsPass(PR); |
101 | initializeNVPTXLowerAllocaPass(PR); |
102 | initializeNVPTXLowerUnreachablePass(PR); |
103 | initializeNVPTXCtorDtorLoweringLegacyPass(PR); |
104 | initializeNVPTXLowerAggrCopiesPass(PR); |
105 | initializeNVPTXProxyRegErasurePass(PR); |
106 | initializeNVPTXDAGToDAGISelPass(PR); |
107 | initializeNVPTXAAWrapperPassPass(PR); |
108 | initializeNVPTXExternalAAWrapperPass(PR); |
109 | } |
110 | |
111 | static std::string computeDataLayout(bool is64Bit, bool UseShortPointers) { |
112 | std::string Ret = "e" ; |
113 | |
114 | if (!is64Bit) |
115 | Ret += "-p:32:32" ; |
116 | else if (UseShortPointers) |
117 | Ret += "-p3:32:32-p4:32:32-p5:32:32" ; |
118 | |
119 | Ret += "-i64:64-i128:128-v16:16-v32:32-n16:32:64" ; |
120 | |
121 | return Ret; |
122 | } |
123 | |
124 | NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT, |
125 | StringRef CPU, StringRef FS, |
126 | const TargetOptions &Options, |
127 | std::optional<Reloc::Model> RM, |
128 | std::optional<CodeModel::Model> CM, |
129 | CodeGenOptLevel OL, bool is64bit) |
130 | // The pic relocation model is used regardless of what the client has |
131 | // specified, as it is the only relocation model currently supported. |
132 | : LLVMTargetMachine(T, computeDataLayout(is64Bit: is64bit, UseShortPointers: UseShortPointersOpt), TT, |
133 | CPU, FS, Options, Reloc::PIC_, |
134 | getEffectiveCodeModel(CM, Default: CodeModel::Small), OL), |
135 | is64bit(is64bit), TLOF(std::make_unique<NVPTXTargetObjectFile>()), |
136 | Subtarget(TT, std::string(CPU), std::string(FS), *this), |
137 | StrPool(StrAlloc) { |
138 | if (TT.getOS() == Triple::NVCL) |
139 | drvInterface = NVPTX::NVCL; |
140 | else |
141 | drvInterface = NVPTX::CUDA; |
142 | if (!DisableRequireStructuredCFG) |
143 | setRequiresStructuredCFG(true); |
144 | initAsmInfo(); |
145 | } |
146 | |
147 | NVPTXTargetMachine::~NVPTXTargetMachine() = default; |
148 | |
149 | void NVPTXTargetMachine32::anchor() {} |
150 | |
151 | NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT, |
152 | StringRef CPU, StringRef FS, |
153 | const TargetOptions &Options, |
154 | std::optional<Reloc::Model> RM, |
155 | std::optional<CodeModel::Model> CM, |
156 | CodeGenOptLevel OL, bool JIT) |
157 | : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} |
158 | |
159 | void NVPTXTargetMachine64::anchor() {} |
160 | |
161 | NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT, |
162 | StringRef CPU, StringRef FS, |
163 | const TargetOptions &Options, |
164 | std::optional<Reloc::Model> RM, |
165 | std::optional<CodeModel::Model> CM, |
166 | CodeGenOptLevel OL, bool JIT) |
167 | : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} |
168 | |
169 | namespace { |
170 | |
171 | class NVPTXPassConfig : public TargetPassConfig { |
172 | public: |
173 | NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM) |
174 | : TargetPassConfig(TM, PM) {} |
175 | |
176 | NVPTXTargetMachine &getNVPTXTargetMachine() const { |
177 | return getTM<NVPTXTargetMachine>(); |
178 | } |
179 | |
180 | void addIRPasses() override; |
181 | bool addInstSelector() override; |
182 | void addPreRegAlloc() override; |
183 | void addPostRegAlloc() override; |
184 | void addMachineSSAOptimization() override; |
185 | |
186 | FunctionPass *createTargetRegisterAllocator(bool) override; |
187 | void addFastRegAlloc() override; |
188 | void addOptimizedRegAlloc() override; |
189 | |
190 | bool addRegAssignAndRewriteFast() override { |
191 | llvm_unreachable("should not be used" ); |
192 | } |
193 | |
194 | bool addRegAssignAndRewriteOptimized() override { |
195 | llvm_unreachable("should not be used" ); |
196 | } |
197 | |
198 | private: |
199 | // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This |
200 | // function is only called in opt mode. |
201 | void addEarlyCSEOrGVNPass(); |
202 | |
203 | // Add passes that propagate special memory spaces. |
204 | void addAddressSpaceInferencePasses(); |
205 | |
206 | // Add passes that perform straight-line scalar optimizations. |
207 | void addStraightLineScalarOptimizationPasses(); |
208 | }; |
209 | |
210 | } // end anonymous namespace |
211 | |
212 | TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) { |
213 | return new NVPTXPassConfig(*this, PM); |
214 | } |
215 | |
216 | MachineFunctionInfo *NVPTXTargetMachine::createMachineFunctionInfo( |
217 | BumpPtrAllocator &Allocator, const Function &F, |
218 | const TargetSubtargetInfo *STI) const { |
219 | return NVPTXMachineFunctionInfo::create<NVPTXMachineFunctionInfo>(Allocator, |
220 | F, STI); |
221 | } |
222 | |
223 | void NVPTXTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) { |
224 | AAM.registerFunctionAnalysis<NVPTXAA>(); |
225 | } |
226 | |
227 | void NVPTXTargetMachine::registerPassBuilderCallbacks( |
228 | PassBuilder &PB, bool PopulateClassToPassNames) { |
229 | #define GET_PASS_REGISTRY "NVPTXPassRegistry.def" |
230 | #include "llvm/Passes/TargetPassRegistry.inc" |
231 | |
232 | PB.registerPipelineStartEPCallback( |
233 | C: [this](ModulePassManager &PM, OptimizationLevel Level) { |
234 | FunctionPassManager FPM; |
235 | FPM.addPass(NVVMReflectPass(Subtarget.getSmVersion())); |
236 | // FIXME: NVVMIntrRangePass is causing numerical discrepancies, |
237 | // investigate and re-enable. |
238 | // FPM.addPass(NVVMIntrRangePass(Subtarget.getSmVersion())); |
239 | PM.addPass(Pass: createModuleToFunctionPassAdaptor(Pass: std::move(FPM))); |
240 | }); |
241 | } |
242 | |
243 | TargetTransformInfo |
244 | NVPTXTargetMachine::getTargetTransformInfo(const Function &F) const { |
245 | return TargetTransformInfo(NVPTXTTIImpl(this, F)); |
246 | } |
247 | |
248 | std::pair<const Value *, unsigned> |
249 | NVPTXTargetMachine::getPredicatedAddrSpace(const Value *V) const { |
250 | if (auto *II = dyn_cast<IntrinsicInst>(Val: V)) { |
251 | switch (II->getIntrinsicID()) { |
252 | case Intrinsic::nvvm_isspacep_const: |
253 | return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_CONST); |
254 | case Intrinsic::nvvm_isspacep_global: |
255 | return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_GLOBAL); |
256 | case Intrinsic::nvvm_isspacep_local: |
257 | return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_LOCAL); |
258 | case Intrinsic::nvvm_isspacep_shared: |
259 | case Intrinsic::nvvm_isspacep_shared_cluster: |
260 | return std::make_pair(x: II->getArgOperand(i: 0), y: llvm::ADDRESS_SPACE_SHARED); |
261 | default: |
262 | break; |
263 | } |
264 | } |
265 | return std::make_pair(x: nullptr, y: -1); |
266 | } |
267 | |
268 | void NVPTXPassConfig::addEarlyCSEOrGVNPass() { |
269 | if (getOptLevel() == CodeGenOptLevel::Aggressive) |
270 | addPass(P: createGVNPass()); |
271 | else |
272 | addPass(P: createEarlyCSEPass()); |
273 | } |
274 | |
275 | void NVPTXPassConfig::addAddressSpaceInferencePasses() { |
276 | // NVPTXLowerArgs emits alloca for byval parameters which can often |
277 | // be eliminated by SROA. |
278 | addPass(P: createSROAPass()); |
279 | addPass(P: createNVPTXLowerAllocaPass()); |
280 | addPass(P: createInferAddressSpacesPass()); |
281 | addPass(P: createNVPTXAtomicLowerPass()); |
282 | } |
283 | |
284 | void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() { |
285 | addPass(P: createSeparateConstOffsetFromGEPPass()); |
286 | addPass(P: createSpeculativeExecutionPass()); |
287 | // ReassociateGEPs exposes more opportunites for SLSR. See |
288 | // the example in reassociate-geps-and-slsr.ll. |
289 | addPass(P: createStraightLineStrengthReducePass()); |
290 | // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or |
291 | // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE |
292 | // for some of our benchmarks. |
293 | addEarlyCSEOrGVNPass(); |
294 | // Run NaryReassociate after EarlyCSE/GVN to be more effective. |
295 | addPass(P: createNaryReassociatePass()); |
296 | // NaryReassociate on GEPs creates redundant common expressions, so run |
297 | // EarlyCSE after it. |
298 | addPass(P: createEarlyCSEPass()); |
299 | } |
300 | |
301 | void NVPTXPassConfig::addIRPasses() { |
302 | // The following passes are known to not play well with virtual regs hanging |
303 | // around after register allocation (which in our case, is *all* registers). |
304 | // We explicitly disable them here. We do, however, need some functionality |
305 | // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the |
306 | // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp). |
307 | disablePass(PassID: &PrologEpilogCodeInserterID); |
308 | disablePass(PassID: &MachineLateInstrsCleanupID); |
309 | disablePass(PassID: &MachineCopyPropagationID); |
310 | disablePass(PassID: &TailDuplicateID); |
311 | disablePass(PassID: &StackMapLivenessID); |
312 | disablePass(PassID: &LiveDebugValuesID); |
313 | disablePass(PassID: &PostRAMachineSinkingID); |
314 | disablePass(PassID: &PostRASchedulerID); |
315 | disablePass(PassID: &FuncletLayoutID); |
316 | disablePass(PassID: &PatchableFunctionID); |
317 | disablePass(PassID: &ShrinkWrapID); |
318 | |
319 | addPass(P: createNVPTXAAWrapperPass()); |
320 | addPass(P: createExternalAAWrapperPass(Callback: [](Pass &P, Function &, AAResults &AAR) { |
321 | if (auto *WrapperPass = P.getAnalysisIfAvailable<NVPTXAAWrapperPass>()) |
322 | AAR.addAAResult(AAResult&: WrapperPass->getResult()); |
323 | })); |
324 | |
325 | // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running |
326 | // it here does nothing. But since we need it for correctness when lowering |
327 | // to NVPTX, run it here too, in case whoever built our pass pipeline didn't |
328 | // call addEarlyAsPossiblePasses. |
329 | const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl(); |
330 | addPass(P: createNVVMReflectPass(SmVersion: ST.getSmVersion())); |
331 | |
332 | if (getOptLevel() != CodeGenOptLevel::None) |
333 | addPass(P: createNVPTXImageOptimizerPass()); |
334 | addPass(P: createNVPTXAssignValidGlobalNamesPass()); |
335 | addPass(P: createGenericToNVVMLegacyPass()); |
336 | |
337 | // NVPTXLowerArgs is required for correctness and should be run right |
338 | // before the address space inference passes. |
339 | addPass(P: createNVPTXLowerArgsPass()); |
340 | if (getOptLevel() != CodeGenOptLevel::None) { |
341 | addAddressSpaceInferencePasses(); |
342 | addStraightLineScalarOptimizationPasses(); |
343 | } |
344 | |
345 | addPass(P: createAtomicExpandLegacyPass()); |
346 | addPass(P: createNVPTXCtorDtorLoweringLegacyPass()); |
347 | |
348 | // === LSR and other generic IR passes === |
349 | TargetPassConfig::addIRPasses(); |
350 | // EarlyCSE is not always strong enough to clean up what LSR produces. For |
351 | // example, GVN can combine |
352 | // |
353 | // %0 = add %a, %b |
354 | // %1 = add %b, %a |
355 | // |
356 | // and |
357 | // |
358 | // %0 = shl nsw %a, 2 |
359 | // %1 = shl %a, 2 |
360 | // |
361 | // but EarlyCSE can do neither of them. |
362 | if (getOptLevel() != CodeGenOptLevel::None) { |
363 | addEarlyCSEOrGVNPass(); |
364 | if (!DisableLoadStoreVectorizer) |
365 | addPass(P: createLoadStoreVectorizerPass()); |
366 | addPass(P: createSROAPass()); |
367 | } |
368 | |
369 | const auto &Options = getNVPTXTargetMachine().Options; |
370 | addPass(P: createNVPTXLowerUnreachablePass(TrapUnreachable: Options.TrapUnreachable, |
371 | NoTrapAfterNoreturn: Options.NoTrapAfterNoreturn)); |
372 | } |
373 | |
374 | bool NVPTXPassConfig::addInstSelector() { |
375 | const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl(); |
376 | |
377 | addPass(P: createLowerAggrCopies()); |
378 | addPass(P: createAllocaHoisting()); |
379 | addPass(P: createNVPTXISelDag(TM&: getNVPTXTargetMachine(), OptLevel: getOptLevel())); |
380 | |
381 | if (!ST.hasImageHandles()) |
382 | addPass(P: createNVPTXReplaceImageHandlesPass()); |
383 | |
384 | return false; |
385 | } |
386 | |
387 | void NVPTXPassConfig::addPreRegAlloc() { |
388 | // Remove Proxy Register pseudo instructions used to keep `callseq_end` alive. |
389 | addPass(P: createNVPTXProxyRegErasurePass()); |
390 | } |
391 | |
392 | void NVPTXPassConfig::addPostRegAlloc() { |
393 | addPass(P: createNVPTXPrologEpilogPass()); |
394 | if (getOptLevel() != CodeGenOptLevel::None) { |
395 | // NVPTXPrologEpilogPass calculates frame object offset and replace frame |
396 | // index with VRFrame register. NVPTXPeephole need to be run after that and |
397 | // will replace VRFrame with VRFrameLocal when possible. |
398 | addPass(P: createNVPTXPeephole()); |
399 | } |
400 | } |
401 | |
402 | FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) { |
403 | return nullptr; // No reg alloc |
404 | } |
405 | |
406 | void NVPTXPassConfig::addFastRegAlloc() { |
407 | addPass(PassID: &PHIEliminationID); |
408 | addPass(PassID: &TwoAddressInstructionPassID); |
409 | } |
410 | |
411 | void NVPTXPassConfig::addOptimizedRegAlloc() { |
412 | addPass(PassID: &ProcessImplicitDefsID); |
413 | addPass(PassID: &LiveVariablesID); |
414 | addPass(PassID: &MachineLoopInfoID); |
415 | addPass(PassID: &PHIEliminationID); |
416 | |
417 | addPass(PassID: &TwoAddressInstructionPassID); |
418 | addPass(PassID: &RegisterCoalescerID); |
419 | |
420 | // PreRA instruction scheduling. |
421 | if (addPass(PassID: &MachineSchedulerID)) |
422 | printAndVerify(Banner: "After Machine Scheduling" ); |
423 | |
424 | addPass(PassID: &StackSlotColoringID); |
425 | |
426 | // FIXME: Needs physical registers |
427 | // addPass(&MachineLICMID); |
428 | |
429 | printAndVerify(Banner: "After StackSlotColoring" ); |
430 | } |
431 | |
432 | void NVPTXPassConfig::addMachineSSAOptimization() { |
433 | // Pre-ra tail duplication. |
434 | if (addPass(PassID: &EarlyTailDuplicateID)) |
435 | printAndVerify(Banner: "After Pre-RegAlloc TailDuplicate" ); |
436 | |
437 | // Optimize PHIs before DCE: removing dead PHI cycles may make more |
438 | // instructions dead. |
439 | addPass(PassID: &OptimizePHIsID); |
440 | |
441 | // This pass merges large allocas. StackSlotColoring is a different pass |
442 | // which merges spill slots. |
443 | addPass(PassID: &StackColoringID); |
444 | |
445 | // If the target requests it, assign local variables to stack slots relative |
446 | // to one another and simplify frame index references where possible. |
447 | addPass(PassID: &LocalStackSlotAllocationID); |
448 | |
449 | // With optimization, dead code should already be eliminated. However |
450 | // there is one known exception: lowered code for arguments that are only |
451 | // used by tail calls, where the tail calls reuse the incoming stack |
452 | // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll). |
453 | addPass(PassID: &DeadMachineInstructionElimID); |
454 | printAndVerify(Banner: "After codegen DCE pass" ); |
455 | |
456 | // Allow targets to insert passes that improve instruction level parallelism, |
457 | // like if-conversion. Such passes will typically need dominator trees and |
458 | // loop info, just like LICM and CSE below. |
459 | if (addILPOpts()) |
460 | printAndVerify(Banner: "After ILP optimizations" ); |
461 | |
462 | addPass(PassID: &EarlyMachineLICMID); |
463 | addPass(PassID: &MachineCSEID); |
464 | |
465 | addPass(PassID: &MachineSinkingID); |
466 | printAndVerify(Banner: "After Machine LICM, CSE and Sinking passes" ); |
467 | |
468 | addPass(PassID: &PeepholeOptimizerID); |
469 | printAndVerify(Banner: "After codegen peephole optimization pass" ); |
470 | } |
471 | |