1//===-- PPCMCTargetDesc.cpp - PowerPC Target Descriptions -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides PowerPC specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/PPCMCTargetDesc.h"
14#include "MCTargetDesc/PPCInstPrinter.h"
15#include "MCTargetDesc/PPCMCAsmInfo.h"
16#include "PPCELFStreamer.h"
17#include "PPCTargetStreamer.h"
18#include "PPCXCOFFStreamer.h"
19#include "TargetInfo/PowerPCTargetInfo.h"
20#include "llvm/ADT/SmallPtrSet.h"
21#include "llvm/ADT/StringRef.h"
22#include "llvm/BinaryFormat/ELF.h"
23#include "llvm/MC/MCAsmBackend.h"
24#include "llvm/MC/MCAssembler.h"
25#include "llvm/MC/MCCodeEmitter.h"
26#include "llvm/MC/MCContext.h"
27#include "llvm/MC/MCDwarf.h"
28#include "llvm/MC/MCELFStreamer.h"
29#include "llvm/MC/MCExpr.h"
30#include "llvm/MC/MCInstrAnalysis.h"
31#include "llvm/MC/MCInstrInfo.h"
32#include "llvm/MC/MCObjectWriter.h"
33#include "llvm/MC/MCRegisterInfo.h"
34#include "llvm/MC/MCSectionXCOFF.h"
35#include "llvm/MC/MCStreamer.h"
36#include "llvm/MC/MCSubtargetInfo.h"
37#include "llvm/MC/MCSymbol.h"
38#include "llvm/MC/MCSymbolELF.h"
39#include "llvm/MC/MCSymbolXCOFF.h"
40#include "llvm/MC/TargetRegistry.h"
41#include "llvm/Support/Casting.h"
42#include "llvm/Support/CodeGen.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/FormattedStream.h"
45#include "llvm/Support/raw_ostream.h"
46#include "llvm/TargetParser/Triple.h"
47
48using namespace llvm;
49
50#define GET_INSTRINFO_MC_DESC
51#define ENABLE_INSTR_PREDICATE_VERIFIER
52#include "PPCGenInstrInfo.inc"
53
54#define GET_SUBTARGETINFO_MC_DESC
55#include "PPCGenSubtargetInfo.inc"
56
57#define GET_REGINFO_MC_DESC
58#include "PPCGenRegisterInfo.inc"
59
60/// stripRegisterPrefix - This method strips the character prefix from a
61/// register name so that only the number is left. Used by for linux asm.
62const char *PPC::stripRegisterPrefix(const char *RegName) {
63 switch (RegName[0]) {
64 case 'a':
65 if (RegName[1] == 'c' && RegName[2] == 'c')
66 return RegName + 3;
67 break;
68 case 'f':
69 if (RegName[1] == 'p')
70 return RegName + 2;
71 [[fallthrough]];
72 case 'r':
73 case 'v':
74 if (RegName[1] == 's') {
75 if (RegName[2] == 'p')
76 return RegName + 3;
77 return RegName + 2;
78 }
79 return RegName + 1;
80 case 'c':
81 if (RegName[1] == 'r')
82 return RegName + 2;
83 break;
84 case 'w':
85 // For wacc and wacc_hi
86 if (RegName[1] == 'a' && RegName[2] == 'c' && RegName[3] == 'c') {
87 if (RegName[4] == '_')
88 return RegName + 7;
89 else
90 return RegName + 4;
91 }
92 break;
93 case 'd':
94 // For dmr, dmrp, dmrrow, dmrrowp
95 if (RegName[1] == 'm' && RegName[2] == 'r') {
96 if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w' &&
97 RegName[6] == 'p')
98 return RegName + 7;
99 else if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w')
100 return RegName + 6;
101 else if (RegName[3] == 'p')
102 return RegName + 4;
103 else
104 return RegName + 3;
105 }
106 break;
107 }
108
109 return RegName;
110}
111
112/// getRegNumForOperand - some operands use different numbering schemes
113/// for the same registers. For example, a VSX instruction may have any of
114/// vs0-vs63 allocated whereas an Altivec instruction could only have
115/// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual
116/// register number needed for the opcode/operand number combination.
117/// The operand number argument will be useful when we need to extend this
118/// to instructions that use both Altivec and VSX numbering (for different
119/// operands).
120unsigned PPC::getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg,
121 unsigned OpNo) {
122 int16_t regClass = Desc.operands()[OpNo].RegClass;
123 switch (regClass) {
124 // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31,
125 // VSX32-VSX63 during encoding/disassembling
126 case PPC::VSSRCRegClassID:
127 case PPC::VSFRCRegClassID:
128 if (PPC::isVFRegister(Reg))
129 return PPC::VSX32 + (Reg - PPC::VF0);
130 break;
131 // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
132 // VSX32-VSX63 during encoding/disassembling
133 case PPC::VSRCRegClassID:
134 if (PPC::isVRRegister(Reg))
135 return PPC::VSX32 + (Reg - PPC::V0);
136 break;
137 // Other RegClass doesn't need mapping
138 default:
139 break;
140 }
141 return Reg;
142}
143
144PPCTargetStreamer::PPCTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
145
146// Pin the vtable to this file.
147PPCTargetStreamer::~PPCTargetStreamer() = default;
148
149static MCInstrInfo *createPPCMCInstrInfo() {
150 MCInstrInfo *X = new MCInstrInfo();
151 InitPPCMCInstrInfo(X);
152 return X;
153}
154
155static MCRegisterInfo *createPPCMCRegisterInfo(const Triple &TT) {
156 bool isPPC64 =
157 (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le);
158 unsigned Flavour = isPPC64 ? 0 : 1;
159 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
160
161 MCRegisterInfo *X = new MCRegisterInfo();
162 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
163 return X;
164}
165
166static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT,
167 StringRef CPU, StringRef FS) {
168 // Set some default feature to MC layer.
169 std::string FullFS = std::string(FS);
170
171 if (TT.isOSAIX()) {
172 if (!FullFS.empty())
173 FullFS = "+aix," + FullFS;
174 else
175 FullFS = "+aix";
176 }
177
178 return createPPCMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FullFS);
179}
180
181static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,
182 const Triple &TheTriple,
183 const MCTargetOptions &Options) {
184 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
185 TheTriple.getArch() == Triple::ppc64le);
186
187 MCAsmInfo *MAI;
188 if (TheTriple.isOSBinFormatXCOFF())
189 MAI = new PPCXCOFFMCAsmInfo(isPPC64, TheTriple);
190 else
191 MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple);
192
193 // Initial state of the frame pointer is R1.
194 unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
195 MCCFIInstruction Inst =
196 MCCFIInstruction::cfiDefCfa(L: nullptr, Register: MRI.getDwarfRegNum(RegNum: Reg, isEH: true), Offset: 0);
197 MAI->addInitialFrameState(Inst);
198
199 return MAI;
200}
201
202static MCStreamer *
203createPPCELFStreamer(const Triple &T, MCContext &Context,
204 std::unique_ptr<MCAsmBackend> &&MAB,
205 std::unique_ptr<MCObjectWriter> &&OW,
206 std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll) {
207 return createPPCELFStreamer(Context, MAB: std::move(MAB), OW: std::move(OW),
208 Emitter: std::move(Emitter));
209}
210
211static MCStreamer *createPPCXCOFFStreamer(
212 const Triple &T, MCContext &Context, std::unique_ptr<MCAsmBackend> &&MAB,
213 std::unique_ptr<MCObjectWriter> &&OW,
214 std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll) {
215 return createPPCXCOFFStreamer(Context, MAB: std::move(MAB), OW: std::move(OW),
216 Emitter: std::move(Emitter));
217}
218
219namespace {
220
221class PPCTargetAsmStreamer : public PPCTargetStreamer {
222 formatted_raw_ostream &OS;
223
224public:
225 PPCTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
226 : PPCTargetStreamer(S), OS(OS) {}
227
228 void emitTCEntry(const MCSymbol &S,
229 MCSymbolRefExpr::VariantKind Kind) override {
230 if (const MCSymbolXCOFF *XSym = dyn_cast<MCSymbolXCOFF>(Val: &S)) {
231 MCSymbolXCOFF *TCSym =
232 cast<MCSectionXCOFF>(Val: Streamer.getCurrentSectionOnly())
233 ->getQualNameSymbol();
234 // On AIX, we have TLS variable offsets (symbol@({gd|ie|le|ld}) depending
235 // on the TLS access method (or model). For the general-dynamic access
236 // method, we also have region handle (symbol@m) for each variable. For
237 // local-dynamic, there is a module handle (_$TLSML[TC]@ml) for all
238 // variables. Finally for local-exec and initial-exec, we have a thread
239 // pointer, in r13 for 64-bit mode and returned by .__get_tpointer for
240 // 32-bit mode.
241 if (Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGD ||
242 Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSGDM ||
243 Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSIE ||
244 Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE ||
245 Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLD ||
246 Kind == MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSML)
247 OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << "@"
248 << MCSymbolRefExpr::getVariantKindName(Kind) << '\n';
249 else
250 OS << "\t.tc " << TCSym->getName() << "," << XSym->getName() << '\n';
251
252 if (TCSym->hasRename())
253 Streamer.emitXCOFFRenameDirective(Name: TCSym, Rename: TCSym->getSymbolTableName());
254 return;
255 }
256
257 OS << "\t.tc " << S.getName() << "[TC]," << S.getName() << '\n';
258 }
259
260 void emitMachine(StringRef CPU) override {
261 OS << "\t.machine " << CPU << '\n';
262 }
263
264 void emitAbiVersion(int AbiVersion) override {
265 OS << "\t.abiversion " << AbiVersion << '\n';
266 }
267
268 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
269 const MCAsmInfo *MAI = Streamer.getContext().getAsmInfo();
270
271 OS << "\t.localentry\t";
272 S->print(OS, MAI);
273 OS << ", ";
274 LocalOffset->print(OS, MAI);
275 OS << '\n';
276 }
277};
278
279class PPCTargetELFStreamer : public PPCTargetStreamer {
280public:
281 PPCTargetELFStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
282
283 MCELFStreamer &getStreamer() {
284 return static_cast<MCELFStreamer &>(Streamer);
285 }
286
287 void emitTCEntry(const MCSymbol &S,
288 MCSymbolRefExpr::VariantKind Kind) override {
289 // Creates a R_PPC64_TOC relocation
290 Streamer.emitValueToAlignment(Alignment: Align(8));
291 Streamer.emitSymbolValue(Sym: &S, Size: 8);
292 }
293
294 void emitMachine(StringRef CPU) override {
295 // FIXME: Is there anything to do in here or does this directive only
296 // limit the parser?
297 }
298
299 void emitAbiVersion(int AbiVersion) override {
300 MCAssembler &MCA = getStreamer().getAssembler();
301 unsigned Flags = MCA.getELFHeaderEFlags();
302 Flags &= ~ELF::EF_PPC64_ABI;
303 Flags |= (AbiVersion & ELF::EF_PPC64_ABI);
304 MCA.setELFHeaderEFlags(Flags);
305 }
306
307 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
308 MCAssembler &MCA = getStreamer().getAssembler();
309
310 // encodePPC64LocalEntryOffset will report an error if it cannot
311 // encode LocalOffset.
312 unsigned Encoded = encodePPC64LocalEntryOffset(LocalOffset);
313
314 unsigned Other = S->getOther();
315 Other &= ~ELF::STO_PPC64_LOCAL_MASK;
316 Other |= Encoded;
317 S->setOther(Other);
318
319 // For GAS compatibility, unless we already saw a .abiversion directive,
320 // set e_flags to indicate ELFv2 ABI.
321 unsigned Flags = MCA.getELFHeaderEFlags();
322 if ((Flags & ELF::EF_PPC64_ABI) == 0)
323 MCA.setELFHeaderEFlags(Flags | 2);
324 }
325
326 void emitAssignment(MCSymbol *S, const MCExpr *Value) override {
327 auto *Symbol = cast<MCSymbolELF>(Val: S);
328
329 // When encoding an assignment to set symbol A to symbol B, also copy
330 // the st_other bits encoding the local entry point offset.
331 if (copyLocalEntry(D: Symbol, S: Value))
332 UpdateOther.insert(Ptr: Symbol);
333 else
334 UpdateOther.erase(Ptr: Symbol);
335 }
336
337 void finish() override {
338 for (auto *Sym : UpdateOther)
339 if (Sym->isVariable())
340 copyLocalEntry(D: Sym, S: Sym->getVariableValue());
341
342 // Clear the set of symbols that needs to be updated so the streamer can
343 // be reused without issues.
344 UpdateOther.clear();
345 }
346
347private:
348 SmallPtrSet<MCSymbolELF *, 32> UpdateOther;
349
350 bool copyLocalEntry(MCSymbolELF *D, const MCExpr *S) {
351 auto *Ref = dyn_cast<const MCSymbolRefExpr>(Val: S);
352 if (!Ref)
353 return false;
354 const auto &RhsSym = cast<MCSymbolELF>(Val: Ref->getSymbol());
355 unsigned Other = D->getOther();
356 Other &= ~ELF::STO_PPC64_LOCAL_MASK;
357 Other |= RhsSym.getOther() & ELF::STO_PPC64_LOCAL_MASK;
358 D->setOther(Other);
359 return true;
360 }
361
362 unsigned encodePPC64LocalEntryOffset(const MCExpr *LocalOffset) {
363 MCAssembler &MCA = getStreamer().getAssembler();
364 int64_t Offset;
365 if (!LocalOffset->evaluateAsAbsolute(Res&: Offset, Asm: MCA))
366 MCA.getContext().reportError(L: LocalOffset->getLoc(),
367 Msg: ".localentry expression must be absolute");
368
369 switch (Offset) {
370 default:
371 MCA.getContext().reportError(
372 L: LocalOffset->getLoc(), Msg: ".localentry expression must be a power of 2");
373 return 0;
374 case 0:
375 return 0;
376 case 1:
377 return 1 << ELF::STO_PPC64_LOCAL_BIT;
378 case 4:
379 case 8:
380 case 16:
381 case 32:
382 case 64:
383 return Log2_32(Value: Offset) << ELF::STO_PPC64_LOCAL_BIT;
384 }
385 }
386};
387
388class PPCTargetMachOStreamer : public PPCTargetStreamer {
389public:
390 PPCTargetMachOStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
391
392 void emitTCEntry(const MCSymbol &S,
393 MCSymbolRefExpr::VariantKind Kind) override {
394 llvm_unreachable("Unknown pseudo-op: .tc");
395 }
396
397 void emitMachine(StringRef CPU) override {
398 // FIXME: We should update the CPUType, CPUSubType in the Object file if
399 // the new values are different from the defaults.
400 }
401
402 void emitAbiVersion(int AbiVersion) override {
403 llvm_unreachable("Unknown pseudo-op: .abiversion");
404 }
405
406 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
407 llvm_unreachable("Unknown pseudo-op: .localentry");
408 }
409};
410
411class PPCTargetXCOFFStreamer : public PPCTargetStreamer {
412public:
413 PPCTargetXCOFFStreamer(MCStreamer &S) : PPCTargetStreamer(S) {}
414
415 void emitTCEntry(const MCSymbol &S,
416 MCSymbolRefExpr::VariantKind Kind) override {
417 const MCAsmInfo *MAI = Streamer.getContext().getAsmInfo();
418 const unsigned PointerSize = MAI->getCodePointerSize();
419 Streamer.emitValueToAlignment(Alignment: Align(PointerSize));
420 Streamer.emitValue(Value: MCSymbolRefExpr::create(Symbol: &S, Kind, Ctx&: Streamer.getContext()),
421 Size: PointerSize);
422 }
423
424 void emitMachine(StringRef CPU) override {
425 llvm_unreachable("Machine pseudo-ops are invalid for XCOFF.");
426 }
427
428 void emitAbiVersion(int AbiVersion) override {
429 llvm_unreachable("ABI-version pseudo-ops are invalid for XCOFF.");
430 }
431
432 void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) override {
433 llvm_unreachable("Local-entry pseudo-ops are invalid for XCOFF.");
434 }
435};
436
437} // end anonymous namespace
438
439static MCTargetStreamer *createAsmTargetStreamer(MCStreamer &S,
440 formatted_raw_ostream &OS,
441 MCInstPrinter *InstPrint,
442 bool isVerboseAsm) {
443 return new PPCTargetAsmStreamer(S, OS);
444}
445
446static MCTargetStreamer *createNullTargetStreamer(MCStreamer &S) {
447 return new PPCTargetStreamer(S);
448}
449
450static MCTargetStreamer *
451createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
452 const Triple &TT = STI.getTargetTriple();
453 if (TT.isOSBinFormatELF())
454 return new PPCTargetELFStreamer(S);
455 if (TT.isOSBinFormatXCOFF())
456 return new PPCTargetXCOFFStreamer(S);
457 return new PPCTargetMachOStreamer(S);
458}
459
460static MCInstPrinter *createPPCMCInstPrinter(const Triple &T,
461 unsigned SyntaxVariant,
462 const MCAsmInfo &MAI,
463 const MCInstrInfo &MII,
464 const MCRegisterInfo &MRI) {
465 return new PPCInstPrinter(MAI, MII, MRI, T);
466}
467
468namespace {
469
470class PPCMCInstrAnalysis : public MCInstrAnalysis {
471public:
472 explicit PPCMCInstrAnalysis(const MCInstrInfo *Info)
473 : MCInstrAnalysis(Info) {}
474
475 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
476 uint64_t &Target) const override {
477 unsigned NumOps = Inst.getNumOperands();
478 if (NumOps == 0 ||
479 Info->get(Opcode: Inst.getOpcode()).operands()[NumOps - 1].OperandType !=
480 MCOI::OPERAND_PCREL)
481 return false;
482 Target = Addr + Inst.getOperand(i: NumOps - 1).getImm() * Size;
483 return true;
484 }
485};
486
487} // end anonymous namespace
488
489static MCInstrAnalysis *createPPCMCInstrAnalysis(const MCInstrInfo *Info) {
490 return new PPCMCInstrAnalysis(Info);
491}
492
493extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTargetMC() {
494 for (Target *T : {&getThePPC32Target(), &getThePPC32LETarget(),
495 &getThePPC64Target(), &getThePPC64LETarget()}) {
496 // Register the MC asm info.
497 RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo);
498
499 // Register the MC instruction info.
500 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createPPCMCInstrInfo);
501
502 // Register the MC register info.
503 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createPPCMCRegisterInfo);
504
505 // Register the MC subtarget info.
506 TargetRegistry::RegisterMCSubtargetInfo(T&: *T, Fn: createPPCMCSubtargetInfo);
507
508 // Register the MC instruction analyzer.
509 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createPPCMCInstrAnalysis);
510
511 // Register the MC Code Emitter
512 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createPPCMCCodeEmitter);
513
514 // Register the asm backend.
515 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createPPCAsmBackend);
516
517 // Register the elf streamer.
518 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createPPCELFStreamer);
519
520 // Register the XCOFF streamer.
521 TargetRegistry::RegisterXCOFFStreamer(T&: *T, Fn: createPPCXCOFFStreamer);
522
523 // Register the object target streamer.
524 TargetRegistry::RegisterObjectTargetStreamer(T&: *T,
525 Fn: createObjectTargetStreamer);
526
527 // Register the asm target streamer.
528 TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createAsmTargetStreamer);
529
530 // Register the null target streamer.
531 TargetRegistry::RegisterNullTargetStreamer(T&: *T, Fn: createNullTargetStreamer);
532
533 // Register the MCInstPrinter.
534 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createPPCMCInstPrinter);
535 }
536}
537

source code of llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp