1 | //===-- RISCVMCTargetDesc.cpp - RISC-V Target Descriptions ----------------===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | /// |
9 | /// This file provides RISC-V specific target descriptions. |
10 | /// |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #include "RISCVMCTargetDesc.h" |
14 | #include "RISCVBaseInfo.h" |
15 | #include "RISCVELFStreamer.h" |
16 | #include "RISCVInstPrinter.h" |
17 | #include "RISCVMCAsmInfo.h" |
18 | #include "RISCVMCObjectFileInfo.h" |
19 | #include "RISCVTargetStreamer.h" |
20 | #include "TargetInfo/RISCVTargetInfo.h" |
21 | #include "llvm/ADT/STLExtras.h" |
22 | #include "llvm/MC/MCAsmBackend.h" |
23 | #include "llvm/MC/MCAsmInfo.h" |
24 | #include "llvm/MC/MCCodeEmitter.h" |
25 | #include "llvm/MC/MCInstrAnalysis.h" |
26 | #include "llvm/MC/MCInstrInfo.h" |
27 | #include "llvm/MC/MCObjectFileInfo.h" |
28 | #include "llvm/MC/MCObjectWriter.h" |
29 | #include "llvm/MC/MCRegisterInfo.h" |
30 | #include "llvm/MC/MCStreamer.h" |
31 | #include "llvm/MC/MCSubtargetInfo.h" |
32 | #include "llvm/MC/TargetRegistry.h" |
33 | #include "llvm/Support/ErrorHandling.h" |
34 | #include <bitset> |
35 | |
36 | #define GET_INSTRINFO_MC_DESC |
37 | #define ENABLE_INSTR_PREDICATE_VERIFIER |
38 | #include "RISCVGenInstrInfo.inc" |
39 | |
40 | #define GET_REGINFO_MC_DESC |
41 | #include "RISCVGenRegisterInfo.inc" |
42 | |
43 | #define GET_SUBTARGETINFO_MC_DESC |
44 | #include "RISCVGenSubtargetInfo.inc" |
45 | |
46 | namespace llvm::RISCVVInversePseudosTable { |
47 | |
48 | using namespace RISCV; |
49 | |
50 | #define GET_RISCVVInversePseudosTable_IMPL |
51 | #include "RISCVGenSearchableTables.inc" |
52 | |
53 | } // namespace llvm::RISCVVInversePseudosTable |
54 | |
55 | using namespace llvm; |
56 | |
57 | static MCInstrInfo *createRISCVMCInstrInfo() { |
58 | MCInstrInfo *X = new MCInstrInfo(); |
59 | InitRISCVMCInstrInfo(X); |
60 | return X; |
61 | } |
62 | |
63 | static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) { |
64 | MCRegisterInfo *X = new MCRegisterInfo(); |
65 | InitRISCVMCRegisterInfo(X, RISCV::X1); |
66 | return X; |
67 | } |
68 | |
69 | static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI, |
70 | const Triple &TT, |
71 | const MCTargetOptions &Options) { |
72 | MCAsmInfo *MAI = new RISCVMCAsmInfo(TT); |
73 | |
74 | MCRegister SP = MRI.getDwarfRegNum(RISCV::RegNum: X2, isEH: true); |
75 | MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(L: nullptr, Register: SP, Offset: 0); |
76 | MAI->addInitialFrameState(Inst); |
77 | |
78 | return MAI; |
79 | } |
80 | |
81 | static MCObjectFileInfo * |
82 | createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC, |
83 | bool LargeCodeModel = false) { |
84 | MCObjectFileInfo *MOFI = new RISCVMCObjectFileInfo(); |
85 | MOFI->initMCObjectFileInfo(MCCtx&: Ctx, PIC, LargeCodeModel); |
86 | return MOFI; |
87 | } |
88 | |
89 | static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, |
90 | StringRef CPU, StringRef FS) { |
91 | if (CPU.empty() || CPU == "generic" ) |
92 | CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32" ; |
93 | |
94 | return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); |
95 | } |
96 | |
97 | static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T, |
98 | unsigned SyntaxVariant, |
99 | const MCAsmInfo &MAI, |
100 | const MCInstrInfo &MII, |
101 | const MCRegisterInfo &MRI) { |
102 | return new RISCVInstPrinter(MAI, MII, MRI); |
103 | } |
104 | |
105 | static MCTargetStreamer * |
106 | createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { |
107 | const Triple &TT = STI.getTargetTriple(); |
108 | if (TT.isOSBinFormatELF()) |
109 | return new RISCVTargetELFStreamer(S, STI); |
110 | return nullptr; |
111 | } |
112 | |
113 | static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S, |
114 | formatted_raw_ostream &OS, |
115 | MCInstPrinter *InstPrint, |
116 | bool isVerboseAsm) { |
117 | return new RISCVTargetAsmStreamer(S, OS); |
118 | } |
119 | |
120 | static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) { |
121 | return new RISCVTargetStreamer(S); |
122 | } |
123 | |
124 | namespace { |
125 | |
126 | class RISCVMCInstrAnalysis : public MCInstrAnalysis { |
127 | int64_t GPRState[31] = {}; |
128 | std::bitset<31> GPRValidMask; |
129 | |
130 | static bool isGPR(unsigned Reg) { |
131 | return Reg >= RISCV::X0 && Reg <= RISCV::X31; |
132 | } |
133 | |
134 | static unsigned getRegIndex(unsigned Reg) { |
135 | assert(isGPR(Reg) && Reg != RISCV::X0 && "Invalid GPR reg" ); |
136 | return Reg - RISCV::X1; |
137 | } |
138 | |
139 | void setGPRState(unsigned Reg, std::optional<int64_t> Value) { |
140 | if (Reg == RISCV::X0) |
141 | return; |
142 | |
143 | auto Index = getRegIndex(Reg); |
144 | |
145 | if (Value) { |
146 | GPRState[Index] = *Value; |
147 | GPRValidMask.set(position: Index); |
148 | } else { |
149 | GPRValidMask.reset(position: Index); |
150 | } |
151 | } |
152 | |
153 | std::optional<int64_t> getGPRState(unsigned Reg) const { |
154 | if (Reg == RISCV::X0) |
155 | return 0; |
156 | |
157 | auto Index = getRegIndex(Reg); |
158 | |
159 | if (GPRValidMask.test(position: Index)) |
160 | return GPRState[Index]; |
161 | return std::nullopt; |
162 | } |
163 | |
164 | public: |
165 | explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info) |
166 | : MCInstrAnalysis(Info) {} |
167 | |
168 | void resetState() override { GPRValidMask.reset(); } |
169 | |
170 | void updateState(const MCInst &Inst, uint64_t Addr) override { |
171 | // Terminators mark the end of a basic block which means the sequentially |
172 | // next instruction will be the first of another basic block and the current |
173 | // state will typically not be valid anymore. For calls, we assume all |
174 | // registers may be clobbered by the callee (TODO: should we take the |
175 | // calling convention into account?). |
176 | if (isTerminator(Inst) || isCall(Inst)) { |
177 | resetState(); |
178 | return; |
179 | } |
180 | |
181 | switch (Inst.getOpcode()) { |
182 | default: { |
183 | // Clear the state of all defined registers for instructions that we don't |
184 | // explicitly support. |
185 | auto NumDefs = Info->get(Opcode: Inst.getOpcode()).getNumDefs(); |
186 | for (unsigned I = 0; I < NumDefs; ++I) { |
187 | auto DefReg = Inst.getOperand(i: I).getReg(); |
188 | if (isGPR(Reg: DefReg)) |
189 | setGPRState(Reg: DefReg, Value: std::nullopt); |
190 | } |
191 | break; |
192 | } |
193 | case RISCV::AUIPC: |
194 | setGPRState(Reg: Inst.getOperand(i: 0).getReg(), |
195 | Value: Addr + (Inst.getOperand(i: 1).getImm() << 12)); |
196 | break; |
197 | } |
198 | } |
199 | |
200 | bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, |
201 | uint64_t &Target) const override { |
202 | if (isConditionalBranch(Inst)) { |
203 | int64_t Imm; |
204 | if (Size == 2) |
205 | Imm = Inst.getOperand(i: 1).getImm(); |
206 | else |
207 | Imm = Inst.getOperand(i: 2).getImm(); |
208 | Target = Addr + Imm; |
209 | return true; |
210 | } |
211 | |
212 | if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) { |
213 | Target = Addr + Inst.getOperand(i: 0).getImm(); |
214 | return true; |
215 | } |
216 | |
217 | if (Inst.getOpcode() == RISCV::JAL) { |
218 | Target = Addr + Inst.getOperand(i: 1).getImm(); |
219 | return true; |
220 | } |
221 | |
222 | if (Inst.getOpcode() == RISCV::JALR) { |
223 | if (auto TargetRegState = getGPRState(Reg: Inst.getOperand(i: 1).getReg())) { |
224 | Target = *TargetRegState + Inst.getOperand(i: 2).getImm(); |
225 | return true; |
226 | } |
227 | |
228 | return false; |
229 | } |
230 | |
231 | return false; |
232 | } |
233 | |
234 | bool isTerminator(const MCInst &Inst) const override { |
235 | if (MCInstrAnalysis::isTerminator(Inst)) |
236 | return true; |
237 | |
238 | switch (Inst.getOpcode()) { |
239 | default: |
240 | return false; |
241 | case RISCV::JAL: |
242 | case RISCV::JALR: |
243 | return Inst.getOperand(i: 0).getReg() == RISCV::X0; |
244 | } |
245 | } |
246 | |
247 | bool isCall(const MCInst &Inst) const override { |
248 | if (MCInstrAnalysis::isCall(Inst)) |
249 | return true; |
250 | |
251 | switch (Inst.getOpcode()) { |
252 | default: |
253 | return false; |
254 | case RISCV::JAL: |
255 | case RISCV::JALR: |
256 | return Inst.getOperand(i: 0).getReg() != RISCV::X0; |
257 | } |
258 | } |
259 | |
260 | bool isReturn(const MCInst &Inst) const override { |
261 | if (MCInstrAnalysis::isReturn(Inst)) |
262 | return true; |
263 | |
264 | switch (Inst.getOpcode()) { |
265 | default: |
266 | return false; |
267 | case RISCV::JALR: |
268 | return Inst.getOperand(i: 0).getReg() == RISCV::X0 && |
269 | maybeReturnAddress(Reg: Inst.getOperand(i: 1).getReg()); |
270 | case RISCV::C_JR: |
271 | return maybeReturnAddress(Reg: Inst.getOperand(i: 0).getReg()); |
272 | } |
273 | } |
274 | |
275 | bool isBranch(const MCInst &Inst) const override { |
276 | if (MCInstrAnalysis::isBranch(Inst)) |
277 | return true; |
278 | |
279 | return isBranchImpl(Inst); |
280 | } |
281 | |
282 | bool isUnconditionalBranch(const MCInst &Inst) const override { |
283 | if (MCInstrAnalysis::isUnconditionalBranch(Inst)) |
284 | return true; |
285 | |
286 | return isBranchImpl(Inst); |
287 | } |
288 | |
289 | bool isIndirectBranch(const MCInst &Inst) const override { |
290 | if (MCInstrAnalysis::isIndirectBranch(Inst)) |
291 | return true; |
292 | |
293 | switch (Inst.getOpcode()) { |
294 | default: |
295 | return false; |
296 | case RISCV::JALR: |
297 | return Inst.getOperand(i: 0).getReg() == RISCV::X0 && |
298 | !maybeReturnAddress(Reg: Inst.getOperand(i: 1).getReg()); |
299 | case RISCV::C_JR: |
300 | return !maybeReturnAddress(Reg: Inst.getOperand(i: 0).getReg()); |
301 | } |
302 | } |
303 | |
304 | private: |
305 | static bool maybeReturnAddress(unsigned Reg) { |
306 | // X1 is used for normal returns, X5 for returns from outlined functions. |
307 | return Reg == RISCV::X1 || Reg == RISCV::X5; |
308 | } |
309 | |
310 | static bool isBranchImpl(const MCInst &Inst) { |
311 | switch (Inst.getOpcode()) { |
312 | default: |
313 | return false; |
314 | case RISCV::JAL: |
315 | return Inst.getOperand(i: 0).getReg() == RISCV::X0; |
316 | case RISCV::JALR: |
317 | return Inst.getOperand(i: 0).getReg() == RISCV::X0 && |
318 | !maybeReturnAddress(Reg: Inst.getOperand(i: 1).getReg()); |
319 | case RISCV::C_JR: |
320 | return !maybeReturnAddress(Reg: Inst.getOperand(i: 0).getReg()); |
321 | } |
322 | } |
323 | }; |
324 | |
325 | } // end anonymous namespace |
326 | |
327 | static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) { |
328 | return new RISCVMCInstrAnalysis(Info); |
329 | } |
330 | |
331 | namespace { |
332 | MCStreamer *createRISCVELFStreamer(const Triple &T, MCContext &Context, |
333 | std::unique_ptr<MCAsmBackend> &&MAB, |
334 | std::unique_ptr<MCObjectWriter> &&MOW, |
335 | std::unique_ptr<MCCodeEmitter> &&MCE, |
336 | bool RelaxAll) { |
337 | return createRISCVELFStreamer(C&: Context, MAB: std::move(MAB), MOW: std::move(MOW), |
338 | MCE: std::move(MCE), RelaxAll); |
339 | } |
340 | } // end anonymous namespace |
341 | |
342 | extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() { |
343 | for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) { |
344 | TargetRegistry::RegisterMCAsmInfo(T&: *T, Fn: createRISCVMCAsmInfo); |
345 | TargetRegistry::RegisterMCObjectFileInfo(T&: *T, Fn: createRISCVMCObjectFileInfo); |
346 | TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createRISCVMCInstrInfo); |
347 | TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createRISCVMCRegisterInfo); |
348 | TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createRISCVAsmBackend); |
349 | TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createRISCVMCCodeEmitter); |
350 | TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createRISCVMCInstPrinter); |
351 | TargetRegistry::RegisterMCSubtargetInfo(T&: *T, Fn: createRISCVMCSubtargetInfo); |
352 | TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createRISCVELFStreamer); |
353 | TargetRegistry::RegisterObjectTargetStreamer( |
354 | T&: *T, Fn: createRISCVObjectTargetStreamer); |
355 | TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createRISCVInstrAnalysis); |
356 | |
357 | // Register the asm target streamer. |
358 | TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createRISCVAsmTargetStreamer); |
359 | // Register the null target streamer. |
360 | TargetRegistry::RegisterNullTargetStreamer(T&: *T, |
361 | Fn: createRISCVNullTargetStreamer); |
362 | } |
363 | } |
364 | |