1/* Integrated Register Allocator (IRA) intercommunication header file.
2 Copyright (C) 2006-2017 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify it under
8the terms of the GNU General Public License as published by the Free
9Software Foundation; either version 3, or (at your option) any later
10version.
11
12GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13WARRANTY; without even the implied warranty of MERCHANTABILITY or
14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING3. If not see
19<http://www.gnu.org/licenses/>. */
20
21#ifndef GCC_IRA_INT_H
22#define GCC_IRA_INT_H
23
24#include "recog.h"
25
26/* To provide consistency in naming, all IRA external variables,
27 functions, common typedefs start with prefix ira_. */
28
29#if CHECKING_P
30#define ENABLE_IRA_CHECKING
31#endif
32
33#ifdef ENABLE_IRA_CHECKING
34#define ira_assert(c) gcc_assert (c)
35#else
36/* Always define and include C, so that warnings for empty body in an
37 'if' statement and unused variable do not occur. */
38#define ira_assert(c) ((void)(0 && (c)))
39#endif
40
41/* Compute register frequency from edge frequency FREQ. It is
42 analogous to REG_FREQ_FROM_BB. When optimizing for size, or
43 profile driven feedback is available and the function is never
44 executed, frequency is always equivalent. Otherwise rescale the
45 edge frequency. */
46#define REG_FREQ_FROM_EDGE_FREQ(freq) \
47 (optimize_function_for_size_p (cfun) \
48 ? REG_FREQ_MAX : (freq * REG_FREQ_MAX / BB_FREQ_MAX) \
49 ? (freq * REG_FREQ_MAX / BB_FREQ_MAX) : 1)
50
51/* A modified value of flag `-fira-verbose' used internally. */
52extern int internal_flag_ira_verbose;
53
54/* Dump file of the allocator if it is not NULL. */
55extern FILE *ira_dump_file;
56
57/* Typedefs for pointers to allocno live range, allocno, and copy of
58 allocnos. */
59typedef struct live_range *live_range_t;
60typedef struct ira_allocno *ira_allocno_t;
61typedef struct ira_allocno_pref *ira_pref_t;
62typedef struct ira_allocno_copy *ira_copy_t;
63typedef struct ira_object *ira_object_t;
64
65/* Definition of vector of allocnos and copies. */
66
67/* Typedef for pointer to the subsequent structure. */
68typedef struct ira_loop_tree_node *ira_loop_tree_node_t;
69
70typedef unsigned short move_table[N_REG_CLASSES];
71
72/* In general case, IRA is a regional allocator. The regions are
73 nested and form a tree. Currently regions are natural loops. The
74 following structure describes loop tree node (representing basic
75 block or loop). We need such tree because the loop tree from
76 cfgloop.h is not convenient for the optimization: basic blocks are
77 not a part of the tree from cfgloop.h. We also use the nodes for
78 storing additional information about basic blocks/loops for the
79 register allocation purposes. */
80struct ira_loop_tree_node
81{
82 /* The node represents basic block if children == NULL. */
83 basic_block bb; /* NULL for loop. */
84 /* NULL for BB or for loop tree root if we did not build CFG loop tree. */
85 struct loop *loop;
86 /* NEXT/SUBLOOP_NEXT is the next node/loop-node of the same parent.
87 SUBLOOP_NEXT is always NULL for BBs. */
88 ira_loop_tree_node_t subloop_next, next;
89 /* CHILDREN/SUBLOOPS is the first node/loop-node immediately inside
90 the node. They are NULL for BBs. */
91 ira_loop_tree_node_t subloops, children;
92 /* The node immediately containing given node. */
93 ira_loop_tree_node_t parent;
94
95 /* Loop level in range [0, ira_loop_tree_height). */
96 int level;
97
98 /* All the following members are defined only for nodes representing
99 loops. */
100
101 /* The loop number from CFG loop tree. The root number is 0. */
102 int loop_num;
103
104 /* True if the loop was marked for removal from the register
105 allocation. */
106 bool to_remove_p;
107
108 /* Allocnos in the loop corresponding to their regnos. If it is
109 NULL the loop does not form a separate register allocation region
110 (e.g. because it has abnormal enter/exit edges and we can not put
111 code for register shuffling on the edges if a different
112 allocation is used for a pseudo-register on different sides of
113 the edges). Caps are not in the map (remember we can have more
114 one cap with the same regno in a region). */
115 ira_allocno_t *regno_allocno_map;
116
117 /* True if there is an entry to given loop not from its parent (or
118 grandparent) basic block. For example, it is possible for two
119 adjacent loops inside another loop. */
120 bool entered_from_non_parent_p;
121
122 /* Maximal register pressure inside loop for given register class
123 (defined only for the pressure classes). */
124 int reg_pressure[N_REG_CLASSES];
125
126 /* Numbers of allocnos referred or living in the loop node (except
127 for its subloops). */
128 bitmap all_allocnos;
129
130 /* Numbers of allocnos living at the loop borders. */
131 bitmap border_allocnos;
132
133 /* Regnos of pseudos modified in the loop node (including its
134 subloops). */
135 bitmap modified_regnos;
136
137 /* Numbers of copies referred in the corresponding loop. */
138 bitmap local_copies;
139};
140
141/* The root of the loop tree corresponding to the all function. */
142extern ira_loop_tree_node_t ira_loop_tree_root;
143
144/* Height of the loop tree. */
145extern int ira_loop_tree_height;
146
147/* All nodes representing basic blocks are referred through the
148 following array. We can not use basic block member `aux' for this
149 because it is used for insertion of insns on edges. */
150extern ira_loop_tree_node_t ira_bb_nodes;
151
152/* Two access macros to the nodes representing basic blocks. */
153#if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007)
154#define IRA_BB_NODE_BY_INDEX(index) __extension__ \
155(({ ira_loop_tree_node_t _node = (&ira_bb_nodes[index]); \
156 if (_node->children != NULL || _node->loop != NULL || _node->bb == NULL)\
157 { \
158 fprintf (stderr, \
159 "\n%s: %d: error in %s: it is not a block node\n", \
160 __FILE__, __LINE__, __FUNCTION__); \
161 gcc_unreachable (); \
162 } \
163 _node; }))
164#else
165#define IRA_BB_NODE_BY_INDEX(index) (&ira_bb_nodes[index])
166#endif
167
168#define IRA_BB_NODE(bb) IRA_BB_NODE_BY_INDEX ((bb)->index)
169
170/* All nodes representing loops are referred through the following
171 array. */
172extern ira_loop_tree_node_t ira_loop_nodes;
173
174/* Two access macros to the nodes representing loops. */
175#if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007)
176#define IRA_LOOP_NODE_BY_INDEX(index) __extension__ \
177(({ ira_loop_tree_node_t const _node = (&ira_loop_nodes[index]); \
178 if (_node->children == NULL || _node->bb != NULL \
179 || (_node->loop == NULL && current_loops != NULL)) \
180 { \
181 fprintf (stderr, \
182 "\n%s: %d: error in %s: it is not a loop node\n", \
183 __FILE__, __LINE__, __FUNCTION__); \
184 gcc_unreachable (); \
185 } \
186 _node; }))
187#else
188#define IRA_LOOP_NODE_BY_INDEX(index) (&ira_loop_nodes[index])
189#endif
190
191#define IRA_LOOP_NODE(loop) IRA_LOOP_NODE_BY_INDEX ((loop)->num)
192
193
194/* The structure describes program points where a given allocno lives.
195 If the live ranges of two allocnos are intersected, the allocnos
196 are in conflict. */
197struct live_range
198{
199 /* Object whose live range is described by given structure. */
200 ira_object_t object;
201 /* Program point range. */
202 int start, finish;
203 /* Next structure describing program points where the allocno
204 lives. */
205 live_range_t next;
206 /* Pointer to structures with the same start/finish. */
207 live_range_t start_next, finish_next;
208};
209
210/* Program points are enumerated by numbers from range
211 0..IRA_MAX_POINT-1. There are approximately two times more program
212 points than insns. Program points are places in the program where
213 liveness info can be changed. In most general case (there are more
214 complicated cases too) some program points correspond to places
215 where input operand dies and other ones correspond to places where
216 output operands are born. */
217extern int ira_max_point;
218
219/* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
220 live ranges with given start/finish point. */
221extern live_range_t *ira_start_point_ranges, *ira_finish_point_ranges;
222
223/* A structure representing conflict information for an allocno
224 (or one of its subwords). */
225struct ira_object
226{
227 /* The allocno associated with this record. */
228 ira_allocno_t allocno;
229 /* Vector of accumulated conflicting conflict_redords with NULL end
230 marker (if OBJECT_CONFLICT_VEC_P is true) or conflict bit vector
231 otherwise. */
232 void *conflicts_array;
233 /* Pointer to structures describing at what program point the
234 object lives. We always maintain the list in such way that *the
235 ranges in the list are not intersected and ordered by decreasing
236 their program points*. */
237 live_range_t live_ranges;
238 /* The subword within ALLOCNO which is represented by this object.
239 Zero means the lowest-order subword (or the entire allocno in case
240 it is not being tracked in subwords). */
241 int subword;
242 /* Allocated size of the conflicts array. */
243 unsigned int conflicts_array_size;
244 /* A unique number for every instance of this structure, which is used
245 to represent it in conflict bit vectors. */
246 int id;
247 /* Before building conflicts, MIN and MAX are initialized to
248 correspondingly minimal and maximal points of the accumulated
249 live ranges. Afterwards, they hold the minimal and maximal ids
250 of other ira_objects that this one can conflict with. */
251 int min, max;
252 /* Initial and accumulated hard registers conflicting with this
253 object and as a consequences can not be assigned to the allocno.
254 All non-allocatable hard regs and hard regs of register classes
255 different from given allocno one are included in the sets. */
256 HARD_REG_SET conflict_hard_regs, total_conflict_hard_regs;
257 /* Number of accumulated conflicts in the vector of conflicting
258 objects. */
259 int num_accumulated_conflicts;
260 /* TRUE if conflicts are represented by a vector of pointers to
261 ira_object structures. Otherwise, we use a bit vector indexed
262 by conflict ID numbers. */
263 unsigned int conflict_vec_p : 1;
264};
265
266/* A structure representing an allocno (allocation entity). Allocno
267 represents a pseudo-register in an allocation region. If
268 pseudo-register does not live in a region but it lives in the
269 nested regions, it is represented in the region by special allocno
270 called *cap*. There may be more one cap representing the same
271 pseudo-register in region. It means that the corresponding
272 pseudo-register lives in more one non-intersected subregion. */
273struct ira_allocno
274{
275 /* The allocno order number starting with 0. Each allocno has an
276 unique number and the number is never changed for the
277 allocno. */
278 int num;
279 /* Regno for allocno or cap. */
280 int regno;
281 /* Mode of the allocno which is the mode of the corresponding
282 pseudo-register. */
283 ENUM_BITFIELD (machine_mode) mode : 8;
284 /* Widest mode of the allocno which in at least one case could be
285 for paradoxical subregs where wmode > mode. */
286 ENUM_BITFIELD (machine_mode) wmode : 8;
287 /* Register class which should be used for allocation for given
288 allocno. NO_REGS means that we should use memory. */
289 ENUM_BITFIELD (reg_class) aclass : 16;
290 /* During the reload, value TRUE means that we should not reassign a
291 hard register to the allocno got memory earlier. It is set up
292 when we removed memory-memory move insn before each iteration of
293 the reload. */
294 unsigned int dont_reassign_p : 1;
295#ifdef STACK_REGS
296 /* Set to TRUE if allocno can't be assigned to the stack hard
297 register correspondingly in this region and area including the
298 region and all its subregions recursively. */
299 unsigned int no_stack_reg_p : 1, total_no_stack_reg_p : 1;
300#endif
301 /* TRUE value means that there is no sense to spill the allocno
302 during coloring because the spill will result in additional
303 reloads in reload pass. */
304 unsigned int bad_spill_p : 1;
305 /* TRUE if a hard register or memory has been assigned to the
306 allocno. */
307 unsigned int assigned_p : 1;
308 /* TRUE if conflicts for given allocno are represented by vector of
309 pointers to the conflicting allocnos. Otherwise, we use a bit
310 vector where a bit with given index represents allocno with the
311 same number. */
312 unsigned int conflict_vec_p : 1;
313 /* Hard register assigned to given allocno. Negative value means
314 that memory was allocated to the allocno. During the reload,
315 spilled allocno has value equal to the corresponding stack slot
316 number (0, ...) - 2. Value -1 is used for allocnos spilled by the
317 reload (at this point pseudo-register has only one allocno) which
318 did not get stack slot yet. */
319 signed int hard_regno : 16;
320 /* Allocnos with the same regno are linked by the following member.
321 Allocnos corresponding to inner loops are first in the list (it
322 corresponds to depth-first traverse of the loops). */
323 ira_allocno_t next_regno_allocno;
324 /* There may be different allocnos with the same regno in different
325 regions. Allocnos are bound to the corresponding loop tree node.
326 Pseudo-register may have only one regular allocno with given loop
327 tree node but more than one cap (see comments above). */
328 ira_loop_tree_node_t loop_tree_node;
329 /* Accumulated usage references of the allocno. Here and below,
330 word 'accumulated' means info for given region and all nested
331 subregions. In this case, 'accumulated' means sum of references
332 of the corresponding pseudo-register in this region and in all
333 nested subregions recursively. */
334 int nrefs;
335 /* Accumulated frequency of usage of the allocno. */
336 int freq;
337 /* Minimal accumulated and updated costs of usage register of the
338 allocno class. */
339 int class_cost, updated_class_cost;
340 /* Minimal accumulated, and updated costs of memory for the allocno.
341 At the allocation start, the original and updated costs are
342 equal. The updated cost may be changed after finishing
343 allocation in a region and starting allocation in a subregion.
344 The change reflects the cost of spill/restore code on the
345 subregion border if we assign memory to the pseudo in the
346 subregion. */
347 int memory_cost, updated_memory_cost;
348 /* Accumulated number of points where the allocno lives and there is
349 excess pressure for its class. Excess pressure for a register
350 class at some point means that there are more allocnos of given
351 register class living at the point than number of hard-registers
352 of the class available for the allocation. */
353 int excess_pressure_points_num;
354 /* Allocno hard reg preferences. */
355 ira_pref_t allocno_prefs;
356 /* Copies to other non-conflicting allocnos. The copies can
357 represent move insn or potential move insn usually because of two
358 operand insn constraints. */
359 ira_copy_t allocno_copies;
360 /* It is a allocno (cap) representing given allocno on upper loop tree
361 level. */
362 ira_allocno_t cap;
363 /* It is a link to allocno (cap) on lower loop level represented by
364 given cap. Null if given allocno is not a cap. */
365 ira_allocno_t cap_member;
366 /* The number of objects tracked in the following array. */
367 int num_objects;
368 /* An array of structures describing conflict information and live
369 ranges for each object associated with the allocno. There may be
370 more than one such object in cases where the allocno represents a
371 multi-word register. */
372 ira_object_t objects[2];
373 /* Accumulated frequency of calls which given allocno
374 intersects. */
375 int call_freq;
376 /* Accumulated number of the intersected calls. */
377 int calls_crossed_num;
378 /* The number of calls across which it is live, but which should not
379 affect register preferences. */
380 int cheap_calls_crossed_num;
381 /* Registers clobbered by intersected calls. */
382 HARD_REG_SET crossed_calls_clobbered_regs;
383 /* Array of usage costs (accumulated and the one updated during
384 coloring) for each hard register of the allocno class. The
385 member value can be NULL if all costs are the same and equal to
386 CLASS_COST. For example, the costs of two different hard
387 registers can be different if one hard register is callee-saved
388 and another one is callee-used and the allocno lives through
389 calls. Another example can be case when for some insn the
390 corresponding pseudo-register value should be put in specific
391 register class (e.g. AREG for x86) which is a strict subset of
392 the allocno class (GENERAL_REGS for x86). We have updated costs
393 to reflect the situation when the usage cost of a hard register
394 is decreased because the allocno is connected to another allocno
395 by a copy and the another allocno has been assigned to the hard
396 register. */
397 int *hard_reg_costs, *updated_hard_reg_costs;
398 /* Array of decreasing costs (accumulated and the one updated during
399 coloring) for allocnos conflicting with given allocno for hard
400 regno of the allocno class. The member value can be NULL if all
401 costs are the same. These costs are used to reflect preferences
402 of other allocnos not assigned yet during assigning to given
403 allocno. */
404 int *conflict_hard_reg_costs, *updated_conflict_hard_reg_costs;
405 /* Different additional data. It is used to decrease size of
406 allocno data footprint. */
407 void *add_data;
408};
409
410
411/* All members of the allocno structures should be accessed only
412 through the following macros. */
413#define ALLOCNO_NUM(A) ((A)->num)
414#define ALLOCNO_REGNO(A) ((A)->regno)
415#define ALLOCNO_REG(A) ((A)->reg)
416#define ALLOCNO_NEXT_REGNO_ALLOCNO(A) ((A)->next_regno_allocno)
417#define ALLOCNO_LOOP_TREE_NODE(A) ((A)->loop_tree_node)
418#define ALLOCNO_CAP(A) ((A)->cap)
419#define ALLOCNO_CAP_MEMBER(A) ((A)->cap_member)
420#define ALLOCNO_NREFS(A) ((A)->nrefs)
421#define ALLOCNO_FREQ(A) ((A)->freq)
422#define ALLOCNO_HARD_REGNO(A) ((A)->hard_regno)
423#define ALLOCNO_CALL_FREQ(A) ((A)->call_freq)
424#define ALLOCNO_CALLS_CROSSED_NUM(A) ((A)->calls_crossed_num)
425#define ALLOCNO_CHEAP_CALLS_CROSSED_NUM(A) ((A)->cheap_calls_crossed_num)
426#define ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS(A) \
427 ((A)->crossed_calls_clobbered_regs)
428#define ALLOCNO_MEM_OPTIMIZED_DEST(A) ((A)->mem_optimized_dest)
429#define ALLOCNO_MEM_OPTIMIZED_DEST_P(A) ((A)->mem_optimized_dest_p)
430#define ALLOCNO_SOMEWHERE_RENAMED_P(A) ((A)->somewhere_renamed_p)
431#define ALLOCNO_CHILD_RENAMED_P(A) ((A)->child_renamed_p)
432#define ALLOCNO_DONT_REASSIGN_P(A) ((A)->dont_reassign_p)
433#ifdef STACK_REGS
434#define ALLOCNO_NO_STACK_REG_P(A) ((A)->no_stack_reg_p)
435#define ALLOCNO_TOTAL_NO_STACK_REG_P(A) ((A)->total_no_stack_reg_p)
436#endif
437#define ALLOCNO_BAD_SPILL_P(A) ((A)->bad_spill_p)
438#define ALLOCNO_ASSIGNED_P(A) ((A)->assigned_p)
439#define ALLOCNO_MODE(A) ((A)->mode)
440#define ALLOCNO_WMODE(A) ((A)->wmode)
441#define ALLOCNO_PREFS(A) ((A)->allocno_prefs)
442#define ALLOCNO_COPIES(A) ((A)->allocno_copies)
443#define ALLOCNO_HARD_REG_COSTS(A) ((A)->hard_reg_costs)
444#define ALLOCNO_UPDATED_HARD_REG_COSTS(A) ((A)->updated_hard_reg_costs)
445#define ALLOCNO_CONFLICT_HARD_REG_COSTS(A) \
446 ((A)->conflict_hard_reg_costs)
447#define ALLOCNO_UPDATED_CONFLICT_HARD_REG_COSTS(A) \
448 ((A)->updated_conflict_hard_reg_costs)
449#define ALLOCNO_CLASS(A) ((A)->aclass)
450#define ALLOCNO_CLASS_COST(A) ((A)->class_cost)
451#define ALLOCNO_UPDATED_CLASS_COST(A) ((A)->updated_class_cost)
452#define ALLOCNO_MEMORY_COST(A) ((A)->memory_cost)
453#define ALLOCNO_UPDATED_MEMORY_COST(A) ((A)->updated_memory_cost)
454#define ALLOCNO_EXCESS_PRESSURE_POINTS_NUM(A) \
455 ((A)->excess_pressure_points_num)
456#define ALLOCNO_OBJECT(A,N) ((A)->objects[N])
457#define ALLOCNO_NUM_OBJECTS(A) ((A)->num_objects)
458#define ALLOCNO_ADD_DATA(A) ((A)->add_data)
459
460/* Typedef for pointer to the subsequent structure. */
461typedef struct ira_emit_data *ira_emit_data_t;
462
463/* Allocno bound data used for emit pseudo live range split insns and
464 to flattening IR. */
465struct ira_emit_data
466{
467 /* TRUE if the allocno assigned to memory was a destination of
468 removed move (see ira-emit.c) at loop exit because the value of
469 the corresponding pseudo-register is not changed inside the
470 loop. */
471 unsigned int mem_optimized_dest_p : 1;
472 /* TRUE if the corresponding pseudo-register has disjoint live
473 ranges and the other allocnos of the pseudo-register except this
474 one changed REG. */
475 unsigned int somewhere_renamed_p : 1;
476 /* TRUE if allocno with the same REGNO in a subregion has been
477 renamed, in other words, got a new pseudo-register. */
478 unsigned int child_renamed_p : 1;
479 /* Final rtx representation of the allocno. */
480 rtx reg;
481 /* Non NULL if we remove restoring value from given allocno to
482 MEM_OPTIMIZED_DEST at loop exit (see ira-emit.c) because the
483 allocno value is not changed inside the loop. */
484 ira_allocno_t mem_optimized_dest;
485};
486
487#define ALLOCNO_EMIT_DATA(a) ((ira_emit_data_t) ALLOCNO_ADD_DATA (a))
488
489/* Data used to emit live range split insns and to flattening IR. */
490extern ira_emit_data_t ira_allocno_emit_data;
491
492/* Abbreviation for frequent emit data access. */
493static inline rtx
494allocno_emit_reg (ira_allocno_t a)
495{
496 return ALLOCNO_EMIT_DATA (a)->reg;
497}
498
499#define OBJECT_ALLOCNO(O) ((O)->allocno)
500#define OBJECT_SUBWORD(O) ((O)->subword)
501#define OBJECT_CONFLICT_ARRAY(O) ((O)->conflicts_array)
502#define OBJECT_CONFLICT_VEC(O) ((ira_object_t *)(O)->conflicts_array)
503#define OBJECT_CONFLICT_BITVEC(O) ((IRA_INT_TYPE *)(O)->conflicts_array)
504#define OBJECT_CONFLICT_ARRAY_SIZE(O) ((O)->conflicts_array_size)
505#define OBJECT_CONFLICT_VEC_P(O) ((O)->conflict_vec_p)
506#define OBJECT_NUM_CONFLICTS(O) ((O)->num_accumulated_conflicts)
507#define OBJECT_CONFLICT_HARD_REGS(O) ((O)->conflict_hard_regs)
508#define OBJECT_TOTAL_CONFLICT_HARD_REGS(O) ((O)->total_conflict_hard_regs)
509#define OBJECT_MIN(O) ((O)->min)
510#define OBJECT_MAX(O) ((O)->max)
511#define OBJECT_CONFLICT_ID(O) ((O)->id)
512#define OBJECT_LIVE_RANGES(O) ((O)->live_ranges)
513
514/* Map regno -> allocnos with given regno (see comments for
515 allocno member `next_regno_allocno'). */
516extern ira_allocno_t *ira_regno_allocno_map;
517
518/* Array of references to all allocnos. The order number of the
519 allocno corresponds to the index in the array. Removed allocnos
520 have NULL element value. */
521extern ira_allocno_t *ira_allocnos;
522
523/* The size of the previous array. */
524extern int ira_allocnos_num;
525
526/* Map a conflict id to its corresponding ira_object structure. */
527extern ira_object_t *ira_object_id_map;
528
529/* The size of the previous array. */
530extern int ira_objects_num;
531
532/* The following structure represents a hard register preference of
533 allocno. The preference represent move insns or potential move
534 insns usually because of two operand insn constraints. One move
535 operand is a hard register. */
536struct ira_allocno_pref
537{
538 /* The unique order number of the preference node starting with 0. */
539 int num;
540 /* Preferred hard register. */
541 int hard_regno;
542 /* Accumulated execution frequency of insns from which the
543 preference created. */
544 int freq;
545 /* Given allocno. */
546 ira_allocno_t allocno;
547 /* All preferences with the same allocno are linked by the following
548 member. */
549 ira_pref_t next_pref;
550};
551
552/* Array of references to all allocno preferences. The order number
553 of the preference corresponds to the index in the array. */
554extern ira_pref_t *ira_prefs;
555
556/* Size of the previous array. */
557extern int ira_prefs_num;
558
559/* The following structure represents a copy of two allocnos. The
560 copies represent move insns or potential move insns usually because
561 of two operand insn constraints. To remove register shuffle, we
562 also create copies between allocno which is output of an insn and
563 allocno becoming dead in the insn. */
564struct ira_allocno_copy
565{
566 /* The unique order number of the copy node starting with 0. */
567 int num;
568 /* Allocnos connected by the copy. The first allocno should have
569 smaller order number than the second one. */
570 ira_allocno_t first, second;
571 /* Execution frequency of the copy. */
572 int freq;
573 bool constraint_p;
574 /* It is a move insn which is an origin of the copy. The member
575 value for the copy representing two operand insn constraints or
576 for the copy created to remove register shuffle is NULL. In last
577 case the copy frequency is smaller than the corresponding insn
578 execution frequency. */
579 rtx_insn *insn;
580 /* All copies with the same allocno as FIRST are linked by the two
581 following members. */
582 ira_copy_t prev_first_allocno_copy, next_first_allocno_copy;
583 /* All copies with the same allocno as SECOND are linked by the two
584 following members. */
585 ira_copy_t prev_second_allocno_copy, next_second_allocno_copy;
586 /* Region from which given copy is originated. */
587 ira_loop_tree_node_t loop_tree_node;
588};
589
590/* Array of references to all copies. The order number of the copy
591 corresponds to the index in the array. Removed copies have NULL
592 element value. */
593extern ira_copy_t *ira_copies;
594
595/* Size of the previous array. */
596extern int ira_copies_num;
597
598/* The following structure describes a stack slot used for spilled
599 pseudo-registers. */
600struct ira_spilled_reg_stack_slot
601{
602 /* pseudo-registers assigned to the stack slot. */
603 bitmap_head spilled_regs;
604 /* RTL representation of the stack slot. */
605 rtx mem;
606 /* Size of the stack slot. */
607 unsigned int width;
608};
609
610/* The number of elements in the following array. */
611extern int ira_spilled_reg_stack_slots_num;
612
613/* The following array contains info about spilled pseudo-registers
614 stack slots used in current function so far. */
615extern struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots;
616
617/* Correspondingly overall cost of the allocation, cost of the
618 allocnos assigned to hard-registers, cost of the allocnos assigned
619 to memory, cost of loads, stores and register move insns generated
620 for pseudo-register live range splitting (see ira-emit.c). */
621extern int64_t ira_overall_cost;
622extern int64_t ira_reg_cost, ira_mem_cost;
623extern int64_t ira_load_cost, ira_store_cost, ira_shuffle_cost;
624extern int ira_move_loops_num, ira_additional_jumps_num;
625
626
627/* This page contains a bitset implementation called 'min/max sets' used to
628 record conflicts in IRA.
629 They are named min/maxs set since we keep track of a minimum and a maximum
630 bit number for each set representing the bounds of valid elements. Otherwise,
631 the implementation resembles sbitmaps in that we store an array of integers
632 whose bits directly represent the members of the set. */
633
634/* The type used as elements in the array, and the number of bits in
635 this type. */
636
637#define IRA_INT_BITS HOST_BITS_PER_WIDE_INT
638#define IRA_INT_TYPE HOST_WIDE_INT
639
640/* Set, clear or test bit number I in R, a bit vector of elements with
641 minimal index and maximal index equal correspondingly to MIN and
642 MAX. */
643#if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007)
644
645#define SET_MINMAX_SET_BIT(R, I, MIN, MAX) __extension__ \
646 (({ int _min = (MIN), _max = (MAX), _i = (I); \
647 if (_i < _min || _i > _max) \
648 { \
649 fprintf (stderr, \
650 "\n%s: %d: error in %s: %d not in range [%d,%d]\n", \
651 __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \
652 gcc_unreachable (); \
653 } \
654 ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \
655 |= ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); }))
656
657
658#define CLEAR_MINMAX_SET_BIT(R, I, MIN, MAX) __extension__ \
659 (({ int _min = (MIN), _max = (MAX), _i = (I); \
660 if (_i < _min || _i > _max) \
661 { \
662 fprintf (stderr, \
663 "\n%s: %d: error in %s: %d not in range [%d,%d]\n", \
664 __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \
665 gcc_unreachable (); \
666 } \
667 ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \
668 &= ~((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); }))
669
670#define TEST_MINMAX_SET_BIT(R, I, MIN, MAX) __extension__ \
671 (({ int _min = (MIN), _max = (MAX), _i = (I); \
672 if (_i < _min || _i > _max) \
673 { \
674 fprintf (stderr, \
675 "\n%s: %d: error in %s: %d not in range [%d,%d]\n", \
676 __FILE__, __LINE__, __FUNCTION__, _i, _min, _max); \
677 gcc_unreachable (); \
678 } \
679 ((R)[(unsigned) (_i - _min) / IRA_INT_BITS] \
680 & ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); }))
681
682#else
683
684#define SET_MINMAX_SET_BIT(R, I, MIN, MAX) \
685 ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS] \
686 |= ((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS)))
687
688#define CLEAR_MINMAX_SET_BIT(R, I, MIN, MAX) \
689 ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS] \
690 &= ~((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS)))
691
692#define TEST_MINMAX_SET_BIT(R, I, MIN, MAX) \
693 ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS] \
694 & ((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS)))
695
696#endif
697
698/* The iterator for min/max sets. */
699struct minmax_set_iterator {
700
701 /* Array containing the bit vector. */
702 IRA_INT_TYPE *vec;
703
704 /* The number of the current element in the vector. */
705 unsigned int word_num;
706
707 /* The number of bits in the bit vector. */
708 unsigned int nel;
709
710 /* The current bit index of the bit vector. */
711 unsigned int bit_num;
712
713 /* Index corresponding to the 1st bit of the bit vector. */
714 int start_val;
715
716 /* The word of the bit vector currently visited. */
717 unsigned IRA_INT_TYPE word;
718};
719
720/* Initialize the iterator I for bit vector VEC containing minimal and
721 maximal values MIN and MAX. */
722static inline void
723minmax_set_iter_init (minmax_set_iterator *i, IRA_INT_TYPE *vec, int min,
724 int max)
725{
726 i->vec = vec;
727 i->word_num = 0;
728 i->nel = max < min ? 0 : max - min + 1;
729 i->start_val = min;
730 i->bit_num = 0;
731 i->word = i->nel == 0 ? 0 : vec[0];
732}
733
734/* Return TRUE if we have more allocnos to visit, in which case *N is
735 set to the number of the element to be visited. Otherwise, return
736 FALSE. */
737static inline bool
738minmax_set_iter_cond (minmax_set_iterator *i, int *n)
739{
740 /* Skip words that are zeros. */
741 for (; i->word == 0; i->word = i->vec[i->word_num])
742 {
743 i->word_num++;
744 i->bit_num = i->word_num * IRA_INT_BITS;
745
746 /* If we have reached the end, break. */
747 if (i->bit_num >= i->nel)
748 return false;
749 }
750
751 /* Skip bits that are zero. */
752 for (; (i->word & 1) == 0; i->word >>= 1)
753 i->bit_num++;
754
755 *n = (int) i->bit_num + i->start_val;
756
757 return true;
758}
759
760/* Advance to the next element in the set. */
761static inline void
762minmax_set_iter_next (minmax_set_iterator *i)
763{
764 i->word >>= 1;
765 i->bit_num++;
766}
767
768/* Loop over all elements of a min/max set given by bit vector VEC and
769 their minimal and maximal values MIN and MAX. In each iteration, N
770 is set to the number of next allocno. ITER is an instance of
771 minmax_set_iterator used to iterate over the set. */
772#define FOR_EACH_BIT_IN_MINMAX_SET(VEC, MIN, MAX, N, ITER) \
773 for (minmax_set_iter_init (&(ITER), (VEC), (MIN), (MAX)); \
774 minmax_set_iter_cond (&(ITER), &(N)); \
775 minmax_set_iter_next (&(ITER)))
776
777struct target_ira_int {
778 ~target_ira_int ();
779
780 void free_ira_costs ();
781 void free_register_move_costs ();
782
783 /* Initialized once. It is a maximal possible size of the allocated
784 struct costs. */
785 size_t x_max_struct_costs_size;
786
787 /* Allocated and initialized once, and used to initialize cost values
788 for each insn. */
789 struct costs *x_init_cost;
790
791 /* Allocated once, and used for temporary purposes. */
792 struct costs *x_temp_costs;
793
794 /* Allocated once, and used for the cost calculation. */
795 struct costs *x_op_costs[MAX_RECOG_OPERANDS];
796 struct costs *x_this_op_costs[MAX_RECOG_OPERANDS];
797
798 /* Hard registers that can not be used for the register allocator for
799 all functions of the current compilation unit. */
800 HARD_REG_SET x_no_unit_alloc_regs;
801
802 /* Map: hard regs X modes -> set of hard registers for storing value
803 of given mode starting with given hard register. */
804 HARD_REG_SET (x_ira_reg_mode_hard_regset
805 [FIRST_PSEUDO_REGISTER][NUM_MACHINE_MODES]);
806
807 /* Maximum cost of moving from a register in one class to a register
808 in another class. Based on TARGET_REGISTER_MOVE_COST. */
809 move_table *x_ira_register_move_cost[MAX_MACHINE_MODE];
810
811 /* Similar, but here we don't have to move if the first index is a
812 subset of the second so in that case the cost is zero. */
813 move_table *x_ira_may_move_in_cost[MAX_MACHINE_MODE];
814
815 /* Similar, but here we don't have to move if the first index is a
816 superset of the second so in that case the cost is zero. */
817 move_table *x_ira_may_move_out_cost[MAX_MACHINE_MODE];
818
819 /* Keep track of the last mode we initialized move costs for. */
820 int x_last_mode_for_init_move_cost;
821
822 /* Array analog of the macro MEMORY_MOVE_COST but they contain maximal
823 cost not minimal. */
824 short int x_ira_max_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
825
826 /* Map class->true if class is a possible allocno class, false
827 otherwise. */
828 bool x_ira_reg_allocno_class_p[N_REG_CLASSES];
829
830 /* Map class->true if class is a pressure class, false otherwise. */
831 bool x_ira_reg_pressure_class_p[N_REG_CLASSES];
832
833 /* Array of the number of hard registers of given class which are
834 available for allocation. The order is defined by the hard
835 register numbers. */
836 short x_ira_non_ordered_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
837
838 /* Index (in ira_class_hard_regs; for given register class and hard
839 register (in general case a hard register can belong to several
840 register classes;. The index is negative for hard registers
841 unavailable for the allocation. */
842 short x_ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
843
844 /* Index [CL][M] contains R if R appears somewhere in a register of the form:
845
846 (reg:M R'), R' not in x_ira_prohibited_class_mode_regs[CL][M]
847
848 For example, if:
849
850 - (reg:M 2) is valid and occupies two registers;
851 - register 2 belongs to CL; and
852 - register 3 belongs to the same pressure class as CL
853
854 then (reg:M 2) contributes to [CL][M] and registers 2 and 3 will be
855 in the set. */
856 HARD_REG_SET x_ira_useful_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
857
858 /* The value is number of elements in the subsequent array. */
859 int x_ira_important_classes_num;
860
861 /* The array containing all non-empty classes. Such classes is
862 important for calculation of the hard register usage costs. */
863 enum reg_class x_ira_important_classes[N_REG_CLASSES];
864
865 /* The array containing indexes of important classes in the previous
866 array. The array elements are defined only for important
867 classes. */
868 int x_ira_important_class_nums[N_REG_CLASSES];
869
870 /* Map class->true if class is an uniform class, false otherwise. */
871 bool x_ira_uniform_class_p[N_REG_CLASSES];
872
873 /* The biggest important class inside of intersection of the two
874 classes (that is calculated taking only hard registers available
875 for allocation into account;. If the both classes contain no hard
876 registers available for allocation, the value is calculated with
877 taking all hard-registers including fixed ones into account. */
878 enum reg_class x_ira_reg_class_intersect[N_REG_CLASSES][N_REG_CLASSES];
879
880 /* Classes with end marker LIM_REG_CLASSES which are intersected with
881 given class (the first index). That includes given class itself.
882 This is calculated taking only hard registers available for
883 allocation into account. */
884 enum reg_class x_ira_reg_class_super_classes[N_REG_CLASSES][N_REG_CLASSES];
885
886 /* The biggest (smallest) important class inside of (covering) union
887 of the two classes (that is calculated taking only hard registers
888 available for allocation into account). If the both classes
889 contain no hard registers available for allocation, the value is
890 calculated with taking all hard-registers including fixed ones
891 into account. In other words, the value is the corresponding
892 reg_class_subunion (reg_class_superunion) value. */
893 enum reg_class x_ira_reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
894 enum reg_class x_ira_reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
895
896 /* For each reg class, table listing all the classes contained in it
897 (excluding the class itself. Non-allocatable registers are
898 excluded from the consideration). */
899 enum reg_class x_alloc_reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
900
901 /* Array whose values are hard regset of hard registers for which
902 move of the hard register in given mode into itself is
903 prohibited. */
904 HARD_REG_SET x_ira_prohibited_mode_move_regs[NUM_MACHINE_MODES];
905
906 /* Flag of that the above array has been initialized. */
907 bool x_ira_prohibited_mode_move_regs_initialized_p;
908};
909
910extern struct target_ira_int default_target_ira_int;
911#if SWITCHABLE_TARGET
912extern struct target_ira_int *this_target_ira_int;
913#else
914#define this_target_ira_int (&default_target_ira_int)
915#endif
916
917#define ira_reg_mode_hard_regset \
918 (this_target_ira_int->x_ira_reg_mode_hard_regset)
919#define ira_register_move_cost \
920 (this_target_ira_int->x_ira_register_move_cost)
921#define ira_max_memory_move_cost \
922 (this_target_ira_int->x_ira_max_memory_move_cost)
923#define ira_may_move_in_cost \
924 (this_target_ira_int->x_ira_may_move_in_cost)
925#define ira_may_move_out_cost \
926 (this_target_ira_int->x_ira_may_move_out_cost)
927#define ira_reg_allocno_class_p \
928 (this_target_ira_int->x_ira_reg_allocno_class_p)
929#define ira_reg_pressure_class_p \
930 (this_target_ira_int->x_ira_reg_pressure_class_p)
931#define ira_non_ordered_class_hard_regs \
932 (this_target_ira_int->x_ira_non_ordered_class_hard_regs)
933#define ira_class_hard_reg_index \
934 (this_target_ira_int->x_ira_class_hard_reg_index)
935#define ira_useful_class_mode_regs \
936 (this_target_ira_int->x_ira_useful_class_mode_regs)
937#define ira_important_classes_num \
938 (this_target_ira_int->x_ira_important_classes_num)
939#define ira_important_classes \
940 (this_target_ira_int->x_ira_important_classes)
941#define ira_important_class_nums \
942 (this_target_ira_int->x_ira_important_class_nums)
943#define ira_uniform_class_p \
944 (this_target_ira_int->x_ira_uniform_class_p)
945#define ira_reg_class_intersect \
946 (this_target_ira_int->x_ira_reg_class_intersect)
947#define ira_reg_class_super_classes \
948 (this_target_ira_int->x_ira_reg_class_super_classes)
949#define ira_reg_class_subunion \
950 (this_target_ira_int->x_ira_reg_class_subunion)
951#define ira_reg_class_superunion \
952 (this_target_ira_int->x_ira_reg_class_superunion)
953#define ira_prohibited_mode_move_regs \
954 (this_target_ira_int->x_ira_prohibited_mode_move_regs)
955
956/* ira.c: */
957
958extern void *ira_allocate (size_t);
959extern void ira_free (void *addr);
960extern bitmap ira_allocate_bitmap (void);
961extern void ira_free_bitmap (bitmap);
962extern void ira_print_disposition (FILE *);
963extern void ira_debug_disposition (void);
964extern void ira_debug_allocno_classes (void);
965extern void ira_init_register_move_cost (machine_mode);
966extern void ira_setup_alts (rtx_insn *insn, HARD_REG_SET &alts);
967extern int ira_get_dup_out_num (int op_num, HARD_REG_SET &alts);
968
969/* ira-build.c */
970
971/* The current loop tree node and its regno allocno map. */
972extern ira_loop_tree_node_t ira_curr_loop_tree_node;
973extern ira_allocno_t *ira_curr_regno_allocno_map;
974
975extern void ira_debug_pref (ira_pref_t);
976extern void ira_debug_prefs (void);
977extern void ira_debug_allocno_prefs (ira_allocno_t);
978
979extern void ira_debug_copy (ira_copy_t);
980extern void debug (ira_allocno_copy &ref);
981extern void debug (ira_allocno_copy *ptr);
982
983extern void ira_debug_copies (void);
984extern void ira_debug_allocno_copies (ira_allocno_t);
985extern void debug (ira_allocno &ref);
986extern void debug (ira_allocno *ptr);
987
988extern void ira_traverse_loop_tree (bool, ira_loop_tree_node_t,
989 void (*) (ira_loop_tree_node_t),
990 void (*) (ira_loop_tree_node_t));
991extern ira_allocno_t ira_parent_allocno (ira_allocno_t);
992extern ira_allocno_t ira_parent_or_cap_allocno (ira_allocno_t);
993extern ira_allocno_t ira_create_allocno (int, bool, ira_loop_tree_node_t);
994extern void ira_create_allocno_objects (ira_allocno_t);
995extern void ira_set_allocno_class (ira_allocno_t, enum reg_class);
996extern bool ira_conflict_vector_profitable_p (ira_object_t, int);
997extern void ira_allocate_conflict_vec (ira_object_t, int);
998extern void ira_allocate_object_conflicts (ira_object_t, int);
999extern void ior_hard_reg_conflicts (ira_allocno_t, HARD_REG_SET *);
1000extern void ira_print_expanded_allocno (ira_allocno_t);
1001extern void ira_add_live_range_to_object (ira_object_t, int, int);
1002extern live_range_t ira_create_live_range (ira_object_t, int, int,
1003 live_range_t);
1004extern live_range_t ira_copy_live_range_list (live_range_t);
1005extern live_range_t ira_merge_live_ranges (live_range_t, live_range_t);
1006extern bool ira_live_ranges_intersect_p (live_range_t, live_range_t);
1007extern void ira_finish_live_range (live_range_t);
1008extern void ira_finish_live_range_list (live_range_t);
1009extern void ira_free_allocno_updated_costs (ira_allocno_t);
1010extern ira_pref_t ira_create_pref (ira_allocno_t, int, int);
1011extern void ira_add_allocno_pref (ira_allocno_t, int, int);
1012extern void ira_remove_pref (ira_pref_t);
1013extern void ira_remove_allocno_prefs (ira_allocno_t);
1014extern ira_copy_t ira_create_copy (ira_allocno_t, ira_allocno_t,
1015 int, bool, rtx_insn *,
1016 ira_loop_tree_node_t);
1017extern ira_copy_t ira_add_allocno_copy (ira_allocno_t, ira_allocno_t, int,
1018 bool, rtx_insn *,
1019 ira_loop_tree_node_t);
1020
1021extern int *ira_allocate_cost_vector (reg_class_t);
1022extern void ira_free_cost_vector (int *, reg_class_t);
1023
1024extern void ira_flattening (int, int);
1025extern bool ira_build (void);
1026extern void ira_destroy (void);
1027
1028/* ira-costs.c */
1029extern void ira_init_costs_once (void);
1030extern void ira_init_costs (void);
1031extern void ira_costs (void);
1032extern void ira_tune_allocno_costs (void);
1033
1034/* ira-lives.c */
1035
1036extern void ira_rebuild_start_finish_chains (void);
1037extern void ira_print_live_range_list (FILE *, live_range_t);
1038extern void debug (live_range &ref);
1039extern void debug (live_range *ptr);
1040extern void ira_debug_live_range_list (live_range_t);
1041extern void ira_debug_allocno_live_ranges (ira_allocno_t);
1042extern void ira_debug_live_ranges (void);
1043extern void ira_create_allocno_live_ranges (void);
1044extern void ira_compress_allocno_live_ranges (void);
1045extern void ira_finish_allocno_live_ranges (void);
1046extern void ira_implicitly_set_insn_hard_regs (HARD_REG_SET *,
1047 alternative_mask);
1048
1049/* ira-conflicts.c */
1050extern void ira_debug_conflicts (bool);
1051extern void ira_build_conflicts (void);
1052
1053/* ira-color.c */
1054extern void ira_debug_hard_regs_forest (void);
1055extern int ira_loop_edge_freq (ira_loop_tree_node_t, int, bool);
1056extern void ira_reassign_conflict_allocnos (int);
1057extern void ira_initiate_assign (void);
1058extern void ira_finish_assign (void);
1059extern void ira_color (void);
1060
1061/* ira-emit.c */
1062extern void ira_initiate_emit_data (void);
1063extern void ira_finish_emit_data (void);
1064extern void ira_emit (bool);
1065
1066
1067
1068/* Return true if equivalence of pseudo REGNO is not a lvalue. */
1069static inline bool
1070ira_equiv_no_lvalue_p (int regno)
1071{
1072 if (regno >= ira_reg_equiv_len)
1073 return false;
1074 return (ira_reg_equiv[regno].constant != NULL_RTX
1075 || ira_reg_equiv[regno].invariant != NULL_RTX
1076 || (ira_reg_equiv[regno].memory != NULL_RTX
1077 && MEM_READONLY_P (ira_reg_equiv[regno].memory)));
1078}
1079
1080
1081
1082/* Initialize register costs for MODE if necessary. */
1083static inline void
1084ira_init_register_move_cost_if_necessary (machine_mode mode)
1085{
1086 if (ira_register_move_cost[mode] == NULL)
1087 ira_init_register_move_cost (mode);
1088}
1089
1090
1091
1092/* The iterator for all allocnos. */
1093struct ira_allocno_iterator {
1094 /* The number of the current element in IRA_ALLOCNOS. */
1095 int n;
1096};
1097
1098/* Initialize the iterator I. */
1099static inline void
1100ira_allocno_iter_init (ira_allocno_iterator *i)
1101{
1102 i->n = 0;
1103}
1104
1105/* Return TRUE if we have more allocnos to visit, in which case *A is
1106 set to the allocno to be visited. Otherwise, return FALSE. */
1107static inline bool
1108ira_allocno_iter_cond (ira_allocno_iterator *i, ira_allocno_t *a)
1109{
1110 int n;
1111
1112 for (n = i->n; n < ira_allocnos_num; n++)
1113 if (ira_allocnos[n] != NULL)
1114 {
1115 *a = ira_allocnos[n];
1116 i->n = n + 1;
1117 return true;
1118 }
1119 return false;
1120}
1121
1122/* Loop over all allocnos. In each iteration, A is set to the next
1123 allocno. ITER is an instance of ira_allocno_iterator used to iterate
1124 the allocnos. */
1125#define FOR_EACH_ALLOCNO(A, ITER) \
1126 for (ira_allocno_iter_init (&(ITER)); \
1127 ira_allocno_iter_cond (&(ITER), &(A));)
1128
1129/* The iterator for all objects. */
1130struct ira_object_iterator {
1131 /* The number of the current element in ira_object_id_map. */
1132 int n;
1133};
1134
1135/* Initialize the iterator I. */
1136static inline void
1137ira_object_iter_init (ira_object_iterator *i)
1138{
1139 i->n = 0;
1140}
1141
1142/* Return TRUE if we have more objects to visit, in which case *OBJ is
1143 set to the object to be visited. Otherwise, return FALSE. */
1144static inline bool
1145ira_object_iter_cond (ira_object_iterator *i, ira_object_t *obj)
1146{
1147 int n;
1148
1149 for (n = i->n; n < ira_objects_num; n++)
1150 if (ira_object_id_map[n] != NULL)
1151 {
1152 *obj = ira_object_id_map[n];
1153 i->n = n + 1;
1154 return true;
1155 }
1156 return false;
1157}
1158
1159/* Loop over all objects. In each iteration, OBJ is set to the next
1160 object. ITER is an instance of ira_object_iterator used to iterate
1161 the objects. */
1162#define FOR_EACH_OBJECT(OBJ, ITER) \
1163 for (ira_object_iter_init (&(ITER)); \
1164 ira_object_iter_cond (&(ITER), &(OBJ));)
1165
1166/* The iterator for objects associated with an allocno. */
1167struct ira_allocno_object_iterator {
1168 /* The number of the element the allocno's object array. */
1169 int n;
1170};
1171
1172/* Initialize the iterator I. */
1173static inline void
1174ira_allocno_object_iter_init (ira_allocno_object_iterator *i)
1175{
1176 i->n = 0;
1177}
1178
1179/* Return TRUE if we have more objects to visit in allocno A, in which
1180 case *O is set to the object to be visited. Otherwise, return
1181 FALSE. */
1182static inline bool
1183ira_allocno_object_iter_cond (ira_allocno_object_iterator *i, ira_allocno_t a,
1184 ira_object_t *o)
1185{
1186 int n = i->n++;
1187 if (n < ALLOCNO_NUM_OBJECTS (a))
1188 {
1189 *o = ALLOCNO_OBJECT (a, n);
1190 return true;
1191 }
1192 return false;
1193}
1194
1195/* Loop over all objects associated with allocno A. In each
1196 iteration, O is set to the next object. ITER is an instance of
1197 ira_allocno_object_iterator used to iterate the conflicts. */
1198#define FOR_EACH_ALLOCNO_OBJECT(A, O, ITER) \
1199 for (ira_allocno_object_iter_init (&(ITER)); \
1200 ira_allocno_object_iter_cond (&(ITER), (A), &(O));)
1201
1202
1203/* The iterator for prefs. */
1204struct ira_pref_iterator {
1205 /* The number of the current element in IRA_PREFS. */
1206 int n;
1207};
1208
1209/* Initialize the iterator I. */
1210static inline void
1211ira_pref_iter_init (ira_pref_iterator *i)
1212{
1213 i->n = 0;
1214}
1215
1216/* Return TRUE if we have more prefs to visit, in which case *PREF is
1217 set to the pref to be visited. Otherwise, return FALSE. */
1218static inline bool
1219ira_pref_iter_cond (ira_pref_iterator *i, ira_pref_t *pref)
1220{
1221 int n;
1222
1223 for (n = i->n; n < ira_prefs_num; n++)
1224 if (ira_prefs[n] != NULL)
1225 {
1226 *pref = ira_prefs[n];
1227 i->n = n + 1;
1228 return true;
1229 }
1230 return false;
1231}
1232
1233/* Loop over all prefs. In each iteration, P is set to the next
1234 pref. ITER is an instance of ira_pref_iterator used to iterate
1235 the prefs. */
1236#define FOR_EACH_PREF(P, ITER) \
1237 for (ira_pref_iter_init (&(ITER)); \
1238 ira_pref_iter_cond (&(ITER), &(P));)
1239
1240
1241/* The iterator for copies. */
1242struct ira_copy_iterator {
1243 /* The number of the current element in IRA_COPIES. */
1244 int n;
1245};
1246
1247/* Initialize the iterator I. */
1248static inline void
1249ira_copy_iter_init (ira_copy_iterator *i)
1250{
1251 i->n = 0;
1252}
1253
1254/* Return TRUE if we have more copies to visit, in which case *CP is
1255 set to the copy to be visited. Otherwise, return FALSE. */
1256static inline bool
1257ira_copy_iter_cond (ira_copy_iterator *i, ira_copy_t *cp)
1258{
1259 int n;
1260
1261 for (n = i->n; n < ira_copies_num; n++)
1262 if (ira_copies[n] != NULL)
1263 {
1264 *cp = ira_copies[n];
1265 i->n = n + 1;
1266 return true;
1267 }
1268 return false;
1269}
1270
1271/* Loop over all copies. In each iteration, C is set to the next
1272 copy. ITER is an instance of ira_copy_iterator used to iterate
1273 the copies. */
1274#define FOR_EACH_COPY(C, ITER) \
1275 for (ira_copy_iter_init (&(ITER)); \
1276 ira_copy_iter_cond (&(ITER), &(C));)
1277
1278/* The iterator for object conflicts. */
1279struct ira_object_conflict_iterator {
1280
1281 /* TRUE if the conflicts are represented by vector of allocnos. */
1282 bool conflict_vec_p;
1283
1284 /* The conflict vector or conflict bit vector. */
1285 void *vec;
1286
1287 /* The number of the current element in the vector (of type
1288 ira_object_t or IRA_INT_TYPE). */
1289 unsigned int word_num;
1290
1291 /* The bit vector size. It is defined only if
1292 OBJECT_CONFLICT_VEC_P is FALSE. */
1293 unsigned int size;
1294
1295 /* The current bit index of bit vector. It is defined only if
1296 OBJECT_CONFLICT_VEC_P is FALSE. */
1297 unsigned int bit_num;
1298
1299 /* The object id corresponding to the 1st bit of the bit vector. It
1300 is defined only if OBJECT_CONFLICT_VEC_P is FALSE. */
1301 int base_conflict_id;
1302
1303 /* The word of bit vector currently visited. It is defined only if
1304 OBJECT_CONFLICT_VEC_P is FALSE. */
1305 unsigned IRA_INT_TYPE word;
1306};
1307
1308/* Initialize the iterator I with ALLOCNO conflicts. */
1309static inline void
1310ira_object_conflict_iter_init (ira_object_conflict_iterator *i,
1311 ira_object_t obj)
1312{
1313 i->conflict_vec_p = OBJECT_CONFLICT_VEC_P (obj);
1314 i->vec = OBJECT_CONFLICT_ARRAY (obj);
1315 i->word_num = 0;
1316 if (i->conflict_vec_p)
1317 i->size = i->bit_num = i->base_conflict_id = i->word = 0;
1318 else
1319 {
1320 if (OBJECT_MIN (obj) > OBJECT_MAX (obj))
1321 i->size = 0;
1322 else
1323 i->size = ((OBJECT_MAX (obj) - OBJECT_MIN (obj)
1324 + IRA_INT_BITS)
1325 / IRA_INT_BITS) * sizeof (IRA_INT_TYPE);
1326 i->bit_num = 0;
1327 i->base_conflict_id = OBJECT_MIN (obj);
1328 i->word = (i->size == 0 ? 0 : ((IRA_INT_TYPE *) i->vec)[0]);
1329 }
1330}
1331
1332/* Return TRUE if we have more conflicting allocnos to visit, in which
1333 case *A is set to the allocno to be visited. Otherwise, return
1334 FALSE. */
1335static inline bool
1336ira_object_conflict_iter_cond (ira_object_conflict_iterator *i,
1337 ira_object_t *pobj)
1338{
1339 ira_object_t obj;
1340
1341 if (i->conflict_vec_p)
1342 {
1343 obj = ((ira_object_t *) i->vec)[i->word_num++];
1344 if (obj == NULL)
1345 return false;
1346 }
1347 else
1348 {
1349 unsigned IRA_INT_TYPE word = i->word;
1350 unsigned int bit_num = i->bit_num;
1351
1352 /* Skip words that are zeros. */
1353 for (; word == 0; word = ((IRA_INT_TYPE *) i->vec)[i->word_num])
1354 {
1355 i->word_num++;
1356
1357 /* If we have reached the end, break. */
1358 if (i->word_num * sizeof (IRA_INT_TYPE) >= i->size)
1359 return false;
1360
1361 bit_num = i->word_num * IRA_INT_BITS;
1362 }
1363
1364 /* Skip bits that are zero. */
1365 for (; (word & 1) == 0; word >>= 1)
1366 bit_num++;
1367
1368 obj = ira_object_id_map[bit_num + i->base_conflict_id];
1369 i->bit_num = bit_num + 1;
1370 i->word = word >> 1;
1371 }
1372
1373 *pobj = obj;
1374 return true;
1375}
1376
1377/* Loop over all objects conflicting with OBJ. In each iteration,
1378 CONF is set to the next conflicting object. ITER is an instance
1379 of ira_object_conflict_iterator used to iterate the conflicts. */
1380#define FOR_EACH_OBJECT_CONFLICT(OBJ, CONF, ITER) \
1381 for (ira_object_conflict_iter_init (&(ITER), (OBJ)); \
1382 ira_object_conflict_iter_cond (&(ITER), &(CONF));)
1383
1384
1385
1386/* The function returns TRUE if at least one hard register from ones
1387 starting with HARD_REGNO and containing value of MODE are in set
1388 HARD_REGSET. */
1389static inline bool
1390ira_hard_reg_set_intersection_p (int hard_regno, machine_mode mode,
1391 HARD_REG_SET hard_regset)
1392{
1393 int i;
1394
1395 gcc_assert (hard_regno >= 0);
1396 for (i = hard_regno_nregs (hard_regno, mode) - 1; i >= 0; i--)
1397 if (TEST_HARD_REG_BIT (hard_regset, hard_regno + i))
1398 return true;
1399 return false;
1400}
1401
1402/* Return number of hard registers in hard register SET. */
1403static inline int
1404hard_reg_set_size (HARD_REG_SET set)
1405{
1406 int i, size;
1407
1408 for (size = i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1409 if (TEST_HARD_REG_BIT (set, i))
1410 size++;
1411 return size;
1412}
1413
1414/* The function returns TRUE if hard registers starting with
1415 HARD_REGNO and containing value of MODE are fully in set
1416 HARD_REGSET. */
1417static inline bool
1418ira_hard_reg_in_set_p (int hard_regno, machine_mode mode,
1419 HARD_REG_SET hard_regset)
1420{
1421 int i;
1422
1423 ira_assert (hard_regno >= 0);
1424 for (i = hard_regno_nregs (hard_regno, mode) - 1; i >= 0; i--)
1425 if (!TEST_HARD_REG_BIT (hard_regset, hard_regno + i))
1426 return false;
1427 return true;
1428}
1429
1430
1431
1432/* To save memory we use a lazy approach for allocation and
1433 initialization of the cost vectors. We do this only when it is
1434 really necessary. */
1435
1436/* Allocate cost vector *VEC for hard registers of ACLASS and
1437 initialize the elements by VAL if it is necessary */
1438static inline void
1439ira_allocate_and_set_costs (int **vec, reg_class_t aclass, int val)
1440{
1441 int i, *reg_costs;
1442 int len;
1443
1444 if (*vec != NULL)
1445 return;
1446 *vec = reg_costs = ira_allocate_cost_vector (aclass);
1447 len = ira_class_hard_regs_num[(int) aclass];
1448 for (i = 0; i < len; i++)
1449 reg_costs[i] = val;
1450}
1451
1452/* Allocate cost vector *VEC for hard registers of ACLASS and copy
1453 values of vector SRC into the vector if it is necessary */
1454static inline void
1455ira_allocate_and_copy_costs (int **vec, enum reg_class aclass, int *src)
1456{
1457 int len;
1458
1459 if (*vec != NULL || src == NULL)
1460 return;
1461 *vec = ira_allocate_cost_vector (aclass);
1462 len = ira_class_hard_regs_num[aclass];
1463 memcpy (*vec, src, sizeof (int) * len);
1464}
1465
1466/* Allocate cost vector *VEC for hard registers of ACLASS and add
1467 values of vector SRC into the vector if it is necessary */
1468static inline void
1469ira_allocate_and_accumulate_costs (int **vec, enum reg_class aclass, int *src)
1470{
1471 int i, len;
1472
1473 if (src == NULL)
1474 return;
1475 len = ira_class_hard_regs_num[aclass];
1476 if (*vec == NULL)
1477 {
1478 *vec = ira_allocate_cost_vector (aclass);
1479 memset (*vec, 0, sizeof (int) * len);
1480 }
1481 for (i = 0; i < len; i++)
1482 (*vec)[i] += src[i];
1483}
1484
1485/* Allocate cost vector *VEC for hard registers of ACLASS and copy
1486 values of vector SRC into the vector or initialize it by VAL (if
1487 SRC is null). */
1488static inline void
1489ira_allocate_and_set_or_copy_costs (int **vec, enum reg_class aclass,
1490 int val, int *src)
1491{
1492 int i, *reg_costs;
1493 int len;
1494
1495 if (*vec != NULL)
1496 return;
1497 *vec = reg_costs = ira_allocate_cost_vector (aclass);
1498 len = ira_class_hard_regs_num[aclass];
1499 if (src != NULL)
1500 memcpy (reg_costs, src, sizeof (int) * len);
1501 else
1502 {
1503 for (i = 0; i < len; i++)
1504 reg_costs[i] = val;
1505 }
1506}
1507
1508extern rtx ira_create_new_reg (rtx);
1509extern int first_moveable_pseudo, last_moveable_pseudo;
1510
1511#endif /* GCC_IRA_INT_H */
1512